TWI748835B - Data processing method and the associated data storage device - Google Patents

Data processing method and the associated data storage device Download PDF

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TWI748835B
TWI748835B TW110100237A TW110100237A TWI748835B TW I748835 B TWI748835 B TW I748835B TW 110100237 A TW110100237 A TW 110100237A TW 110100237 A TW110100237 A TW 110100237A TW I748835 B TWI748835 B TW I748835B
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TW202203038A (en
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陳瑜達
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慧榮科技股份有限公司
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Abstract

A data storage device includes a memory device and a memory controller. The memory controller is configured to update content of a read count table in response to a read command issued by a host device with a transfer length greater than 1 for designating more than one logical address to be read, select at least one sub-region to be rearranged according to the content of the read count table and perform a data rearrangement procedure to move data of the logical addresses belonging to the selected at least one sub-region to a first memory space of the memory device having continuous physical addresses. The read count table includes a plurality of fields, each field records a read count associated with one sub-region and the memory controller updates the content of the read count table by increasing the read count(s) associated with the sub-region(s) that the logical addresses designated in the read command belong to.

Description

資料處理方法及對應之資料儲存裝置Data processing method and corresponding data storage device

本發明係有關於一種可有效改善記憶體裝置之存取效能之資料處理方法及對應之資料儲存裝置。The invention relates to a data processing method that can effectively improve the access performance of a memory device and a corresponding data storage device.

隨著資料儲存裝置的科技在近幾年快速地成長，許多資料儲存裝置，如符合安全數位(Secure Digital，縮寫為SD)/ 多媒體卡(Multi Media Card，縮寫為MMC)規格、複合式快閃記憶體(Compact flash，縮寫為CF)規格、記憶條(Memory Stick，縮寫為MS)規格與極數位(Extreme Digital，縮寫為XD)規格的記憶卡、固態硬碟、嵌入式多媒體記憶卡(embedded Multi Media Card，縮寫為eMMC)以及通用快閃記憶體儲存(Universal Flash Storage，縮寫為UFS)已經廣泛地被應用在多種用途上。因此，在這些資料儲存裝置上，有效率的存取控制也變成一個重要的議題。As the technology of data storage devices has grown rapidly in recent years, many data storage devices, such as compliant with Secure Digital (SD)/Multi Media Card (MMC) specifications, composite flash Memory (Compact flash, abbreviated as CF) specifications, memory stick (Memory Stick, abbreviated as MS) specifications and extreme digital (Extreme Digital, abbreviated as XD) specifications of memory cards, solid state drives, embedded multimedia memory cards (embedded Multi Media Card, abbreviated as eMMC) and Universal Flash Storage (abbreviated as UFS) have been widely used in a variety of purposes. Therefore, efficient access control has also become an important issue on these data storage devices.

為了輔助資料儲存裝置的存取操作，資料儲存裝置端可建立並維護一或多個映射表格，用以紀錄實體位址與邏輯位址間的映射關係。邏輯位址為由連接資料儲存裝置之一主機裝置所使用的位址，主機裝置可利用邏輯位址識別不同的記憶空間。實體位址為資料儲存裝置所使用的位址，資料儲存裝置可利用實體位址識別不同的記憶空間。記憶體控制器根據記憶體裝置的存取操作管理這些映射表格。In order to assist the access operation of the data storage device, the data storage device can create and maintain one or more mapping tables to record the mapping relationship between physical addresses and logical addresses. The logical address is an address used by a host device connected to a data storage device, and the host device can use the logical address to identify different memory spaces. The physical address is the address used by the data storage device, and the data storage device can use the physical address to identify different memory spaces. The memory controller manages these mapping tables according to the access operations of the memory device.

響應於帶有欲讀取之邏輯位址之一讀取指令，記憶體控制器必須查找映射表格，以取得儲存欲讀取之邏輯位址之資料的實體位址。然而，表格的查找或搜尋通常為較耗時的操作。此外，表格大小通常會隨著記憶體裝置的容量增加而增加。因此，在映射表格中查找或搜索所需的時間會隨著映射表格的大小增加而大幅增加。In response to a read command with the logical address to be read, the memory controller must look up the mapping table to obtain the physical address that stores the data of the logical address to be read. However, the search or search of the table is usually a time-consuming operation. In addition, the table size usually increases as the capacity of the memory device increases. Therefore, the time required to find or search in the mapping table will increase significantly as the size of the mapping table increases.

為解決此問題並且改善記憶體裝置的讀取速度，需要一種可有效處理記憶體裝置所儲存之資料並改善記憶體裝置存取效能的資料處理方法。In order to solve this problem and improve the reading speed of the memory device, a data processing method that can effectively process the data stored in the memory device and improve the access performance of the memory device is needed.

本發明之一目的在於解決前述問題，並且改善記憶體裝置的讀取速度。An object of the present invention is to solve the aforementioned problems and improve the reading speed of the memory device.

根據本發明之一實施例，一種資料儲存裝置包括一記憶體裝置與一記憶體控制器。記憶體裝置包括複數記憶體區塊，記憶體區塊對應於複數邏輯單元，各邏輯單元分別對應於複數邏輯位址，各邏輯單元所對應之邏輯位址被劃分為複數區域，並且各區域進一步被劃分為複數子區域。記憶體控制器耦接至記憶體裝置，用以存取記憶體裝置，並且響應於由一主機裝置發出之一讀取指令更新一讀取次數表格的內容，其中讀取指令帶有大於1之一傳輸長度，以選定一個以上要被讀取的邏輯位址。讀取次數表格包括複數欄位，各欄位用以記錄相關聯之一子區域所對應之一讀取次數，並且記憶體控制器藉由增加於讀取指令中選定的邏輯位址所屬之一或多個子區域所對應之一或多個讀取次數更新讀取次數表格的內容。記憶體控制器更根據讀取次數表格的內容選擇至少一個子區域，並且執行一資料重排程序用以將屬於被選擇的至少一個子區域的邏輯位址的資料搬移至記憶體裝置中具有連續實體位址的一第一記憶空間。According to an embodiment of the present invention, a data storage device includes a memory device and a memory controller. The memory device includes a plurality of memory blocks, the memory blocks correspond to a plurality of logical units, each logical unit corresponds to a plurality of logical addresses, the logical address corresponding to each logical unit is divided into a plurality of areas, and each area is further Is divided into plural sub-areas. The memory controller is coupled to the memory device for accessing the memory device, and updates the content of a read count table in response to a read command issued by a host device, wherein the read command has a value greater than 1 A transfer length to select more than one logical address to be read. The read count table includes a plurality of fields, and each field is used to record a read count corresponding to a related sub-area, and the memory controller adds one of the logical addresses selected in the read command. One or more reading times corresponding to the multiple sub-regions update the content of the reading times table. The memory controller further selects at least one sub-area according to the content of the read count table, and executes a data rearrangement procedure to move the data belonging to the logical address of the selected at least one sub-area to the memory device with continuous A first memory space of the physical address.

根據本發明之另一實施例，一種資料處理方法，適用於一資料儲存裝置，其中資料儲存裝置包括一記憶體裝置與一記憶體控制器，記憶體裝置包括複數記憶體區塊，記憶體區塊對應於複數邏輯單元，各邏輯單元分別對應於複數邏輯位址，各邏輯單元所對應之邏輯位址被劃分為複數區域，並且各區域進一步被劃分為複數子區域，記憶體控制器耦接至記憶體裝置，用以存取記憶體裝置，資料處理方法由記憶體控制器所執行並包括：建立一讀取次數表格，並且響應於由一主機裝置發出之一讀取指令更新讀取次數表格的內容，其中讀取指令帶有大於1之一傳輸長度，以選定一個以上要被讀取的邏輯位址，讀取次數表格包括複數欄位，各欄位用以記錄相關聯之一子區域所對應之一讀取次數，並且讀取次數表格的內容係藉由增加於讀取指令中選定的邏輯位址所屬之一或多個子區域所對應之一或多個讀取次數而被更新；根據讀取次數表格的內容選擇至少一個子區域；以及執行一資料重排程序，用以將屬於被選擇的至少一個子區域的邏輯位址的資料搬移至記憶體裝置中具有連續實體位址的一第一記憶空間。According to another embodiment of the present invention, a data processing method is applicable to a data storage device, wherein the data storage device includes a memory device and a memory controller, and the memory device includes a plurality of memory blocks, a memory area A block corresponds to a complex number of logical units, each logical unit corresponds to a complex number of logical addresses, the logical address corresponding to each logical unit is divided into a plurality of areas, and each area is further divided into a plurality of sub-areas, and the memory controller is coupled To the memory device for accessing the memory device, the data processing method is executed by the memory controller and includes: creating a read count table, and updating the read count in response to a read command issued by a host device The content of the table, where the read command has a transmission length greater than 1 to select more than one logical address to be read. The read count table includes multiple fields, and each field is used to record the associated one. A read count corresponding to the area, and the content of the read count table is updated by adding one or more read counts corresponding to one or more sub-areas to which the logical address selected in the read command belongs ; Select at least one sub-area according to the content of the read count table; and perform a data rearrangement procedure to move the data belonging to the logical address of the selected at least one sub-area to the memory device with a continuous physical address One of the first memory space.

在下文中，描述了許多具體細節以提供對本發明實施例的透徹理解。然而，本領域技術人員仍將理解如何在缺少一個或多個具體細節或依賴於其他方法、元件或材料的情況下實施本發明。在其他情況下，未詳細示出或描述公知的結構、材料或操作，以避免模糊本發明的主要概念。In the following, many specific details are described to provide a thorough understanding of the embodiments of the present invention. However, those skilled in the art will still understand how to implement the present invention without one or more specific details or relying on other methods, elements or materials. In other cases, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the main concept of the present invention.

在整個說明書中對「一實施例」或「一範例」的引用意味著結合該實施例或範例所描述的特定特徵、結構或特性係包括於本發明之多個實施例的至少一個實施例中。因此，貫穿本說明書在各個地方出現的短語「於本發明之一實施例中」、「根據本發明之一實施例」、「於一範例中」或「根據本發明之一範例」不一定都指到相同的實施例或範例。此外，特定特徵、結構或特性可以在一個或多個實施例或範例中以任何合適的組合和/或子組合進行結合。Reference to "an embodiment" or "an example" throughout the specification means that a specific feature, structure, or characteristic described in conjunction with the embodiment or example is included in at least one of the multiple embodiments of the present invention . Therefore, the phrases "in an embodiment of the present invention", "in accordance with an embodiment of the present invention", "in an example" or "in accordance with an example of the present invention" appearing in various places throughout this specification are not necessarily All refer to the same embodiment or example. In addition, specific features, structures or characteristics can be combined in any suitable combination and/or sub-combination in one or more embodiments or examples.

此外，為讓本發明之目的、特徵和優點能更明顯易懂，下文特舉出本發明之具體實施例，並配合所附圖式，作詳細說明如下。目的在於說明本發明之精神而非用以限定本發明之保護範圍，應理解下列實施例可經由軟體、硬體、韌體、或上述任意組合來實現。In addition, in order to make the purpose, features and advantages of the present invention more comprehensible, specific embodiments of the present invention are listed below, with the accompanying drawings, and detailed descriptions are as follows. The purpose is to illustrate the spirit of the present invention and not to limit the protection scope of the present invention. It should be understood that the following embodiments can be implemented by software, hardware, firmware, or any combination of the foregoing.

第1圖係顯示根據本發明之一實施例所述之資料儲存裝置的方塊圖範例。資料儲存裝置100可包括一記憶體裝置120與一記憶體控制器110。記憶體控制器110用以存取(Access)記憶體裝置120及控制記憶體裝置120之運作。記憶體裝置120可為一非揮發性(non-volatile，縮寫為NV)記憶體裝置(例如，一快閃記憶體(flash memory))，並且可包括一或多個記憶元件(例如，一或多個快閃記憶體晶粒、一或多個快閃記憶體晶片、或其他類似元件)。Fig. 1 shows an example of a block diagram of a data storage device according to an embodiment of the present invention. The data storage device 100 may include a memory device 120 and a memory controller 110. The memory controller 110 is used to access the memory device 120 and control the operation of the memory device 120. The memory device 120 may be a non-volatile (NV) memory device (for example, a flash memory), and may include one or more memory elements (for example, one or Multiple flash memory dies, one or more flash memory chips, or other similar components).

資料儲存裝置100可耦接至一主機裝置130。主機裝置130可至少包括一處理器、一電源電路、以及至少一隨機存取記憶體(Random Access Memory，縮寫為RAM)，例如至少一動態隨機存取記憶體(Dynamic RAM，縮寫為DRAM)、至少一靜態隨機存取記憶體(Static RAM，縮寫為SRAM)等(以上未示於第1圖)。處理器與隨機存取記憶體可透過一匯流排彼此相互連接，並且可耦接至電源電路以取得電源。處理器可控制主機裝置130之運作。電源電路可將電源供應至處理器、隨機存取記憶體以及資料儲存裝置100，例如輸出一或多個驅動電壓至資料儲存裝置100。資料儲存裝置100可自主機裝置130取得所述驅動電壓作為資料儲存裝置100的電源，並且為主機裝置130提供儲存空間。The data storage device 100 can be coupled to a host device 130. The host device 130 may include at least a processor, a power supply circuit, and at least one random access memory (Random Access Memory, abbreviated as RAM), such as at least one dynamic random access memory (Dynamic RAM, abbreviated as DRAM), At least one static random access memory (Static RAM, abbreviated as SRAM), etc. (not shown in Figure 1 above). The processor and the random access memory can be connected to each other through a bus, and can be coupled to a power circuit to obtain power. The processor can control the operation of the host device 130. The power circuit can supply power to the processor, the random access memory and the data storage device 100, for example, output one or more driving voltages to the data storage device 100. The data storage device 100 can obtain the driving voltage from the host device 130 as a power source for the data storage device 100 and provide storage space for the host device 130.

根據本發明之一實施例，記憶體控制器110可包括一微處理器112、一唯讀記憶體(Read Only Memory，縮寫為ROM)112M、一記憶體介面114、一緩衝記憶體116、與一主機介面118。唯讀記憶體112M係用以儲存程式碼112C。而微處理器112則用來執行程式碼112C以控制對記憶體裝置120之存取。程式碼112C可包括一或多個程式模組，例如啟動載入(boot loader)程式碼。當資料儲存裝置100自主機裝置130取得電源時，微處理器112可藉由執行程式碼112C執行資料儲存裝置100之一初始化程序。於初始化程序中，微處理器112可自記憶體裝置120載入一組系統內編程(In-System Programming，縮寫為ISP)程式碼(未示於第1圖)。微處理器112可執行該組系統內編程程式碼，使得資料儲存裝置100可具備各種功能。根據本發明之一實施例，該組系統內編程程式碼可包括，但不限於：一或多個與記憶體存取(例如，讀取、寫入與抹除)相關的程式模組，例如一讀取操作模組、一查找表格模組、一損耗均衡(wear leveling)模組、一讀取刷新(read refresh) 模組、一讀取回收(read reclaim)模組、一垃圾回收模組、一非預期斷電恢復(Sudden Power Off Recovery，縮寫為SPOR)模組、以及一不可更正錯誤更正碼(Uncorrectable Error Correction Code，縮寫為UECC)模組，其分別被提供用以執行對應之讀取、查找表格、損耗均衡、讀取刷新、讀取回收、垃圾回收、非預期斷電恢復以及對偵測到的UECC錯誤進行錯誤處理等操作。According to an embodiment of the present invention, the memory controller 110 may include a microprocessor 112, a read-only memory (Read Only Memory, abbreviated as ROM) 112M, a memory interface 114, a buffer memory 116, and A host interface 118. The read-only memory 112M is used to store the program code 112C. The microprocessor 112 is used to execute the program code 112C to control the access to the memory device 120. The program code 112C may include one or more program modules, such as a boot loader program code. When the data storage device 100 obtains power from the host device 130, the microprocessor 112 can execute an initialization procedure of the data storage device 100 by executing the program code 112C. In the initialization process, the microprocessor 112 can load a set of In-System Programming (ISP) code (not shown in FIG. 1) from the memory device 120. The microprocessor 112 can execute the set of in-system programming codes, so that the data storage device 100 can have various functions. According to an embodiment of the present invention, the set of in-system programming code may include, but is not limited to: one or more program modules related to memory access (eg, read, write, and erase), such as A read operation module, a lookup table module, a wear leveling module, a read refresh module, a read reclaim module, and a garbage collection module , A Sudden Power Off Recovery (SPOR) module, and an Uncorrectable Error Correction Code (UECC) module, which are respectively provided to perform the corresponding reading Fetch, lookup table, wear leveling, read refresh, read recovery, garbage collection, unexpected power failure recovery, and error handling for detected UECC errors.

記憶體介面114包含了一編碼器132以及一解碼器134，其中編碼器132用來對需被寫入記憶體裝置120的資料進行編碼，例如執行錯誤更正碼(ECC)編碼，而解碼器134用來對從記憶體裝置120所讀出的資料進行解碼。The memory interface 114 includes an encoder 132 and a decoder 134. The encoder 132 is used to encode data to be written into the memory device 120, such as performing error correction code (ECC) encoding, and the decoder 134 It is used to decode the data read from the memory device 120.

於典型狀況下，記憶體裝置120包含了多個記憶元件，例如多個快閃記憶體晶粒或多個快閃記憶體晶片，各記憶元件可包含複數個記憶體區塊(Block)。記憶體控制器110對記憶體裝置120進行抹除資料運作係以區塊為單位來進行。另外，一記憶體區塊可記錄(包含)特定數量的資料頁(Page)，例如，實體資料頁，其中記憶體控制器110對記憶體裝置120進行寫入資料之運作係以資料頁為單位來進行寫入。In a typical situation, the memory device 120 includes a plurality of memory elements, such as a plurality of flash memory dies or a plurality of flash memory chips, and each memory element may include a plurality of memory blocks. The memory controller 110 erases data from the memory device 120 in units of blocks. In addition, a memory block can record (include) a specific number of data pages (Pages), for example, physical data pages, in which the memory controller 110 writes data to the memory device 120 in units of data pages To write.

實作上，記憶體控制器110可利用其本身內部之元件來進行諸多控制運作，例如：利用記憶體介面114來控制記憶體裝置120之存取運作(尤其是對至少一記憶體區塊或至少一資料頁之存取運作)、利用緩衝記憶體116進行所需之緩衝處理、以及利用主機介面118來與主機裝置130溝通。In practice, the memory controller 110 can use its own internal components to perform many control operations, such as: using the memory interface 114 to control the access operations of the memory device 120 (especially for at least one memory block or At least one data page access operation), the buffer memory 116 is used to perform the required buffer processing, and the host interface 118 is used to communicate with the host device 130.

在一實施例中，記憶體控制器110透過主機介面118並使用一標準通訊協定與主機裝置130溝通。舉例而言，上述之標準通訊協定包含(但不限於)：通用序列匯流排(Universal Serial Bus ，縮寫為USB)標準、SD介面標準、超高速一代 (Ultra High Speed-I，縮寫為UHS-I) 介面標準、超高速二代 (Ultra High Speed-II，縮寫為UHS-II) 介面標準、CF介面標準、MMC介面標準、eMMC介面標準、UFS介面標準、高技術組態(Advanced Technology Attachment，縮寫為ATA)標準、序列高技術組態(Serial ATA，縮寫為SATA)標準、快捷外設互聯標準(Peripheral Component Interconnect Express，縮寫為PCI-E)標準、並列先進附件(Parallel Advanced Technology Attachment，縮寫為PATA)標準等。In one embodiment, the memory controller 110 communicates with the host device 130 through the host interface 118 and using a standard communication protocol. For example, the aforementioned standard communication protocols include (but are not limited to): Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) ) Interface standard, Ultra High Speed-II (UHS-II) interface standard, CF interface standard, MMC interface standard, eMMC interface standard, UFS interface standard, Advanced Technology Attachment (Advanced Technology Attachment, abbreviation) ATA) standard, Serial ATA (SATA) standard, Peripheral Component Interconnect Express (PCI-E) standard, Parallel Advanced Technology Attachment (Parallel Advanced Technology Attachment, abbreviated as PATA) standards and so on.

在一實施例中，緩衝記憶體116係以隨機存取記憶體來實施。例如，緩衝記憶體116可以是靜態隨機存取記憶體，但本發明亦不限於此。於其他實施例中，緩衝記憶體116可以是動態隨機存取記憶體。In one embodiment, the buffer memory 116 is implemented as a random access memory. For example, the buffer memory 116 may be a static random access memory, but the invention is not limited to this. In other embodiments, the buffer memory 116 may be a dynamic random access memory.

在一實施例中，資料儲存裝置100可以是可攜式記憶體裝置(例如：符合SD/MMC、CF、MS、XD標準之記憶卡)，且主機裝置130為一可與資料儲存裝置連接的電子裝置，例如手機、筆記型電腦、桌上型電腦…等等。而在另一實施例中，資料儲存裝置100可以是固態硬碟或符合UFS或eMMC規格之嵌入式儲存裝置，並且可被設置在一電子裝置中，例如設置在手機、筆記型電腦、桌上型電腦之中，而此時主機裝置130可以是該電子裝置的一處理器。In one embodiment, the data storage device 100 can be a portable memory device (for example, a memory card that complies with SD/MMC, CF, MS, and XD standards), and the host device 130 can be connected to the data storage device Electronic devices, such as mobile phones, laptops, desktop computers... etc. In another embodiment, the data storage device 100 may be a solid-state drive or an embedded storage device conforming to UFS or eMMC specifications, and may be installed in an electronic device, such as a mobile phone, a notebook computer, or a desktop. In a large-scale computer, the host device 130 may be a processor of the electronic device at this time.

主機裝置130可對資料儲存裝置100發出指令，例如，讀取指令或寫入指令，用以存取記憶體裝置120所儲存之資料，或者主機裝置130可對資料儲存裝置100發出指令以進一步控制、管理資料儲存裝置100。The host device 130 can issue commands to the data storage device 100, for example, read commands or write commands to access data stored in the memory device 120, or the host device 130 can issue commands to the data storage device 100 for further control , Manage the data storage device 100.

記憶體裝置120可儲存一全域邏輯至實體(Logical to Physical，縮寫為L2P)(或稱主機至快閃記憶體(Host to Flash，縮寫為H2F))映射表格，供記憶體控制器110存取記憶體裝置120之資料時使用。全域L2P映射表格可位於記憶體裝置120之一既定區域，例如一系統區域，但本發明並不限於此。全域L2P映射表格可被分為複數區域L2P映射表格，區域L2P映射表格可被儲存於相同或不同的記憶元件內。例如，一記憶元件可儲存一個區域L2P映射表格。於需要時，記憶體控制器110可將全域L2P映射表格的至少一部分(例如，一部分或全部)載入緩衝記憶體116或其他記憶體內。例如，記憶體控制器110可載入一區域L2P映射表格作為一暫時的L2P映射表格，用以根據此區域L2P映射表格存取記憶體裝置120的資料，但本發明並不限於此。The memory device 120 can store a logical to physical (L2P) (or Host to Flash (H2F)) mapping table for the memory controller 110 to access Used when storing data in the memory device 120. The global L2P mapping table may be located in a predetermined area of the memory device 120, such as a system area, but the invention is not limited to this. The global L2P mapping table can be divided into a plurality of area L2P mapping tables, and the area L2P mapping tables can be stored in the same or different memory elements. For example, a memory element can store a regional L2P mapping table. When necessary, the memory controller 110 can load at least a part (for example, a part or all) of the global L2P mapping table into the buffer memory 116 or other memory. For example, the memory controller 110 can load a regional L2P mapping table as a temporary L2P mapping table for accessing data of the memory device 120 according to the regional L2P mapping table, but the invention is not limited to this.

為了改善讀取效能，近期已發布了主機性能增強器(Host Performance Booster，縮寫為HPB)系列標準。HPB利用主機裝置端的一個記憶體裝置(例如，主機裝置130之DRAM)暫存於UFS裝置端(例如，依循UFS規格實施的資料儲存裝置100)所維護的映射資訊。所述映射資訊可自前述之全域或區域L2P映射表格中取得。借助此映射資訊，主機裝置130可發出帶有主機裝置130所欲讀取之邏輯位址(例如，邏輯區塊位址(logical block addresses，縮寫為LBAs)所對應的實體位址之相關資訊(例如，實體區塊位址(physical block addresses，縮寫為PBAs)的特定讀取指令(以下稱為HPB讀取(HPB READ)指令)以讀取資料，其中所述實體位址之相關資訊可被承載於一或多個HPB項目(HPB entry)中。如此一來，記憶體控制器110可節省自記憶體裝置120讀取及載入全域或區域L2P映射表格所花費的時間，以及節省於載入之L2P映射表格中搜尋出主機裝置130所欲讀取之邏輯位址所對應的實體位址所花費的時間。藉此，讀取效能可被改善。In order to improve reading performance, a host performance booster (Host Performance Booster, abbreviated as HPB) series of standards have recently been released. The HPB uses a memory device on the host device side (for example, the DRAM of the host device 130) to temporarily store the mapping information maintained on the UFS device side (for example, the data storage device 100 implemented in accordance with the UFS specification). The mapping information can be obtained from the aforementioned global or regional L2P mapping table. With the help of this mapping information, the host device 130 can send out relevant information ( For example, physical block addresses (physical block addresses, abbreviated as PBAs) specific read commands (hereinafter referred to as HPB READ commands) to read data, wherein the relevant information of the physical address can be Loaded in one or more HPB entries (HPB entry). In this way, the memory controller 110 can save the time spent on reading and loading the global or regional L2P mapping table from the memory device 120, and save on loading The time it takes to search for the physical address corresponding to the logical address to be read by the host device 130 from the entered L2P mapping table. With this, the read performance can be improved.

一般而言，記憶體裝置120可被劃分為多個分區，各分區可被視為一個邏輯單元，且各邏輯單元可對應於複數邏輯區塊位址。第2圖係顯示邏輯單元200與其對應之邏輯區塊位址的一個範例。如HPB規格所定義，各邏輯單元所對應的邏輯區塊位址(例如，邏輯區塊位址LBA 0~LBA Z，其中Z為正整數)可被劃分為複數個HPB區域(例如，HPB區域HPB_Rgn_0~ HPB_Rgn_(N-1)，其中N為大於1之一正整數)，並且各HPB區域可進一步被劃分為複數HPB子區域(例如，HPB子區域HPB_Sub_Rgn_0~ HPB_Sub_Rgn_(L-1)，其中L為一正整數)。一個HPB子區域的大小可小於或等於一個HPB區域的大小。為簡化說明，以下將HPB子區域簡稱為子區域，以及將HPB區域簡稱為區域。Generally speaking, the memory device 120 can be divided into multiple partitions, each partition can be regarded as a logical unit, and each logical unit can correspond to a plurality of logical block addresses. FIG. 2 shows an example of the logic unit 200 and its corresponding logic block address. As defined in the HPB specification, the logical block address corresponding to each logical unit (for example, logical block address LBA 0~LBA Z, where Z is a positive integer) can be divided into a plurality of HPB areas (for example, HPB area) HPB_Rgn_0~HPB_Rgn_(N-1), where N is a positive integer greater than 1), and each HPB region can be further divided into multiple HPB subregions (for example, HPB subregion HPB_Sub_Rgn_0~HPB_Sub_Rgn_(L-1), where L Is a positive integer). The size of an HPB sub-region can be less than or equal to the size of an HPB region. To simplify the description, the HPB sub-area is referred to as a sub-area, and the HPB area is referred to as an area in the following.

於本發明之實施例中，有兩種取得HPB項目的模式，包括主機控制模式與裝置控制模式。In the embodiment of the present invention, there are two modes for obtaining HPB items, including host control mode and device control mode.

第3圖為一示意圖，用以顯示於主機控制模式下可有的操作。於主機控制模式下，主機系統(例如，主機裝置130)可確認要被活化(activate)的新的子區域(操作A-1)，並發出一HPB讀取緩衝(HPB READ BUFFER)指令(操作A-2)，以請求要被活化之子區域所對應的HPB項目。響應於HPB讀取緩衝指令之接收，UFS裝置(例如，記憶體控制器110)可自記憶體裝置120讀取L2P映射表格之至少一部分(例如，讀取全域L2P映射表格或區域L2P映射表格)，該部分係對應於選定要被活化之子區域，並且根據L2P映射表格所紀錄之映射資訊提供HPB項目(操作A-3)。UFS裝置接著可透過送入資料(DATA IN)之通用快閃記憶體儲存通訊協定資訊單元(UFS Protocol Information Unit，縮寫為UPIU)封包將HPB項目傳送至主機系統(操作A-4)。主機系統可於系統記憶體內配置一HPB區域(亦可稱為HPB快取區)，用以儲存HPB項目(操作A-5)。Figure 3 is a schematic diagram showing the possible operations in the host control mode. In the host control mode, the host system (for example, the host device 130) can confirm the new sub-area to be activated (operation A-1), and issue an HPB READ BUFFER command (operation A-2) to request the HPB item corresponding to the child area to be activated. In response to receiving the HPB read buffer command, the UFS device (for example, the memory controller 110) can read at least a part of the L2P mapping table from the memory device 120 (for example, read the global L2P mapping table or the area L2P mapping table) , This part corresponds to the selected sub-region to be activated, and the HPB item is provided based on the mapping information recorded in the L2P mapping table (operation A-3). The UFS device can then send the HPB item to the host system through the universal flash memory storage of the data (DATA IN) storage protocol information unit (UFS Protocol Information Unit, abbreviated as UPIU) packet (Operation A-4). The host system can configure an HPB area (also called HPB cache area) in the system memory to store HPB items (operation A-5).

主機系統亦可確認要被去活化(deactivate)的區域(操作B-1)，並發出一HPB寫入緩衝(HPB WRITE BUFFER)指令，以請求將一區域去活化(操作B-2)。UFS裝置可響應於HPB寫入緩衝指令之接收將對應之區域去活化(操作B-3)。The host system can also confirm the area to be deactivated (operation B-1), and issue an HPB write buffer (HPB WRITE BUFFER) command to request an area to be deactivated (operation B-2). The UFS device can deactivate the corresponding area in response to receiving the HPB write buffer command (operation B-3).

此外，當UFS裝置判斷需要更新任何子區域所對應之HPB項目時，例如，當UFS裝置修改了一已活化之子區域所對應之L2P映射資訊 (操作C-1)，UFS裝置可傳送一回應UPIU封包至主機系統，以建議主機系統更新子區域所對應之HPB項目(操作C-2)。響應於回應UPIU封包之接收，主機系統可發出一HPB讀取緩衝指令 (操作C-3)，並將之傳送給UFS裝置以請求已活化之子區域所對應之更新過的HPB項目(操作C-4)。響應於HPB讀取緩衝指令之接收，UFS裝置可讀取L2P映射表格中之對應於已活化之子區域之部分，並且根據L2P映射表格所紀錄之映射資訊提供HPB項目(操作C-5)。同樣地，UFS裝置接著可透過送入資料之通用快閃記憶體儲存通訊協定資訊單元(DATA IN UPIU)封包將HPB項目傳送至主機系統(操作C-6)。主機系統可根據接收到的資訊更新HPB快取區內所儲存之HPB項目(操作C-7)。In addition, when the UFS device determines that the HPB item corresponding to any sub-area needs to be updated, for example, when the UFS device modifies the L2P mapping information corresponding to an activated sub-area (operation C-1), the UFS device can send a response UPIU Packets to the host system to suggest that the host system update the HPB item corresponding to the sub-area (operation C-2). In response to the reception of the UPIU packet, the host system can issue an HPB read buffer command (operation C-3) and send it to the UFS device to request the updated HPB item corresponding to the activated sub-area (operation C- 4). In response to receiving the HPB read buffer command, the UFS device can read the part of the L2P mapping table corresponding to the activated sub-region, and provide HPB items based on the mapping information recorded in the L2P mapping table (operation C-5). Similarly, the UFS device can then send the HPB item to the host system through the universal flash memory storage protocol information unit (DATA IN UPIU) packet that sends the data (operation C-6). The host system can update the HPB items stored in the HPB cache area according to the received information (operation C-7).

第4圖為一示意圖，用以顯示於裝置控制模式下可有的操作。於裝置控制模式下，UFS裝置可確認要被活化的新的子區域及/或要被去活化之區域(操作D-1)，並傳送一回應UPIU封包至主機系統，以建議主機系統活化選定之新的子區域或去活化選定之區域(操作D-2)。對於將選定之區域去活化，主機系統可捨棄不再活化之區域所對應的HPB項目(操作D-3)。對於活化的新的子區域，主機系統可發出一HPB讀取緩衝指令，並將之傳送給UFS裝置以請求要被活化之子區域所對應的HPB項目(操作D-4)。類似地，響應於HPB讀取緩衝指令之接收，UFS裝置可自記憶體裝置120讀取L2P映射表格之至少一部分(例如，讀取全域L2P映射表格或區域L2P映射表格)，該部分係對應於選定要被活化之子區域，並且根據L2P映射表格所紀錄之映射資訊提供HPB項目(操作D-5)。UFS裝置接著可透過送入資料之通用快閃記憶體儲存通訊協定資訊單元(DATA IN UPIU)封包將HPB項目傳送至主機系統(操作D-6)。主機系統可於系統記憶體內配置一HPB區域(亦可稱為HPB快取區)，用以儲存HPB項目(操作D-7)。Figure 4 is a schematic diagram showing the possible operations in the device control mode. In the device control mode, the UFS device can confirm the new sub-area to be activated and/or the area to be deactivated (operation D-1), and send a response UPIU packet to the host system to suggest the host system activation selection The new sub-region or deactivate the selected region (operation D-2). For deactivating the selected area, the host system can discard the HPB item corresponding to the area that is no longer activated (operation D-3). For the activated new sub-area, the host system can issue an HPB read buffer command and send it to the UFS device to request the HPB item corresponding to the sub-area to be activated (operation D-4). Similarly, in response to receiving the HPB read buffer command, the UFS device can read at least a part of the L2P mapping table from the memory device 120 (for example, read the global L2P mapping table or the area L2P mapping table), which part corresponds to Select the sub-area to be activated, and provide the HPB item according to the mapping information recorded in the L2P mapping table (operation D-5). The UFS device can then send the HPB item to the host system through the universal flash memory storage protocol information unit (DATA IN UPIU) packet sent to the data (operation D-6). The host system can configure an HPB area (also called HPB cache area) in the system memory to store HPB items (operation D-7).

第5圖係顯示HPB項目的一個範例格式。於本發明之一實施例中，一個HPB項目的大小為8位元組(Byte)。於此範例格式中，4位元組用以記載自L2P映射表格(例如，全域或區域L2P映射表格，或者由記憶體控制器110載入緩衝記憶體116之暫時的L2P映射表格) 取得的映射資訊(例如，實體位址)，而其餘4位元組用以記載另一實體位址，此實體位址係快閃記憶體內實際用以儲存前述全域或區域L2P映射表格的位址。更具體的說，於第5圖所示之範例格式中，第一個4位元組大小的PBA與第二個4位元組大小的PBA被合併形成一個HPB項目，其中第一個PBA為儲存於表格1(亦稱為T1表格)的實體區塊位址，此實體區塊位址為一邏輯區塊位址所映射之實體區塊位址，而第二個PBA為儲存於表格2(亦稱為T2表格)的實體區塊位址，此實體區塊位址則為T1表格的實體區塊位址。於此，T1表格可以是記憶體裝置120內所儲存的全域或區域L2P映射表格，T2表格可以一個系統表格，用以紀錄各管理表格(例如，全域或區域L2P映射表格) 實際被儲存於記憶體裝置120的實體位址。Figure 5 shows an example format of the HPB project. In an embodiment of the present invention, the size of an HPB item is 8 bytes (Byte). In this example format, 4 bytes are used to record the mapping obtained from the L2P mapping table (for example, the global or regional L2P mapping table, or the temporary L2P mapping table loaded into the buffer memory 116 by the memory controller 110) Information (for example, physical address), and the remaining 4 bytes are used to record another physical address. This physical address is actually used to store the aforementioned global or regional L2P mapping table in the flash memory. More specifically, in the example format shown in Figure 5, the first 4-byte PBA and the second 4-byte PBA are combined to form an HPB project, where the first PBA is The physical block address stored in table 1 (also called T1 table), this physical block address is the physical block address mapped by a logical block address, and the second PBA is stored in table 2 (Also called T2 form) physical block address, this physical block address is the physical block address of T1 form. Here, the T1 table can be a global or regional L2P mapping table stored in the memory device 120, and the T2 table can be a system table for recording that each management table (for example, a global or regional L2P mapping table) is actually stored in the memory The physical address of the body device 120.

由於當一管理表格(例如，全域或區域L2P映射表格)的內容(例如，映射資訊)需被更新時，記憶體控制器110可配置另一個記憶體空間儲存此管理表格更新後的內容，因此，當由一邏輯區塊位址所映射之實體區塊位址改變時，不僅T1表格的內容需要修改，T1表格的更新內容也會被儲存於記憶體裝置120的另一個新的儲存空間。因此，系統表格內所紀錄之T1表格所對應之實體位址也會隨之改變。如此一來，HPB項目內所記載的T2表格的內容便能用於驗證由此HPB項目所對應之一邏輯區塊位址所映射之實體區塊位址所儲存資料是否仍為有效資料。當HPB項目所記載之T2表格內容與記憶體控制器110所維護之最新的T1表格的實體位址相符時，代表儲存於此HPB項目所記載之實體區塊位址(T1表格內容)之資料仍為有效資料。反之，代表儲存於此HPB項目所記載之實體區塊位址之資料已為無效資料。需注意的是，前述一實體區塊位址所儲存之資料是否仍為有效資料的驗證可由資料儲存裝置端的記憶體控制器110執行。When the content (e.g., mapping information) of a management table (e.g., global or regional L2P mapping table) needs to be updated, the memory controller 110 can allocate another memory space to store the updated content of the management table. When the physical block address mapped by a logical block address changes, not only the content of the T1 table needs to be modified, but the updated content of the T1 table will also be stored in another new storage space of the memory device 120. Therefore, the physical address corresponding to the T1 table recorded in the system table will also change accordingly. In this way, the content of the T2 table recorded in the HPB project can be used to verify whether the data stored in the physical block address mapped by a logical block address corresponding to the HPB project is still valid data. When the content of the T2 table recorded in the HPB item matches the physical address of the latest T1 table maintained by the memory controller 110, it represents the data stored in the physical block address (T1 table content) recorded in the HPB item Still valid information. On the contrary, it means that the data stored in the physical block address recorded in this HPB project is invalid data. It should be noted that the verification of whether the data stored in the aforementioned physical block address is still valid data can be performed by the memory controller 110 on the data storage device side.

以下HPB項目表格1為第一個HPB項目表格範例，其中「…」之標記係表示為了簡潔起見而省略一些表格內容。HPB項目表格1中標示的T2表格內容與T1表格內容(例如，十六進制的值)可分別代表自前述T2表格與T1表格取得的內容。T1表格內容欄位中所例示的實體位址{0x0000A000, 0x0000A001, …}可做為由與HPB項目{0, 1…}相關聯之一序列的邏輯位址所映射的實體位址的實例，而反覆出現於T2表格內容欄位所記錄的一序列實體位址{0x00004030, 0x00004030, …}中的實體位址0x00004030則做為T1表格之實體位址的實例，而於此T1表格可以是一區域L2P映射表格。 HPB項目表格1 HPB項目 T2 表格內容 T1表格內容 0 0x00004030 0x0000A000 1 0x00004030 0x0000A001 2 0x00004030 0x0000A002 3 0x00004030 0x0000A003 4 0x00004030 0x0000A004 5 0x00004030 0x0000A005 6 0x00004030 0x0000B009 7 0x00004030 0x0000A007 8 0x00004030 0x0000A008 9 0x00004030 0x0000A009 10 0x00004030 0x0000A00A 11 0x00004030 0x0000B00A 12 0x00004030 0x0000A00C … … … The following HPB project table 1 is an example of the first HPB project table. The mark "..." indicates that some table contents are omitted for the sake of brevity. The content of the T2 table and the content of the T1 table (for example, a hexadecimal value) marked in the HPB item table 1 can represent the content obtained from the aforementioned T2 table and the T1 table, respectively. The physical address {0x0000A000, 0x0000A001, …} illustrated in the content field of the T1 table can be used as an example of a physical address mapped by a sequence of logical addresses associated with HPB items {0, 1…}, The physical address 0x00004030 in a sequence of physical addresses {0x00004030, 0x00004030, …} recorded in the content field of the T2 form repeatedly is used as an example of the physical address of the T1 form, and here the T1 form can be a Regional L2P mapping table. HPB Project Form 1 HPB project T2 form content T1 form content 0 0x00004030 0x0000A000 1 0x00004030 0x0000A001 2 0x00004030 0x0000A002 3 0x00004030 0x0000A003 4 0x00004030 0x0000A004 5 0x00004030 0x0000A005 6 0x00004030 0x0000B009 7 0x00004030 0x0000A007 8 0x00004030 0x0000A008 9 0x00004030 0x0000A009 10 0x00004030 0x0000A00A 11 0x00004030 0x0000B00A 12 0x00004030 0x0000A00C … … …

第6圖係顯示HPB項目的另一個範例格式。於此範例格式中，28位元用於承載自L2P映射表格(例如，全域或區域L2P映射表格，或者由記憶體控制器110載入緩衝記憶體116之暫時的L2P映射表格)取得的映射資訊，24位元用於承載全域或區域L2P映射表格實際被儲存於快閃記憶體內哪個的實體位址的資訊，而剩餘的12位元則用於承載相關聯的LBA的連續性資訊。更具體的說，於第6圖所示之範例格式中，第一個PBA、第二個PBA與一LBA的連續性資訊可被合併形成一個HPB項目，其中第一個PBA為儲存於T1表格的實體區塊位址，此實體區塊位址為前述LBA所映射之實體區塊位址，第二個PBA為儲存於T2表格的實體區塊位址，此實體區塊位址則為T1表格的實體區塊位址。於本發明之實施例中，連續性資訊可由能指示出連續長度的一個數值或者一個連續位元表格來表示。Figure 6 shows another example format of the HPB project. In this example format, 28 bits are used to carry the mapping information obtained from the L2P mapping table (for example, the global or regional L2P mapping table, or the temporary L2P mapping table loaded into the buffer memory 116 by the memory controller 110) , 24 bits are used to carry the information of the physical address of the global or regional L2P mapping table actually stored in the flash memory, and the remaining 12 bits are used to carry the continuity information of the associated LBA. More specifically, in the example format shown in Figure 6, the continuity information of the first PBA, the second PBA, and an LBA can be combined to form an HPB item, where the first PBA is stored in the T1 table The physical block address is the physical block address mapped by the aforementioned LBA, the second PBA is the physical block address stored in the T2 table, and the physical block address is T1 The physical block address of the table. In the embodiment of the present invention, the continuity information can be represented by a numerical value or a continuous bit table that can indicate the length of the continuation.

以下HPB項目表格2為第二個HPB項目表格範例，其中「…」之標記係表示為了簡潔起見而省略一些表格內容。T1表格內容欄位中所例示的實體位址{0x000A000, 0x000A001, …, 0x000A005, 0x000B009, 0x000A007, …, 0x000A00A, 0x000B00A, 0x000A00C, …}可做為由與HPB項目{0, 1…}相關聯之一序列的邏輯位址所映射的實體位址的實例，反覆出現於T2表格內容欄位所記錄的一序列實體位址{0x00004030, 0x00004030, …}中的實體位址0x00004030則做為T1表格之實體位址的實例，而於此T1表格可以是一區域L2P映射表格。 HPB項目表格2 HPB項目 連續長度 T2 表格內容 T1表格內容 0 0x5 0x004030 0x000A000 1 0x4 0x004030 0x000A001 2 0x3 0x004030 0x000A002 3 0x2 0x004030 0x000A003 4 0x1 0x004030 0x000A004 5 0x0 0x004030 0x000A005 6 0x0 0x004030 0x000B009 7 0x3 0x004030 0x000A007 8 0x2 0x004030 0x000A008 9 0x1 0x004030 0x000A009 10 0x0 0x004030 0x000A00A 11 0x0 0x004030 0x000B00A 12 … 0x004030 0x000A00C … … … … The following HPB project form 2 is an example of the second HPB project form, in which the mark "..." indicates that some form contents are omitted for the sake of brevity. The physical address {0x000A000, 0x000A001, …, 0x000A005, 0x000B009, 0x000A007, …, 0x000A00A, 0x000B00A, 0x000A00C, …} illustrated in the content field of the T1 table can be associated with HPB items {0, 1…} An example of a physical address mapped by a sequence of logical addresses, which repeatedly appears in a sequence of physical addresses {0x00004030, 0x00004030, …} recorded in the content field of the T2 table. The physical address 0x00004030 is used as the T1 table An example of the physical address of, and here the T1 table can be a regional L2P mapping table. HPB Project Form 2 HPB project Continuous length T2 form content T1 form content 0 0x5 0x004030 0x000A000 1 0x4 0x004030 0x000A001 2 0x3 0x004030 0x000A002 3 0x2 0x004030 0x000A003 4 0x1 0x004030 0x000A004 5 0x0 0x004030 0x000A005 6 0x0 0x004030 0x000B009 7 0x3 0x004030 0x000A007 8 0x2 0x004030 0x000A008 9 0x1 0x004030 0x000A009 10 0x0 0x004030 0x000A00A 11 0x0 0x004030 0x000B00A 12 … 0x004030 0x000A00C … … … …

此外，記憶體控制器110可分別計算並產生(例如，紀錄及/或更新)在HPB項目表格所相關聯的多個實體位址中，接續在一個HPB項目所對應之實體位址之後的連續實體位址數量，並以此作為前述連續長度。舉例而言，對於HPB項目0，記憶體控制器110可計算並產生(例如，紀錄及/或更新)在實體位址{0x000A000, 0x000A001, …, 0x000A005, 0x000B009, 0x000A007, …, 0x000A00A, 0x000B00A, 0x000A00C, …}中，接續在實體位址0x000A000之後的連續實體位址(例如，實體位址{0x000A001, …, 0x000A005})的數量，作為HPB項目0所對應的連續長度(例如，於此範例為0x5)。對於HPB項目1，記憶體控制器110可計算並產生(例如，紀錄及/或更新)在實體位址{0x000A000, 0x000A001, …, 0x000A005, 0x000B009, 0x000A007, …, 0x000A00A, 0x000B00A, 0x000A00C, …}中，接續在實體位址0x000A001之後的連續實體位址{0x000A002, …, 0x000A005}的數量，作為HPB項目1所對應的連續長度(例如，於此範例為0x4)。其餘項目則以此類推。In addition, the memory controller 110 can separately calculate and generate (for example, record and/or update) the multiple physical addresses associated with the HPB item table, which are successively after the physical address corresponding to one HPB item The number of physical addresses, and use this as the aforementioned continuous length. For example, for HPB item 0, the memory controller 110 can calculate and generate (for example, record and/or update) the physical address {0x000A000, 0x000A001, …, 0x000A005, 0x000B009, 0x000A007, …, 0x000A00A, 0x000B00A, 0x000A00C, …}, the number of consecutive physical addresses following the physical address 0x000A000 (for example, physical address {0x000A001, …, 0x000A005}) is used as the continuous length corresponding to HPB item 0 (for example, in this example Is 0x5). For HPB item 1, the memory controller 110 can calculate and generate (for example, record and/or update) the physical address {0x000A000, 0x000A001, …, 0x000A005, 0x000B009, 0x000A007, …, 0x000A00A, 0x000B00A, 0x000A00C, …} , The number of consecutive physical addresses {0x000A002, …, 0x000A005} following the physical address 0x000A001 is taken as the continuous length corresponding to HPB item 1 (for example, 0x4 in this example). The rest of the projects follow this analogy.

以下HPB項目表格3為第三個HPB項目表格範例，其中「…」之標記係表示為了簡潔起見而省略一些表格內容。T1表格內容欄位中所例示的實體位址{0x000A000, 0x000A001, …, 0x000A005, 0x000B009, 0x000A007, …, 0x000A00A, 0x000B00A, 0x000A00C, …}可做為由與HPB項目{0, 1…}相關聯之一序列的邏輯位址所映射的實體位址的實例，反覆出現於T2表格內容欄位所記錄的一序列實體位址{0x00004030, 0x00004030, …}中的實體位址0x00004030則做為T1表格之實體位址的實例，而於此T1表格可以是一區域L2P映射表格。 HPB項目表格3 HPB項目 連續位元表格 T2 表格內容 T1表格內容 0 0xBDF (101111011111) 0x004030 0x000A000 1 0xDEF (110111101111) 0x004030 0x000A001 2 0xEF7 (111011110111) 0x004030 0x000A002 3 0xF7B (111101111011) 0x004030 0x000A003 4 … 0x004030 0x000A004 5 … 0x004030 0x000A005 6 … 0x004030 0x000B009 7 … 0x004030 0x000A007 8 … 0x004030 0x000A008 9 … 0x004030 0x000A009 10 … 0x004030 0x000A00A 11 … 0x004030 0x000B00A 12 … 0x004030 0x000A00C 13 … 0x004030 0x000A00D 14 … 0x004030 0x000A00E 15 … 0x004030 0x000A00F … … … … The following HPB project table 3 is an example of the third HPB project table. The mark "..." indicates that some table contents are omitted for the sake of brevity. The physical address {0x000A000, 0x000A001, …, 0x000A005, 0x000B009 , 0x000A007, …, 0x000A00A, 0x000B00A , 0x000A00C, …} illustrated in the content field of the T1 form can be associated with HPB items {0, 1…} An example of a physical address mapped by a sequence of logical addresses, which repeatedly appears in a sequence of physical addresses {0x00004030, 0x00004030, …} recorded in the content field of the T2 table. The physical address 0x00004030 is used as the T1 table An example of the physical address of, and here the T1 table can be a regional L2P mapping table. HPB Project Form 3 HPB project Continuous bit table T2 form content T1 form content 0 0xBDF (101111011111) 0x004030 0x000A000 1 0xDEF (110111101111) 0x004030 0x000A001 2 0xEF7 (111011110111) 0x004030 0x000A002 3 0xF7B (111101111011) 0x004030 0x000A003 4 … 0x004030 0x000A004 5 … 0x004030 0x000A005 6 … 0x004030 0x000B009 7 … 0x004030 0x000A007 8 … 0x004030 0x000A008 9 … 0x004030 0x000A009 10 … 0x004030 0x000A00A 11 … 0x004030 0x000B00A 12 … 0x004030 0x000A00C 13 … 0x004030 0x000A00D 14 … 0x004030 0x000A00E 15 … 0x004030 0x000A00F … … … …

此外，記憶體控制器110可分別確認在HPB項目表格所相關聯的多個實體位址中，接續在一個HPB項目所對應之實體位址之後的多個實體位址的連續性，以產生可指示出後續多個實體位址的連續性的連續位元表格。舉例而言，對於HPB項目0，記憶體控制器110可分別確認在實體位址{0x000A000, 0x000A001, …, 0x000A005, 0x000B009, 0x000A007, …, 0x000A00A, 0x000B00A, 0x000A00C, 0x000A00D, 0x000A00E, 0x000A00F, …}中，接續在實體位址0x000A000之後的12個實體位址(例如，實體位址{0x000A001, …, 0x000A005, 0x000B009, 0x000A007, …, 0x000A00A, 0x000B00A, 0x000A00C})的連續性，以產生連續位元表格0xBDF，其可指示出後續12個實體位址{0x000A001, …, 0x000A005, 0x000B009, 0x000A007, …, 0x000A00A, 0x000B00A, 0x000A00C}的連續性，連續位元表格以位元展開表示則可為，例如，從最低有效位元(Least Significant Bit，縮寫LSB)開始到最高有效位元(Most Significant Bit，縮寫MSB)的101111011111，其中的第0-11個位元(例如，從LSB開始的12個位元)可分別指示出後續的12個實體位址{0x000A001, …, 0x000A005, 0x000B009, 0x000A007, …, 0x000A00A, 0x000B00A, 0x000A00C}的連續性。對於HPB項目1，記憶體控制器110可分別確認在實體位址{0x000A000, 0x000A001, …, 0x000A005, 0x000B009, 0x000A007, …, 0x000A00A, 0x000B00A, 0x000A00C, 0x000A00D, 0x000A00E, 0x000A00F, …}中，接續在實體位址0x000A001之後的12個實體位址{0x000A002, …, 0x000A005, 0x000B009, 0x000A007, …, 0x000A00A, 0x000B00A, 0x000A00C, 0x000A00D}的連續性，以產生連續位元表格0xDEF，其可指示出後續12個實體位址{0x000A002, …, 0x000A005, 0x000B009, 0x000A007, …, 0x000A00A, 0x000B00A, 0x000A00C, 0x000A00D}的連續性，連續位元表格以位元展開表示則可為，例如，從LSB開始到MSB的110111101111，其中的第0-11個位元(例如，從LSB開始的12個位元) 可分別指示出後續的12個實體位址{0x000A002, …, 0x000A005, 0x000B009, 0x000A007, …, 0x000A00A, 0x000B00A, 0x000A00C, 0x000A00D}的連續性。其餘項目則以此類推。 In addition, the memory controller 110 can respectively confirm the continuity of the multiple physical addresses following the physical address corresponding to one HPB entry among the multiple physical addresses associated with the HPB entry table, so as to generate the continuity A continuous bit table indicating the continuity of multiple subsequent physical addresses. For example, for HPB item 0, the memory controller 110 can be respectively confirmed at the physical address {0x000A000, 0x000A001, …, 0x000A005, 0x000B009 , 0x000A007, …, 0x000A00A, 0x000B00A , 0x000A00C, 0x000A00D, 0x000A00E, 0x000A00E, 0x000A00E, 0x000A00D In, the continuity of the 12 physical addresses following the physical address 0x000A000 (for example, the physical address {0x000A001, …, 0x000A005, 0x000B009 , 0x000A007, …, 0x000A00A, 0x000B00A , 0x000A00C}) to generate continuous bits Table 0xBDF, which can indicate the continuity of the subsequent 12 physical addresses {0x000A001, …, 0x000A005, 0x000B009 , 0x000A007, …, 0x000A00A, 0x000B00A , 0x000A00C}, the continuous bit table can be expressed in bit expansion, for example , Starting from the least significant bit (Least Significant Bit, abbreviated LSB) to 101111011111 of the most significant bit (Most Significant Bit, abbreviated MSB), where the 0-11th bit (for example, 12 bits starting from LSB) Yuan) can respectively indicate the continuity of the subsequent 12 physical addresses {0x000A001, …, 0x000A005, 0x000B009 , 0x000A007, …, 0x000A00A, 0x000B00A , 0x000A00C}. For HPB project 1, the memory controller 110 can be confirmed in the physical address {0x000A000, 0x000A001, …, 0x000A005, 0x000B009 , 0x000A007, …, 0x000A00A, 0x000B00A , 0x000A00C, 0x000A00D, 0x000A00C, 0x000A00D, 0x000A00E, 0x000A00D, 0x000A00E, continue in… The continuity of the 12 physical addresses {0x000A002, …, 0x000A005, 0x000B009 , 0x000A007, …, 0x000A00A, 0x000B00A , 0x000A00C, 0x000A00D} after the physical address 0x000A001 can indicate the subsequent continuous bit table 0xDEF, which can indicate The continuity of physical addresses {0x000A002, …, 0x000A005, 0x000B009 , 0x000A007, …, 0x000A00A, 0x000B00A , 0x000A00C, 0x000A00D}, the continuous bit table can be expressed in bit expansion, for example, from LSB to MSB 110111101111, where the 0-11th bits (for example, 12 bits starting from LSB) can respectively indicate the subsequent 12 physical addresses {0x000A002, …, 0x000A005, 0x000B009 , 0x000A007, …, 0x000A00A, 0x000B00A , 0x000A00C, 0x000A00D} continuity. The rest of the projects follow this analogy.

借助HPB項目所提供的資訊，主機裝置130可發出前述HPB讀取指令，此HPB讀取指令可承載主機裝置130試圖讀取的起始邏輯地址、傳輸長度(TRANSFER LENGTH)、以及HPB項目所記載的內容等相關資訊，用以讀取資料。第7圖為一示意圖，用以顯示HPB讀取指令的對應操作。主機系統可自HPB快取區取得所需之HPB項目資訊，並且傳送一HPB讀取指令給UFS裝置(操作E-1)，此HPB讀取指令帶有一邏輯區塊位址LBA(例如，起始LBA)、此LBA所對應之HPB項目內容以及傳輸長度，並透過HPB讀取指令UPIU封包傳送(操作E-2)。於一特定實施例中，傳輸長度可被限定為1，但本發明並不限於此。於本發明之其他實施例中，傳輸長度可被設定為任意正整數。例如，於HPB 2.0標準中，傳輸長度可被設定為大於1的正整數。於接收到HPB讀取指令時，UFS裝置可解碼此對應於主機系統試圖讀取的一個選定的LBA的HPB項目，以取得此選定的LBA所對應的實體位址或PBA的相關資訊，並且根據此實體位址或PBA的相關資訊存取記憶體裝置，以取得主機系統試圖讀取的資料(操作E-3)。UFS裝置可於操作E-3中判斷接收到的HPB項目是否仍為有效。例如，透過前述判斷HPB項目所記載之T2表格內容與記憶體控制器110所維護之最新的T1表格的實體位址是否相符判斷HPB項目是否仍為有效。若HPB項目的內容為有效的，UFS裝置可取得主機裝置130試圖讀取的資料(即，圖中所示之「邏輯區塊資料」)，並傳送一或多個送入資料之通用快閃記憶體儲存通訊協定資訊單元(DATA IN UPIU)封包至主機系統，以傳送此資料(操作E-4)給主機系統，並且於資料傳輸完成後傳送回應UPIU封包(操作E-5)至主機系統，其中所述「邏輯區塊資料」係指主機裝置130所選定欲讀取的邏輯位址LBA所對應的資料。另一方面，若判斷接收到的HPB項目為無效的，則UFS裝置可略過操作E-4，直接執行操作E-5，藉由傳送一回應UPIU封包至主機系統，以建議主機系統更新對應的HPB項目。With the help of the information provided by the HPB item, the host device 130 can issue the aforementioned HPB read command, which can carry the starting logical address, the transfer length (TRANSFER LENGTH), and the HPB item record that the host device 130 is trying to read The content and other related information for reading data. Figure 7 is a schematic diagram showing the corresponding operation of the HPB read command. The host system can obtain the required HPB item information from the HPB cache, and send an HPB read command to the UFS device (operation E-1). The HPB read command carries a logical block address LBA (for example, from Start LBA), the HPB item content and transmission length corresponding to this LBA, and send it through the HPB read command UPIU packet (operation E-2). In a specific embodiment, the transmission length can be limited to 1, but the invention is not limited to this. In other embodiments of the present invention, the transmission length can be set to any positive integer. For example, in the HPB 2.0 standard, the transmission length can be set to a positive integer greater than 1. Upon receiving the HPB read command, the UFS device can decode the HPB item corresponding to a selected LBA that the host system is trying to read to obtain the physical address or PBA related information corresponding to the selected LBA, and according to The physical address or PBA related information accesses the memory device to obtain the data that the host system is trying to read (operation E-3). The UFS device can determine whether the received HPB item is still valid in operation E-3. For example, by judging whether the content of the T2 table recorded in the HPB item matches the physical address of the latest T1 table maintained by the memory controller 110 to determine whether the HPB item is still valid. If the content of the HPB item is valid, the UFS device can obtain the data that the host device 130 is trying to read (ie, the "logical block data" shown in the figure), and send one or more general flashes of the input data The memory stores the DATA IN UPIU packet to the host system to send the data (operation E-4) to the host system, and send the response UPIU packet (operation E-5) to the host system after the data transmission is completed , Wherein the "logical block data" refers to the data corresponding to the logical address LBA selected by the host device 130 to be read. On the other hand, if the received HPB item is judged to be invalid, the UFS device can skip operation E-4 and directly execute operation E-5, by sending a response UPIU packet to the host system to suggest that the host system update the corresponding HPB project.

需注意的是，於本發明之一些實施例中，UFS裝置端可主動地建議主機系統更新HPB項目，例如，於前述操作C-2或操作D-2中UFS裝置端藉由傳送一回應UPIU封包主動地建議主機系統更新HPB項目或建議主機系統活化新的子區域。而於本發明之另一些實施例中，UFS裝置端也可不主動地建議主機系統更新HPB項目。於該些實施例中，UFS裝置端可改為在判斷HPB項目為無效的之後，再藉由傳送一回應UPIU封包至主機系統，以建議主機系統更新對應的HPB項目。例如，UFS裝置於接收到HPB讀取指令後，若於前述操作E-3中判斷HPB項目為無效的，透過回應UPIU封包建議主機系統更新對應的HPB項目。It should be noted that in some embodiments of the present invention, the UFS device side can actively suggest that the host system update the HPB item, for example, in the aforementioned operation C-2 or operation D-2, the UFS device side sends a response UPIU The packet actively suggests that the host system update the HPB project or suggest that the host system activate a new sub-area. In other embodiments of the present invention, the UFS device side may not actively suggest that the host system update the HPB item. In these embodiments, the UFS device may instead send a response UPIU packet to the host system after determining that the HPB item is invalid, so as to suggest that the host system update the corresponding HPB item. For example, after the UFS device receives the HPB read command, if it determines that the HPB item is invalid in the aforementioned operation E-3, it advises the host system to update the corresponding HPB item by responding to the UPIU packet.

由於傳輸長度可被設定為大於1的正整數，即，主機裝置130可試圖利用HPB項目的資訊快速讀取的一個以上LBA的資料，因此，如何改善連續邏輯位址的資料實際被儲存於記憶體裝置120的連續性成為一個值得關注的議題。Since the transmission length can be set to a positive integer greater than 1, that is, the host device 130 can try to use the HPB item information to quickly read more than one LBA data, therefore, how to improve the continuous logical address data actually stored in the memory The continuity of the body device 120 has become an issue worthy of attention.

於本發明之實施例中，記憶體控制器110可記錄及/或分析主機裝置130的存取行為、根據紀錄的主機裝置130的存取行為選擇一或多個要進行資料重整或資料重排的子區域，並且主動地執行一資料重整或資料重排程序，用以將被選擇的該至少一個子區域的資料搬移至記憶體裝置120中具有連續實體位址的一記憶空間(例如，一記憶體區塊)。In the embodiment of the present invention, the memory controller 110 can record and/or analyze the access behavior of the host device 130, and select one or more data reorganization or data reconfiguration based on the recorded access behavior of the host device 130. Row sub-regions, and actively perform a data rearrangement or data rearrangement process to move the data of the selected at least one sub-region to a memory space with consecutive physical addresses in the memory device 120 (for example, , A memory block).

根據本發明之第一實施例，記憶體控制器110可建立一活化次數表格(例如，子區域活化次數表格)，並且響應於由主機裝置130發出的指令維護或更新活化次數表格的內容。活化次數表格可包括複數欄位，各欄位用以記錄相關聯之一子區域(例如，前述之HPB子區域)所對應之一活化次數。因此，活化次數表格所包含的欄位總數可等於記憶裝置120所包含的HPB子區域總數。如上所述，記憶體裝置120可被劃分為多個分區，各分區可被視為一個邏輯單元，且各邏輯單元可對應於複數邏輯區塊位址。各邏輯單元所對應的邏輯區塊位址可被劃分為複數個HPB區域，並且各HPB區域可進一步被劃分為複數HPB子區域。因此，於本發明之實施例中，各邏輯單元可包括複數區域，並且各區域包括複數子區域。According to the first embodiment of the present invention, the memory controller 110 can create an activation frequency table (for example, a sub-region activation frequency table), and maintain or update the content of the activation frequency table in response to an instruction issued by the host device 130. The activation times table may include a plurality of fields, and each field is used to record an activation times corresponding to an associated sub-region (for example, the aforementioned HPB sub-region). Therefore, the total number of fields included in the activation count table can be equal to the total number of HPB sub-areas included in the memory device 120. As described above, the memory device 120 can be divided into multiple partitions, each partition can be regarded as a logical unit, and each logical unit can correspond to a plurality of logical block addresses. The logical block address corresponding to each logical unit can be divided into a plurality of HPB areas, and each HPB area can be further divided into a plurality of HPB sub-areas. Therefore, in the embodiment of the present invention, each logic unit may include a plurality of regions, and each region includes a plurality of sub-regions.

於本發明之第一實施例中，一子區域所對應的活化次數係用以紀錄該子區域被主機裝置130活化的次數。例如，活化次數可為一計數值，用以計算對應之子區域請求被活化的次數。根據本發明之一實施例，記憶體控制器110可響應於由主機裝置130發出的HPB讀取緩衝(HPB READ BUFFER)指令更新活化次數表格的內容。如上所述，主機系統(例如，主機裝置130)可確認要被活化的新的子區域，並發出一HPB讀取緩衝指令，以請求要被活化之子區域所對應的HPB項目。因此，一或多個要被活化的子區域會被主機裝置130標識於HPB讀取緩衝指令，或其相關資訊會被承載於HPB讀取緩衝指令中。響應於HPB讀取緩衝指令之接收，記憶體控制器110可藉由增加HPB讀取緩衝指令中標識出的一或多個要被活化的子區域所對應的一或多個活化次數更新活化次數表格的內容(例如，為每次的活化加1)。In the first embodiment of the present invention, the number of activations corresponding to a sub-region is used to record the number of activations of the sub-region by the host device 130. For example, the number of activations can be a count value used to calculate the number of times the corresponding sub-region is requested to be activated. According to an embodiment of the present invention, the memory controller 110 can update the content of the activation count table in response to the HPB READ BUFFER command issued by the host device 130. As described above, the host system (for example, the host device 130) can confirm the new sub-region to be activated and issue an HPB read buffer command to request the HPB item corresponding to the sub-region to be activated. Therefore, one or more sub-regions to be activated will be identified by the host device 130 in the HPB read buffer command, or their related information will be carried in the HPB read buffer command. In response to receiving the HPB read buffer command, the memory controller 110 can update the number of activations by increasing one or more activation times corresponding to the one or more sub-regions to be activated identified in the HPB read buffer command The content of the table (for example, add 1 to each activation).

根據本發明之一實施例，記憶體控制器110可更將活化次數表格中記錄的活化次數排序，並且根據排序過的活化次數選擇一或多個要進行資料重排的子區域。例如，記憶體控制器110可選擇一或多個活化次數高於一既定值的子區域作為要進行資料重排的子區域。於一實施例中，記憶體控制器110可依序根據排序過的活化次數選擇出目前活化次數最多的子區域，並且對所選的子區域執行對應的資料重排程序，接著將已被資料重排過的子區域所對應的活化次數自排序過的活化次數中移除。於需要時，前述的選擇與資料重排程序可反覆地對不同子區域執行。According to an embodiment of the present invention, the memory controller 110 may further sort the activation times recorded in the activation times table, and select one or more sub-regions for data rearrangement according to the sorted activation times. For example, the memory controller 110 may select one or more sub-regions whose activation times are higher than a predetermined value as the sub-regions to perform data rearrangement. In one embodiment, the memory controller 110 may sequentially select the sub-regions with the most current activation times according to the sorted activation times, and perform the corresponding data rearrangement process on the selected sub-regions, and then store the data that has been The activation times corresponding to the rearranged subregions are removed from the sorted activation times. When necessary, the aforementioned selection and data rearrangement procedures can be repeatedly executed for different sub-regions.

第8圖係顯示根據本發明之第一實施例所述之資料處理方法流程圖。本發明之資料處理方法適用於一資料儲存裝置，可由記憶體控制器110執行並包括以下步驟：Fig. 8 shows a flowchart of the data processing method according to the first embodiment of the present invention. The data processing method of the present invention is suitable for a data storage device, can be executed by the memory controller 110 and includes the following steps:

S802: 建立一活化次數表格，並且響應於由一主機裝置發出之一指令更新活化次數表格的內容。於本發明之實施例中，主機裝置會在指令中指出一或多個要被活化的子區域。S802: Create an activation frequency table, and update the content of the activation frequency table in response to a command issued by a host device. In the embodiment of the present invention, the host device will indicate one or more sub-areas to be activated in the command.

S804: 根據活化次數表格的內容選擇至少一個子區域。S804: Select at least one sub-region according to the content of the activation count table.

S806: 執行一資料重排程序，用以將被選擇的至少一個子區域的資料搬移(或者重新寫入)至記憶體裝置中具有連續實體位址的一記憶空間。S806: Perform a data rearrangement procedure to move (or rewrite) the data of the selected at least one sub-region to a memory space with continuous physical addresses in the memory device.

需注意的是，第一實施例所述之資料處理方法可被應用於主機控制模式或裝置控制模式。It should be noted that the data processing method described in the first embodiment can be applied to the host control mode or the device control mode.

根據本發明之第二實施例，記憶體裝置110可建立一讀取次數表格(例如，子區域讀取次數表格)，並且響應於由主機裝置130發出的讀取指令維護或更新讀取次數表格的內容，所述讀取指令帶有至少一個選定的邏輯位址。讀取次數表格可包括複數欄位，各欄位用以記錄相關聯之一子區域(例如，前述之HPB子區域)所對應之一讀取次數。因此，讀取次數表格所包含的欄位總數可等於記憶裝置120所包含的HPB子區域總數。如上所述，記憶體裝置120可被劃分為多個分區，各分區可被視為一個邏輯單元，且各邏輯單元可對應於複數邏輯區塊位址。各邏輯單元所對應的邏輯區塊位址可被劃分為複數個HPB區域，並且各HPB區域可進一步被劃分為複數HPB子區域。因此，於本發明之實施例中，各邏輯單元可包括複數區域，並且各區域包括複數子區域。According to the second embodiment of the present invention, the memory device 110 can create a read count table (for example, a sub-area read count table), and maintain or update the read count table in response to a read command issued by the host device 130 The read instruction has at least one selected logical address. The read count table may include a plurality of fields, and each field is used to record a read count corresponding to an associated sub-area (for example, the aforementioned HPB sub-area). Therefore, the total number of columns included in the read count table can be equal to the total number of HPB sub-areas included in the memory device 120. As described above, the memory device 120 can be divided into multiple partitions, each partition can be regarded as a logical unit, and each logical unit can correspond to a plurality of logical block addresses. The logical block address corresponding to each logical unit can be divided into a plurality of HPB areas, and each HPB area can be further divided into a plurality of HPB sub-areas. Therefore, in the embodiment of the present invention, each logic unit may include a plurality of regions, and each region includes a plurality of sub-regions.

於本發明之第二實施例中，一子區域所對應的讀取次數係用以紀錄該子區域被主機裝置130讀取的次數。例如，讀取次數可為一計數值，用以計算主機裝置130發出指令讀取對應之子區域所包含的邏輯位址的資料的次數。根據本發明之一實施例，記憶體控制器110可響應於由主機裝置130發出的一般讀取指令更新讀取次數表格的內容。響應於帶有一起始邏輯區塊位址與一欲讀取之資料長度(以下稱為讀取長度)的一讀取指令之接收，記憶體控制器110可藉由增加選定的邏輯位址(例如，起始邏輯區塊位址及根據起始邏輯區塊位址與讀取長度推算出來後續的邏輯區塊位址)所屬之一或多個子區域所對應之一或多個讀取次數更新讀取次數表格的內容(例如，為每次的讀取加1)。根據本發明之另一實施例，記憶體控制器110可響應於由主機裝置130所發出帶有讀取長度大於一既定讀取長度臨界值以選定一個以上要讀取的邏輯位址的讀取指令更新讀取次數表格的內容。例如，記憶體控制器110可藉由增加選定的邏輯位址(例如，起始邏輯區塊位址及根據起始邏輯區塊位址與讀取長度推算出來後續的邏輯區塊位址)所屬之一或多個子區域所對應之一或多個讀取次數更新讀取次數表格的內容(例如，為每次的讀取加1)。In the second embodiment of the present invention, the number of read times corresponding to a sub-area is used to record the number of times the sub-area is read by the host device 130. For example, the number of reads may be a count value used to count the number of times the host device 130 sends an instruction to read the data of the logical address contained in the corresponding sub-area. According to an embodiment of the present invention, the memory controller 110 can update the content of the read count table in response to a general read command issued by the host device 130. In response to receiving a read command with a starting logical block address and a data length to be read (hereinafter referred to as read length), the memory controller 110 can increase the selected logical address ( For example, the starting logical block address and the subsequent logical block address calculated based on the starting logical block address and the read length) belong to one or more sub-regions corresponding to one or more read times update The content of the read count table (for example, add 1 to each read). According to another embodiment of the present invention, the memory controller 110 can select more than one logical address to be read in response to a read sent by the host device 130 with a read length greater than a predetermined read length threshold. Command to update the content of the read count table. For example, the memory controller 110 can be assigned by adding a selected logical address (for example, the starting logical block address and the subsequent logical block address calculated based on the starting logical block address and the read length) One or more reading times corresponding to one or more sub-regions update the content of the reading times table (for example, add 1 to each reading).

根據本發明之一實施例，記憶體控制器110可更將讀取次數表格中記錄的讀取次數排序，並且根據排序過的讀取次數選擇一或多個要進行資料重排的子區域。例如，記憶體控制器110可選擇一或多個讀取次數高於一既定值的子區域作為要進行資料重排的子區域。於一實施例中，記憶體控制器110可依序根據排序過的讀取次數選擇出目前讀取次數最多的子區域，並且對所選的子區域執行對應的資料重排程序，接著將已被資料重排過的子區域所對應的讀取次數自排序過的讀取次數中移除。於需要時，前述的選擇與資料重排程序可反覆地對不同子區域執行。According to an embodiment of the present invention, the memory controller 110 may further sort the read counts recorded in the read count table, and select one or more sub-regions for data rearrangement according to the sorted read counts. For example, the memory controller 110 may select one or more sub-regions whose read times are higher than a predetermined value as the sub-regions to perform data rearrangement. In one embodiment, the memory controller 110 may sequentially select the sub-region with the most current read times according to the sorted read times, and execute the corresponding data rearrangement process on the selected sub-region, and then reset the The read times corresponding to the sub-regions that have been rearranged by the data are removed from the sorted read times. When necessary, the aforementioned selection and data rearrangement procedures can be repeatedly executed for different sub-regions.

根據本發明之另一實施例，記憶體控制器110可根據讀取次數表格所記錄之讀取次數計算一平均讀取次數，並且根據平均讀取次數選擇至少一個子區域。例如，記憶體控制器110可選擇一或多個讀取次數高於平均讀取次數的子區域作為要進行資料重排的子區域。According to another embodiment of the present invention, the memory controller 110 can calculate an average read count according to the read count recorded in the read count table, and select at least one sub-area according to the average read count. For example, the memory controller 110 may select one or more sub-regions whose read times are higher than the average read times as the sub-regions to perform data rearrangement.

第9圖係顯示根據本發明之第二實施例所述之資料處理方法流程圖。本發明之資料處理方法適用於一資料儲存裝置，可由記憶體控制器110執行並包括以下步驟：Figure 9 is a flow chart of the data processing method according to the second embodiment of the present invention. The data processing method of the present invention is suitable for a data storage device, can be executed by the memory controller 110 and includes the following steps:

步驟S902: 建立一讀取次數表格，並且響應於由一主機裝置發出之一讀取指令更新讀取次數表格的內容。於本發明之實施例中，讀取指令帶有至少一個選定的邏輯位址。Step S902: Create a read count table, and update the content of the read count table in response to a read command issued by a host device. In the embodiment of the present invention, the read command carries at least one selected logical address.

步驟S904: 根據讀取次數表格的內容選擇至少一個子區域。Step S904: Select at least one sub-region according to the content of the read count table.

步驟S906: 執行一資料重排程序，用以將屬於被選擇的至少一個子區域的邏輯位址的資料(即，被選擇的至少一個子區域的資料)搬移(或者重新寫入)至記憶體裝置中具有連續實體位址的記憶空間。Step S906: Perform a data rearrangement process to move (or rewrite) the data belonging to the logical address of the selected at least one sub-area (that is, the data of the selected at least one sub-area) to the memory The device has a memory space with consecutive physical addresses.

需注意的是，第二實施例所述之資料處理方法可被應用於主機控制模式或裝置控制模式。It should be noted that the data processing method described in the second embodiment can be applied to the host control mode or the device control mode.

根據本發明之第三實施例，記憶體裝置110可建立另一讀取次數表格(例如，子區域HPB讀取次數表格)(為了與本發明之第二實施例所述之讀取次數表格有所區隔，以下稱之為HPB讀取次數表格)，並且響應於由主機裝置130發出的帶有大於1的傳輸長度的HPB讀取指令維護或更新HPB讀取次數表格的內容，其中主機裝置130藉由帶有大於1的傳輸長度的HPB讀取指令選定一個以上要被讀取的邏輯位址。HPB讀取次數表格可包括複數欄位，各欄位用以記錄相關聯之一子區域(例如，前述之HPB子區域)所對應之一HPB讀取次數。因此，HPB讀取次數表格所包含的欄位總數可等於記憶裝置120所包含的HPB子區域總數。According to the third embodiment of the present invention, the memory device 110 can create another read count table (for example, the sub-region HPB read count table) (in order to be consistent with the read count table described in the second embodiment of the present invention). The partition is hereinafter referred to as the HPB read count table), and maintains or updates the content of the HPB read count table in response to the HPB read command with a transmission length greater than 1 issued by the host device 130, where the host device 130 selects more than one logical address to be read by the HPB read command with a transfer length greater than one. The HPB read count table may include a plurality of fields, and each field is used to record an HPB read count corresponding to an associated sub-region (for example, the aforementioned HPB sub-region). Therefore, the total number of columns included in the HPB read count table can be equal to the total number of HPB sub-areas included in the memory device 120.

於本發明之第三實施例中，一子區域所對應的HPB讀取次數係用以紀錄該子區域被主機裝置130透過發出HPB讀取指令讀取的次數。例如，HPB讀取次數可為一計數值，用以計算主機裝置130發出HPB讀取指令讀取對應之子區域所包含的邏輯位址的資料的次數。根據本發明之一實施例，記憶體控制器110可響應於由主機裝置130發出的帶有傳輸長度大於1的HPB讀取指令更新HPB讀取次數表格的內容。響應於帶有一起始邏輯區塊位址與大於1的傳輸長度的一HPB讀取指令之接收，記憶體控制器110可藉由增加被選定的邏輯位址(例如，起始邏輯區塊位址及根據起始邏輯區塊位址與傳輸長度推算出來後續的邏輯區塊位址)所屬之一或多個子區域所對應之一或多個HPB讀取次數更新HPB讀取次數表格的內容(例如，為每次的HPB讀取加1)。In the third embodiment of the present invention, the number of HPB read times corresponding to a sub-area is used to record the number of times the sub-area is read by the host device 130 through the HPB read command. For example, the number of HPB reads may be a count value used to count the number of times the host device 130 sends out the HPB read command to read the data of the logical address contained in the corresponding sub-area. According to an embodiment of the present invention, the memory controller 110 can update the content of the HPB read count table in response to an HPB read command with a transfer length greater than one issued by the host device 130. In response to receiving an HPB read command with an initial logical block address and a transmission length greater than 1, the memory controller 110 can increase the selected logical address (for example, the initial logical block bit) The address and the subsequent logical block address calculated from the starting logical block address and the transmission length) belong to one or more of the sub-regions corresponding to one or more HPB read times to update the content of the HPB read times table ( For example, add 1) for each HPB read.

根據本發明之一實施例，記憶體控制器110可更將HPB讀取次數表格中記錄的HPB讀取次數排序，並且根據排序過的HPB讀取次數選擇一或多個要進行資料重排的子區域。例如，記憶體控制器110可選擇一或多個HPB讀取次數高於一既定值的子區域作為要進行資料重排的子區域。於一實施例中，記憶體控制器110可依序根據排序過的HPB讀取次數選擇出目前HPB讀取次數最多的子區域，並且對所選的子區域執行對應的資料重排程序，接著將已被資料重排過的子區域所對應的HPB讀取次數自排序過的HPB讀取次數中移除。於需要時，前述的選擇與資料重排程序可反覆地對不同子區域執行。According to an embodiment of the present invention, the memory controller 110 may further sort the HPB reading times recorded in the HPB reading times table, and select one or more data to be rearranged according to the sorted HPB reading times Sub-area. For example, the memory controller 110 may select one or more sub-regions whose HPB reading times are higher than a predetermined value as the sub-regions to perform data rearrangement. In one embodiment, the memory controller 110 may sequentially select the sub-region with the most current HPB reading times according to the sorted HPB reading times, and execute the corresponding data rearrangement procedure on the selected sub-regions, and then Remove the HPB reading times corresponding to the sub-regions that have been rearranged from the sorted HPB reading times. When necessary, the aforementioned selection and data rearrangement procedures can be repeatedly executed for different sub-regions.

根據本發明之另一實施例，記憶體控制器110可根據HPB讀取次數表格所記錄之HPB讀取次數計算一平均HPB讀取次數，並且根據平均HPB讀取次數選擇至少一個子區域。例如，記憶體控制器110可選擇一或多個HPB讀取次數高於平均HPB讀取次數的子區域作為要進行資料重排的子區域。According to another embodiment of the present invention, the memory controller 110 may calculate an average HPB read count based on the HPB read count recorded in the HPB read count table, and select at least one sub-region based on the average HPB read count. For example, the memory controller 110 may select one or more sub-regions whose HPB reading times are higher than the average HPB reading times as the sub-regions to perform data rearrangement.

第10圖係顯示根據本發明之第三實施例所述之資料處理方法流程圖。本發明之資料處理方法適用於一資料儲存裝置，可由記憶體控制器110執行並包括以下步驟：Figure 10 is a flow chart of the data processing method according to the third embodiment of the present invention. The data processing method of the present invention is suitable for a data storage device, can be executed by the memory controller 110 and includes the following steps:

步驟S1002: 建立一讀取次數表格(例如，HPB讀取次數表格)，並且響應於由一主機裝置發出之一讀取指令(例如，HPB讀取指令)更新讀取次數表格的內容，其中讀取指令帶有大於1之一傳輸長度，以選定一個以上要被讀取的邏輯位址。Step S1002: Create a read count table (for example, HPB read count table), and update the content of the read count table in response to a read command (for example, HPB read command) issued by a host device, where the read The instruction fetch has a transfer length greater than 1 to select more than one logical address to be read.

步驟S1004: 根據讀取次數表格的內容選擇至少一個子區域。Step S1004: Select at least one sub-region according to the content of the read count table.

步驟S1006: 執行一資料重排程序，用以將屬於被選擇的至少一個子區域的該等邏輯位址的資料(即，被選擇的至少一個子區域的資料)搬移(或者重新寫入)至記憶體裝置中具有連續實體位址的記憶空間。Step S1006: Perform a data rearrangement procedure to move (or rewrite) the data of the logical addresses belonging to the selected at least one sub-area (that is, the data of the selected at least one sub-area) to A memory space with consecutive physical addresses in a memory device.

需注意的是，第三實施例所述之資料處理方法可被應用於主機控制模式或裝置控制模式。It should be noted that the data processing method described in the third embodiment can be applied to the host control mode or the device control mode.

此外，於本發明之一些實施例中，資料重排程序(例如，於前述第一、第二與第三實施例之任一者中所述之資料重排程序)可為一垃圾回收程序，或者可被合併於一垃圾回收程序中，而前述之要進行資料重排的子區域的選擇可於一垃圾回收程序被觸發時連帶被觸發。更具體的說，當任一可觸發資料回收程序的條件達成時(例如，當閒置記憶體區塊(spare memory block)的總數量低於一既定閒置記憶體區塊臨界值時)，除了選擇存有需被搬移(或者，重新寫入)至目的記憶體區塊的有效資料的來源記憶體區塊外，記憶體控制器110可進一步選擇一或多個要進行資料重排的子區域，並且執行對應之資料重排程序，用以將被選擇的子區域的資料搬移(或者重新寫入)至記憶體裝置中具有連續實體位址的記憶空間。In addition, in some embodiments of the present invention, the data rearrangement procedure (for example, the data rearrangement procedure described in any one of the foregoing first, second, and third embodiments) may be a garbage collection procedure, Or it can be incorporated into a garbage collection process, and the aforementioned selection of sub-regions to be rearranged can be triggered when a garbage collection process is triggered. More specifically, when any condition that can trigger the data recovery process is met (for example, when the total number of spare memory blocks is lower than a predetermined free memory block threshold), except for selecting In addition to the source memory block where the valid data that needs to be moved (or rewritten) to the destination memory block is stored, the memory controller 110 may further select one or more sub-regions for data rearrangement. And execute the corresponding data rearrangement procedure to move (or rewrite) the data of the selected sub-region to the memory space with consecutive physical addresses in the memory device.

於本發明之其他實施例中，資料重排程序也可被合併於其他資料搬移程序中，例如，用以將一或多個抹除次數高於一既定抹除次數臨界值的記憶體區塊的資料搬移至抹除次數相對少的記憶體區塊之一損耗均衡(wear leveling)程序、用以將具有ECC錯誤位元數量高於一既定錯誤位元數量之資料搬移至一新的記憶體區塊之一讀取回收(read reclaim)程序、用以將具有讀取次數高於一既定讀取次數臨界值之資料搬移至一新的記憶體區塊之一讀取刷新(read refresh)程序、或其他。此外，要進行資料重排的子區域的選擇也可於資料搬移程序被觸發時連帶被觸發。In other embodiments of the present invention, the data rearrangement process can also be combined with other data transfer processes, for example, to increase one or more memory blocks whose erasing times are higher than a predetermined threshold of erasing times The data is moved to a wear leveling process in the memory block with relatively few erasures, which is used to move the data with the number of ECC error bits higher than a predetermined number of error bits to a new memory A read reclaim process of a block, which is used to move data with a read count higher than a predetermined read count threshold to a new memory block. A read refresh process ,or others. In addition, the selection of the sub-area to be rearranged can also be triggered when the data movement procedure is triggered.

於本發明之又另一些實施例中，資料重排程序也可於資料儲存裝置100閒置時(例如，當資料儲存裝置100於一既定期間內均未自主機裝置130接收到任何指令時，資料儲存裝置100可進入閒置模式)被執行。In still other embodiments of the present invention, the data rearrangement process can also be used when the data storage device 100 is idle (for example, when the data storage device 100 has not received any commands from the host device 130 within a predetermined period of time, the data The storage device 100 may enter an idle mode) to be executed.

根據本發明之一實施例，在如前述第一、第二與第三實施例中將活化次數表格/讀取次數表格/HPB讀取次數表格中記錄的活化次數/讀取次數/HPB讀取次數排序，並且根據排序過的活化次數/讀取次數/HPB讀取次數選擇至少一個子區域後，記憶體控制器110可進一步判斷屬於被選擇的至少一個子區域的複數邏輯位址的資料是否並未被儲存於連續實體位址。記憶體控制器110可藉由根據屬於被選擇的至少一個子區域的複數邏輯位址查找L2P映射表格的內容以判斷屬於被選擇的至少一個子區域的複數邏輯位址的資料是否被儲存於連續實體位址。當屬於被選擇的至少一個子區域的邏輯位址的資料並未被儲存於連續實體位址時，記憶體控制器110將該等邏輯位址的資料搬移(或者，重新寫入)至具有連續實體位址的記憶空間。當被選擇的至少一個子區域的資料已被儲存於連續實體位址時，記憶體控制器110則可省略資料搬移的操作。具有連續實體位址的記憶空間可以是一記憶體區塊(例如，一目的記憶體區塊)，或者一記憶體區塊中具有連續實體位址的一部分儲存單元。According to an embodiment of the present invention, in the aforementioned first, second and third embodiments, the activation times/reading times/HPB readings recorded in the activation times table/reading times table/HPB reading times table are After selecting at least one sub-area according to the sorted activation times/reading times/HPB reading times, the memory controller 110 may further determine whether the data belonging to the plural logical addresses of the selected at least one sub-area is It is not stored in a continuous physical address. The memory controller 110 can search the contents of the L2P mapping table according to the plural logical addresses belonging to the selected at least one sub-area to determine whether the data belonging to the plural logical addresses of the selected at least one sub-area is stored in consecutive Physical address. When the data belonging to the logical address of the selected at least one sub-area is not stored in a continuous physical address, the memory controller 110 moves (or rewrites) the data of the logical address to a continuous physical address. The memory space of the physical address. When the data of the selected at least one sub-area has been stored in the continuous physical address, the memory controller 110 can omit the operation of data transfer. The memory space with continuous physical addresses can be a memory block (for example, a destination memory block), or a part of storage units with continuous physical addresses in a memory block.

第11圖係顯示根據本發明之一實施例所述之資料重排程序(例如，於前述第一、第二與第三實施例之任一者中所述之資料重排程序)的操作。記憶體控制器110可根據邏輯位址的數值或索引值的內容推算出此邏輯位址屬於哪個子區域以及哪個區域。第2圖已顯示出一個邏輯位址(例如，邏輯區塊位址LBA)與HPB區域/HPB子區域之間的關係的範例。此技術領域中具有通常知識者當可理解如何根據一邏輯位址推算出此邏輯位址屬於哪個子區域以及哪個區域，故於此不再贅述。FIG. 11 shows the operation of the data rearrangement procedure according to an embodiment of the present invention (for example, the data rearrangement procedure described in any one of the foregoing first, second, and third embodiments). The memory controller 110 can calculate which sub-region and which region the logical address belongs to according to the value of the logical address or the content of the index value. Figure 2 has shown an example of the relationship between a logical address (for example, a logical block address LBA) and the HPB area/HPB sub-area. Those with ordinary knowledge in this technical field should understand how to calculate which sub-region and which region the logical address belongs to based on a logical address, so it will not be repeated here.

於第11圖所示之範例中，假設一個HPB區域的大小為32百萬位元組(MB)，一個HPB子區域的大小為4百萬位元組，並且一個邏輯區塊位址的大小為4千位元祖(KB)，則一個HPB子區域可包括1000個邏輯區塊位址。因此，具有索引值(或數值)0~999的邏輯區塊位址LBA 0~LBA 999屬於索引值為0的HPB區域HPB_Rgn_0以及索引值為0的HPB子區域HPB_Sub_Rgn_0。In the example shown in Figure 11, suppose that the size of an HPB area is 32 megabytes (MB), the size of an HPB sub-area is 4 megabytes, and the size of a logical block address If it is 4 kilobytes (KB), an HPB sub-area can include 1000 logical block addresses. Therefore, the logical block addresses LBA 0 to LBA 999 with index values (or values) 0 to 999 belong to the HPB area HPB_Rgn_0 with an index value of 0 and the HPB sub-area HPB_Sub_Rgn_0 with an index value of 0.

當記憶體控制器110如上述實施例根據活化次數表格/讀取次數表格/HPB讀取次數表格的內容判斷HPB子區域HPB_Sub_Rgn_0需要進行資料重排，並且選擇出HPB子區域HPB_Sub_Rgn_0時，記憶體控制器110可如第11圖所示將邏輯區塊位址LBA 0~LBA 999的資料自實體位址{0x000A000, 0x000A001, 0x000A002, 0x000B003, 0x000A004, 0x000A005, 0x000B009, …}搬移至具有連續實體位址{0x0000C000, 0x0000C001, 0x0000C002, 0x0000C003, 0x0000C004, 0x0000C005, 0x0000C006, …}的一個新的記憶空間。When the memory controller 110 determines that the HPB sub-region HPB_Sub_Rgn_0 needs to be rearranged according to the contents of the activation count table/read count table/HPB read count table as in the above embodiment, and selects the HPB subregion HPB_Sub_Rgn_0, the memory controls The device 110 can move the data of the logical block address LBA 0~LBA 999 from the physical address {0x000A000, 0x000A001, 0x000A002, 0x000B003, 0x000A004, 0x000A005, 0x000B009, …} to a continuous physical address as shown in Figure 11 {0x0000C000, 0x0000C001, 0x0000C002, 0x0000C003, 0x0000C004, 0x0000C005, 0x0000C006, …} a new memory space.

需注意的是，於本發明之一些實施例中，記憶體控制器110也可對包含被選擇的一或多個子區域的一或多個區域執行資料重排程序(例如，於前述第一、第二與第三實施例之任一者中所述之資料重排程序)，用以將屬於包含被選擇的一或多個子區域的一或多個區域的所有邏輯位址的資料都搬移至記憶體裝置120中具有連續實體位址的記憶空間。此技術領域中具有通常知識者當可根據如第11圖所示之範例推導出將一整個區域的資料搬移至具有連續實體位址的記憶空間的資料重排操作，故於此不再贅述。It should be noted that, in some embodiments of the present invention, the memory controller 110 may also perform a data rearrangement process on one or more regions including the selected one or more subregions (for example, in the aforementioned first, The data rearrangement procedure described in either of the second and third embodiments) is used to move all the data of logical addresses belonging to one or more regions including the selected one or more subregions to The memory device 120 has a memory space with consecutive physical addresses. Those with ordinary knowledge in this technical field can derive the data rearrangement operation of moving the data of an entire area to the memory space with continuous physical addresses according to the example shown in FIG. 11, so it will not be repeated here.

根據本發明之一實施例，記憶體控制器110也可於一映射表格中為資料重排程序(例如，於前述第一、第二與第三實施例之任一者中所述之資料重排程序)中作為目的記憶空間使用的記憶空間對應地記錄複數邏輯位址。例如，前述具有連續實體位址且於資料重排程序作為目的記憶空間使用的記憶空間可被包含於一記憶體區塊(於以下段落稱之為目的記憶體區塊)。記憶體控制器110可於目的記憶體區塊所對應之一映射表格中對應地記錄複數邏輯位址。此映射表格可為一實體至邏輯(Physical to Logical，縮寫為P2L) (或稱快閃記憶體至主機 (Flash to Host，縮寫為F2H))映射表格。不同於前述儲存於記憶體裝置120的全域或區域L2P映射表格，對應於目的記憶體區塊的P2L映射表格可被儲存於緩衝記憶體116內，作為一臨時的映射表格。According to an embodiment of the present invention, the memory controller 110 can also perform a data rearrangement procedure in a mapping table (for example, the data rearrangement procedure described in any of the foregoing first, second, and third embodiments). The memory space used as the destination memory space in the program) records plural logical addresses correspondingly. For example, the aforementioned memory space that has continuous physical addresses and is used as the target memory space in the data rearrangement process can be included in a memory block (referred to as the target memory block in the following paragraphs). The memory controller 110 can correspondingly record a plurality of logical addresses in a mapping table corresponding to the target memory block. The mapping table can be a physical to logical (P2L) (or Flash to Host (F2H)) mapping table. Unlike the aforementioned global or regional L2P mapping table stored in the memory device 120, the P2L mapping table corresponding to the target memory block can be stored in the buffer memory 116 as a temporary mapping table.

於本發明之一實施例中，P2L映射表格可包括複數欄位，P2L映射表格之一欄位對應於目的記憶體區塊的一個實體位址，用以紀錄此實體位址之映射資訊，其中四個實體位址可對應於一實體資料頁。例如，一實體位址可用以儲存4 KB之資料，而一實體資料頁的大小可為16 KB。目的記憶體區塊的P2L映射表格內所紀錄之一個實體位址的映射資訊為儲存於目的記憶體區塊之該實體位址之資料係指向哪個邏輯位址的實體至邏輯映射資訊。In an embodiment of the present invention, the P2L mapping table may include a plurality of fields, one of the fields of the P2L mapping table corresponds to a physical address of the target memory block, and is used to record the mapping information of the physical address. Four physical addresses can correspond to a physical data page. For example, a physical address can be used to store 4 KB of data, and the size of a physical data page can be 16 KB. The mapping information of a physical address recorded in the P2L mapping table of the destination memory block is the physical-to-logical mapping information of which logical address the data of the physical address stored in the destination memory block points.

此外，儲存於記憶體裝置120之全域或區域L2P映射表格(以下一併稱為L2P映射表格)可包括複數欄位，L2P映射表格之一欄位用以紀錄一邏輯位址之映射資訊。其中一邏輯位址可對應於一邏輯資料頁。L2P映射表格內所紀錄之一邏輯位址或一邏輯資料頁的映射資訊為記憶體裝置之哪個實體位址儲存有此邏輯位址或邏輯資料頁之資料的邏輯至實體映射資訊。In addition, the global or regional L2P mapping table (hereinafter referred to as the L2P mapping table) stored in the memory device 120 may include a plurality of fields, and one of the fields in the L2P mapping table is used to record the mapping information of a logical address. One of the logical addresses can correspond to a logical data page. The mapping information of a logical address or a logical data page recorded in the L2P mapping table is which physical address of the memory device stores the logical-to-physical mapping information of the data of the logical address or logical data page.

於本發明之實施例中，記憶體控制器110可更響應於將被選擇的一或多個子區域的資料搬移至目的記憶體區塊的操作更新目的記憶體區塊所對應之P2L映射表格的內容並且記錄目的記憶體區塊的複數實體位址的實體至邏輯映射資訊。此外，於本發明之實施例中，於執行資料重排程序(例如，於前述第一、第二與第三實施例之任一者中所述之資料重排程序)後，記憶體控制器110可進一步於更新目的記憶體區塊所對應之P2L映射表格的內容後，直接根據此更新過的內容更新L2P映射表格的內容。需注意的是，於執行資料重排程序後，即使目的記憶體區塊尚未被寫滿，記憶體控制器110仍可直接根據更新過的目的記憶體區塊所對應之P2L映射表格的內容更新L2P映射表格的內容。即，於目的記憶體區塊尚未被寫滿之前，只要記憶體控制器110執行過資料重排程序，即可根據目的記憶體區塊所對應之P2L映射表格的最新的內容更新L2P映射表格的內容。In the embodiment of the present invention, the memory controller 110 may further update the P2L mapping table corresponding to the target memory block in response to the operation of moving the data of the selected one or more sub-regions to the target memory block. The content also records the entity-to-logical mapping information of the plural physical addresses of the target memory block. In addition, in the embodiment of the present invention, after executing the data rearrangement procedure (for example, the data rearrangement procedure described in any one of the foregoing first, second, and third embodiments), the memory controller 110 may further update the content of the L2P mapping table according to the updated content after updating the content of the P2L mapping table corresponding to the target memory block. It should be noted that after the data rearrangement process is executed, even if the target memory block is not full, the memory controller 110 can still directly update the contents of the P2L mapping table corresponding to the updated target memory block The content of the L2P mapping table. That is, before the target memory block is full, as long as the memory controller 110 has executed the data rearrangement process, the L2P mapping table can be updated according to the latest content of the P2L mapping table corresponding to the target memory block. content.

此外，於本發明之實施例中，記憶體控制器110可更建立一子區域連續性表格，並且於執行資料重排程序(例如，於前述第一、第二與第三實施例之任一者中所述之資料重排程序)後更新子區域連續性表格的內容。子區域連續性表格可包括複數欄位，各欄位與一子區域相關聯，用以紀錄相關聯之子區域的資料是否被儲存於連續實體位址。例如，子區域連續性表格的各欄位可儲存一位元。當一子區域的資料經由前述資料重排程序中被搬移至具有連續實體位址的記憶空間時，記憶體控制器110可將與此子區域相關聯的位元值設定為1。反之，與此子區域相關聯的位元值可被設定為0(其可以是一預設值)。In addition, in the embodiment of the present invention, the memory controller 110 can further create a sub-region continuity table, and execute the data rearrangement process (for example, in any of the aforementioned first, second, and third embodiments). After the data rearrangement procedure described in the above), update the content of the sub-region continuity table. The sub-region continuity table may include a plurality of fields, and each field is associated with a sub-region to record whether the data of the associated sub-region is stored in a continuous physical address. For example, each field of the subregional continuity table can store one bit. When the data of a sub-region is moved to the memory space with consecutive physical addresses in the aforementioned data rearrangement process, the memory controller 110 may set the bit value associated with this sub-region to 1. Conversely, the bit value associated with this sub-region can be set to 0 (it can be a preset value).

借助子區域連續性表格所記錄的資訊，於自主機裝置130接收到HPB讀取指令時，特別是當HPB讀取指令所帶的傳輸長度(TRANSFER LENGTH)大於1時，記憶體控制器110可藉由檢視子區域連續性表格中與HPB讀取指令中所帶的邏輯位址(例如，起始邏輯位址)所屬的子區域相關聯的位元值判斷HPB讀取指令中所帶的邏輯位址是否屬於資料被儲存於連續實體位址的子區域(例如，判斷子區域連續性表格中與起始邏輯位址所屬的子區域相關聯的位元值是否被設定為1)。若是，只要此起始邏輯位址之後的一或多個後續邏輯位址也屬於資料被儲存於連續實體位址的子區域，則記憶體控制器110可直接根據編碼於起始邏輯位址所對應的HPB項目中的實體位址推導出儲存此起始邏輯位址之後的一或多個後續邏輯位址的資料的一或多個實體位址。如此一來，當藉由子區域連續性表格的內容判斷出起始邏輯位址的資料與一或多個後續邏輯位址的資料被儲存於連續的實體位址時，記憶體控制器110可直接決定略過查找或搜尋L2P映射表格所記錄的映射資訊以找出儲存後續一或多個欲讀取的邏輯位址的資料的一或多個實體位址的操作。因記憶體控制器110僅需參考子區域連續性表格的內容便可推導出所需的實體位址，並判斷是否可略過查找或搜尋L2P映射表格的操作，藉此可使存取操作的速度大幅提升。With the help of the information recorded in the sub-region continuity table, when the HPB read command is received from the host device 130, especially when the transfer length (TRANSFER LENGTH) of the HPB read command is greater than 1, the memory controller 110 can Judging the logic carried in the HPB read command by viewing the bit value associated with the sub-region to which the logical address (for example, the starting logical address) in the HPB read command belongs in the sub-region continuity table Whether the address belongs to the subregion where the data is stored in the continuous physical address (for example, it is determined whether the bit value associated with the subregion to which the initial logical address belongs in the subregion continuity table is set to 1). If so, as long as one or more subsequent logical addresses after the starting logical address also belong to the sub-area where the data is stored in the continuous physical address, the memory controller 110 can directly encode the data in the starting logical address. The physical address in the corresponding HPB item is derived from one or more physical addresses that store data of one or more subsequent logical addresses after the initial logical address. In this way, when it is determined from the content of the sub-region continuity table that the data of the initial logical address and the data of one or more subsequent logical addresses are stored in consecutive physical addresses, the memory controller 110 can directly Decide to skip the search or search for the mapping information recorded in the L2P mapping table to find out the operation of one or more physical addresses that store the data of one or more logical addresses to be read later. Because the memory controller 110 only needs to refer to the content of the sub-region continuity table to derive the required physical address, and determine whether the search or search for the L2P mapping table can be skipped, thereby enabling the access operation The speed is greatly improved.

需注意的是，由於資料的更新將導致子區域的資料被儲存於不連續的實體位址，因此，當一個子區域所包含的任一邏輯位址的資料被更新且被儲存於其他實體位址時，子區域連續性表格中所記錄的與此子區域相關聯的位元值將由1修改為0。It should be noted that the update of the data will cause the data of the sub-area to be stored in discontinuous physical addresses. Therefore, when the data of any logical address contained in a sub-area is updated and stored in other physical locations When addressing, the bit value associated with this sub-area recorded in the sub-area continuity table will be changed from 1 to 0.

此外，需注意的是，於本發明之又一些實施例中，記憶體控制器110可建立且同時維護一個以上的前述活化次數表格、讀取次數表格與HPB讀取次數表格，並且可根據紀錄於前述活化次數表格、讀取次數表格與HPB讀取次數表格之內容的任意組合選擇一或多個要進行資料重排的子區域。例如，記憶體控制器110可將前述表格中所記錄各子區域所對應的活化次數、讀取次數與HPB讀取次數加總或取其平均值並加以排序後，根據排序過的加總或平均結果選擇一或多個要進行資料重排的子區域。In addition, it should be noted that, in other embodiments of the present invention, the memory controller 110 can create and maintain more than one activation count table, read count table, and HPB read count table at the same time, and can be based on records Select one or more sub-regions for data rearrangement in any combination of the contents of the aforementioned activation count table, read count table, and HPB read count table. For example, the memory controller 110 may add the activation times, read times, and HPB read times corresponding to each sub-area recorded in the aforementioned table, or take the average value and sort them, and then sort them according to the sorted total or For the average result, select one or more sub-regions for data rearrangement.

當儲存於記憶體裝置120的資料的連續性可藉由根據前述活化次數表格、讀取次數表格及/或HPB讀取次數表格所記錄的之資訊執行資料重排程序而被加強時，存取操作的速度可大幅地被提升，且存取效能也可大幅地被改善。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 When the continuity of the data stored in the memory device 120 can be enhanced by performing a data rearrangement process based on the information recorded in the activation count table, read count table, and/or HPB read count table, access The operation speed can be greatly improved, and the access performance can also be greatly improved. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

100:資料儲存裝置 110:記憶體控制器 112:微處理器 112C:程式碼 112M:唯讀記憶體 114:記憶體介面 116:緩衝記憶體 118:主機介面 120:記憶體裝置 130:主機裝置 132:編碼器 134:解碼器 200:邏輯單元 A-1、A-2、A-3、A-4、B-1、B-2、B-3、C-1、C-2、C-3、C-4、C-5、C-6、D-1、D-2、D-3、D-4、D-5、D-6、D-7:操作 DATA IN UPIU:送入資料之通用快閃記憶體儲存通訊協定資訊單元 HPB_Rgn_0、HPB_Rgn_(N-1) :HPB區域 HPB_Sub_Rgn_0、HPB_Sub_Rgn_(L-1) :HPB子區域 LBA:邏輯區塊位址100: Data storage device 110: Memory Controller 112: Microprocessor 112C: Code 112M: Read only memory 114: Memory Interface 116: buffer memory 118: Host Interface 120: Memory device 130: host device 132: Encoder 134: Decoder 200: logical unit A-1, A-2, A-3, A-4, B-1, B-2, B-3, C-1, C-2, C-3, C-4, C-5, C- 6. D-1, D-2, D-3, D-4, D-5, D-6, D-7: Operation DATA IN UPIU: Universal flash memory storage protocol information unit for data input HPB_Rgn_0, HPB_Rgn_(N-1): HPB area HPB_Sub_Rgn_0, HPB_Sub_Rgn_(L-1): HPB sub area LBA: logical block address

第1圖係顯示根據本發明之一實施例所述之資料儲存裝置的方塊圖範例。 第2圖係顯示邏輯單元與其對應之邏輯區塊位址的一個範例。 第3圖係顯示於主機控制模式下可有的操作。 第4圖係顯示於裝置控制模式下可有的操作。 第5圖係顯示HPB項目的一個範例格式。 第6圖係顯示HPB項目的另一個範例格式。 第7圖係顯示HPB讀取指令的對應操作。 第8圖係顯示根據本發明之第一實施例所述之資料處理方法流程圖。 第9圖係顯示根據本發明之第二實施例所述之資料處理方法流程圖。 第10圖係顯示根據本發明之第三實施例所述之資料處理方法流程圖。 第11圖係顯示根據本發明之一實施例所述之資料重排程序的操作。 Fig. 1 shows an example of a block diagram of a data storage device according to an embodiment of the present invention. Figure 2 shows an example of a logical unit and its corresponding logical block address. Figure 3 shows the possible operations in the host control mode. Figure 4 shows the possible operations in the device control mode. Figure 5 shows an example format of the HPB project. Figure 6 shows another example format of the HPB project. Figure 7 shows the corresponding operation of the HPB read command. Fig. 8 shows a flowchart of the data processing method according to the first embodiment of the present invention. Figure 9 is a flow chart of the data processing method according to the second embodiment of the present invention. Figure 10 is a flow chart of the data processing method according to the third embodiment of the present invention. Figure 11 shows the operation of the data rearrangement program according to an embodiment of the present invention.

100:資料儲存裝置 100: Data storage device

110:記憶體控制器 110: Memory Controller

112:微處理器 112: Microprocessor

112C:程式碼 112C: Code

112M:唯讀記憶體 112M: Read only memory

114:記憶體介面 114: Memory Interface

116:緩衝記憶體 116: buffer memory

118:主機介面 118: Host Interface

120:記憶體裝置 120: Memory device

130:主機裝置 130: host device

132:編碼器 132: Encoder

134:解碼器 134: Decoder

Claims (16)

一種資料儲存裝置，包括： 一記憶體裝置，包括複數記憶體區塊，該等記憶體區塊對應於複數邏輯單元，各邏輯單元分別對應於複數邏輯位址，各邏輯單元所對應之該等邏輯位址被劃分為複數區域，並且各區域進一步被劃分為複數子區域；以及 一記憶體控制器，耦接至該記憶體裝置，用以存取該記憶體裝置，並且響應於由一主機裝置發出之一讀取指令更新一讀取次數表格的內容，其中該讀取指令帶有大於1之一傳輸長度，以選定一個以上要被讀取的邏輯位址， 其中該讀取次數表格包括複數欄位，各欄位用以記錄相關聯之一子區域所對應之一讀取次數，並且該記憶體控制器藉由增加於該讀取指令中選定的邏輯位址所屬之一或多個子區域所對應之一或多個讀取次數更新該讀取次數表格的內容，並且 其中該記憶體控制器更根據該讀取次數表格的內容選擇至少一個子區域，並且執行一資料重排程序用以將屬於被選擇的該至少一個子區域的該等邏輯位址的資料搬移至該記憶體裝置中具有連續實體位址的一第一記憶空間。 A data storage device, including: A memory device includes a plurality of memory blocks, the memory blocks correspond to a plurality of logical units, each logical unit corresponds to a plurality of logical addresses, and the logical addresses corresponding to each logical unit are divided into a plurality of logical units Areas, and each area is further divided into plural sub-areas; and A memory controller is coupled to the memory device for accessing the memory device, and updates the content of a read count table in response to a read command issued by a host device, wherein the read command With a transmission length greater than 1, to select more than one logical address to be read, The read count table includes a plurality of fields, and each field is used to record a read count corresponding to a related sub-area, and the memory controller adds the selected logical bit in the read command. One or more reading times corresponding to one or more sub-areas to which the address belongs to update the contents of the reading times table, and The memory controller further selects at least one sub-area according to the content of the read count table, and executes a data rearrangement procedure to move the data of the logical addresses belonging to the selected at least one sub-area to The memory device has a first memory space with consecutive physical addresses. 如申請專利範圍第1項所述之資料儲存裝置，其中該記憶體控制器更將該讀取次數表格中記錄的該等讀取次數排序，並且根據排序過的該等讀取次數選擇該至少一個子區域。For example, the data storage device described in item 1 of the scope of patent application, wherein the memory controller further sorts the read times recorded in the read times table, and selects the at least one according to the sorted read times A sub-area. 如申請專利範圍第1項所述之資料儲存裝置，其中該記憶體控制器更判斷屬於被選擇的該至少一個子區域的該等邏輯位址的資料是否被儲存於連續實體位址，以及當屬於被選擇的該至少一個子區域的該等邏輯位址的資料並未被儲存於連續實體位址時，該記憶體控制器更將該等邏輯位址的資料搬移至具有連續實體位址的該第一記憶空間。Such as the data storage device described in item 1 of the scope of patent application, wherein the memory controller further determines whether the data of the logical addresses belonging to the selected at least one sub-area is stored in a continuous physical address, and when When the data of the logical addresses belonging to the selected at least one sub-area is not stored in the continuous physical address, the memory controller moves the data of the logical address to the one with the continuous physical address The first memory space. 如申請專利範圍第1項所述之資料儲存裝置，其中該記憶體控制器更根據該讀取次數表格所記錄之該等讀取次數計算一平均讀取次數，並且根據該平均讀取次數選擇該至少一個子區域。For the data storage device described in item 1 of the scope of patent application, the memory controller further calculates an average read count based on the read counts recorded in the read count table, and selects according to the average read count The at least one sub-area. 如申請專利範圍第1項所述之資料儲存裝置，其中由該主機裝置發出之該讀取指令為一主機性能增強器(Host Performance Booster，縮寫為HPB)讀取指令。For the data storage device described in item 1 of the scope of patent application, the read command issued by the host device is a host performance booster (Host Performance Booster, abbreviated as HPB) read command. 如申請專利範圍第1項所述之資料儲存裝置，其中該記憶體控制器更於該資料重排程序中將被選擇的該至少一個子區域所屬之一區域的資料搬移至該記憶體裝置中具有連續實體位址的一第二記憶空間。As for the data storage device described in item 1 of the scope of patent application, the memory controller further moves the data of a region to which the selected at least one subregion belongs to the memory device in the data rearrangement process A second memory space with consecutive physical addresses. 如申請專利範圍第1項所述之資料儲存裝置，其中該第一記憶空間為一第一記憶體區塊，該記憶體控制器更響應於將屬於被選擇的該至少一個子區域的該等邏輯位址的資料搬移至該第一記憶空間的操作更新一第一映射表格的內容，該第一映射表格用以紀錄該第一記憶體區塊之複數實體位址之實體至邏輯映射資訊，並且該記憶體控制器更於執行該資料重排程序後直接根據該第一映射表格的內容更新一第二映射表格的內容，其中該第二映射表格用以紀錄該記憶體裝置之該等邏輯位址之邏輯至實體映射資訊。For the data storage device described in claim 1, wherein the first memory space is a first memory block, and the memory controller is more responsive to the at least one selected sub-region The operation of moving the data of the logical address to the first memory space updates the content of a first mapping table for recording the entity-to-logical mapping information of the plural physical addresses of the first memory block. And the memory controller directly updates the content of a second mapping table according to the content of the first mapping table after executing the data rearrangement process, wherein the second mapping table is used to record the logic of the memory device The logical-to-physical mapping information of the address. 如申請專利範圍第1項所述之資料儲存裝置，其中該記憶體控制器更建立一子區域連續性表格，並且於執行該資料重排程序後更新該子區域連續性表格的內容，其中該子區域連續性表格包括複數欄位，各欄位與一子區域相關聯，用以紀錄屬於相關聯之該子區域的該等邏輯位址的資料是否被儲存於連續實體位址。For the data storage device described in item 1 of the scope of patent application, the memory controller further creates a sub-region continuity table, and updates the content of the sub-region continuity table after executing the data rearrangement process, wherein the The sub-region continuity table includes a plurality of fields, and each field is associated with a sub-region to record whether the data of the logical addresses belonging to the associated sub-region is stored in a continuous physical address. 一種資料處理方法，適用於一資料儲存裝置，其中該資料儲存裝置包括一記憶體裝置與一記憶體控制器，該記憶體裝置包括複數記憶體區塊，該等記憶體區塊對應於複數邏輯單元，各邏輯單元分別對應於複數邏輯位址，各邏輯單元所對應之該等邏輯位址被劃分為複數區域，並且各區域進一步被劃分為複數子區域，該記憶體控制器耦接至該記憶體裝置，用以存取該記憶體裝置，該資料處理方法由該記憶體控制器所執行並包括： 建立一讀取次數表格，並且響應於由一主機裝置發出之一讀取指令更新該讀取次數表格的內容，其中該讀取指令帶有大於1之一傳輸長度，以選定一個以上要被讀取的邏輯位址，該讀取次數表格包括複數欄位，各欄位用以記錄相關聯之一子區域所對應之一讀取次數，並且該讀取次數表格的內容係藉由增加於該讀取指令中選定的邏輯位址所屬之一或多個子區域所對應之一或多個讀取次數而被更新； 根據該讀取次數表格的內容選擇至少一個子區域；以及 執行一資料重排程序，用以將屬於被選擇的該至少一個子區域的該等邏輯位址的資料搬移至該記憶體裝置中具有連續實體位址的一第一記憶空間。 A data processing method is suitable for a data storage device, wherein the data storage device includes a memory device and a memory controller, the memory device includes a plurality of memory blocks, the memory blocks corresponding to the plurality of logic Each logical unit corresponds to a plurality of logical addresses, the logical addresses corresponding to each logical unit are divided into a plurality of areas, and each area is further divided into a plurality of sub-areas, and the memory controller is coupled to the The memory device is used to access the memory device, and the data processing method is executed by the memory controller and includes: Create a read count table, and update the content of the read count table in response to a read command issued by a host device, wherein the read command has a transmission length greater than 1 to select more than one to be read The read count table includes a plurality of fields, each field is used to record a read count corresponding to a sub-area, and the content of the read count table is added to the One or more reading times corresponding to one or more sub-regions of the logical address selected in the read instruction are updated; Select at least one sub-region according to the content of the read count table; and A data rearrangement process is performed to move the data of the logical addresses belonging to the selected at least one sub-area to a first memory space with consecutive physical addresses in the memory device. 如申請專利範圍第9項所述之資料處理方法，其中根據該讀取次數表格的內容選擇該至少一個子區域之步驟更包括： 將該讀取次數表格中記錄的該等讀取次數排序；以及 根據排序過的該等讀取次數選擇該至少一個子區域。 For example, the data processing method described in item 9 of the scope of patent application, wherein the step of selecting the at least one sub-region according to the content of the read count table further includes: Sort the read times recorded in the read times table; and The at least one sub-region is selected according to the sorted reading times. 如申請專利範圍第9項所述之資料處理方法，其中執行該資料重排程序之步驟更包括： 判斷屬於被選擇的該至少一個子區域的該等邏輯位址的資料是否被儲存於連續實體位址；以及 當屬於被選擇的該至少一個子區域的該等邏輯位址的資料並未被儲存於連續實體位址時，將該等邏輯位址的資料搬移至具有連續實體位址的該第一記憶空間。 For example, the data processing method described in item 9 of the scope of patent application, wherein the steps of executing the data rearrangement procedure further include: Determine whether the data of the logical addresses belonging to the selected at least one sub-area is stored in consecutive physical addresses; and When the data of the logical addresses belonging to the selected at least one sub-area is not stored in the continuous physical address, move the data of the logical address to the first memory space with the continuous physical address . 如申請專利範圍第9項所述之資料處理方法，其中根據該讀取次數表格的內容選擇該至少一個子區域之步驟更包括： 根據該讀取次數表格所記錄之該等讀取次數計算一平均讀取次數；以及 根據該平均讀取次數選擇該至少一個子區域。 For example, the data processing method described in item 9 of the scope of patent application, wherein the step of selecting the at least one sub-region according to the content of the read count table further includes: Calculate an average read count based on the read counts recorded in the read count table; and The at least one sub-region is selected according to the average number of readings. 如申請專利範圍第9項所述之資料處理方法，其中由該主機裝置發出之該讀取指令為一主機性能增強器(Host Performance Booster，縮寫為HPB)讀取指令。According to the data processing method described in item 9 of the scope of patent application, the read command issued by the host device is a host performance booster (Host Performance Booster, abbreviated as HPB) read command. 如申請專利範圍第9項所述之資料處理方法，其中執行該資料重排程序之步驟更包括： 將被選擇的該至少一個子區域所屬之一區域的資料搬移至該記憶體裝置中具有連續實體位址的一第二記憶空間。 For example, the data processing method described in item 9 of the scope of patent application, wherein the steps of executing the data rearrangement procedure further include: The data of a region to which the selected at least one subregion belongs is moved to a second memory space with continuous physical addresses in the memory device. 如申請專利範圍第9項所述之資料處理方法，其中該第一記憶空間為一第一記憶體區塊，該資料處理方法更包括： 響應於將被屬於被選擇的該至少一個子區域的該等邏輯位址的資料搬移至該第一記憶空間的操作更新一第一映射表格的內容，其中該第一映射表格用以紀錄該第一記憶體區塊之複數實體位址之實體至邏輯映射資訊；以及 於執行該資料重排程序後直接根據該第一映射表格的內容更新一第二映射表格的內容，其中該第二映射表格用以紀錄該記憶體裝置之該等邏輯位址之邏輯至實體映射資訊。 For example, the data processing method described in item 9 of the scope of patent application, wherein the first memory space is a first memory block, and the data processing method further includes: In response to the operation of moving the data of the logical addresses belonging to the selected at least one sub-region to the first memory space, the content of a first mapping table is updated, wherein the first mapping table is used to record the first memory space. Physical-to-logical mapping information of a plurality of physical addresses of a memory block; and After executing the data rearrangement process, the content of a second mapping table is directly updated according to the content of the first mapping table, wherein the second mapping table is used to record the logical-to-physical mapping of the logical addresses of the memory device Information. 如申請專利範圍第9項所述之資料處理方法，更包括： 建立一子區域連續性表格，其中該子區域連續性表格包括複數欄位，各欄位與一子區域相關聯，用以紀錄屬於相關聯之該子區域的該等邏輯位址的資料是否被儲存於連續實體位址；以及 於執行該資料重排程序後更新該子區域連續性表格的內容。 For example, the data processing method described in item 9 of the scope of patent application includes: Create a sub-region continuity table, where the sub-region continuity table includes a plurality of fields, and each field is associated with a sub-region to record whether the data of the logical addresses belonging to the associated sub-region has been Stored in a continuous physical address; and Update the content of the sub-region continuity table after executing the data rearrangement procedure.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150301964A1 (en) * 2014-02-18 2015-10-22 Alistair Mark Brinicombe Methods and systems of multi-memory, control and data plane architecture
US20170123890A1 (en) * 2015-10-29 2017-05-04 Commvault Systems, Inc. Monitoring, diagnosing, and repairing a management database in a data storage management system
US20170372448A1 (en) * 2016-06-28 2017-12-28 Ingo Wald Reducing Memory Access Latencies During Ray Traversal
US20180300145A1 (en) * 2017-04-17 2018-10-18 Intel Corporation Memory-based dependency tracking and cache pre-fetch hardware for multi-resolution shading
US20200089409A1 (en) * 2018-09-14 2020-03-19 Commvault Systems, Inc. Redundant distributed data storage system
US20200167091A1 (en) * 2018-11-27 2020-05-28 Commvault Systems, Inc. Using interoperability between components of a data storage management system and appliances for data storage and deduplication to generate secondary and tertiary copies

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8713380B2 (en) * 2011-05-03 2014-04-29 SanDisk Technologies, Inc. Non-volatile memory and method having efficient on-chip block-copying with controlled error rate
US9007860B2 (en) * 2013-02-28 2015-04-14 Micron Technology, Inc. Sub-block disabling in 3D memory
TWI585778B (en) * 2013-11-05 2017-06-01 威盛電子股份有限公司 Operation method of non-volatile memory device
KR20150135980A (en) * 2014-05-26 2015-12-04 삼성전자주식회사 Method for controlling display and electronic device
WO2016175028A1 (en) * 2015-04-28 2016-11-03 日本電気株式会社 Information processing system, storage control device, storage control method, and storage control program
TWI691839B (en) * 2016-11-28 2020-04-21 慧榮科技股份有限公司 Method for data management
US10534718B2 (en) * 2017-07-31 2020-01-14 Micron Technology, Inc. Variable-size table for address translation
CN109671458A (en) * 2017-10-17 2019-04-23 联发科技股份有限公司 The method of management flash memory module and relevant flash controller
TWI661303B (en) * 2017-11-13 2019-06-01 慧榮科技股份有限公司 Method for accessing flash memory module and associated flash memory controller and electronic device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150301964A1 (en) * 2014-02-18 2015-10-22 Alistair Mark Brinicombe Methods and systems of multi-memory, control and data plane architecture
US20170123890A1 (en) * 2015-10-29 2017-05-04 Commvault Systems, Inc. Monitoring, diagnosing, and repairing a management database in a data storage management system
US20170372448A1 (en) * 2016-06-28 2017-12-28 Ingo Wald Reducing Memory Access Latencies During Ray Traversal
US20180300145A1 (en) * 2017-04-17 2018-10-18 Intel Corporation Memory-based dependency tracking and cache pre-fetch hardware for multi-resolution shading
US20200089409A1 (en) * 2018-09-14 2020-03-19 Commvault Systems, Inc. Redundant distributed data storage system
US20200167091A1 (en) * 2018-11-27 2020-05-28 Commvault Systems, Inc. Using interoperability between components of a data storage management system and appliances for data storage and deduplication to generate secondary and tertiary copies

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