TWI748488B

TWI748488B - Double gate metal oxide semiconductor field effect transistor and manufacturing method thereof

Info

Publication number: TWI748488B
Application number: TW109118191A
Authority: TW
Inventors: 簡鳳佐; 王志哲; 王鈞毅
Original assignee: 逢甲大學
Priority date: 2020-05-29
Filing date: 2020-05-29
Publication date: 2021-12-01
Also published as: TW202145576A

Abstract

本發明所提供雙閘極金氧半導體場效電晶體元件之製造方法，其主要之技術特徵係在於將用以構成兩個閘極之掺雜層於同一微影製程中將之定義為在同一範圍內之相同形狀者，從而確保兩個閘極彼此間的自我對準狀態，避免習知技術對於兩個閘極分別定義所衍生之成本增加與位準偏移的缺失。The main technical feature of the manufacturing method of the double-gate metal oxide semiconductor field-effect transistor device provided by the present invention is that the doped layers used to form the two gates are defined as being in the same lithography process in the same lithography process. It can ensure the self-alignment state of the two gates with each other, avoiding the cost increase and the lack of level shifting derived from the separate definition of the two gates in the prior art.

Description

雙閘極金氧半導體場效電晶體元件及其製造方法Double-gate metal oxide semiconductor field effect transistor and manufacturing method thereof

本發明係與金氧半導體場效電晶體有關，特別是關於一種雙閘極金氧半導體場效電晶體元件及其製造方法。 The invention relates to a metal oxide semiconductor field effect transistor, and particularly relates to a double-gate metal oxide semiconductor field effect transistor and a manufacturing method thereof.

隨著微電子工業中之製造技術不斷地提昇，電子元件的尺寸也隨之縮小，舉以金氧半導體場效電晶體為例，其在小於65nm的尺寸下，已然面對了許多物理上的限制，從而導致了漏電流的增加與短通道效應等不良影響，而為克服是等缺失，習知技術遂有透過改變元件結構來加以避免之技術被公開，其中，被用以改進上述缺失之雙閘極金氧半導體場效電晶體(Double Gate MOSFETs)元件結構，除能達到對於離子遷移率、短通道效應與起始次振翼之改善效果外，亦具有較佳的元件特性，是等功效上的增進使得雙閘極金氧半導體場效電晶體成為產業所青睞之微電子元件。 With the continuous improvement of manufacturing technology in the microelectronics industry, the size of electronic components has also shrunk. Take the metal oxide semiconductor field-effect transistor as an example. Its size is less than 65nm, and it has already faced many physical problems. Limitations have resulted in increased leakage current and short-channel effects. In order to overcome such shortcomings, conventional technologies have been disclosed to avoid such shortcomings by changing the device structure. Among them, it is used to improve the above-mentioned shortcomings. The device structure of Double Gate MOSFETs can not only improve the ion mobility, short-channel effect and initial secondary wing, but also has better device characteristics, etc. The increase in efficiency makes double-gate MOSFETs become the most popular microelectronic components in the industry.

然而由於雙閘極金氧半導體場效電晶體之製程相較於單閘極之製程而言係相對地較為繁複，而其中，在不同製程步驟中所分別形成的上下閘極，因甚易導致其彼此之位置產生偏移，成為製造上所必需加以克服之障礙，雖然習知技術可以透過微影技術來精確地定義不同的加工區域來加以克服，依序地定義出下閘極(Bottom Gate)、通道主動區(Active)、上閘極(Top Gate)、金屬接觸區 (Contact Hole)與金屬層，但如此一來，其即必需透過五道光罩製程始得以完成雙閘極金氧半導體場效電晶體之製造，而伴隨著製造成本之增加。 However, the manufacturing process of double-gate MOSFETs is relatively more complicated than the single-gate manufacturing process. Among them, the upper and lower gates formed in different process steps can easily lead to The offset between their positions has become an obstacle that must be overcome in manufacturing. Although the conventional technology can use lithography technology to precisely define different processing areas to overcome it, and sequentially define the bottom gate (Bottom Gate). ), channel active area (Active), top gate (Top Gate), metal contact area (Contact Hole) and the metal layer, but in this way, it is necessary to complete the manufacture of the double-gate MOS field-effect transistor through five photomask manufacturing processes, which is accompanied by an increase in manufacturing costs.

因此，本發明之主要目的即係在提供一種雙閘極金氧半導體場效電晶體元件之製造方法，其係可在確保閘極彼此間自我對準狀態下，減少對於微影技術之使用，以降低製造之成本。 Therefore, the main purpose of the present invention is to provide a method for manufacturing a double-gate MOSFET device, which can reduce the use of lithography technology while ensuring that the gates are self-aligned with each other. In order to reduce the cost of manufacturing.

緣是，為達成上述目的，本發明所提供雙閘極金氧半導體場效電晶體元件之製造方法，其主要之技術特徵係在於將用以構成兩個閘極之掺雜層於同一微影製程中將之定義為在同一範圍內之相同形狀者，從而確保兩個閘極彼此間的自我對準狀態，避免習知技術對於兩個閘極分別定義所衍生之成本增加與位準偏移的缺失。 The reason is that, in order to achieve the above-mentioned object, the main technical feature of the method for manufacturing a double-gate MOSFET device provided by the present invention is that the doped layer used to form the two gates is placed on the same lithography In the manufacturing process, it is defined as the same shape in the same range, so as to ensure the self-alignment of the two gates with each other, avoiding the cost increase and level shift derived from the separate definition of the two gates in the conventional technology Missing.

就上述主要技術特徵之技術內容而言，其乃係對一位於一基板上之複層定義出一保留區，並將該複層位於該保留區以外之部位予以去除，從而得以該保留區內之該複層中之特定層分別形成各該閘極者，其中，該複層係由多數之層彼此由下而上依序疊接而成，其依序為一第一掺雜層、一第一介電層、一通道層、一第二介電層以及一第二掺雜層，其中，該第一掺雜層與該第二掺雜層係分別形成各該閘極。 As far as the technical content of the above-mentioned main technical features is concerned, it is to define a reserved area for a multi-layer on a substrate, and remove the part of the multi-layer outside the reserved area, so as to obtain the reserved area The specific layers in the multi-layer respectively form each of the gates, wherein the multi-layer is formed by stacking a plurality of layers sequentially from bottom to top, which in turn are a first doped layer, a The first dielectric layer, a channel layer, a second dielectric layer, and a second doped layer, wherein the first doped layer and the second doped layer respectively form the gates.

進一步地，其係以該通道層形成一導電通道。 Further, it uses the channel layer to form a conductive channel.

為於該導電通道之兩端分別形成一源極與一汲極，係可於上述保留區周側形成一絕緣層，而於該第一掺雜層與該第一介電層之周側形成絕緣後，在於該基板上方形成一第三掺雜層，並使該第三掺雜層覆蓋於該複層與該絕緣層上，然後再以化學機械研磨除去該第三掺雜層位於該保留區範圍內之部分，並對該第三掺雜層位於該保留區範圍外之部分定義出一主動區後，去除該第三掺雜層位於該主動區範圍外之部分，以及該第三掺雜層位於該主動區範圍內之厚度，使去除完成之該第三掺雜層僅與該通道層相連接，以定義出位於該導電通道兩端之該源極與該汲極。 In order to form a source electrode and a drain electrode at both ends of the conductive channel respectively, an insulating layer may be formed on the periphery of the reserved area, and formed on the periphery of the first doped layer and the first dielectric layer After insulation, a third doped layer is formed on the substrate, and the third doped layer is covered on the composite layer and the insulating layer, and then the third doped layer is removed by chemical mechanical polishing. Within the area After dividing and defining an active region for the part of the third doped layer outside the reserved region, remove the part of the third doped layer outside the active region, and the third doped layer is located on the The thickness within the active region is such that the removed third doped layer is only connected to the channel layer to define the source and drain at both ends of the conductive channel.

本發明之另一目的則係在提供一種雙閘極金氧半導體場效電晶體元件，其係使兩個閘極彼此間適於對準，以確保元件之品質者。 Another object of the present invention is to provide a dual-gate MOSFET device, which makes the two gates suitable for alignment with each other to ensure the quality of the device.

而為達成是一目的，該雙閘極金氧半導體場效電晶體元件乃係包含有一基板、一第一閘極與一第二閘極、一導電通道、一源極、一汲極、一第一絕緣部與一第二絕緣部；該第一閘極與該第二閘極係彼此平行且上下相隔開來地位於該基板上方，並使該第一閘極介於該第二閘極與該基板之間；該導電通道係介於該第一閘極與該第二閘極之間；該源極與該汲極係分別連接於該導電通道之通道兩端，並使該第一閘極介於其彼此之間；該第一絕緣部係位於該第一閘極之一側地設於該基板上，並以一側直接鄰接該第一閘極之一側，以及以另側直接鄰接該源極，且該第一絕緣部包含一絕緣材料，以於該第一閘極與該源極間形成絕緣；該第二絕緣部係位於該第一閘極之另側地設於該基板上，並以一側直接鄰接該第一閘極之另側，以及以另側直接鄰接該汲極，且該第二絕緣部包含一絕緣材料，以於該第一閘極與該汲極間形成絕緣，並且，該第一絕緣部與該第二絕緣部係為彼此相隔開來的各自獨立元件。 To achieve one goal, the dual-gate MOSFET device includes a substrate, a first gate and a second gate, a conductive channel, a source, a drain, and a A first insulating portion and a second insulating portion; the first gate and the second gate are located above the substrate in parallel and spaced apart from each other, and the first gate is interposed between the second gate And the substrate; the conductive channel is between the first gate and the second gate; the source and the drain are connected to both ends of the conductive channel, and make the first The gates are interposed between them; the first insulating part is located on one side of the first gate and is arranged on the substrate, and one side is directly adjacent to one side of the first gate, and the other side Directly adjacent to the source, and the first insulating portion includes an insulating material to form insulation between the first gate and the source; the second insulating portion is located on the other side of the first gate On the substrate, one side is directly adjacent to the other side of the first gate, and the other side is directly adjacent to the drain, and the second insulating portion includes an insulating material to connect the first gate and the drain. Insulation is formed between the poles, and the first insulating portion and the second insulating portion are separate components separated from each other.

其中，該第一閘極與該第二閘極在彼此平行對應的範圍內，兩者係具相同之形狀。 Wherein, the first gate and the second gate are in a range corresponding to each other in parallel, and both have the same shape.

(10):雙閘極金氧半導體場效電晶體元件 (10): Double gate metal oxide semiconductor field effect transistor

(11):基板 (11): Substrate

(12):緩衝層 (12): Buffer layer

(13):複層 (13): Multilayer

(131):第一掺雜層 (131): The first doped layer

(132):第一介電層 (132): First dielectric layer

(133):通道層 (133): Channel layer

(134):第二介電層 (134): second dielectric layer

(135):第二掺雜層 (135): second doped layer

(136):阻層 (136): Resistant layer

(14):保留區 (14): Reserved area

(15):絕緣層 (15): Insulation layer

(16):第三掺雜層 (16): The third doped layer

(17):保護層 (17): Protective layer

(20):第一閘極 (20): The first gate

(30):第二閘極 (30): The second gate

(40):主動區 (40): Active area

(41):源極 (41): Source

(42):汲極 (42): Dip pole

(50):金屬接觸區 (50): Metal contact area

(60):金屬層 (60): Metal layer

圖1係示意本發明一較佳實施例需以光罩進行定義之示意圖。 FIG. 1 is a schematic diagram showing that a preferred embodiment of the present invention needs to be defined by a photomask.

圖2(A)及圖2(B)係本發明一教佳實施例之製造方法示意圖。 2(A) and 2(B) are schematic diagrams of the manufacturing method of a teaching embodiment of the present invention.

圖3係以本發明一較佳實施例所製成之雙閘極金氧半導體場效電晶體元件之剖視圖。 FIG. 3 is a cross-sectional view of a double-gate metal oxide semiconductor field-effect transistor device made according to a preferred embodiment of the present invention.

圖4係本發明一較佳實施例所製成之雙閘極金氧半導體場效電晶體元件與習知技術之電場峰值圖。 FIG. 4 is a diagram of electric field peak values of a double-gate MOSFET fabricated in a preferred embodiment of the present invention and the conventional technology.

圖5係習知雙閘極金氧半導體場效電晶體元件之離子碰撞產生率模擬圖。 Figure 5 is a simulation diagram of the ion collision generation rate of a conventional double-gate MOSFET.

圖6係本發明一較佳實施例所製成之雙閘極金氧半導體場效電晶體元件之離子碰撞產生率模擬圖。 FIG. 6 is a simulation diagram of the ion collision generation rate of a double-gate MOSFET fabricated in a preferred embodiment of the present invention.

圖7係本發明一較佳實施例所製成之雙閘極金氧半導體場效電晶體元件與習知技術之輸出特性曲線圖。 FIG. 7 is a graph showing the output characteristic curve of a double-gate MOSFET made in a preferred embodiment of the present invention and the conventional technology.

首先，請參閱圖1所示，在本發明一較佳實施例中所提供雙閘極金氧半導體場效電晶體元件之製造方法，其在以微影技術進行特定區域之定義與加工時，係以光罩定義如圖1(a)所示之第一閘極(Bottom Gate,20)與一第二閘極(Top Gate,30)、如圖1(b)所示之主動區(Active,40)、如圖1(c)所示之金屬接觸區(Contact Hole,50)以及如圖1(d)所示之金屬層(Metal Pad,60)，換言之，就本實施例所提供之製造方法之整體而言，其僅需求四道光罩即可完成電晶體元件之製造，相較於習知技術而言，其非僅僅是減少一道光罩加工程序之簡化功效達成，更可降低製造之成本來提高產品之競爭力，惟關於利用光罩進行形狀定義之微影技術內容乃屬習知之技術，復非本發明所擬改進之技術標的，是以於此乃不予贅陳。 First of all, please refer to FIG. 1. In a preferred embodiment of the present invention, the method for manufacturing a double-gate metal oxide semiconductor field-effect transistor device is used to define and process a specific region by lithography technology. The mask defines the first gate (Bottom Gate, 20) and the second gate (Top Gate, 30) as shown in Figure 1(a), and the active area (Active Area) as shown in Figure 1(b). 40), the metal contact area (Contact Hole, 50) as shown in Figure 1(c) and the metal layer (Metal Pad, 60) as shown in Figure 1(d), in other words, the one provided in this embodiment As a whole, the manufacturing method requires only four photomasks to complete the manufacturing of the transistor element. Compared with the conventional technology, it is not only the reduction of the simplification effect of one photomask processing procedure, but also the reduction of manufacturing. The cost of the product is to improve the competitiveness of the product, but the content of the lithography technology using the mask to define the shape is a conventional technology, and it is not the technical target of the improvement of the present invention, so it will not be repeated here.

續請參閱圖2(A)及圖2(B)所示，該雙閘極金氧半導體場效電晶體元件之製造方法，乃係包含有下述之步驟： Please continue to refer to Figure 2(A) and Figure 2(B). The manufacturing method of the double-gate MOSFET device includes the following steps:

a.取用一矽之基板(11)，並以濕氧氧化於該基板(11)之上側表面上沉積5000Å之氧化層作為緩衝層(12)。 a. Take a silicon substrate (11), and deposit a 5000Å oxide layer on the upper surface of the substrate (11) by wet oxygen oxidation as a buffer layer (12).

b.於該緩衝層(12)之表面上形成一複層(13)，該複層(13)由下而上依序為一第一掺雜層(131)、一第一介電層(132)、一通道層(133)一第二介電層(134)、一第二掺雜層(135)以及一用以阻擋蝕刻之阻層(136)；該第一掺雜層(131)與該第二掺雜層(135)係分別為厚度約2000Å之掺雜複晶矽(Doped Poly-Si)、該第一介電層(132)與該第二介電層(134)則分別為以四乙氧基矽烷(TEOS)所沉積成厚度約500Å之介電質薄膜層(TEOS oxide)，而該通道層(133)為厚度約1000Å之非晶矽(α-Si)，而該阻層(136)則係以四乙氧基矽烷(TEOS)所沉積成厚度約1000Å之薄膜層(TEOS oxide)；其中，藉由沉積所形成之該複層(13)，係在沉積該第一掺雜層(131)、該第一介電層(132)與該通道層(133)後，先使構成該通道層(133)之非晶矽經由固相結晶(Solid.Phase Crystallization,SPC)轉變成為複晶矽，然後再進行該第二介電層(134)、該第二掺雜層(135)與該阻層(136)之沉積， b. A multiple layer (13) is formed on the surface of the buffer layer (12), and the multiple layer (13) from bottom to top is a first doped layer (131) and a first dielectric layer ( 132), a channel layer (133), a second dielectric layer (134), a second doped layer (135), and a resist layer (136) for blocking etching; the first doped layer (131) And the second doped layer (135) are doped poly-Si (Doped Poly-Si) with a thickness of about 2000 Å, the first dielectric layer (132) and the second dielectric layer (134) are respectively Is a dielectric film layer (TEOS oxide) with a thickness of about 500Å deposited by tetraethoxysilane (TEOS), and the channel layer (133) is an amorphous silicon (α-Si) with a thickness of about 1000Å, and the The barrier layer (136) is deposited with tetraethoxysilane (TEOS) to form a thin film layer (TEOS oxide) with a thickness of about 1000 Å; wherein, the multi-layer (13) formed by deposition is deposited on the After a doped layer (131), the first dielectric layer (132) and the channel layer (133), the amorphous silicon constituting the channel layer (133) is first subjected to solid phase crystallization (Solid. Phase Crystallization, SPC). ) Is transformed into polycrystalline silicon, and then the second dielectric layer (134), the second doped layer (135) and the resist layer (136) are deposited,

c.於該複層(13)上以微影技術定義出一保留區(14)，再經由蝕刻將複層(13)位於該保留區(14)以外之部分予以去除，以保留該複層(13)位於該保留區(14)中之部分如圖2(c)所示，並以之由該第一掺雜層(131)形成該第一閘極(20)、以該第二掺雜層(135)形成該第二閘極(30)，以及以該通道層(133)形成一導電通道(70)。 c. A reserved area (14) is defined on the multi-layer (13) by photolithography technology, and then the part of the multi-layer (13) outside the reserved area (14) is removed by etching to retain the multi-layer (13) The part located in the reserved area (14) is shown in Figure 2(c), and the first gate (20) is formed by the first doped layer (131), and the second doped The impurity layer (135) forms the second gate (30), and the channel layer (133) forms a conductive channel (70).

d.於該保留區(14)之周圍沉積一為氮化矽(Nitride)之絕緣層(15)，並使該絕緣層(15)包覆於該第一掺雜層(131)與該第一介電層(132)之周側。 d. Deposit an insulating layer (15) made of silicon nitride (Nitride) around the reserved area (14), and make the insulating layer (15) cover the first doped layer (131) and the first doped layer (131) The peripheral side of a dielectric layer (132).

e.於該基板(11)上沉積一為掺雜複晶矽(Doped Poly-Si)之第三掺雜層(16)，並使該第三掺雜層(16)之沉積範圍大於該保留區(14)之範圍、沉積厚度則大於該複層(13)之厚度，從而使該第三掺雜層(16)覆蓋於該複層(13)、該絕緣層(15)與該緩衝層(12)上。 e. Deposit a third doped layer (16) of doped poly-Si on the substrate (11), and make the deposition range of the third doped layer (16) larger than the reserved The range and deposition thickness of the region (14) are greater than the thickness of the composite layer (13), so that the third doped layer (16) covers the composite layer (13), the insulating layer (15) and the buffer layer (12) On.

f.以化學機械研磨(Chemical-Mechanical Planarization,CMP)去除位於該第三掺雜層(16)大於該複層(13)厚度以上之部位，以除去位於該保留區(14)範圍內之該第三掺雜層(16)部分，同時使位於該保留區(14)範圍以外之該第三掺雜層(16)之頂面平坦化，從而確保該第三掺雜層(16)之仍存留於該基板(11)上之部位，其厚度得以均一。 f. Use Chemical-Mechanical Planarization (CMP) to remove the part located in the third doped layer (16) which is greater than the thickness of the multi-layer (13) to remove the part located in the reserved area (14) Part of the third doped layer (16), while flattening the top surface of the third doped layer (16) outside the range of the reserved region (14), so as to ensure that the third doped layer (16) remains The thickness of the part remaining on the substrate (11) is uniform.

g.以微影技術對該第三掺雜層(16)定義出該主動區(40)。 g. The active region (40) is defined on the third doped layer (16) by lithography technology.

h.對該第三掺雜層(16)進行蝕刻，以除去該第三掺雜層(16)位於主動區(40)以外之部分，同時蝕去該第三掺雜層(16)位於主動區(40)內對應於該第二介電層(134)、該第二掺雜層(135)與該阻層(136)之範圍內之厚度，據以於該導電通道(70)之通道兩端分別形成一源極(41)與一汲極(42)，以及使該源極(41)與該汲極(42)相鄰於該保留區(14)之一側僅與該通道層(133)與該絕緣層(15)鄰接，從而得以該絕緣層(15)隔絕該第一閘極(20)與該源極(41)及該汲極(42)。 h. The third doped layer (16) is etched to remove the part of the third doped layer (16) outside the active region (40), and the third doped layer (16) is etched away at the same time. The area (40) corresponds to the thickness within the range of the second dielectric layer (134), the second doped layer (135) and the resistance layer (136), according to the channel of the conductive channel (70) A source (41) and a drain (42) are respectively formed at both ends, and the source (41) and the drain (42) are adjacent to one side of the reserved area (14) only with the channel layer (133) is adjacent to the insulating layer (15), so that the insulating layer (15) isolates the first gate electrode (20) from the source electrode (41) and the drain electrode (42).

i.最後則再以四乙氧基矽烷(TEOS)所沉積成厚度約3000Å之保護層(17,TEOS oxide)，並以微影技術定義並形成該金屬接觸區(50)後，再次地以微影技術定義並形成該金屬層(60)，據以製成雙閘極金氧半導體場效電晶體元件(10)。 i. Finally, tetraethoxysilane (TEOS) is deposited into a protective layer (17, TEOS oxide) with a thickness of about 3000 Å, and the metal contact area (50) is defined and formed by lithography technology, and then again with The metal layer (60) is defined and formed by the lithography technology, and a double-gate metal oxide semiconductor field effect transistor (10) is manufactured accordingly.

續請參閱圖3所示，該雙閘極金氧半導體場效電晶體元件(10)在構造中，該第一閘極(20)與該第二閘極(30)乃係在於同一微影製程中透過同一光罩加以定義，藉以確保該第一閘極(20)與該第二閘極(30)彼此間之位準狀態，以避免產生如習知技術將不同閘極在不同程序加以定義並形成所衍生的位置失準狀態，同時，該雙閘極金氧半導體場效電晶體元件(10)更進一步地將該源極(41)與該汲極(42)之厚度增加，據以降低汲極端之電場，從而克服習知技術因汲極端之過大電場所衍生之熱載子效應(Hot Carrier Effect)、扭結效應(Kink Effect)或漏電流效應(Leakage Effect)等，達到有效且顯著改善之功效。 Please refer to FIG. 3 again. In the structure of the double-gate MOSFET (10), the first gate (20) and the second gate (30) are in the same lithography During the manufacturing process, the same mask is used to define, so as to ensure the level state of the first gate (20) and the second gate (30) to avoid the generation of different gates in different processes as in the conventional technology. Define and form the derived positional misalignment At the same time, the double-gate MOSFET (10) further increases the thickness of the source (41) and the drain (42), thereby reducing the electric field of the drain terminal, thereby overcoming The conventional technology achieves an effective and significant improvement effect due to the Hot Carrier Effect, Kink Effect, or Leakage Effect, etc. derived from the excessively large electric field.

再請參閱圖4所示，其係以ISE-TCAD在VG=5V與VD=8.5V條件下所進行電場模擬之電場峰值圖，由圖示可知，傳統單閘極金氧半導體場效電晶體元件雖具有較低2.8e5(V/cm)之電場峰值，但習知之雙閘極金氧半導體場效電晶體元件之電場峰值則昇高至3.65e5(V/cm)，其相較於本發明所提供之該雙閘極金氧半導體場效電晶體元件(10)所具有3e5(V/cm)之電場峰值而言，本發明所提供之技術內容係可降低約18%之電場強度，已足以佐證上述功效之達成。 Please refer to Figure 4 again, which is the electric field peak diagram of the electric field simulation performed by ISE-TCAD under the conditions of VG=5V and VD=8.5V. As can be seen from the figure, the traditional single-gate MOSFET Although the device has a lower electric field peak value of 2.8e5 (V/cm), the electric field peak value of the conventional double-gate MOSFET device is increased to 3.65e5 (V/cm), which is compared with the original In terms of the electric field peak value of 3e5 (V/cm) provided by the double-gate MOSFET (10) provided by the invention, the technical content provided by the invention can reduce the electric field intensity by about 18%. It is sufficient to support the achievement of the above-mentioned effects.

復請參閱圖5及圖6所示，其係習知雙閘極金氧半導體場效電晶體元件與本發明所提供之該雙閘極金氧半導體場效電晶體元件(10)各自之離子碰撞產生率模擬圖，模擬之結果顯示，本發明之離子碰撞產生率為1.6e28(cm-3．s-1)，而習知之離子碰撞產生率則為4.3e28(cm-3．s-1)，相較之下，本發明所提供之技術內容係可降低63%之離子碰撞產生率。 Please refer to Figures 5 and 6, which are the respective ions of the conventional double-gate MOSFET device and the double-gate MOSFET device (10) provided by the present invention Collision generation rate simulation diagram. The simulation results show that the ion collision generation rate of the present invention is 1.6e28 (cm-3.s-1), while the conventional ion collision generation rate is 4.3e28 (cm-3.s-1) ). In contrast, the technical content provided by the present invention can reduce the ion collision generation rate by 63%.

進一步地，由圖7之輸出特性曲線圖更可顯示出該雙閘極金氧半導體場效電晶體元件(10)在8.5V之扭結效應上，較習知技術亦有大幅之改善。 Furthermore, the output characteristic curve of FIG. 7 can further show that the double-gate MOSFET (10) has a kink effect of 8.5V, which is greatly improved compared with the conventional technology.

綜上所陳，本發明所提供之雙閘極金氧半導體場效電晶體元件及其製造方法非僅可以降低製造之成本，更使電晶體元件得以具有更佳的效能表現，避免或降低不當效應之發生，其功效已屬顯著，當合於專利法所稱之發明。 In summary, the double-gate MOSFET device and its manufacturing method provided by the present invention can not only reduce the manufacturing cost, but also enable the transistor device to have better performance and avoid or reduce improper performance. When the effect occurs, its effect is already significant, and it should be in accordance with the invention referred to in the Patent Law.

(20)第一閘極(30)第二閘極(40)主動區(50)金屬接觸區(60)金屬層(20) First gate (30) Second gate (40) Active area (50) Metal contact area (60) Metal layer

Claims

一種雙閘極金氧半導體場效電晶體元件，包含有：一基板；一第一閘極與一第二閘極，係彼此平行且上下相隔開來地位於該基板上方，並使該第一閘極介於該第二閘極與該基板之間；一具預定通道長度之導電通道，係介於該第一閘極與該第二閘極之間；一源極，係設於該基板上而位於該第一閘極之一側外，且連接於該導電通道之通道一端；一汲極，係設於該基板上而位於該第一閘極之另側外，且連接於該導電通道之通道另端；一第一絕緣部，係位於該第一閘極之一側地設於該基板上，並以一側直接鄰接該第一閘極之一側，以及以另側直接鄰接該源極，且該第一絕緣部包含一絕緣材料，以於該第一閘極與該源極間形成絕緣；一第二絕緣部，係位於該第一閘極之另側地設於該基板上，並以一側直接鄰接該第一閘極之另側，以及以另側直接鄰接該汲極，且該第二絕緣部包含一絕緣材料，以於該第一閘極與該汲極間形成絕緣；其中，該第一絕緣部與該第二絕緣部係為彼此相隔開來的各自獨立元件。 A double-gate metal oxide semiconductor field-effect transistor element includes: a substrate; a first gate and a second gate, which are parallel to each other and spaced up and down above the substrate, and make the first The gate is between the second gate and the substrate; a conductive channel with a predetermined channel length is between the first gate and the second gate; a source is provided on the substrate The upper side is located outside one side of the first gate and connected to one end of the channel of the conductive channel; a drain is provided on the substrate and located outside the other side of the first gate, and is connected to the conductive The other end of the channel; a first insulating part is arranged on the substrate on one side of the first gate, and one side is directly adjacent to one side of the first gate, and the other side is directly adjacent The source and the first insulating part include an insulating material to form insulation between the first gate and the source; a second insulating part is located on the other side of the first gate. On the substrate, one side is directly adjacent to the other side of the first gate, and the other side is directly adjacent to the drain, and the second insulating portion includes an insulating material for the first gate and the drain Insulation is formed between; wherein, the first insulating portion and the second insulating portion are separate components separated from each other.

如請求項1所述雙閘極金氧半導體場效電晶體元件，其中，該源極之厚度係大於該導電通道之厚度。 The double-gate MOSFET device according to claim 1, wherein the thickness of the source electrode is greater than the thickness of the conductive channel.

如請求項1所述雙閘極金氧半導體場效電晶體元件，其中，該汲極之厚度係大於該導電通道之厚度。 The double-gate MOSFET device according to claim 1, wherein the thickness of the drain is greater than the thickness of the conductive channel.

如請求項1所述雙閘極金氧半導體場效電晶體元件，其係更包含有二介電層，係分別介於該導電通道之上下兩側與該第二閘極及該第一閘極之間。 The double-gate MOSFET device according to claim 1, which further includes two dielectric layers, which are respectively located between the upper and lower sides of the conductive channel and the second gate and the first gate Between the poles.

如請求項1所述雙閘極金氧半導體場效電晶體元件，其中，構成該第一絕緣部與該第二絕緣部之絕緣材料係為氮化矽。 The double-gate MOSFET device according to claim 1, wherein the insulating material constituting the first insulating portion and the second insulating portion is silicon nitride.

如請求項1所述雙閘極金氧半導體場效電晶體元件，其中，該第一絕緣部鄰接該源極之一側係呈弧形，且使弧形之一端與該導電通道一端之底緣相切。 The double-gate MOSFET device according to claim 1, wherein the side of the first insulating portion adjacent to the source is arc-shaped, and one end of the arc is connected to the bottom of one end of the conductive channel The edge is tangent.

如請求項1所述雙閘極金氧半導體場效電晶體元件，其中，該第二絕緣部鄰接該汲極之一側係呈弧形，且使弧形之一端與該導電通道另端之底緣相切。 The double-gate MOSFET device of claim 1, wherein the side of the second insulating portion adjacent to the drain is arc-shaped, and one end of the arc is connected to the other end of the conductive channel. The bottom edge is tangent.

一種雙閘極金氧半導體場效電晶體元件之製造方法，包含有下述步驟：a.取用一基板；b.於該基板上方形成一複層，該複層由下而上依序為一第一掺雜層、一第一介電層、一通道層、一第二介電層、一第二掺雜層以及一阻層；c.對該複層定義出一保留區，並除去該複層位於該保留區範圍外之部位，以定義出由該第一掺雜層所形成之一第一閘極、由該第二掺雜層所形成之一第二閘極，以及由該通道層所形成之一導電通道；d.於該保留區周側形成一絕緣層，且使該絕緣層鄰接於該第一掺雜層與該第一介電層，但不與該通道層相接；e.於該基板上方形成一第三掺雜層，使該第三掺雜層覆蓋於該複層與該絕緣層上；f.以化學機械研磨除去該第三掺雜層位於該保留區範圍內之部分； g.對該第三掺雜層位於該保留區範圍外之部分定義出一主動區；h.去除該第三掺雜層位於該主動區範圍外之部分，以及該第三掺雜層位於該主動區範圍內之厚度，使去除完成之該第三掺雜層僅與該通道層相連接，以定義出位於該導電通道兩端之一源極與一汲極。 A method for manufacturing a double-gate metal oxide semiconductor field-effect transistor device includes the following steps: a. Take a substrate; b. Form a multiple layer on the substrate, the multiple layers are sequentially from bottom to top A first doped layer, a first dielectric layer, a channel layer, a second dielectric layer, a second doped layer, and a resist layer; c. define a reserved area for the composite layer, and remove The multiple layer is located outside the reserved area to define a first gate formed by the first doped layer, a second gate formed by the second doped layer, and a second gate formed by the second doped layer. A conductive channel formed by the channel layer; d. An insulating layer is formed on the periphery of the reserved area, and the insulating layer is adjacent to the first doped layer and the first dielectric layer, but not to the channel layer Then; e. A third doped layer is formed above the substrate, so that the third doped layer covers the composite layer and the insulating layer; f. The third doped layer is removed by chemical mechanical polishing in the remaining The part within the area; g. Define an active region for the portion of the third doped layer located outside the range of the reserved region; h. Remove the portion of the third doped layer located outside the range of the active region, and the third doped layer is located on the The thickness of the active region is such that the removed third doped layer is only connected to the channel layer to define a source and a drain located at both ends of the conductive channel.

如請求項8所述雙閘極金氧半導體場效電晶體元件之製造方法，其中，於該步驟b中，該通道層係以非晶矽為材料形成層狀物後，再轉變為複晶矽，而後始於其上依序形成該第二介電層、該第二掺雜層與該阻層。 The method for manufacturing a double-gate metal oxide semiconductor field-effect transistor device according to claim 8, wherein, in step b, the channel layer is made of amorphous silicon as a material to form a layer, and then converted into a polycrystalline Silicon, and then begin to form the second dielectric layer, the second doped layer and the resist layer on it in sequence.

如請求項8所述雙閘極金氧半導體場效電晶體元件之製造方法，其中，於該步驟h中，係以蝕刻進行去除。 The method for manufacturing a double-gate metal oxide semiconductor field-effect transistor device according to claim 8, wherein, in this step h, it is removed by etching.