TWI747387B - Method for manufacturing thin film transistor - Google Patents

Method for manufacturing thin film transistor Download PDF

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TWI747387B
TWI747387B TW109124431A TW109124431A TWI747387B TW I747387 B TWI747387 B TW I747387B TW 109124431 A TW109124431 A TW 109124431A TW 109124431 A TW109124431 A TW 109124431A TW I747387 B TWI747387 B TW I747387B
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forming step
sputtering
oxide semiconductor
speed
film
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TW202107718A (en
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松尾大輔
安東靖典
瀬戸口佳孝
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日商日新電機股份有限公司
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

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Abstract

本發明提供一種薄膜電晶體的製造方法，能夠高效率地形成與其他層的界面處的氧缺失等缺陷少的氧化物半導體層。本發明的薄膜電晶體的製造方法是製造於基板上積層有閘極電極、閘極絕緣層、氧化物半導體層、源極電極及汲極電極的薄膜電晶體的方法，其包括藉由使用電漿來濺鍍靶材而形成所述氧化物半導體層的半導體層形成步驟，且所述半導體層形成步驟包括：高速成膜步驟，對所述靶材施加規定值的偏壓來進行濺鍍；以及低速成膜步驟，對所述靶材施加絕對值較所述規定值小的偏壓來進行濺鍍。The present invention provides a method for manufacturing a thin film transistor, which can efficiently form an oxide semiconductor layer with few defects such as oxygen deficiency at the interface with other layers. The manufacturing method of the thin film transistor of the present invention is a method of manufacturing a thin film transistor in which a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode, and a drain electrode are laminated on a substrate. A step of forming the oxide semiconductor layer by sputtering a target with a slurry, and the step of forming the semiconductor layer includes: a high-speed film forming step, applying a predetermined value of bias to the target to perform sputtering; And a low-speed film forming step, applying a bias voltage having an absolute value smaller than the predetermined value to the target material to perform sputtering.

Description

薄膜電晶體的製造方法Method for manufacturing thin film transistor

本發明是有關於一種薄膜電晶體的製造方法。且特別是有關於一種使用電漿來濺鍍靶材而形成氧化物半導體層的薄膜電晶體的製造方法。The invention relates to a method for manufacturing a thin film transistor. In particular, it relates to a method for manufacturing a thin film transistor that uses plasma to sputter a target material to form an oxide semiconductor layer.

近年來，正在積極進行將In-Ga-Zn-O系（IGZO）的氧化物半導體用於通道層的薄膜電晶體的開發。於具有此種氧化物半導體層的薄膜電晶體的製造步驟中，若於氧化物半導體層中、特別是與其他層的界面處存在大量氧缺失等缺陷，則其導電率發生變化，並有使薄膜電晶體的電特性劣化之虞。因此，為了減少氧化物半導體層中的氧缺失等缺陷，自先前以來進行了各種嘗試。In recent years, the development of thin film transistors using In-Ga-Zn-O-based (IGZO) oxide semiconductors for the channel layer has been actively carried out. In the manufacturing steps of a thin film transistor having such an oxide semiconductor layer, if there are a large number of defects such as oxygen deficiency in the oxide semiconductor layer, especially at the interface with other layers, its conductivity will change and cause The electrical characteristics of thin-film transistors may deteriorate. Therefore, in order to reduce defects such as oxygen deficiency in the oxide semiconductor layer, various attempts have been made since the past.

例如，專利文獻1中揭示有如下方法：將氧流量相對於濺鍍氣體的總流量的比例設為90%以上、100%以下來濺鍍作為靶材的金屬氧化物，藉此形成氧過剩的狀態的氧化物半導體層，並設為利用緻密的金屬氧化物覆蓋該氧化物半導體層的構成，藉此獲得具有氧過剩的氧化物半導體層的薄膜電晶體。 [現有技術文獻] [專利文獻]For example, Patent Document 1 discloses a method in which the ratio of the oxygen flow rate to the total flow rate of the sputtering gas is set to 90% or more and 100% or less to sputter a metal oxide as a target, thereby forming an excess of oxygen. The state of the oxide semiconductor layer is configured to cover the oxide semiconductor layer with a dense metal oxide, thereby obtaining a thin film transistor having an oxide semiconductor layer with excess oxygen. [Prior Art Literature] [Patent Literature]

[專利文獻1]日本專利特開2012-119672號公報[Patent Document 1] Japanese Patent Laid-Open No. 2012-119672

[發明所欲解決之課題] 但是，關於專利文獻1中所揭示的方法，由於使用高濃度的氧氣作為濺鍍氣體，因此靶材的表面附近所生成的電漿的密度降低。因此，存在濺鍍率降低而無法高效率地形成氧化物半導體層的問題。[The problem to be solved by the invention] However, regarding the method disclosed in Patent Document 1, since a high concentration of oxygen is used as the sputtering gas, the density of the plasma generated near the surface of the target material is reduced. Therefore, there is a problem that the sputtering rate is reduced and the oxide semiconductor layer cannot be formed efficiently.

本發明是鑒於所述問題而成者，主要課題在於提供一種薄膜電晶體的製造方法，其可高效率地形成與其他層的界面處的氧缺失等缺陷少的氧化物半導體層。 [解決課題之手段]The present invention was made in view of the aforementioned problems, and its main subject is to provide a method of manufacturing a thin film transistor that can efficiently form an oxide semiconductor layer with few defects such as oxygen deficiency at the interface with other layers. [Means to solve the problem]

即，本發明的薄膜電晶體的製造方法為製造於基板上積層有閘極電極、閘極絕緣層、氧化物半導體層、源極電極及汲極電極的薄膜電晶體的方法，且所述薄膜電晶體的製造方法的特徵在於：包括藉由使用電漿來濺鍍靶材而形成所述氧化物半導體層的半導體層形成步驟，且所述半導體層形成步驟包括：高速成膜步驟，對所述靶材施加規定值的偏壓來進行濺鍍；以及低速成膜步驟，對所述靶材施加絕對值較所述規定值小的偏壓來進行濺鍍。That is, the method of manufacturing a thin film transistor of the present invention is a method of manufacturing a thin film transistor in which a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode, and a drain electrode are laminated on a substrate, and the thin film The method of manufacturing a transistor is characterized in that it includes a semiconductor layer forming step of forming the oxide semiconductor layer by sputtering a target using plasma, and the semiconductor layer forming step includes: a high-speed film forming step, The target is subjected to sputtering by applying a bias voltage of a predetermined value; and in the low-speed film forming step, the target is subjected to sputtering by applying a bias with a smaller absolute value than the predetermined value.

在高速成膜步驟中，藉由施加與低速成膜步驟相比絕對值大的偏壓進行濺鍍，雖然成膜的氧化物半導體的膜密度與低速成膜步驟相比變低，但能夠以更大的成膜速度成膜氧化物半導體。另一方面，在低速成膜步驟中，藉由施加與高速成膜步驟相比絕對值小的偏壓進行濺鍍，雖然成膜速度與高速成膜步驟相比變小，但能夠成膜更緻密且膜密度更高的氧化物半導體。 根據本發明的製造方法，藉由在半導體層形成步驟中組合所述高速成膜步驟與所述低速成膜步驟，例如在使氧化物半導體層的厚度成長的階段（塊體階段）藉由高速成膜步驟進行濺鍍，在形成與閘極絕緣層等其他層的界面的階段切換為低速成膜步驟來進行濺鍍，能夠高效率地形成與其他層的界面處的膜密度高且缺陷少的氧化物半導體層。藉此，能夠使界面的缺失密度降低，因此能夠製造具有高信賴性的優異的薄膜電晶體。In the high-speed film-forming step, sputtering is performed by applying a bias with a larger absolute value than that of the low-speed film-forming step. Although the film density of the deposited oxide semiconductor becomes lower than that of the low-speed film-forming step, it can be Larger film forming speed to form oxide semiconductor films. On the other hand, in the low-speed film-forming step, sputtering is performed by applying a bias with a smaller absolute value compared with the high-speed film-forming step. Although the film-forming speed becomes smaller than the high-speed film-forming step, the film can be formed more quickly. A dense and denser oxide semiconductor. According to the manufacturing method of the present invention, by combining the high-speed film-forming step and the low-speed film-forming step in the semiconductor layer forming step, for example, the high-speed film forming step is used to grow the thickness of the oxide semiconductor layer (bulk stage). Sputtering is performed in the film formation step, and the sputtering step is switched to the low-speed film formation step at the stage of forming the interface with other layers such as the gate insulating layer, and the film density at the interface with other layers can be formed efficiently and with few defects.的oxide semiconductor layer. Thereby, the density of the interface defect can be reduced, and therefore, an excellent thin film transistor with high reliability can be manufactured.

在所述半導體層形成步驟中，較佳為在進行所述低速成膜步驟之後進行所述高速成膜步驟，其後進而進行所述低速成膜步驟。 如此，能夠在氧化物半導體層與其他層之間形成的整個界面處提高膜密度，因此能夠製造電特性更優異的薄膜電晶體。In the semiconductor layer forming step, it is preferable to perform the high-speed film-forming step after performing the low-speed film-forming step, and then to further perform the low-speed film-forming step. In this way, it is possible to increase the film density at the entire interface formed between the oxide semiconductor layer and other layers, and therefore it is possible to manufacture a thin film transistor with more excellent electrical characteristics.

較佳為所述低速成膜步驟中的濺鍍時間較所述高速成膜步驟中的濺鍍時間短。 如此，藉由使成膜速度大的高速成膜步驟較低速成膜步驟變長，能夠更有效率地形成氧化物半導體層。Preferably, the sputtering time in the low-speed film forming step is shorter than the sputtering time in the high-speed film forming step. In this way, the oxide semiconductor layer can be formed more efficiently by making the high-speed film-forming step with a high film-forming speed lower and the film-forming step longer.

在所述高速成膜步驟及所述低速成膜步驟中，較佳為使用相同組成的靶材進行濺鍍。 如此，由於無需在半導體層形成步驟的中途更換靶材，故能夠更有效率地形成氧化物半導體層。In the high-speed film forming step and the low-speed film forming step, it is preferable to use a target material of the same composition for sputtering. In this way, since there is no need to replace the target material in the middle of the semiconductor layer forming step, the oxide semiconductor layer can be formed more efficiently.

在所述高速成膜步驟及所述低速成膜步驟中，較佳為供給相同組成的濺鍍氣體進行濺鍍。 如此，由於無需在半導體層形成步驟的中途更換濺鍍氣體，故能夠更有效率地形成氧化物半導體層。In the high-speed film forming step and the low-speed film forming step, it is preferable to supply a sputtering gas of the same composition for sputtering. In this way, since there is no need to replace the sputtering gas in the middle of the semiconductor layer forming step, the oxide semiconductor layer can be formed more efficiently.

在所述高速成膜步驟及所述低速成膜步驟中，較佳為僅供給氬氣作為濺鍍氣體來進行濺鍍。 如此，與除氬氣以外，亦供給氧氣等的情況相比，可加快成膜速度，而可更有效率地形成氧化物半導體層。再者，所謂「僅供給氬氣作為濺鍍氣體」，是指所供給的濺鍍氣體中的氬氣的濃度為99.9999%以上。In the high-speed film forming step and the low-speed film forming step, it is preferable to supply only argon gas as a sputtering gas for sputtering. In this way, compared with the case where oxygen or the like is supplied in addition to argon gas, the film formation speed can be increased, and the oxide semiconductor layer can be formed more efficiently. Furthermore, the so-called "only argon gas is supplied as sputtering gas" means that the concentration of argon gas in the sputtering gas supplied is 99.9999% or more.

較佳為在所述半導體層形成步驟中，所述高速成膜步驟中，對所述靶材施加-1 kV以上且小於-0.4 kV的負的偏壓來進行濺鍍，所述低速成膜步驟中，對所述靶材施加-0.4 kV以上且小於0 kV的負的偏壓來進行濺鍍。 如此，對靶材施加的偏壓的絕對值小至1 kV以下，因此能夠抑制氧發生脫離的濺鍍粒子的生成。其結果，於基板上形成維持與靶材材料相同的氧化物狀態的膜，可形成膜密度更高、質量更高的氧化物半導體層。Preferably, in the semiconductor layer forming step, in the high-speed film forming step, a negative bias voltage of -1 kV or more and less than -0.4 kV is applied to the target to perform sputtering, and the low-speed film forming In the step, a negative bias voltage of not less than -0.4 kV and less than 0 kV is applied to the target to perform sputtering. In this way, the absolute value of the bias voltage applied to the target material is as small as 1 kV or less, and therefore, it is possible to suppress the generation of sputtered particles from which oxygen is released. As a result, a film that maintains the same oxide state as the target material is formed on the substrate, and an oxide semiconductor layer with higher film density and higher quality can be formed.

作為構成氧化物半導體層的氧化物半導體的具體形態，可列舉IGZO。As a specific form of the oxide semiconductor constituting the oxide semiconductor layer, IGZO can be cited.

較佳為在所述高速成膜步驟及所述低速成膜步驟中，使用濺鍍裝置來進行濺鍍，所述濺鍍裝置包括：真空容器，進行真空排氣且導入氣體；基板保持部，於所述真空容器內對基板進行保持；靶材保持部，於所述真空容器內與所述基板相向且對所述靶材進行保持；以及多個天線，沿由所述基板保持部保持的所述基板的表面排列，並產生所述電漿。 藉由使用此種濺鍍裝置，可獨立地進行對天線供給的高頻電壓與對靶材施加的偏壓的設定，因此可與電漿的生成獨立地，來變更施加至靶材的偏壓的值，故能夠在濺鍍中任意地變更高速成膜步驟及低速成膜步驟。另外，可與電漿的生成獨立地，將偏壓設定為如下程度的低電壓：將電漿中的離子引入至靶材並加以濺鍍的程度。因此，可將濺鍍時對靶材施加的負的偏壓設定為-1 kV以上的小值。 [發明的效果]Preferably, in the high-speed film forming step and the low-speed film forming step, a sputtering device is used for sputtering, and the sputtering device includes: a vacuum container for performing vacuum exhaust and introducing gas; a substrate holding part, The substrate is held in the vacuum container; a target holding portion facing the substrate in the vacuum container and holding the target; and a plurality of antennas are held along the substrate holding portion The surface of the substrate is aligned, and the plasma is generated. By using this sputtering device, the high-frequency voltage supplied to the antenna and the bias voltage applied to the target can be set independently, so the bias voltage applied to the target can be changed independently from the generation of plasma Therefore, it is possible to arbitrarily change the high-speed film forming step and the low-speed film forming step during sputtering. In addition, independently of the generation of plasma, the bias voltage can be set to a low voltage of such a degree that the ions in the plasma are introduced into the target and sputtered. Therefore, the negative bias voltage applied to the target during sputtering can be set to a small value of -1 kV or more. [Effects of the invention]

根據如上所述般構成的本發明，可提供一種薄膜電晶體的製造方法，其能夠高效率地形成與其他層的界面處的氧缺失等缺陷少的氧化物半導體層。According to the present invention constituted as described above, it is possible to provide a method of manufacturing a thin film transistor that can efficiently form an oxide semiconductor layer with few defects such as oxygen deficiency at the interface with other layers.

以下，對本發明的一實施方式的薄膜電晶體及其製造方法進行說明。Hereinafter, a thin film transistor and a manufacturing method thereof according to an embodiment of the present invention will be described.

＜1.薄膜電晶體＞ 本實施方式的薄膜電晶體1為所謂的底部閘極型的薄膜電晶體。具體而言，如圖1所示，具有基板2、閘極電極3、閘極絕緣層4、作為通道層的氧化物半導體層5、源極電極6及汲極電極7，且自基板2側依序配置（形成）。以下，對各部分進行詳細敘述。＜1. Thin film transistors＞ The thin film transistor 1 of this embodiment is a so-called bottom gate type thin film transistor. Specifically, as shown in FIG. 1, it has a substrate 2, a gate electrode 3, a gate insulating layer 4, an oxide semiconductor layer 5 as a channel layer, a source electrode 6 and a drain electrode 7, and is from the substrate 2 side Sequential arrangement (formation). Hereinafter, each part will be described in detail.

基板2包含可透光的材料，例如可包含聚對苯二甲酸乙二酯（Polyethylene Terephthalate，PET）、聚萘二甲酸乙二酯（Polyethylene Naphthalate，PEN）、聚醚碸（Polyether Sulfone，PES）、丙烯酸、聚醯亞胺等的塑膠（合成樹脂）或玻璃等。The substrate 2 includes a light-transmissive material, such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyether sulfone (PES). , Acrylic, polyimide and other plastic (synthetic resin) or glass.

於基板2的表面設置有閘極電極3。閘極電極3包含具有高導電性的材料，例如可包含選自Si、Al、Mo、Cr、Ta、Ti、Pt、Au、Ag等中的一種以上的金屬。另外，亦可包含Al-Nd、Ag合金、氧化錫、氧化鋅、氧化銦、氧化銦錫（Indium Tin Oxide，ITO）、氧化銦鋅（Indium Zinc Oxide，IZO）、In-Ga-Zn-O（IGZO）等金屬氧化物的導電性膜。閘極電極3可包含該些導電性膜的單層結構或兩層以上的積層結構。A gate electrode 3 is provided on the surface of the substrate 2. The gate electrode 3 includes a material with high conductivity, and may include, for example, one or more metals selected from Si, Al, Mo, Cr, Ta, Ti, Pt, Au, Ag, and the like. In addition, it may also contain Al-Nd, Ag alloy, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (Indium Zinc Oxide, IZO), In-Ga-Zn-O (IGZO) and other conductive films of metal oxides. The gate electrode 3 may include a single-layer structure of these conductive films or a multilayer structure of two or more layers.

於閘極電極3上配置有閘極絕緣層4。閘極絕緣層4包含具有高絕緣性的材料，例如可為包含選自SiO2 、SiNx 、SiON、Al2 O3 、Y2 O3 、Ta2 O5 、Hf2 等中的一種以上的氧化物的絕緣膜。閘極絕緣層4可為將該些導電性膜設為單層結構或兩層以上的積層結構而成者。A gate insulating layer 4 is arranged on the gate electrode 3. The gate insulating layer 4 includes a material with high insulation, for example, it may include one or more selected from the group consisting of SiO 2 , SiN x , SiON, Al 2 O 3 , Y 2 O 3 , Ta 2 O 5 , Hf 2, etc. Oxide insulating film. The gate insulating layer 4 may have a single-layer structure or a laminated structure of two or more layers of these conductive films.

於閘極絕緣層4上配置有氧化物半導體層5。An oxide semiconductor layer 5 is arranged on the gate insulating layer 4.

氧化物半導體層5包含以含有In的氧化物為主成分的非晶質（amorphous）的氧化物半導體。所謂含有In的氧化物，例如是In-Ga-Zn-O、In-Al-Mg-O、In-Al-Zn-O或In-Hf-Zn-O等氧化物。再者，氧化物半導體層5為非晶質的氧化物半導體的情況例如只要是In-Ga-Zn-O（IGZO），則可藉由在所述利用X射線繞射（X-Ray Diffraction，XRD）的測定中，於2θ=31°附近不出現急劇的波峰來確認。The oxide semiconductor layer 5 includes an amorphous oxide semiconductor whose main component is an oxide containing In. The oxide containing In is, for example, an oxide such as In-Ga-Zn-O, In-Al-Mg-O, In-Al-Zn-O, or In-Hf-Zn-O. Furthermore, when the oxide semiconductor layer 5 is an amorphous oxide semiconductor, for example, as long as it is In-Ga-Zn-O (IGZO), it can be achieved by using X-ray diffraction (X-Ray Diffraction, In the XRD measurement, it was confirmed that there was no sharp peak around 2θ=31°.

氧化物半導體層5由膜密度不同的多個（此處為3個）膜積層而構成。具體而言，氧化物半導體層5包括：形成與閘極絕緣層4的界面的第一氧化物半導體膜5a、形成與源極電極6及汲極電極7的界面的第二氧化物半導體膜5b、以及配置在第一氧化物半導體膜5a與第二氧化物半導體膜5b之間的第三氧化物半導體膜5c。第一氧化物半導體膜5a及第二氧化物半導體膜5b的膜密度高於第三氧化物半導體膜5c的膜密度。第三氧化物半導體膜5c的膜厚構成為大於第一氧化物半導體膜5a及第二氧化物半導體膜5b的各者的膜厚。The oxide semiconductor layer 5 is composed of a plurality of (here, three) film layers having different film densities. Specifically, the oxide semiconductor layer 5 includes: a first oxide semiconductor film 5a forming an interface with the gate insulating layer 4, and a second oxide semiconductor film 5b forming an interface with the source electrode 6 and the drain electrode 7 , And a third oxide semiconductor film 5c disposed between the first oxide semiconductor film 5a and the second oxide semiconductor film 5b. The film density of the first oxide semiconductor film 5a and the second oxide semiconductor film 5b is higher than the film density of the third oxide semiconductor film 5c. The film thickness of the third oxide semiconductor film 5c is configured to be larger than the film thickness of each of the first oxide semiconductor film 5a and the second oxide semiconductor film 5b.

於氧化物半導體層5上配置有源極電極6及汲極電極7。源極電極6及汲極電極7分別包含具有高導電性的材料以便作為電極發揮功能。例如，可由與閘極電極3相同的材料構成，亦可由不同的材料構成。源極電極6及汲極電極7可包括金屬或導電性氧化物的單層結構，亦可包括兩層以上的積層結構。A source electrode 6 and a drain electrode 7 are arranged on the oxide semiconductor layer 5. The source electrode 6 and the drain electrode 7 each include a material having high conductivity so as to function as electrodes. For example, it may be composed of the same material as the gate electrode 3, or may be composed of a different material. The source electrode 6 and the drain electrode 7 may include a single-layer structure of metal or conductive oxide, or may include a multilayer structure of two or more layers.

於氧化物半導體層5、源極電極6及汲極電極7上可配置用以對該些進行保護的保護膜8。保護膜8例如可包含氧化矽膜（SiO2 ）、於氮化矽膜中含有氟的氟化氮化矽膜（SiN：F）等。A protective film 8 for protecting the oxide semiconductor layer 5, the source electrode 6 and the drain electrode 7 can be arranged. The protective film 8 may include, for example, a silicon oxide film (SiO 2 ), a fluorinated silicon nitride film (SiN:F) containing fluorine in the silicon nitride film, and the like.

＜2.薄膜電晶體的製造方法＞ 繼而，參照圖2（a）～圖2（d）及圖3（e）～圖3（g）對所述結構的薄膜電晶體1的製造方法進行說明。 本實施方式的薄膜電晶體1的製造方法包括閘極電極形成步驟、閘極絕緣層形成步驟、半導體層形成步驟、源極/汲極電極形成步驟。以下，對各步驟進行說明。<2. Method of manufacturing thin film transistors> Next, a method of manufacturing the thin film transistor 1 of the structure will be described with reference to FIGS. 2(a) to 2(d) and FIGS. 3(e) to 3(g). The method of manufacturing the thin film transistor 1 of this embodiment includes a gate electrode forming step, a gate insulating layer forming step, a semiconductor layer forming step, and a source/drain electrode forming step. Hereinafter, each step will be described.

（1）閘極電極形成步驟 首先，如圖2（a）所示，準備例如包含石英玻璃的基板2，並於基板2的表面形成閘極電極3。閘極電極3的形成方法並無特別限制，例如可藉由真空蒸鍍法、直流（Direct Current，DC）濺鍍法等已知的方法來形成。(1) Steps for forming gate electrode First, as shown in FIG. 2( a ), a substrate 2 made of, for example, quartz glass is prepared, and a gate electrode 3 is formed on the surface of the substrate 2. The method of forming the gate electrode 3 is not particularly limited. For example, it can be formed by a known method such as a vacuum evaporation method and a direct current (DC) sputtering method.

（2）閘極絕緣層形成步驟 繼而，如圖2（b）所示，以覆蓋基板2及閘極電極3的表面的方式形成閘極絕緣層4。閘極絕緣層4的形成方法並無特別限定，可藉由已知的方法來形成。(2) Steps for forming gate insulating layer Then, as shown in FIG. 2( b ), the gate insulating layer 4 is formed so as to cover the surfaces of the substrate 2 and the gate electrode 3. The method of forming the gate insulating layer 4 is not particularly limited, and it can be formed by a known method.

（3）半導體層形成步驟 繼而，如圖2（c）～圖3（e）所示，於閘極絕緣層4上形成作為通道層的氧化物半導體層5。所述半導體層形成步驟中，藉由使用電漿濺鍍靶材，而在閘極絕緣層4上依次成膜所述的第一氧化物半導體膜5a、第三氧化物半導體膜5c及第二氧化物半導體膜5b，從而形成氧化物半導體層5。(3) Steps for forming semiconductor layer Then, as shown in FIGS. 2( c) to 3 (e ), an oxide semiconductor layer 5 as a channel layer is formed on the gate insulating layer 4. In the semiconductor layer forming step, the first oxide semiconductor film 5a, the third oxide semiconductor film 5c, and the second oxide semiconductor film 5a are sequentially formed on the gate insulating layer 4 by using a plasma sputtering target. The oxide semiconductor film 5b is formed, thereby forming the oxide semiconductor layer 5.

（3-1）濺鍍裝置 於所述半導體層形成步驟中，可使用如圖4所示般的濺鍍裝置100，所述濺鍍裝置100使用感應耦合型的電漿P來濺鍍靶材T。濺鍍裝置100包括：真空容器20；基板保持部30，於真空容器20內對基板2進行保持；靶材保持部40，於真空容器20內與基板2相向且對靶材T進行保持；多個天線50，沿由基板保持部30保持的基板2的表面排列，並產生電漿P；高頻電源60，向多個天線50施加用於在真空容器20內生成感應耦合型的電漿P的高頻；以及靶材偏置電源11，向靶材T施加靶材偏壓。藉由使用此種濺鍍裝置100，可獨立地進行對天線50供給的高頻電壓與靶材T的偏壓的設定。因此，可與電漿P的生成獨立地，將偏壓設定為如下程度的低電壓：將電漿中的離子引入至靶材並加以濺鍍的程度，且可將濺鍍時對靶材T施加的負的偏壓設定為-1 kV以上（即絕對值為1 kV以下）的負電壓。進而，可與電漿P的生成獨立地，在濺鍍中任意地變更施加至靶材T的偏壓的值。將靶材（例如IGZO）T配置於濺鍍裝置100的靶材保持部40並將基板2配置於基板保持部30來進行濺鍍。(3-1) Sputtering device In the semiconductor layer forming step, a sputtering device 100 as shown in FIG. 4 can be used, and the sputtering device 100 uses an inductively coupled plasma P to sputter the target T. The sputtering device 100 includes: a vacuum vessel 20; a substrate holding portion 30 that holds the substrate 2 in the vacuum vessel 20; a target holding portion 40 that faces the substrate 2 in the vacuum vessel 20 and holds the target material T; more A plurality of antennas 50 are arranged along the surface of the substrate 2 held by the substrate holding portion 30 to generate plasma P; a high-frequency power source 60 is applied to the plurality of antennas 50 for generating inductive coupling type plasma P in the vacuum container 20 And the target bias power supply 11 applies a target bias voltage to the target T. By using such a sputtering apparatus 100, the high-frequency voltage supplied to the antenna 50 and the bias voltage of the target T can be set independently. Therefore, independently of the generation of the plasma P, the bias voltage can be set to a low voltage such that the ions in the plasma are introduced into the target material and sputtered, and the target material T can be sputtered during sputtering. The applied negative bias voltage is set to a negative voltage above -1 kV (that is, the absolute value is below 1 kV). Furthermore, independently of the generation of the plasma P, the value of the bias voltage applied to the target T can be arbitrarily changed during sputtering. A target (for example, IGZO) T is arranged in the target holding portion 40 of the sputtering apparatus 100 and the substrate 2 is arranged in the substrate holding portion 30 to perform sputtering.

（3-2）高速成膜步驟及低速成膜步驟 在本實施方式的半導體層形成步驟中，包括：高速成膜步驟，對靶材T施加規定值的負的偏壓來進行濺鍍；以及低速成膜步驟（第一低速成膜步驟及第二低速成膜步驟），對靶材T施加絕對值較在高速成膜步驟中施加的偏壓小的負的偏壓來進行濺鍍。如圖5所示，藉由變更對靶材T施加的偏壓的大小，能夠在高速成膜步驟中高速地成膜膜密度相對低的氧化物半導體膜，在低速成膜步驟中低速地成膜膜密度相對高的氧化物半導體膜。藉由組合該些成膜步驟，變更施加於靶材T的偏壓來進行濺鍍，從而能夠有效率地形成具有與其他層的界面處的膜密度高的氧化物半導體膜的氧化物半導體層5。(3-2) High-speed film forming steps and low-speed film forming steps The semiconductor layer formation step of this embodiment includes: a high-speed film formation step, applying a predetermined value of negative bias to the target T to perform sputtering; and a low-speed film formation step (the first low-speed film formation step and the second low-speed film formation step). In the low-speed film forming step), sputtering is performed by applying a negative bias voltage having an absolute value smaller than the bias voltage applied in the high-speed film forming step to the target material T. As shown in FIG. 5, by changing the magnitude of the bias voltage applied to the target material T, an oxide semiconductor film with a relatively low film density can be formed at a high speed in a high-speed film formation step, and an oxide semiconductor film with a relatively low film density can be formed at a low speed in a low-speed film formation step. An oxide semiconductor film with a relatively high film density. By combining these film forming steps and changing the bias voltage applied to the target T to perform sputtering, it is possible to efficiently form an oxide semiconductor layer having an oxide semiconductor film with a high film density at the interface with other layers 5.

（3-2-1）第一低速成膜步驟 如圖2（c）所示，首先，藉由第一低速成膜步驟，於閘極絕緣層4上形成第一氧化物半導體膜5a。具體而言，將濺鍍裝置100的真空容器20真空排氣至3×10-6 Torr以下後，一邊以50 sccm以上、200 sccm以下導入濺鍍氣體90，一邊將真空容器20內的壓力調整為0.5 Pa以上、3.1 Pa以下。然後，對多個天線50供給1 kW以上、10 kW以下的高頻電力來生成感應耦合型的電漿，並對其進行維持。對靶材施加直流電壓脈衝來進行靶材的濺鍍。(3-2-1) The first low-speed film forming step is shown in FIG. 2(c). First, the first low-speed film forming step is used to form the first oxide semiconductor film 5a on the gate insulating layer 4. Specifically, after evacuating the vacuum container 20 of the sputtering apparatus 100 to 3×10 -6 Torr or less, while introducing the sputtering gas 90 at 50 sccm or more and 200 sccm or less, the pressure in the vacuum container 20 is adjusted It is 0.5 Pa or more and 3.1 Pa or less. Then, high-frequency power of 1 kW or more and 10 kW or less is supplied to the plurality of antennas 50 to generate and maintain inductively coupled plasma. A DC voltage pulse is applied to the target material to sputter the target material.

此處，在第一低速成膜步驟中，自在與閘極絕緣層4的界面處形成膜密度高的氧化物半導體膜的觀點出發，較佳為使施加於靶材T的電壓與高速成膜步驟中施加的偏壓相比絕對值變小，具體而言，較佳為-0.4 kV以上且小於0 V的負電壓。再者，真空容器20內的壓力、濺鍍氣體的流量、供給至天線的電力量等偏壓值以外的濺鍍條件可適當變更。Here, in the first low-speed film formation step, from the viewpoint of forming an oxide semiconductor film with a high film density at the interface with the gate insulating layer 4, it is preferable to make the voltage applied to the target T and the high-speed film formation The bias voltage applied in the step becomes smaller than the absolute value. Specifically, it is preferably a negative voltage greater than -0.4 kV and less than 0 V. In addition, sputtering conditions other than the bias value, such as the pressure in the vacuum container 20, the flow rate of the sputtering gas, and the amount of electric power supplied to the antenna, can be changed as appropriate.

（3-2-2）高速成膜步驟 於第一低速成膜步驟之後，藉由高速成膜步驟，如圖2（d）所示，於第一氧化物半導體膜5a上形成第三氧化物半導體膜5c。具體而言，與第一低速成膜步驟同樣地使用濺鍍裝置100來進行靶材T的濺鍍，藉此形成第三氧化物半導體膜5c。(3-2-2) High-speed film forming steps After the first low-speed film forming step, a high-speed film forming step is performed, as shown in FIG. 2(d), to form a third oxide semiconductor film 5c on the first oxide semiconductor film 5a. Specifically, the sputtering device 100 is used to sputter the target material T in the same manner as in the first low-speed film formation step, thereby forming the third oxide semiconductor film 5c.

在所述高速成膜步驟中，自提高成膜速度的觀點出發，較佳為使施加於靶材T的偏壓與在第一低速成膜步驟及第二低速成膜步驟中施加的偏壓相比絕對值變大，具體而言為-1 kV以上且小於-0.4 kV的負電壓。高速成膜步驟中的施加於靶材T的偏壓以外的濺鍍條件可與第一低速成膜步驟不同，但自提高成膜速度的觀點出發，較佳為與第一低速成膜步驟相同。In the high-speed film-forming step, from the viewpoint of increasing the film-forming speed, it is preferable that the bias voltage applied to the target material T be the same as the bias voltage applied in the first low-speed film-forming step and the second low-speed film-forming step The absolute value becomes larger than the absolute value, specifically, it is a negative voltage of -1 kV or more and less than -0.4 kV. The sputtering conditions other than the bias applied to the target material T in the high-speed film formation step may be different from the first low-speed film formation step, but from the viewpoint of increasing the film formation speed, it is preferably the same as the first low-speed film formation step .

（3-2-3）第二低速成膜步驟 在高速成膜步驟之後，藉由第二低速成膜步驟，如圖3（e）所示，在第三氧化物半導體膜5c上形成第二氧化物半導體膜5b。具體而言，與第一低速成膜步驟及高速成膜步驟同樣地，使用濺鍍裝置100進行靶材T的濺鍍，藉此形成第二氧化物半導體膜5b。(3-2-3) The second low-speed film forming step After the high-speed film formation step, a second low-speed film formation step is performed, as shown in FIG. 3(e), to form a second oxide semiconductor film 5b on the third oxide semiconductor film 5c. Specifically, similarly to the first low-speed film formation step and the high-speed film formation step, the sputtering device 100 is used to sputter the target T, thereby forming the second oxide semiconductor film 5b.

在所述第二低速成膜步驟中，自於與源極電極6及汲極電極7的界面處形成膜密度高的氧化物半導體膜的觀點出發，使施加至靶材T的電壓與高速成膜步驟中施加的偏壓相比絕對值變小，具體而言成為-0.4 kV以上且小於0 V的負電壓。再者，第二低速成膜步驟中施加於靶材T的偏壓的值可與第一低速成膜步驟中施加於靶材T的偏壓的值相同，亦可不同。第二低速成膜步驟中的、施加於靶材T的偏壓以外的濺鍍條件可與高速成膜步驟不同，但自提高成膜速度的觀點出發，較佳為與高速成膜步驟相同。In the second low-speed film forming step, from the viewpoint of forming an oxide semiconductor film with a high film density at the interface with the source electrode 6 and the drain electrode 7, the voltage applied to the target T is made to be high-speed The bias voltage applied in the filming step becomes smaller than the absolute value, and specifically becomes a negative voltage of -0.4 kV or more and less than 0 V. Furthermore, the value of the bias voltage applied to the target material T in the second low-speed film forming step may be the same as or different from the value of the bias voltage applied to the target material T in the first low-speed film forming step. The sputtering conditions other than the bias voltage applied to the target T in the second low-speed film-forming step may be different from the high-speed film-forming step, but from the viewpoint of increasing the film-forming speed, it is preferably the same as the high-speed film-forming step.

（3-3）濺鍍氣體 自高效率地形成氧化物半導體層5的觀點出發，在本實施方式中，較佳為在高速成膜步驟及低速成膜步驟中所供給的濺鍍氣體的組成相同，更佳為濺鍍氣體中所含的氧氣濃度以體積分率計為2 vol%以下，進而佳為僅供給氬氣（即，體積分率為99.999 vol%以上）作為濺鍍氣體。(3-3) Sputtering gas From the viewpoint of efficiently forming the oxide semiconductor layer 5, in this embodiment, the composition of the sputtering gas supplied in the high-speed film formation step and the low-speed film formation step is preferably the same, and the sputtering gas is more preferred The oxygen concentration contained in it is 2 vol% or less in volume fraction, and it is more preferable to supply only argon gas (that is, 99.999 vol% or more in volume fraction) as the sputtering gas.

（3-4）濺鍍時間 另外，自高效率地形成氧化物半導體層5的觀點出發，在本實施方式中，較佳為在低速成膜步驟中進行濺鍍的時間較在高速成膜步驟中進行濺鍍的時間短。在各低速成膜步驟中，只要以能夠形成具有約10 nm以上的膜厚的氧化物半導體膜的程度進行濺鍍即可。(3-4) Sputtering time In addition, from the viewpoint of efficiently forming the oxide semiconductor layer 5, in this embodiment, the time for sputtering in the low-speed film formation step is preferably shorter than the time for sputtering in the high-speed film formation step. In each low-speed film formation step, sputtering may be performed to the extent that an oxide semiconductor film having a film thickness of about 10 nm or more can be formed.

（4）源極/汲極電極形成步驟 繼而，如圖3（f）所示，於氧化物半導體層5上形成源極電極6及汲極電極7。源極電極6及汲極電極7的形成例如可藉由使用射頻（Radio Frequency，RF）磁控濺鍍等的已知的方法來形成。(4) Steps for forming source/drain electrodes Then, as shown in FIG. 3( f ), a source electrode 6 and a drain electrode 7 are formed on the oxide semiconductor layer 5. The source electrode 6 and the drain electrode 7 can be formed by, for example, a known method using radio frequency (RF) magnetron sputtering or the like.

其他 其後，如圖3（g）所示，例如可利用電漿化學氣相沈積（chemical vapor deposition，CVD）法以覆蓋所形成的氧化物半導體層5、源極電極6以及汲極電極7的上表面的方式形成保護膜8。另外，視需要可在包含氧的大氣壓下的環境中進行熱處理。other Thereafter, as shown in FIG. 3(g), for example, a plasma chemical vapor deposition (chemical vapor deposition, CVD) method may be used to cover the formed oxide semiconductor layer 5, the source electrode 6 and the drain electrode 7 The protective film 8 is formed on the upper surface. In addition, if necessary, the heat treatment may be performed in an atmosphere under an atmospheric pressure containing oxygen.

藉由以上，可獲得本實施方式的薄膜電晶體1。Through the above, the thin film transistor 1 of this embodiment can be obtained.

＜3.靶材電壓與膜密度及成膜速度的關係＞ 使用所述本實施方式的濺鍍裝置100，確認了施加於靶材T的偏壓的大小與所成膜的氧化物半導體膜的膜密度及成膜速度的關係。＜3. The relationship between target voltage, film density and film forming speed＞ Using the sputtering apparatus 100 of the present embodiment described above, the relationship between the magnitude of the bias voltage applied to the target T, the film density of the formed oxide semiconductor film, and the film formation speed was confirmed.

具體而言，在對濺鍍裝置100的真空容器20進行真空排氣之後，僅供給氬氣作為濺鍍氣體，將真空容器20內的壓力調整為1.33 Pa。然後，對多個天線50供給7 kW的高頻電力，生成感應耦合型的電漿，並對其進行維持。作為靶材T使用IGZO（1114），向靶材T施加直流電壓脈衝進行濺鍍。一邊變更施加於靶材T的偏壓的大小一邊進行成膜，測定各偏壓下的成膜速度、以及所成膜的氧化物半導體膜的膜密度。膜密度的測定採用X射線反射率法（（X-Ray Reflectivity，XRR）法、測定儀器：布魯克（Bruker）公司 D8 迪斯卡沃（DISCOVER））進行。將其結果示於圖6。Specifically, after the vacuum container 20 of the sputtering apparatus 100 is evacuated, only argon is supplied as the sputtering gas, and the pressure in the vacuum container 20 is adjusted to 1.33 Pa. Then, 7 kW of high-frequency power is supplied to the plurality of antennas 50 to generate and maintain inductively coupled plasma. IGZO (1114) was used as the target T, and a DC voltage pulse was applied to the target T to perform sputtering. The film formation was performed while changing the magnitude of the bias voltage applied to the target T, and the film formation speed under each bias voltage and the film density of the formed oxide semiconductor film were measured. The film density is measured by X-ray reflectivity (X-Ray Reflectivity, XRR) method, measuring instrument: Bruker D8 DISCOVER). The results are shown in Fig. 6.

由圖6可知，可確認到雖然越使靶材電壓變大，氧化物半導體膜的成膜速度變得越大，但其膜密度變小。另一方面，可知雖然越使靶材電壓變小，氧化物半導體膜的成膜速度變得越小，但其膜密度變大，接近IGZO的1114單相結晶的理論密度（6.378 g/cm3 ）。It can be seen from FIG. 6 that although the higher the target voltage, the higher the deposition rate of the oxide semiconductor film, the lower the film density. On the other hand, it can be seen that although the film formation rate of the oxide semiconductor film becomes smaller as the target voltage becomes smaller, the film density becomes larger, which is close to the theoretical density of 1114 single-phase crystal of IGZO (6.378 g/cm 3 ).

＜4.本實施方式的效果＞ 根據如上所述般的本實施方式的薄膜電晶體1的製造方法，由於在形成與其他層的界面的半導體形成步驟的初始階段及最終階段藉由低速成膜步驟進行濺鍍，因此能夠在與閘極絕緣層4之間的界面處形成膜密度高且缺陷少的第一氧化物半導體膜5a，在與源極電極6及汲極電極7以及保護膜8之間的界面處形成膜密度高且缺陷少的第二氧化物半導體膜5b。而且，在使氧化物半導體層5生長的塊體階段，由於藉由高速成膜步驟進行濺鍍，故能夠高效率地使氧化物半導體層5成長。藉此，能夠高效率地形成與其他層的界面處的氧缺失等缺陷少的氧化物半導體層5，從而製造具有高信賴性的薄膜電晶體1。<4. Effects of this embodiment> According to the method of manufacturing the thin film transistor 1 of the present embodiment as described above, since sputtering is performed by the low-speed film formation step in the initial and final stages of the semiconductor formation step that forms the interface with other layers, it can A first oxide semiconductor film 5a with a high film density and few defects is formed at the interface between the gate insulating layers 4, and a high film density is formed at the interface with the source electrode 6 and the drain electrode 7 and the protective film 8. And the second oxide semiconductor film 5b with few defects. Furthermore, in the bulk stage of growing the oxide semiconductor layer 5, since sputtering is performed by a high-speed film forming step, the oxide semiconductor layer 5 can be grown efficiently. Thereby, the oxide semiconductor layer 5 with few defects such as oxygen deficiency at the interface with other layers can be formed efficiently, and the thin film transistor 1 with high reliability can be manufactured.

＜5.其他變形實施方式＞ 再者，本發明並不限定於所述實施方式。<5. Other modified implementation methods> In addition, this invention is not limited to the said embodiment.

所述實施方式的薄膜電晶體1是自基板2側依次積層有閘極電極3、閘極絕緣層4及氧化物半導體層5的底部閘極型的薄膜電晶體，但並不限於此。在其他實施方式中，如圖7所示，薄膜電晶體1亦可為自基板2側起依次積層有氧化物半導體層5、閘極絕緣層4及閘極電極3的頂部閘極型的薄膜電晶體。The thin film transistor 1 of the above embodiment is a bottom gate type thin film transistor in which a gate electrode 3, a gate insulating layer 4, and an oxide semiconductor layer 5 are sequentially laminated from the substrate 2 side, but it is not limited to this. In other embodiments, as shown in FIG. 7, the thin film transistor 1 may also be a top gate type thin film in which an oxide semiconductor layer 5, a gate insulating layer 4, and a gate electrode 3 are sequentially laminated from the substrate 2 side. Transistor.

所述實施方式的製造方法在氧化物半導體層形成步驟中，隔著高速成膜步驟進行兩次低速成膜步驟，但不限於此。在其他實施方式中，亦可依次各進行一次高速成膜步驟及低速成膜步驟。在此種情況下，在薄膜電晶體1是底部閘極型的情況下，較佳為首先進行低速成膜步驟，繼而進行高速成膜步驟。另一方面，在薄膜電晶體1是頂部閘極型的情況下，較佳為首先進行高速成膜步驟，繼而進行低速成膜步驟。如此，能夠在與閘極絕緣層4的界面處形成膜密度相對高的氧化物半導體膜。In the manufacturing method of the above-mentioned embodiment, in the oxide semiconductor layer forming step, the low-speed film-forming step is performed twice via the high-speed film-forming step, but it is not limited to this. In other embodiments, the high-speed film-forming step and the low-speed film-forming step may be sequentially performed once. In this case, when the thin film transistor 1 is of a bottom gate type, it is preferable to perform a low-speed film formation step first, and then perform a high-speed film formation step. On the other hand, in the case where the thin film transistor 1 is of a top gate type, it is preferable to perform a high-speed film formation step first, and then a low-speed film formation step. In this way, an oxide semiconductor film with a relatively high film density can be formed at the interface with the gate insulating layer 4.

在高速成膜步驟及低速成膜步驟中對靶材T施加的偏壓的值在各步驟中可固定，亦可不固定。The value of the bias voltage applied to the target material T in the high-speed film forming step and the low-speed film forming step may or may not be fixed in each step.

於所述實施方式中，為具有多個靶材保持部40的構成，但亦可為具有一個靶材保持部40的構成。該情況下，亦理想的是具有多個天線50的構成，但是亦可為具有一個天線50的構成。In the above-mentioned embodiment, the structure has a plurality of target holding portions 40, but a structure having one target holding portion 40 may also be used. In this case, it is also desirable to have a configuration with a plurality of antennas 50, but a configuration with one antenna 50 may also be used.

另外，本發明並不限定於所述實施方式，於不脫離其主旨的範圍內當然可進行各種變形。In addition, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the gist of the present invention.

1:薄膜電晶體 2:基板 3:閘極電極 4:閘極絕緣層 5:氧化物半導體層 5a:第一氧化物半導體膜 5b:第二氧化物半導體膜 5c:第三氧化物半導體膜 6:源極電極 7:汲極電極 8:保護膜 11:靶材偏置電源 20:真空容器 30:基板保持部 40:靶材保持部 50:天線 60:高頻電源 90:濺鍍氣體 100:濺鍍裝置 P:電漿 T:靶材1: Thin film transistor 2: substrate 3: Gate electrode 4: Gate insulation layer 5: Oxide semiconductor layer 5a: First oxide semiconductor film 5b: Second oxide semiconductor film 5c: third oxide semiconductor film 6: Source electrode 7: Drain electrode 8: Protective film 11: Target bias power supply 20: Vacuum container 30: Board holding part 40: Target holding part 50: Antenna 60: High frequency power supply 90: Sputtering gas 100: Sputtering device P: Plasma T: target

圖1是示意性表示本實施方式的薄膜電晶體的構成的縱剖面圖。 圖2（a）～圖2（d）是示意性表示相同實施方式的薄膜電晶體的製造步驟的剖面圖。 圖3（e）～圖3（g）是示意性表示相同實施方式的薄膜電晶體的製造步驟的剖面圖。 圖4是示意性表示於相同實施方式的薄膜電晶體的半導體層形成步驟中使用的濺鍍裝置的構成的圖。 圖5是示意性表示相同實施方式的半導體層形成步驟的流程的圖。 圖6是表示靶材電壓與膜密度及成膜速度的關係的圖表。 圖7是示意性表示另一實施方式的薄膜電晶體的構成的縱剖面圖。FIG. 1 is a longitudinal sectional view schematically showing the structure of the thin film transistor of the present embodiment. 2(a) to 2(d) are cross-sectional views schematically showing the manufacturing steps of the thin film transistor of the same embodiment. 3(e) to 3(g) are cross-sectional views schematically showing the manufacturing steps of the thin film transistor of the same embodiment. 4 is a diagram schematically showing the configuration of a sputtering apparatus used in the semiconductor layer forming step of the thin film transistor of the same embodiment. FIG. 5 is a diagram schematically showing the flow of the semiconductor layer forming step in the same embodiment. Fig. 6 is a graph showing the relationship between the target voltage, the film density, and the film formation speed. FIG. 7 is a longitudinal sectional view schematically showing the structure of a thin film transistor of another embodiment.

Claims (8)

一種薄膜電晶體的製造方法，製造於基板上積層有閘極電極、閘極絕緣層、氧化物半導體層、源極電極及汲極電極的薄膜電晶體，且所述薄膜電晶體的製造方法包括藉由使用電漿來濺鍍靶材而形成所述氧化物半導體層的半導體層形成步驟，所述半導體層形成步驟包括：高速成膜步驟，對所述靶材施加規定值的偏壓來進行濺鍍；以及低速成膜步驟，對所述靶材施加絕對值較所述規定值小的偏壓來進行濺鍍，在所述半導體層形成步驟中，在進行所述低速成膜步驟之後進行所述高速成膜步驟，其後進而進行所述低速成膜步驟。 A method for manufacturing a thin film transistor, a thin film transistor having a gate electrode, a gate insulating layer, an oxide semiconductor layer, a source electrode, and a drain electrode laminated on a substrate, and the method for manufacturing the thin film transistor includes A semiconductor layer forming step of forming the oxide semiconductor layer by sputtering a target material using plasma, the semiconductor layer forming step includes: a high-speed film forming step, which is performed by applying a predetermined value of a bias voltage to the target material Sputtering; and a low-speed film forming step of applying a bias voltage having an absolute value smaller than the predetermined value to the target to perform sputtering, and in the semiconductor layer forming step, performing the low-speed film forming step The high-speed film forming step is followed by the low-speed film forming step. 如請求項1所述的薄膜電晶體的製造方法，其中所述低速成膜步驟中的濺鍍時間較所述高速成膜步驟中的濺鍍時間短。 The method of manufacturing a thin film transistor according to claim 1, wherein the sputtering time in the low-speed film forming step is shorter than the sputtering time in the high-speed film forming step. 如請求項1或請求項2所述的薄膜電晶體的製造方法，其中在所述高速成膜步驟及所述低速成膜步驟中，使用相同組成的靶材進行濺鍍。 The method of manufacturing a thin film transistor according to claim 1 or claim 2, wherein in the high-speed film forming step and the low-speed film forming step, sputtering is performed using a target material of the same composition. 如請求項1或請求項2所述的薄膜電晶體的製造方法，其中在所述高速成膜步驟及所述低速成膜步驟中，供給相同組成的濺鍍氣體進行濺鍍。 The method for manufacturing a thin film transistor according to claim 1 or claim 2, wherein in the high-speed film forming step and the low-speed film forming step, sputtering gas of the same composition is supplied for sputtering. 如請求項4所述的薄膜電晶體的製造方法，其中在所述高速成膜步驟及所述低速成膜步驟中，僅供給氬氣作為濺鍍氣體來進行濺鍍。 The method of manufacturing a thin film transistor according to claim 4, wherein in the high-speed film forming step and the low-speed film forming step, only argon gas is supplied as a sputtering gas for sputtering. 如請求項1或請求項2所述的薄膜電晶體的製造方法，其中所述高速成膜步驟中，對所述靶材施加-1kV以上且小於-0.4kV的負的偏壓來進行濺鍍，所述低速成膜步驟中，對所述靶材施加-0.4kV以上且小於0kV的負的偏壓來進行濺鍍。 The method of manufacturing a thin film transistor according to claim 1 or claim 2, wherein in the high-speed film forming step, a negative bias voltage of -1 kV or more and less than -0.4 kV is applied to the target to perform sputtering In the low-speed film forming step, a negative bias voltage of -0.4 kV or more and less than 0 kV is applied to the target to perform sputtering. 如請求項1或請求項2所述的薄膜電晶體的製造方法，其中構成氧化物半導體層的氧化物半導體為IGZO。 The method of manufacturing a thin film transistor according to claim 1 or 2, wherein the oxide semiconductor constituting the oxide semiconductor layer is IGZO. 如請求項1或請求項2所述的薄膜電晶體的製造方法，其中在所述高速成膜步驟及所述低速成膜步驟中，使用濺鍍裝置來進行濺鍍，所述濺鍍裝置包括：真空容器，進行真空排氣且導入氣體；基板保持部，於所述真空容器內對所述基板進行保持；靶材保持部，於所述真空容器內與所述基板相向且對所述靶材進行保持；以及多個天線，沿由所述基板保持部保持的所述基板的表面排列，並產生所述電漿。 The method of manufacturing a thin film transistor according to claim 1 or claim 2, wherein in the high-speed film forming step and the low-speed film forming step, sputtering is performed using a sputtering device, the sputtering device comprising ：Vacuum container for vacuum exhaust and gas introduction; substrate holding part for holding the substrate in the vacuum container; target holding part for facing the substrate and facing the target in the vacuum container And a plurality of antennas are arranged along the surface of the substrate held by the substrate holding portion and generate the plasma.
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