TWI745794B - Amplifier linearization apparatus - Google Patents

Abstract

The present invention provides an amplifier linearization apparatus, comprising an amplifier and a linearizer, the linearizer comprising a first transistor, the first transistor comprising a first terminal coupled to an input of the amplifier, a second terminal configured to be coupled to a DC supply voltage, and a control terminal configured to control a current flowing between the first and second terminals and configured to receive a DC bias voltage different from a voltage of the first terminal.

Description

放大器線性化裝置Amplifier linearization device

本發明涉及放大器，更具體地，涉及通過使用線性化器（linearizer）來改善放大器的線性度。The present invention relates to amplifiers, and more specifically, to improving the linearity of amplifiers by using a linearizer.

功率放大器是已知的用於增加交流（Alternating Current，AC）信號功率的電子設備。通常，放大器使用來自直流（Direct Current，DC）電源的電能將輸入到放大器的AC信號的電壓幅度乘以增益因數，並提供相乘後的信號作為輸出。A power amplifier is a known electronic device used to increase the power of an alternating current (AC) signal. Generally, an amplifier uses electrical energy from a direct current (DC) power supply to multiply the voltage amplitude of an AC signal input to the amplifier by a gain factor, and provide the multiplied signal as an output.

期望放大器在盡可能寬的電壓幅度範圍內線性地操作。在放大器線性操作的輸入電壓範圍內，放大器輸出的交流信號與輸入的交流信號按照增益因數成比例，其中增益因數在該輸入電壓範圍內恒定。在增益因數非恒定的輸入電壓範圍內，放大器非線性地操作，而這種非線性是不希望的。It is desirable for the amplifier to operate linearly in the widest possible voltage amplitude range. In the input voltage range of the linear operation of the amplifier, the AC signal output by the amplifier is proportional to the input AC signal according to the gain factor, wherein the gain factor is constant within the input voltage range. In the input voltage range where the gain factor is not constant, the amplifier operates non-linearly, and such non-linearity is undesirable.

因此，本發明的目的是提供一種改善放大器的線性度的技術，其中通過使用線性化器（linearizer）來補償放大器的非線性，以解決上述問題。Therefore, the object of the present invention is to provide a technique for improving the linearity of an amplifier, in which a linearizer is used to compensate the nonlinearity of the amplifier to solve the above-mentioned problem.

根據本發明的一個實施例，提供了一種放大器線性化裝置，包括放大器和線性化器。所述線性化器包括第一電晶體，第一電晶體包括耦接至放大器的輸入端的第一端子、耦接到直流電源的第二端子、以及控制端子，控制端子被配置為控制在第一端子和第二端子之間流動的電流以及接收與第一端子的電壓不同的直流偏置電壓。According to an embodiment of the present invention, there is provided an amplifier linearization device, including an amplifier and a linearizer. The linearizer includes a first transistor, the first transistor includes a first terminal coupled to the input of the amplifier, a second terminal coupled to a DC power supply, and a control terminal, the control terminal is configured to control the first terminal The current flowing between the terminal and the second terminal and receiving a DC bias voltage different from the voltage of the first terminal.

根據本發明的另一個實施例，提供了一種放大器線性化裝置，包括放大器和線性化器。所述放大器包括輸入端、輸出端以及耦接在輸入端和輸出端之間的第一組電晶體，所述第一組電晶體包括一個或多個電晶體。所述線性化器包括耦接在直流電源和放大器的輸入端之間的第二組電晶體，所述第二組電晶體包括一個或多個電晶體。其中第一組電晶體和第二組電晶體具有相同的拓撲結構。According to another embodiment of the present invention, there is provided an amplifier linearization device, including an amplifier and a linearizer. The amplifier includes an input terminal, an output terminal, and a first group of transistors coupled between the input terminal and the output terminal. The first group of transistors includes one or more transistors. The linearizer includes a second set of transistors coupled between the DC power supply and the input terminal of the amplifier, and the second set of transistors includes one or more transistors. The first group of transistors and the second group of transistors have the same topological structure.

本發明中通過使用線性化器來補償放大器，使得線性化器和放大器結合在一起具有改善的整體線性度。In the present invention, the linearizer is used to compensate the amplifier, so that the linearizer and the amplifier are combined to have an improved overall linearity.

在閱讀了在各個附圖和附圖中示出的優選實施例的以下詳細描述之後，本發明的這些和其他目的將對本領域習知技藝者變得顯而易見。These and other objects of the present invention will become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments shown in the respective drawings and drawings.

放大器的實現，例如在射頻（radio-frequency，RF）傳輸系統中使用的功率放大器的實現，將會涉及到放大器的效率和線性度之間的折衷。具有更好線性度的放大器通常具有較差的工作效率，通常會將一半以上的全部運行功率耗散為熱量，而不是轉化到放大器輸出的AC信號中。例如，與C類（class C）功率放大器相比，A類功率放大器可以在很大範圍的輸入電壓上線性操作，但其工作效率低於50％，甚至常常低於10％。具有更好工作效率的放大器通常具有較差的線性度，其增益因數恒定的電壓範圍相對較小。例如，C類功率放大器可以以高達70％或更高的效率工作，但與A類放大器相比，在顯著減小的輸入電壓範圍內線性工作。因此，放大器的選擇涉及效率和線性度之間的權衡。The realization of amplifiers, such as the realization of power amplifiers used in radio-frequency (RF) transmission systems, will involve a trade-off between amplifier efficiency and linearity. Amplifiers with better linearity usually have poor operating efficiency, and usually dissipate more than half of all operating power as heat instead of converting it into the AC signal output by the amplifier. For example, compared with class C (class C) power amplifiers, class A power amplifiers can operate linearly over a wide range of input voltages, but their operating efficiency is less than 50%, and often even less than 10%. Amplifiers with better operating efficiency generally have poor linearity and a relatively small voltage range with a constant gain factor. For example, a class C power amplifier can operate at efficiencies as high as 70% or higher, but compared to a class A amplifier, it operates linearly in a significantly reduced input voltage range. Therefore, the choice of amplifier involves a trade-off between efficiency and linearity.

本發明提出了通過使用線性化器（linearizer）來補償放大器以改善具有非線性放大器的系統中的線性度的技術。線性化器可以耦接到放大器的輸入端，並且用於為放大器的輸入端處接收的AC信號提供非恒定的阻抗傳遞函數（impedance transfer function）。線性化器的非恒定阻抗傳遞函數可以在輸入電壓範圍內補償放大器的非線性回應。例如，如果放大器的增益因數由於放大器的非線性而在特定電壓範圍內增加，則線性化器的阻抗傳遞函數可以通過在電壓範圍內減小來進行補償，使得線性化器與放大器一起的整體線性度在整個電壓範圍內得到改善。因此，與單獨的放大器相比，線性化器和放大器結合在一起可以被實現為具有改善的整體線性度。The present invention proposes a technique of improving the linearity in a system with a nonlinear amplifier by using a linearizer to compensate the amplifier. The linearizer may be coupled to the input terminal of the amplifier and used to provide a non-constant impedance transfer function for the AC signal received at the input terminal of the amplifier. The non-constant impedance transfer function of the linearizer can compensate the nonlinear response of the amplifier within the input voltage range. For example, if the gain factor of the amplifier increases within a certain voltage range due to the non-linearity of the amplifier, the impedance transfer function of the linearizer can be compensated by decreasing within the voltage range, so that the linearizer and the amplifier are overall linear The degree is improved over the entire voltage range. Therefore, compared with a separate amplifier, the linearizer and the amplifier can be combined to have an improved overall linearity.

第1A圖是例示根據一些實施例的示例系統100的框圖，系統100包括由線性化器110補償的放大器130。線性化器110與放大器130並行耦接。系統100的輸入端102a和102b耦接至線性化器110和放大器130中的每一個，系統100的輸出端104a和104b耦接至放大器130。在一些實施例中，如第1A圖中的虛線所示，輸出端104a和104b可以耦接到線性化器110。FIG. 1A is a block diagram illustrating an example system 100 according to some embodiments. The system 100 includes an amplifier 130 compensated by a linearizer 110. The linearizer 110 and the amplifier 130 are coupled in parallel. The input terminals 102 a and 102 b of the system 100 are coupled to each of the linearizer 110 and the amplifier 130, and the output terminals 104 a and 104 b of the system 100 are coupled to the amplifier 130. In some embodiments, the output terminals 104a and 104b may be coupled to the linearizer 110 as shown by the dashed line in FIG. 1A.

線性化器110和放大器130耦接在輸入端102a和102b與輸出端104a和104b之間。作為非限制性示例，輸入端102a和102b可以耦接到基帶至RF的混頻器，輸出端104a和104b可以耦接到RF天線。在輸入端102a和102b處接收的以及在輸出端104a和104b處產生的AC信號可以是差動信號，其中在輸入端102a處接收的以及在輸出端104a處產生的是高值（+）信號，在輸入端102b處接收的以及在輸出端104b處產生的是低值（-）信號。備選地，AC信號可以是單端信號。例如，可以不包括輸入端102b和輸出端104b，或者輸入端102b和輸出端104b可以連接到固定的參考電壓。The linearizer 110 and the amplifier 130 are coupled between the input terminals 102a and 102b and the output terminals 104a and 104b. As a non-limiting example, the input terminals 102a and 102b may be coupled to a baseband to RF mixer, and the output terminals 104a and 104b may be coupled to an RF antenna. The AC signals received at the input terminals 102a and 102b and generated at the output terminals 104a and 104b may be differential signals, where the AC signals received at the input terminal 102a and generated at the output terminal 104a are high value (+) signals The signal received at the input terminal 102b and generated at the output terminal 104b is a low value (-) signal. Alternatively, the AC signal may be a single-ended signal. For example, the input terminal 102b and the output terminal 104b may not be included, or the input terminal 102b and the output terminal 104b may be connected to a fixed reference voltage.

放大器130可以用於將輸入端102a和102b處接收的信號乘以增益因數，並將結果提供至輸出端104a和104b。放大器130可以包括一個或多個電晶體，可以基於電晶體的配置，例如電晶體的放置位置和連接方式以及電壓偏置條件，來設置放大器130的增益因數。The amplifier 130 may be used to multiply the signals received at the input terminals 102a and 102b by a gain factor, and provide the result to the output terminals 104a and 104b. The amplifier 130 may include one or more transistors, and the gain factor of the amplifier 130 may be set based on the configuration of the transistors, such as the placement position and connection mode of the transistors, and voltage bias conditions.

線性化器110可以用於為在系統100的輸入端102a和102b處接收的AC信號提供非線性的分路阻抗（shunt impedance）。例如，線性化器110可以耦接在輸入端102a和102b與DC電源之間。在輸入端102a和102b處接收的AC信號可以通過線性化器110傳導至DC電源，使得線性化器110為系統100提供分路阻抗。線性化器110可以包括一個或多個電晶體，可以基於電晶體的配置（例如電晶體的放置位置和連接方式以及電壓偏置條件）來設置線性化器110的非線性分路阻抗。The linearizer 110 may be used to provide a non-linear shunt impedance for the AC signals received at the input terminals 102a and 102b of the system 100. For example, the linearizer 110 may be coupled between the input terminals 102a and 102b and the DC power supply. The AC signals received at the input terminals 102a and 102b can be conducted to the DC power source through the linearizer 110, so that the linearizer 110 provides the system 100 with shunt impedance. The linearizer 110 may include one or more transistors, and the nonlinear shunt impedance of the linearizer 110 may be set based on the configuration of the transistors (for example, the placement position and connection mode of the transistors and the voltage bias condition).

在系統100中，與放大器130的增益因數相比，線性化器110和放大器130相組合能夠提供線性度得以改善的整體傳遞函數。當組合時，系統100在輸入端102a和102b與輸出端104a和104b之間的整體傳遞函數，與放大器130的增益因數相比，在AC信號電壓範圍內顯著地更加恒定。例如，在輸入端102a和102b處接收的信號的特定電壓範圍內，放大器130可以具有非線性增益因數。為了補償放大器130的非線性增益因數，線性化器110可以被配置為提供非線性阻抗，使得輸入端102a和102b與輸出端104a和104b之間的整體傳遞函數與放大器130的增益因數相比，在該特定電壓範圍內具有改善的線性度。這裡將參照第1B圖來描述放大器130的增益因數、線性化器110的非線性阻抗以及系統100的整體傳遞函數。In the system 100, the combination of the linearizer 110 and the amplifier 130 can provide an overall transfer function with improved linearity compared to the gain factor of the amplifier 130. When combined, the overall transfer function of the system 100 between the input terminals 102a and 102b and the output terminals 104a and 104b is significantly more constant over the AC signal voltage range compared to the gain factor of the amplifier 130. For example, within a specific voltage range of the signal received at the input terminals 102a and 102b, the amplifier 130 may have a non-linear gain factor. In order to compensate for the nonlinear gain factor of the amplifier 130, the linearizer 110 may be configured to provide a nonlinear impedance so that the overall transfer function between the input terminals 102a and 102b and the output terminals 104a and 104b is compared with the gain factor of the amplifier 130, It has improved linearity in this specific voltage range. Here, the gain factor of the amplifier 130, the nonlinear impedance of the linearizer 110, and the overall transfer function of the system 100 will be described with reference to FIG. 1B.

儘管未在第1A圖中示出，應當理解，線性化器110和放大器130均連接到DC電源。例如，線性化器110可以將在輸入端102a和102b處接收的AC信號耦接到DC電源，放大器130可以將從DC電源接收的功率轉換成信號功率，以放大輸出端104a和104b處的AC信號。Although not shown in Figure 1A, it should be understood that both the linearizer 110 and the amplifier 130 are connected to a DC power source. For example, the linearizer 110 may couple the AC signals received at the input terminals 102a and 102b to a DC power source, and the amplifier 130 may convert the power received from the DC power source into signal power to amplify the AC signals at the output terminals 104a and 104b. Signal.

第1B圖示出了一系列曲線圖150、170和190，這些曲線圖對應於如第1A圖所示系統100中元件的各種傳遞函數。曲線圖150示出了線性化器110的阻抗傳遞函數154，以及恒定的阻抗傳遞函數152。曲線圖170示出了放大器130的增益因數174，以及恒定的增益因數172。曲線圖190示出了從輸入端102a和102到輸出端104a和104b的系統100的整體傳遞函數194，以及恒定的傳遞函數192。例如，整體傳遞函數194是阻抗傳遞函數154和增益因數174的乘積。阻抗傳遞函數154、增益因數174和整體傳遞函數194是在輸入電壓V_IN 的V₁ 至V₂ 範圍內繪製。Figure 1B shows a series of graphs 150, 170, and 190 that correspond to various transfer functions of the components in the system 100 shown in Figure 1A. The graph 150 shows the impedance transfer function 154 of the linearizer 110 and the constant impedance transfer function 152. The graph 170 shows the gain factor 174 of the amplifier 130 and the constant gain factor 172. The graph 190 shows the overall transfer function 194 of the system 100 from the input terminals 102 a and 102 to the output terminals 104 a and 104 b, and the constant transfer function 192. For example, the overall transfer function 194 is the product of the impedance transfer function 154 and the gain factor 174. The impedance transfer function 154, the gain factor 174, and the overall transfer function 194 are plotted in the range of V ₁ to V _{2 of the input voltage V IN.}

如曲線圖150所示，線性化器110的阻抗傳遞函數154在V₁ 至V₂ 之間偏離恒定阻抗傳遞函數152。例如，線性化器110可以包括一個或多個電晶體，這些電晶體被偏置為在V₁ 和V₂ 之間產生期望的非線性通道阻抗（channel impedance）。因此，阻抗傳遞函數154相對於從V₁ 至V₂ 的輸入電壓V_IN 是非線性的。As shown in the graph 150, the impedance transfer function 154 of the linearizer 110 deviates from the constant impedance transfer function 152 between _{V 1} and V _2. For example, the linearizer 110 may include one or more transistors that are biased to produce a desired non-linear channel impedance between _{V 1} and V _2. Therefore, the impedance transfer function 154 is non-linear with respect to the input voltage V _{IN from V 1} to V _2.

如曲線圖170所示，放大器130的增益因數174在電壓V₁ 和V₂ 之間偏離恒定增益因數172。例如，放大器130可以是在電壓V₁ 至V₂ 之間具有較差線性度的C類功率放大器。因此，增益因數174相對於從V₁ 至V₂ 的輸入電壓V_IN 是非線性的。As shown in the graph 170, the gain factor 174 of the amplifier 130 deviates from the constant gain factor 172 between the _{voltages V 1} and V _2. For example, the amplifier 130 may be a class C power amplifier with poor linearity between the _{voltages V 1} and V _2. Therefore, the gain factor 174 is non-linear with respect to the input voltage V _{IN from V 1} to V _2.

如曲線圖190所示，系統100（包括放大器130以及分路耦接的線性化器110）的整體傳遞函數194，在電壓V₁ 和V₂ 之間基本上等於恒定的傳遞函數192。阻抗傳遞函數154和增益因數174的乘積可以產生在電壓V₁ 和V₂ 之間線性度得以改善的整體傳遞函數。例如，線性化器110的電晶體可以被偏置為產生電晶體的非線性通道阻抗，這可以抵消在電壓V₁ 和V₂ 之間放大器130的增益因數174中的非線性。由於整體傳遞函數194是阻抗傳遞函數154和增益因數174的乘積，因此與增益因數174相比，整體傳遞函數194在電壓V₁ 和V₂ 之間具有改善的線性度。As shown in the graph 190, the overall transfer function 194 of the system 100 (including the amplifier 130 and the shunt-coupled linearizer 110) is substantially equal to the constant transfer function 192 between the _{voltages V 1} and V _2. The product of the impedance transfer function 154 and the gain factor 174 can produce an overall transfer function with improved linearity between the _{voltages V 1} and V _2. For example, the transistor of the linearizer 110 can be biased to produce a non-linear channel impedance of the transistor, which can cancel the non-linearity in the gain factor 174 of the amplifier 130 between the _{voltages V 1} and V _2. Since the overall transfer function 194 is the product of the impedance transfer function 154 and the gain factor 174, compared to the gain factor 174, the overall transfer function 194 has improved linearity between the _{voltages V 1} and V _2.

本發明提出了由一個或多個耦接到放大器的電晶體實現的線性化器。例如，這些電晶體可以耦接到放大器的輸入端，這些電晶體的通道（channel）被配置為對輸入端處接收的信號提供非線性阻抗。第2A圖至第2C圖示出了示例性系統200a、200b和200c的電路圖，每個系統具有由一個或多個耦接至放大器的電晶體實現的線性化器。系統200a、200b和200c中的每一個均可以被配置為按照結合第1A圖至第1B圖的系統100所描述的方式進行操作。The present invention proposes a linearizer implemented by one or more transistors coupled to an amplifier. For example, these transistors may be coupled to the input of an amplifier, and the channels of these transistors are configured to provide non-linear impedance to the signal received at the input. Figures 2A to 2C show circuit diagrams of exemplary systems 200a, 200b, and 200c, each system having a linearizer implemented by one or more transistors coupled to an amplifier. Each of the systems 200a, 200b, and 200c may be configured to operate in the manner described in conjunction with the system 100 of FIGS. 1A to 1B.

第2A圖是例示系統200a的電路圖，系統200a包括耦接在輸入端202和輸出端204之間的由線性化器210a補償的單端放大器230a。系統200a被示為單端系統。因此，在輸入端202處接收的以及在輸出端204處提供的信號可以是單端信號。FIG. 2A is a circuit diagram illustrating a system 200a. The system 200a includes a single-ended amplifier 230a coupled between an input terminal 202 and an output terminal 204 and compensated by a linearizer 210a. System 200a is shown as a single-ended system. Therefore, the signal received at the input 202 and provided at the output 204 may be a single-ended signal.

放大器230a包括電晶體232，其可以被配置為放大在控制端子處接收的信號，並在耦接到輸出端204的通道端子（channel terminal）處提供放大器結果。在第2A圖的示例實施例中，電晶體232是共源極（common-source）配置的FET，電晶體232的控制端子是連接到輸入端202的閘極（gate）。電晶體232的汲極連接到輸出端204，並且還連接到匹配網路242（例如，線性無源匹配網路）。匹配網路242可以包括例如電感器的無源元件和/或不平衡變壓器（balun）。匹配網路242耦接到電流鏡240，電流鏡240為偏置電晶體232提供電流。在一些實施例中，電晶體232的汲極可以連接到串疊式電晶體（cascode transistor）的源極，串疊式電晶體的汲極可以耦接到電流鏡240。電晶體232的源極耦接到公共電壓端子，例如地。然而，電晶體232的源極可以耦接到其他元件。例如，在一些實施例中，電晶體232的源極耦接到電流鏡240。The amplifier 230a includes a transistor 232, which can be configured to amplify the signal received at the control terminal and provide the amplifier result at a channel terminal coupled to the output terminal 204. In the example embodiment of FIG. 2A, the transistor 232 is a FET with a common-source configuration, and the control terminal of the transistor 232 is a gate connected to the input terminal 202. The drain of the transistor 232 is connected to the output terminal 204, and is also connected to a matching network 242 (for example, a linear passive matching network). The matching network 242 may include passive components such as inductors and/or baluns. The matching network 242 is coupled to the current mirror 240, and the current mirror 240 provides current for the bias transistor 232. In some embodiments, the drain of the transistor 232 may be connected to the source of a cascode transistor, and the drain of the cascode transistor may be coupled to the current mirror 240. The source of the transistor 232 is coupled to a common voltage terminal, such as ground. However, the source of the transistor 232 may be coupled to other elements. For example, in some embodiments, the source of the transistor 232 is coupled to the current mirror 240.

在所例示的共源配置中，電晶體232被配置為在其閘極處接收AC信號，基於增益因數放大AC信號，並在其汲極處提供增益後的AC信號。例如，可以基於電晶體232的閘極、汲極和源極處的DC偏置電壓以及基於電流鏡240提供的電流來設置增益因數。在閘極處的AC信號電壓的範圍內，增益因數可以是非線性的。在耦接到輸出端204的汲極處，電晶體232可以提供增益後的AC信號。In the illustrated common source configuration, the transistor 232 is configured to receive an AC signal at its gate, amplify the AC signal based on a gain factor, and provide a gained AC signal at its drain. For example, the gain factor may be set based on the DC bias voltage at the gate, drain, and source of the transistor 232 and based on the current provided by the current mirror 240. Within the range of the AC signal voltage at the gate, the gain factor can be non-linear. At the drain coupled to the output terminal 204, the transistor 232 can provide a gained AC signal.

應當理解，一些實施例不包括電流鏡240。例如，在一些實施例中，匹配網路242可以耦接到DC電源206。在一些實施例中，電晶體232可以接收輸入或提供輸出至放大器230a的附加放大級的一個或多個電晶體。應當理解，電晶體232可以具有不同的放大器配置，例如，共閘極（common-gate）或共汲極（common-drain）。另外，電晶體232可以是不同類型的電晶體，例如BJT、HEMT、IGBT或HBT等，並且類似地可以具有與對應的電晶體類型相適應的配置，例如共基極（common-base）、共射極（common-emitter）或共集極（common-collector）。It should be understood that some embodiments do not include the current mirror 240. For example, in some embodiments, the matching network 242 may be coupled to the DC power source 206. In some embodiments, the transistor 232 may receive input or provide one or more transistors output to the additional amplifier stage of the amplifier 230a. It should be understood that the transistor 232 may have different amplifier configurations, for example, common-gate or common-drain. In addition, the transistor 232 may be different types of transistors, such as BJT, HEMT, IGBT or HBT, etc., and similarly may have a configuration compatible with the corresponding transistor type, such as common-base, common-base, and common-base. Common-emitter or common-collector.

線性化器210a被配置為提供非線性阻抗以補償放大器230a。在第2A圖，線性化器210a包括電晶體212，該電晶體212具有耦接在輸入端202和DC電源206之間的通道（channel），並且具有與DC偏置電壓214相連的控制端子，DC偏置電壓214與輸入端202處接收的AC信號不同。電晶體212可以被配置為使得在輸入端202處接收的AC信號通過非線性通道阻抗傳導至DC電源206。DC電源206可以構成在輸入端202處接收的AC信號的交流地。例如，在輸入端202接收的AC信號可以包括圍繞直流偏置工作的交流分量，並且在DC電源206處基本上沒有交流分量。因此，儘管由於信號的直流分量仍然存在，AC信號在DC電源206處沒有被完全接地，但是AC信號的交流分量在DC電源206處可以忽略不計，就像接地一樣。在第2A圖中，電晶體212是FET，其源極耦接到輸入端202，其汲極耦接到DC電源206，其控制端子（閘極）用於控制在源極和汲極之間流動的電流。如果該FET被偏置到飽和區域中，則該FET的通道阻抗可以是非線性的，使得通道阻抗根據輸入端202處AC信號的電壓而變化。應當理解，電晶體212可以是不同類型的電晶體，諸如BJT、HEMT、IGBT或HBT。在該示例中，電晶體212的控制端子處的電壓應當比其耦接到輸入端202的源極處的電壓高至少閾值電壓，並且應當比其汲極所耦接的DC電源206的電壓小至少閾值電壓。The linearizer 210a is configured to provide a non-linear impedance to compensate the amplifier 230a. In Figure 2A, the linearizer 210a includes a transistor 212 having a channel coupled between the input terminal 202 and the DC power source 206, and a control terminal connected to the DC bias voltage 214, The DC bias voltage 214 is different from the AC signal received at the input terminal 202. The transistor 212 may be configured such that the AC signal received at the input 202 is conducted to the DC power source 206 through the non-linear channel impedance. The DC power source 206 may constitute an AC ground for the AC signal received at the input terminal 202. For example, the AC signal received at the input 202 may include an AC component working around a DC bias, and there is substantially no AC component at the DC power source 206. Therefore, although the AC signal is not completely grounded at the DC power source 206 because the DC component of the signal still exists, the AC component of the AC signal is negligible at the DC power source 206, just like grounding. In Figure 2A, the transistor 212 is a FET, its source is coupled to the input 202, its drain is coupled to the DC power supply 206, and its control terminal (gate) is used to control between the source and the drain Flowing current. If the FET is biased into the saturation region, the channel impedance of the FET may be non-linear, so that the channel impedance varies according to the voltage of the AC signal at the input 202. It should be understood that the transistor 212 may be a different type of transistor, such as BJT, HEMT, IGBT, or HBT. In this example, the voltage at the control terminal of the transistor 212 should be at least a threshold voltage higher than the voltage at its source coupled to the input terminal 202, and should be lower than the voltage of the DC power source 206 to which its drain is coupled At least the threshold voltage.

本發明還提出了被實現為具有可選阻抗的線性化器。例如，線性化器的一個或多個電晶體可以接收可選擇的控制端子偏置電壓（例如，用於FET的閘極偏置電壓或用於BJT的基極偏置電壓），這使得能夠選擇線性化器的阻抗。例如，控制端子偏置電壓可以設置電晶體的通道阻抗，這有助於線性化器的阻抗。在第2A圖中，DC偏置電壓214設置電晶體212的非線性通道阻抗。因此，可以通過相應地設置DC偏置電壓214來實現針對通過電晶體212耦接在輸入端202和DC電源206之間的AC信號的某一期望的非線性通道阻抗。例如，DC偏置電壓214可以為操作在第一AC電壓電平和第二AC電壓電平之間的接收的AC信號設置特定的非線性通道阻抗。在一些實施例中，DC偏置電壓214可以是用於產生電晶體212的期望非線性通道阻抗的可選偏置電壓。The present invention also proposes a linearizer that is implemented with selectable impedance. For example, one or more transistors of the linearizer can receive a selectable control terminal bias voltage (eg, gate bias voltage for FET or base bias voltage for BJT), which enables selection The impedance of the linearizer. For example, controlling the terminal bias voltage can set the channel impedance of the transistor, which helps the impedance of the linearizer. In Figure 2A, the DC bias voltage 214 sets the non-linear channel impedance of the transistor 212. Therefore, a certain desired nonlinear channel impedance for the AC signal coupled between the input terminal 202 and the DC power source 206 through the transistor 212 can be achieved by setting the DC bias voltage 214 accordingly. For example, the DC bias voltage 214 may set a specific non-linear channel impedance for the received AC signal operating between the first AC voltage level and the second AC voltage level. In some embodiments, the DC bias voltage 214 may be an optional bias voltage used to generate the desired non-linear channel impedance of the transistor 212.

以可選阻抗來實現線性化器可以減小線性化器的整體尺寸，從而降低製造成本並提高線性化器的工作效率。在沒有可選阻抗的線性化器中，線性化器的阻抗可以由線性化器內器件的通道尺寸來設置。例如，線性化器可以包括二極體連接方式（diode-connected）的電晶體，線性化器的阻抗由電晶體的通道尺寸（例如通道寬度）設置。為了補償放大器的非線性回應，這種線性化器的電晶體需要具有與放大器的電晶體大約相同尺寸的通道寬度，以匹配放大器的電流密度。然而，放大器中電晶體的通道寬度可能較大，因此當以積體電路實現時，實現對放大器進行補償的線性化器時將導致製造成本增加。另外，大的電晶體通道寬度將導致大的電晶體內部電容，需要更多的功率來導通電晶體。因此，線性化器會具有較高成本並且需要更多的功率來運行。Implementing the linearizer with optional impedance can reduce the overall size of the linearizer, thereby reducing manufacturing costs and improving the working efficiency of the linearizer. In the linearizer without optional impedance, the impedance of the linearizer can be set by the channel size of the device in the linearizer. For example, the linearizer may include a diode-connected transistor, and the impedance of the linearizer is set by the channel size (eg, channel width) of the transistor. In order to compensate for the nonlinear response of the amplifier, the transistor of this linearizer needs to have a channel width approximately the same size as the transistor of the amplifier to match the current density of the amplifier. However, the channel width of the transistor in the amplifier may be relatively large, so when implemented as an integrated circuit, the implementation of a linearizer that compensates the amplifier will increase the manufacturing cost. In addition, a large transistor channel width will result in a large internal capacitance of the transistor, requiring more power to turn on the transistor. Therefore, the linearizer will have a higher cost and require more power to operate.

與沒有可選阻抗的線性化器相比，以可選阻抗實現的線性化器，諸如這裡參照第2A圖所描述的，可以被配置為以較小的通道寬度提供期望的阻抗。不僅可以基於線性化器的電晶體的通道寬度而且還可以根據電晶體的可選控制端子偏置電壓，來設置線性化器的阻抗。例如，可以相對於放大器的一個或多個電晶體的控制端子偏置電壓來設置該控制端子偏置電壓，以調節放大器中的非線性。當控制端子偏置電壓能補償通道寬度減小對線性化器的阻抗的影響時，可以減小線性化器的電晶體的通道寬度。因此，與沒有可選阻抗的線性化器相比，該線性化器可以實現為較小的通道寬度，同時保持與放大器中的電流密度匹配的能力，從而降低製造成本和提高工作效率。在一些實施例中，線性化器的電晶體的通道寬度可以在放大器的電晶體的通道寬度的5％與10％之間。Compared to a linearizer without a selectable impedance, a linearizer implemented with a selectable impedance, such as described herein with reference to Figure 2A, can be configured to provide a desired impedance with a smaller channel width. The impedance of the linearizer can be set not only based on the channel width of the transistor of the linearizer, but also based on the optional control terminal bias voltage of the transistor. For example, the control terminal bias voltage can be set relative to the control terminal bias voltage of one or more transistors of the amplifier to adjust the nonlinearity in the amplifier. When the control terminal bias voltage can compensate the influence of the channel width reduction on the impedance of the linearizer, the channel width of the transistor of the linearizer can be reduced. Therefore, compared with a linearizer without a selectable impedance, the linearizer can be implemented with a smaller channel width while maintaining the ability to match the current density in the amplifier, thereby reducing manufacturing costs and improving work efficiency. In some embodiments, the channel width of the transistor of the linearizer may be between 5% and 10% of the channel width of the transistor of the amplifier.

本發明提出了被實現為包括共控制端子（common-control terminal）配置的電晶體（例如，用於FET的共閘極或用於BJT的共基極）的線性化器。例如，在第2A圖中，電晶體212是共閘極（common-gate）配置的FET，其源極耦接至輸入端202，汲極耦接至DC電源206A。電晶體212的閘極耦接到不同於DC電源電壓且不同於輸入端202處電壓的DC偏置電壓。The present invention proposes a linearizer that is implemented as a transistor including a common-control terminal configuration (for example, a common gate for FET or a common base for BJT). For example, in Figure 2A, the transistor 212 is a FET with a common-gate configuration, the source of which is coupled to the input terminal 202, and the drain of which is coupled to the DC power supply 206A. The gate of the transistor 212 is coupled to a DC bias voltage different from the DC power supply voltage and different from the voltage at the input terminal 202.

本發明提出了被實現為具有串疊式（cascode）共控制端子配置的電晶體的線性化器。例如，第一和第二FET可以以共閘極（common-gate）配置佈置在放大器的輸入端與DC電源之間。第2B圖是示出系統200b的電路圖，該系統200b包括由耦接在輸入端202和DC電源206之間的串疊式線性化器210b補償的單端放大器230b。如第2B圖所示，線性化器210b包括具有串疊式拓撲結構（cascode topology）的電晶體212a和212b。應當理解，系統200b可以被配置為按照結合系統200a所描述的方式進行操作。例如，放大器230b可以被配置為按照針對放大器230a所描述的方式操作。The present invention proposes a linearizer implemented as a transistor with a cascode common control terminal configuration. For example, the first and second FETs may be arranged between the input terminal of the amplifier and the DC power supply in a common-gate configuration. FIG. 2B is a circuit diagram showing a system 200b, which includes a single-ended amplifier 230b compensated by a cascade linearizer 210b coupled between an input terminal 202 and a DC power supply 206. As shown in FIG. 2B, the linearizer 210b includes transistors 212a and 212b having a cascode topology. It should be understood that the system 200b may be configured to operate in the manner described in connection with the system 200a. For example, the amplifier 230b may be configured to operate in the manner described for the amplifier 230a.

線性化器210b可以被配置為基於在電晶體212a和212b的控制端子處提供的DC偏置電壓214a和214b，在輸入端202和DC電源206之間提供非線性阻抗。DC偏置電壓214a和214b可以被配置為設置電晶體212a和212b中的每一個電晶體的非線性通道阻抗。DC偏置電壓214a和214b可以是可選偏置電壓，用於產生電晶體212a和212b的期望的非線性通道阻抗。因此，在輸入端202處接收的AC信號傳導通過由DC偏置電壓214a和214b設置的電晶體212a和212b的非線性通道阻抗。應當理解，DC偏置電壓214a和214b可以是相同的DC偏置電壓，或者可以是不同的DC偏置電壓。The linearizer 210b may be configured to provide a non-linear impedance between the input terminal 202 and the DC power source 206 based on the DC bias voltages 214a and 214b provided at the control terminals of the transistors 212a and 212b. The DC bias voltages 214a and 214b may be configured to set the nonlinear channel impedance of each of the transistors 212a and 212b. The DC bias voltages 214a and 214b may be selectable bias voltages used to generate the desired non-linear channel impedance of the transistors 212a and 212b. Therefore, the AC signal received at the input 202 is conducted through the non-linear channel impedance of the transistors 212a and 212b set by the DC bias voltages 214a and 214b. It should be understood that the DC bias voltages 214a and 214b may be the same DC bias voltage, or may be different DC bias voltages.

本發明提出了配置為用於差動系統的線性化器。第2C圖是示出系統200c的電路圖，該系統包括耦接在輸入端202a和202b與輸出端204a和204b之間由線性化器210c補償的差動放大器230c。與系統200a和200b相反，在系統200c的輸入端202a和202b處接收的信號可以是差動信號，其中在輸入端202a處接收差動信號的高值分量，在輸入端202b處接收差動信號的低值分量。如第2C圖所示，線性化器210c可以被配置為對輸入端202a和202b處接收的差動信號提供非線性阻抗。The present invention proposes a linearizer configured for use in a differential system. Figure 2C is a circuit diagram showing a system 200c, which includes a differential amplifier 230c coupled between input terminals 202a and 202b and output terminals 204a and 204b and compensated by a linearizer 210c. In contrast to the systems 200a and 200b, the signals received at the input terminals 202a and 202b of the system 200c may be differential signals, wherein the high value component of the differential signal is received at the input terminal 202a, and the differential signal is received at the input terminal 202b. The low-value component. As shown in Figure 2C, the linearizer 210c may be configured to provide a non-linear impedance to the differential signal received at the input terminals 202a and 202b.

放大器230c可以被配置為按照結合第2A圖至第2B圖描述的放大器230a和230b的方式操作。然而，與第2A圖和第2B圖相反，放大器230c被配置為放大輸入端202a和202b處接收的差動信號。例如，放大器230c包括電晶體232a和232b，其中電晶體232a被配置為放大輸入端202a處接收的差動信號的高值分量，電晶體232b被配置為放大在輸入端202b處接收的差動信號的低值分量。如第2C圖所示，電晶體232a和232b的控制端子耦接到輸入端202a和202b，電晶體232a和232b的通道耦接到輸出端204a和204b。可以通過在控制端子處以及跨過電晶體232a和232b的通道的DC偏置來設置電晶體232a和232b的增益因數，如結合第2A圖對電晶體232所述的方式。電晶體232a和232b還被配置為在輸出端204a和204b處分別提供差動信號的相應放大分量。電晶體232a和232b的DC偏置條件可以基本上相同，使得電晶體232a和232b具有基本上相同的增益因數，以避免對輸出端204a和204b處提供的信號的分量增加失真。The amplifier 230c may be configured to operate in the manner of the amplifiers 230a and 230b described in conjunction with FIGS. 2A to 2B. However, in contrast to Figures 2A and 2B, the amplifier 230c is configured to amplify the differential signal received at the input terminals 202a and 202b. For example, the amplifier 230c includes transistors 232a and 232b, wherein the transistor 232a is configured to amplify the high value component of the differential signal received at the input terminal 202a, and the transistor 232b is configured to amplify the differential signal received at the input terminal 202b The low-value component. As shown in Figure 2C, the control terminals of the transistors 232a and 232b are coupled to the input terminals 202a and 202b, and the channels of the transistors 232a and 232b are coupled to the output terminals 204a and 204b. The gain factors of transistors 232a and 232b can be set by DC bias at the control terminals and across the channels of transistors 232a and 232b, as described for transistor 232 in connection with Figure 2A. The transistors 232a and 232b are also configured to provide corresponding amplified components of the differential signal at the output terminals 204a and 204b, respectively. The DC bias conditions of the transistors 232a and 232b may be substantially the same, so that the transistors 232a and 232b have substantially the same gain factor to avoid adding distortion to the components of the signal provided at the output terminals 204a and 204b.

線性化器210c包括耦接在輸入端202a和DC電源206之間的電晶體212a，以及耦接在輸入端202b和DC電源206之間的電晶體212b。電晶體212a和212b的控制端子耦接到DC偏置電壓214a和214b，使得可以根據DC偏置電壓214a和214b來設置電晶體212a和212b的非線性通道阻抗。例如，DC偏置電壓214a和214b可以是可選偏置電壓，用於為電晶體212a和212b產生期望的非線性通道阻抗。電晶體212a和212b可以具有基本相同的尺寸以及基本等效的配置，例如具有基本相等的DC偏置電壓214a和214b，以避免對輸入端202a和202b處接收的差動信號添加失真。放大器230c的電晶體232a和232b的控制端子處的信號中的失真將產生較低品質的信號，這對於被配置為接收由系統200c的輸出端204a和204b提供的信號的系統而言是不利的。The linearizer 210c includes a transistor 212a coupled between the input terminal 202a and the DC power source 206, and a transistor 212b coupled between the input terminal 202b and the DC power source 206. The control terminals of the transistors 212a and 212b are coupled to the DC bias voltages 214a and 214b, so that the nonlinear channel impedance of the transistors 212a and 212b can be set according to the DC bias voltages 214a and 214b. For example, the DC bias voltages 214a and 214b may be selectable bias voltages used to generate the desired nonlinear channel impedance for the transistors 212a and 212b. The transistors 212a and 212b may have substantially the same size and substantially equivalent configuration, such as substantially the same DC bias voltages 214a and 214b, to avoid adding distortion to the differential signal received at the input terminals 202a and 202b. Distortion in the signal at the control terminals of the transistors 232a and 232b of the amplifier 230c will produce a lower quality signal, which is disadvantageous for a system configured to receive the signal provided by the output terminals 204a and 204b of the system 200c .

本發明提出的線性化器可以被實現為具有與將被補償的放大器相同的拓撲。第3A圖至第3B圖示出了根據一些實施例的包括放大器和線性化器的示例性系統，其中該放大器和線性化器具有相同的拓撲。The linearizer proposed by the present invention can be implemented to have the same topology as the amplifier to be compensated. Figures 3A to 3B show an exemplary system including an amplifier and a linearizer according to some embodiments, where the amplifier and the linearizer have the same topology.

第3A圖是示出系統300a的電路圖，該系統300a包括耦接在輸入端302a和302b與輸出端304a和304b之間的用串疊式（cascode）線性化器310a補償的串疊式差動放大器330a。線性化器310a和放大器330a均具有串疊式配置，因此具有相同的拓撲。在所示的實施例中，線性化器310a和放大器330a均具有串疊式拓撲。應當理解，系統300a可以被配置為按照結合第2C圖所描述的方式進行操作。例如，系統300a可以被配置為在輸入端302a和302b處接收差動信號。Figure 3A is a circuit diagram showing a system 300a, which includes a cascode linearizer 310a compensated by a cascode linearizer 310a coupled between the input terminals 302a and 302b and the output terminals 304a and 304b Amplifier 330a. The linearizer 310a and the amplifier 330a both have a cascade configuration, and therefore have the same topology. In the illustrated embodiment, both the linearizer 310a and the amplifier 330a have a tandem topology. It should be understood that the system 300a may be configured to operate in the manner described in conjunction with Figure 2C. For example, the system 300a may be configured to receive differential signals at the input terminals 302a and 302b.

放大器330a可以具有電晶體332a、332b、332c和332d的串疊式拓撲。電晶體332a和332b可以具有共控制端子（common-control terminal）配置。例如，電晶體332a和332b可以是FET，其閘極連接到DC偏置電壓334a和334b，DC偏置電壓334a和334b可以相同。電晶體332c和332d可以具有共通道端子（common-channel terminal）配置。例如，電晶體332c和332d可以是FET，其閘極耦接到輸入端302a和302b，汲極可以耦接到電晶體332a和332b，使得放大器330a具有串疊式拓撲結構。The amplifier 330a may have a tandem topology of transistors 332a, 332b, 332c, and 332d. The transistors 332a and 332b may have a common-control terminal configuration. For example, the transistors 332a and 332b may be FETs, the gates of which are connected to the DC bias voltages 334a and 334b, and the DC bias voltages 334a and 334b may be the same. The transistors 332c and 332d may have a common-channel terminal configuration. For example, the transistors 332c and 332d can be FETs, the gates of which are coupled to the input terminals 302a and 302b, and the drains can be coupled to the transistors 332a and 332b, so that the amplifier 330a has a tandem topology.

線性化器310a可以包括以串疊式拓撲結構配置的電晶體312a、312b、312c和312d。電晶體312a、312b、312c和312d可以由DC偏置電壓314a、314b、314c和314d偏置。DC偏置電壓314a和314b可以基本相等，DC偏置電壓314c和314d可以基本相等，從而避免將失真添加到在輸入端302a和302b處接收的信號。在一些實施例中，DC偏置電壓314a、314b、314c和314d可以全部基本上彼此相等。The linearizer 310a may include transistors 312a, 312b, 312c, and 312d configured in a tandem topology. Transistors 312a, 312b, 312c, and 312d may be biased by DC bias voltages 314a, 314b, 314c, and 314d. The DC bias voltages 314a and 314b may be substantially equal, and the DC bias voltages 314c and 314d may be substantially equal, thereby avoiding adding distortion to the signals received at the input terminals 302a and 302b. In some embodiments, the DC bias voltages 314a, 314b, 314c, and 314d may all be substantially equal to each other.

第3B圖是示出單端系統300b的電路圖，該單端系統300b包括耦接在輸入端302和輸出端304之間的由串疊式線性放大器310b補償的串疊式單端放大器330b。線性化器310b和放大器330b均具有串疊式配置，因此具有相同的拓撲。系統300b可以被配置為按照結合第2B圖所描述的方式進行操作。FIG. 3B is a circuit diagram showing a single-ended system 300b. The single-ended system 300b includes a cascaded single-ended amplifier 330b coupled between an input terminal 302 and an output terminal 304 and compensated by a cascaded linear amplifier 310b. Both the linearizer 310b and the amplifier 330b have a cascade configuration and therefore have the same topology. The system 300b may be configured to operate in the manner described in connection with Figure 2B.

本發明提出了耦接到要進行補償的放大器的輸入端和輸出端的線性化器。第4A圖至第4B圖是示出根據一些實施例的示例性系統的電路圖，示例性系統包括放大器和輸出端耦接的（output-coupled）線性化器。The present invention proposes a linearizer coupled to the input and output of the amplifier to be compensated. FIGS. 4A to 4B are circuit diagrams showing exemplary systems according to some embodiments, the exemplary system including an amplifier and an output-coupled linearizer.

第4A圖是示出系統400a的電路圖，系統400a包括耦接在輸入端402和輸出端404之間的由輸出端耦接的線性化器410a補償的單端放大器430a。系統400a可以被配置為按照結合第2A圖對系統200a所描述的方式操作。例如，線性化器410a可以被配置為對在輸入端402處接收的信號提供與放大器430a並聯的非線性阻抗。另外，在輸入端402處接收的信號可以通過線性化器410a耦接到輸出端404。FIG. 4A is a circuit diagram showing a system 400a. The system 400a includes a single-ended amplifier 430a coupled between an input terminal 402 and an output terminal 404 and compensated by a linearizer 410a coupled to an output terminal. The system 400a may be configured to operate in the manner described for the system 200a in connection with Figure 2A. For example, the linearizer 410a may be configured to provide a non-linear impedance in parallel with the amplifier 430a to the signal received at the input terminal 402. In addition, the signal received at the input terminal 402 may be coupled to the output terminal 404 through the linearizer 410a.

由於通過線性化器410a傳導的信號可能不會發生頻率偏移（frequency shift），因此這些信號可以疊加在放大器430a的輸出端處。因此，系統400a可以保持（preserve）在輸入端402處接收的基本上所有信號，並在輸出端404處提供放大器信號。應該理解，在一些實施例中，線性化器410a可以被配置為匹配放大器430a的相位偏移（phase shift），使得在輸入端402處接收的信號通過線性化器410a到達輸出端404時與通過放大器430a到達輸出端404的信號同相（in phase）。在一些實施例中，線性化器410a可以被配置為提供180度的相位偏移，使得在輸入端402處接收的信號通過線性化器410a到達輸出端404時與通過放大器430a到達輸出端404的信號反相（out of phase）。根據各種實施例，線性化器410a可以被配置為對輸入端402處接收的信號提供任何期望的相位偏移。另外，應當理解，儘管線性化器410a和放大器430a被示出為具有相同的非串疊式（non-cascode）拓撲，但是根據各種實施例，線性化器410a和放大器430a可以具有不同的拓撲。Since the signals conducted through the linearizer 410a may not have a frequency shift, these signals may be superimposed on the output terminal of the amplifier 430a. Therefore, the system 400a can preserve substantially all signals received at the input terminal 402 and provide an amplifier signal at the output terminal 404. It should be understood that, in some embodiments, the linearizer 410a may be configured to match the phase shift of the amplifier 430a, so that the signal received at the input terminal 402 passes through the linearizer 410a to the output terminal 404 and passes through the linearizer 410a. The signal arriving at the output terminal 404 of the amplifier 430a is in phase. In some embodiments, the linearizer 410a may be configured to provide a phase offset of 180 degrees, so that the signal received at the input terminal 402 passes through the linearizer 410a to the output terminal 404 and the signal received at the output terminal 404 through the amplifier 430a. The signal is out of phase. According to various embodiments, the linearizer 410a may be configured to provide any desired phase offset to the signal received at the input 402. In addition, it should be understood that although the linearizer 410a and the amplifier 430a are shown as having the same non-cascode topology, the linearizer 410a and the amplifier 430a may have different topologies according to various embodiments.

第4B圖是示出根據一些實施例的示例性系統400b的電路圖，該示例性系統400b包括由輸出端耦接的串疊式線性放大器410b補償的串疊式差動放大器430b。系統400b可以被配置為按照結合第4A圖所描述的方式操作。例如，線性化器410b耦接在輸入端402a和402b與輸出端404a和404b之間，可以被配置為與放大器430b並行地提供非線性阻抗。然而，與第4A圖相反，系統400b被配置為在輸入端402a和402b處接收差動信號，並且線性化器410b和放大器430b具有串疊式拓撲結構。應當理解，線性化器410b和放大器430b可以被配置為按照結合第3A圖對線性化器310a和放大器330a所描述的方式操作。Figure 4B is a circuit diagram illustrating an exemplary system 400b according to some embodiments, the exemplary system 400b including a cascaded differential amplifier 430b compensated by a cascaded linear amplifier 410b coupled to an output terminal. The system 400b may be configured to operate in the manner described in connection with Figure 4A. For example, the linearizer 410b is coupled between the input terminals 402a and 402b and the output terminals 404a and 404b, and may be configured to provide a nonlinear impedance in parallel with the amplifier 430b. However, contrary to FIG. 4A, the system 400b is configured to receive differential signals at the input terminals 402a and 402b, and the linearizer 410b and the amplifier 430b have a tandem topology. It should be understood that the linearizer 410b and the amplifier 430b may be configured to operate in the manner described for the linearizer 310a and the amplifier 330a in connection with FIG. 3A.

第5A圖是示出根據一些實施例的示例性系統500a的電路圖，系統500a包括用PMOS線性化器510a補償的單端放大器530a。系統500a可以被配置為按照結合第2A圖描述的方式進行操作。例如，線性化器510a可以被配置為與放大器530a並行地提供非線性阻抗。然而，與第2A圖的線性化器210a相反，線性化器510a包括PMOS電晶體512，其具有由DC偏置電壓514偏置的控制端子。在一些實施例中，DC偏置電壓514可以是來自DC電源506的負電源電壓。應當理解，線性化器510a可以配置為按照結合第2A圖對線性化器210a所描述的方式操作。在該示例中，PMOS電晶體512的控制端子處的電壓應當比其耦接到輸入端202的源極處的電壓小至少閾值電壓，並且應當比其汲極所耦接的DC電源506的電壓高至少閾值電壓。Figure 5A is a circuit diagram illustrating an exemplary system 500a according to some embodiments. The system 500a includes a single-ended amplifier 530a compensated with a PMOS linearizer 510a. The system 500a may be configured to operate in the manner described in connection with Figure 2A. For example, the linearizer 510a may be configured to provide nonlinear impedance in parallel with the amplifier 530a. However, in contrast to the linearizer 210a of FIG. 2A, the linearizer 510a includes a PMOS transistor 512 having a control terminal biased by a DC bias voltage 514. In some embodiments, the DC bias voltage 514 may be a negative power supply voltage from the DC power supply 506. It should be understood that the linearizer 510a may be configured to operate in the manner described for the linearizer 210a in connection with Figure 2A. In this example, the voltage at the control terminal of the PMOS transistor 512 should be less than the voltage at its source coupled to the input terminal 202 by at least the threshold voltage, and should be greater than the voltage of the DC power source 506 to which its drain is coupled. High at least the threshold voltage.

第5B圖是示出根據一些實施例的示例性系統500b的電路圖，該示例性系統500b包括由PMOS和NMOS線性化器510b補償的單端放大器530b。系統500b可以被配置為按照結合第2A圖描述的方式操作。例如，線性化器510b可以被配置為與放大器530b並行地提供非線性阻抗。然而，與第2A圖的線性化器210a相反，線性化器510b包括NMOS電晶體512a和PMOS電晶體512b。NMOS電晶體512a由DC偏置電壓514a偏置，該DC偏置電壓514a可以按照結合第2A圖對DC偏置電壓214所述的方式配置。PMOS電晶體512b由DC偏置電壓514b偏置，該DC偏置電壓514b可以按照結合第5A圖對DC偏置電壓514所描述的方式配置。Figure 5B is a circuit diagram illustrating an exemplary system 500b according to some embodiments, the exemplary system 500b including a single-ended amplifier 530b compensated by a PMOS and NMOS linearizer 510b. The system 500b may be configured to operate in the manner described in connection with Figure 2A. For example, the linearizer 510b may be configured to provide nonlinear impedance in parallel with the amplifier 530b. However, contrary to the linearizer 210a of FIG. 2A, the linearizer 510b includes an NMOS transistor 512a and a PMOS transistor 512b. The NMOS transistor 512a is biased by a DC bias voltage 514a, which can be configured in the manner described for the DC bias voltage 214 in connection with FIG. 2A. The PMOS transistor 512b is biased by a DC bias voltage 514b, which can be configured in the manner described for the DC bias voltage 514 in connection with FIG. 5A.

本文所述的裝置和技術的各個方面可以單獨使用、組合使用或者按照先前描述的實施例中未具體討論的各種佈置使用，因此，其應用並不限於在先前的描述中闡述的或在附圖中示出的組件的細節和佈置。例如，一個實施例中描述的多個方面可以以任意方式與其他實施例中描述的方面相組合。The various aspects of the devices and technologies described herein can be used alone, in combination, or in various arrangements not specifically discussed in the previously described embodiments. Therefore, their applications are not limited to those set forth in the previous description or in the accompanying drawings. The details and arrangement of the components shown in. For example, various aspects described in one embodiment may be combined with aspects described in other embodiments in any manner.

應當理解，上述電晶體可以以各種方式中的任何一種方式來實現。例如，一個或多個電晶體可以實現為雙極結型電晶體或場效應電晶體（field-effect transistor，FET），例如金屬氧化物半導體場效應電晶體（metal-oxide semiconductor field-effect transistor，MOSFET）、結型場效應電晶體（junction field-effect transistor，JFET）、異質結構場效應電晶體（heterostructure field-effect transistor，HFET）、異質結雙極電晶體（heterojunction bipolar transistor，HBT）和高電子遷移率電晶體（high electron mobility transistor，HEMT）。在本文描述的一個或多個電晶體被實現為BJT的情況下，以上針對此類電晶體描述的閘極、源極和汲極端子可以分別是基極、發射極和集電極端子。It should be understood that the above-mentioned transistor can be implemented in any of various ways. For example, one or more transistors may be implemented as a bipolar junction transistor or a field-effect transistor (FET), such as a metal-oxide semiconductor field-effect transistor (metal-oxide semiconductor field-effect transistor, MOSFET), junction field-effect transistor (JFET), heterostructure field-effect transistor (HFET), heterojunction bipolar transistor (HBT) and high High electron mobility transistor (HEMT). In the case where one or more transistors described herein are implemented as BJTs, the gate, source, and drain terminals described above for such transistors may be base, emitter, and collector terminals, respectively.

另外，應當理解，本文描述的放大器可以包括共源極、共控制端子和/或串疊式配置的電晶體的多個級聯級。在一些實施例中，放大器130可以包括C類功率放大器。在一些實施例中，本文描述的放大器可以包括屬於A、B、AB、C、D、E、F、G和H類中的任何一類的功率放大器。在一些實施例中，放大器130可以包括低雜訊放大器。In addition, it should be understood that the amplifier described herein may include multiple cascaded stages of transistors in a common source, common control terminal, and/or tandem configuration. In some embodiments, the amplifier 130 may include a class C power amplifier. In some embodiments, the amplifiers described herein may include power amplifiers belonging to any of the A, B, AB, C, D, E, F, G, and H classes. In some embodiments, the amplifier 130 may include a low noise amplifier.

另外，應當理解，示例的省略電流鏡240的實施例也可以適用於包括電流鏡240。In addition, it should be understood that the exemplary embodiment in which the current mirror 240 is omitted can also be applied to include the current mirror 240.

在申請專利範圍中使用諸如“第一”、“第二”、“第三”等序數術語來修飾申請專利範圍中的要素，其本身並不表示一個申請專利範圍中的要素相對於另一個申請專利範圍中的要素的任何優先順序、或先後順序或者執行方法步驟的時間順序，其僅用作標記，以區分具有相同名稱的一個申請專利範圍要素與具有相同名稱的另一個要素。The use of ordinal terms such as "first", "second", and "third" in the scope of patent application to modify the elements in the scope of the patent application does not mean that the elements in the scope of one application are relative to another application. Any priority or sequence of the elements in the patent scope or the chronological order of performing method steps is only used as a mark to distinguish one element in the patent scope with the same name from another element with the same name.

另外，本文所使用的措詞和術語是出於描述的目的，並且不應被視為限制。本文中“包括”、“包含”、“具有”、“含有”或“涉及”及其變體的使用其意在涵蓋其後列出的項目及其等同物以及其他項目。In addition, the wording and terminology used herein are for descriptive purposes and should not be considered as limiting. The use of "including", "including", "having", "containing" or "involving" and variations thereof in this article is intended to cover the items listed thereafter and their equivalents as well as other items.

使用“耦接”或“連接”是指電路元件或信號可以直接彼此連接，也可以通過中間元件連接。The use of "coupled" or "connected" means that circuit elements or signals can be directly connected to each other, or can be connected through intermediate elements.

措詞“大約”、“基本上”和“約”可以在一些實施例中表示在目標值的±20％之內，在一些實施例中表示在目標值的±10％之內，在一些實施例中表示在目標值的±5％之內，在一些實施例中表示在目標值的±2％之內。術語“基本上” 、“大約”和“約”可以包括目標值。The words "approximately", "substantially" and "about" may in some embodiments mean within ±20% of the target value, in some embodiments, mean within ±10% of the target value, and in some embodiments In the example, it is within ±5% of the target value, and in some embodiments, it is within ±2% of the target value. The terms "substantially", "about" and "about" may include the target value.

100:系統 110:線性化器 130:放大器 102a、102b:輸入端 104a、104b:輸出端 150、170和190:曲線圖 154、152:阻抗傳遞函數 172、174:增益因數 192、194:整體傳遞函數 200a、200b、200c:系統 202、202a、202b:輸入端 204、204a、204b:輸出端 210a、210b、210c:線性化器 230a、230b、230c:放大器 212、212a、212b、232、232a、232b:電晶體 214、214a、214b:DC偏置電壓 242、342、442、542:匹配網路 240、340、440、540:電流鏡 206、306、406、506:DC電源 300a、300b、400a、400b、500a、500b:系統 302、302a、302b、402、402a、402b、502:輸入端 304、304a、304b、404、404a、404b、504:輸出端 310a、310b、410a、410b、510a、510b:線性化器 330a、330b、430a、430b、530a、530b:放大器 312a、312b、312c、312d、332a、332b、332c、332d:電晶體 314a、314b、314c、314d、334a、334b:DC偏置電壓 412、412a、412b、412c、412d、432、432a、432b、432c、432d:電晶體 414、414a、414b、414c、414d、434a、434b:DC偏置電壓 512、512a、512b、532:電晶體 514、514a、514b:DC偏置電壓100: System 110: Linearizer 130: Amplifier 102a, 102b: input 104a, 104b: output terminal 150, 170, and 190: graphs 154, 152: Impedance transfer function 172, 174: gain factor 192, 194: Overall transfer function 200a, 200b, 200c: system 202, 202a, 202b: input 204, 204a, 204b: output 210a, 210b, 210c: linearizer 230a, 230b, 230c: amplifier 212, 212a, 212b, 232, 232a, 232b: Transistor 214, 214a, 214b: DC bias voltage 242, 342, 442, 542: matching network 240, 340, 440, 540: current mirror 206, 306, 406, 506: DC power supply 300a, 300b, 400a, 400b, 500a, 500b: system 302, 302a, 302b, 402, 402a, 402b, 502: input 304, 304a, 304b, 404, 404a, 404b, 504: output 310a, 310b, 410a, 410b, 510a, 510b: linearizer 330a, 330b, 430a, 430b, 530a, 530b: amplifier 312a, 312b, 312c, 312d, 332a, 332b, 332c, 332d: Transistor 314a, 314b, 314c, 314d, 334a, 334b: DC bias voltage 412, 412a, 412b, 412c, 412d, 432, 432a, 432b, 432c, 432d: Transistor 414, 414a, 414b, 414c, 414d, 434a, 434b: DC bias voltage 512, 512a, 512b, 532: Transistor 514, 514a, 514b: DC bias voltage

第1A圖是例示根據一些實施例的示例系統的框圖，系統包括由線性化器補償的放大器。 第1B圖示出了對應於第1A圖所示系統的一系列曲線圖。 第2A圖是根據一些實施例的例示系統的電路圖，系統包括由線性化器補償的單端放大器。 第2B圖是根據一些實施例的例示系統的電路圖，該系統包括由串疊式線性化器補償的單端放大器。 第2C圖是根據一些實施例的例示系統的電路圖，該系統包括以線性化器補償的差動放大器。 第3A圖是根據一些實施例的例示系統的電路圖，該系統包括用串疊式（cascode）線性化器補償的串疊式差動放大器。 第3B圖是根據一些實施例的例示系統的電路圖，該系統包括由串疊式線性放大器補償的串疊式單端放大器。 第4A圖是根據一些實施例的例示系統的電路圖，系統包括由輸出端耦接的線性化器補償的單端放大器。 第4B圖是根據一些實施例的例示系統的電路圖，該系統包括由輸出端耦接的串疊式線性放大器補償的串疊式差動放大器。 第5A圖是根據一些實施例的例示系統的電路圖，該系統包括用PMOS線性化器補償的單端放大器。 第5B圖是根據一些實施例的例示系統的電路圖，該系統包括由PMOS和NMOS線性化器補償的單端放大器。Figure 1A is a block diagram illustrating an example system according to some embodiments, the system including an amplifier compensated by a linearizer. Figure 1B shows a series of graphs corresponding to the system shown in Figure 1A. Figure 2A is a circuit diagram of an exemplary system according to some embodiments. The system includes a single-ended amplifier compensated by a linearizer. Figure 2B is a circuit diagram of an exemplary system according to some embodiments, the system including a single-ended amplifier compensated by a cascade linearizer. Figure 2C is a circuit diagram of an exemplary system according to some embodiments, the system including a differential amplifier compensated with a linearizer. Figure 3A is a circuit diagram of an exemplary system according to some embodiments, the system including a cascode linearizer compensated with a cascode linearizer. Figure 3B is a circuit diagram of an exemplary system according to some embodiments, the system including a cascaded single-ended amplifier compensated by a cascaded linear amplifier. Figure 4A is a circuit diagram of an exemplary system according to some embodiments. The system includes a single-ended amplifier compensated by a linearizer coupled to an output. FIG. 4B is a circuit diagram of an exemplary system according to some embodiments, the system including a cascade differential amplifier compensated by a cascade linear amplifier coupled to an output terminal. Figure 5A is a circuit diagram of an exemplary system according to some embodiments, the system including a single-ended amplifier compensated with a PMOS linearizer. Figure 5B is a circuit diagram of an exemplary system according to some embodiments, the system including a single-ended amplifier compensated by PMOS and NMOS linearizers.

200a、200b、200c:系統 200a, 200b, 200c: system

202:輸入端 202: Input

204:輸出端 204: output

210a:線性化器 210a: Linearizer

230a:放大器 230a: amplifier

212、232:電晶體 212, 232: Transistor

242:匹配網路 242: matching network

240:電流鏡 240: current mirror

206:DC電源 206: DC power supply

214:DC偏置電壓 214: DC bias voltage

Claims (17)

一種放大器線性化裝置，包括：放大器；以及線性化器，所述線性化器包括第一電晶體，所述第一電晶體包括：源極端子，耦接至所述放大器的輸入端；汲極端子，被配置為接收從直流電源傳送到所述汲極端子的直流電源電壓；以及控制端子，被配置為控制在所述源極端子和所述汲極端子之間流動的電流，並且被配置為接收與所述源極端子的電壓不同的直流偏置電壓，其中，所述直流偏置電壓是從多個直流偏置電壓中可選擇的偏置電壓，使得所述第一電晶體在特定的電壓區間產生期望的非線性通道阻抗以抵消所述放大器的非線性增益因數。 An amplifier linearization device includes: an amplifier; and a linearizer, the linearizer includes a first transistor, and the first transistor includes: a source terminal coupled to an input terminal of the amplifier; a drain terminal A sub, configured to receive a DC power supply voltage transmitted from a DC power supply to the drain terminal; and a control terminal, configured to control a current flowing between the source terminal and the drain terminal, and configured In order to receive a DC bias voltage different from the voltage of the source terminal, wherein the DC bias voltage is a bias voltage selectable from a plurality of DC bias voltages, so that the first transistor is at a specific The voltage interval of φ generates the desired nonlinear channel impedance to cancel the nonlinear gain factor of the amplifier. 如申請專利範圍第1項所述的放大器線性化裝置，其中，響應於接收所述直流偏置電壓，所述第一電晶體被配置為控制所述源極端子和所述汲極端子之間的阻抗。 The amplifier linearization device according to claim 1, wherein, in response to receiving the DC bias voltage, the first transistor is configured to control the relationship between the source terminal and the drain terminal的impedance. 如申請專利範圍第1項所述的放大器線性化裝置，其中，所述放大器包括具有共通道端子配置的第一電晶體。 The amplifier linearization device according to the first item of the scope of patent application, wherein the amplifier includes a first transistor having a common channel terminal configuration. 如申請專利範圍第3項所述的放大器線性化裝置，其中，所述放大器還包括具有共控制端子配置的第二電晶體。 The amplifier linearization device according to the third item of the scope of patent application, wherein the amplifier further includes a second transistor with a common control terminal configuration. 如申請專利範圍第4項所述的放大器線性化裝置，其中，所述放大器的所述第一電晶體和所述放大器的所述第二電晶體分別是具有共源極和共閘極配置的場效應電晶體(FET)。 The amplifier linearization device according to claim 4, wherein the first transistor of the amplifier and the second transistor of the amplifier have common source and common gate configurations, respectively Field Effect Transistor (FET). 如申請專利範圍第1項所述的放大器線性化裝置，其中，所述線性化器還包括第二電晶體，所述第一電晶體通過所述第二電晶體耦接至所述放 大器的輸入端，所述第二電晶體包括：第一端子，耦接到所述放大器的輸入端；第二端子，耦接所述第一電晶體的所述源極端子；以及控制端子，被配置為控制在所述第二電晶體的所述第一端子和所述第二電晶體的所述第二端子之間流動的電流，並且被配置為接收與所述第二電晶體的所述第一端子的電壓不同的另一直流偏置電壓。 The amplifier linearization device according to claim 1, wherein the linearizer further includes a second transistor, and the first transistor is coupled to the amplifier through the second transistor. The input terminal of the amplifier, the second transistor includes: a first terminal coupled to the input terminal of the amplifier; a second terminal coupled to the source terminal of the first transistor; and a control terminal , Is configured to control the current flowing between the first terminal of the second transistor and the second terminal of the second transistor, and is configured to receive communication with the second transistor Another DC bias voltage with a different voltage at the first terminal. 如申請專利範圍第1項所述的放大器線性化裝置，其中所述第一電晶體的所述汲極端子耦接到所述放大器的輸出端。 The amplifier linearization device according to the first item of the scope of patent application, wherein the drain terminal of the first transistor is coupled to the output terminal of the amplifier. 如申請專利範圍第1項所述的放大器線性化裝置，其中，所述控制端子處的電壓為：比所述源極端子處的電壓大至少所述第一電晶體的閾值電壓，並且比所述汲極端子處的電壓小至少所述閾值電壓；或者比所述源極端子處的電壓小至少所述閾值電壓，並且比所述汲極端子處的電壓大至少所述閾值電壓。 The amplifier linearization device according to claim 1, wherein the voltage at the control terminal is greater than the voltage at the source terminal by at least the threshold voltage of the first transistor, and is greater than the voltage at the source terminal. The voltage at the drain terminal is smaller by at least the threshold voltage; or the voltage at the source terminal is smaller than the voltage at the source terminal by at least the threshold voltage, and the voltage at the drain terminal is larger than the voltage at the drain terminal by at least the threshold voltage. 一種放大器線性化裝置，包括：放大器，包括：輸入端；輸出端；以及耦接在所述輸入端和所述輸出端之間的第一組電晶體，所述第一組電晶體包括一個或多個電晶體；以及線性化器，包括：第二組電晶體，耦接在直流電源和所述放大器的所述輸入端之間，所述第二組電晶體包括一個或多個電晶體，所述第二組電晶體在特定的電壓區間產生期望的非線性通道阻抗以抵消所述放大器的非線性增益因數；以及 其中所述第一組電晶體和所述第二組電晶體具有相同的拓撲結構，其中所述第二組電晶體被配置為接收從所述直流電源傳送到所述第二組電晶體的直流電源電壓。 An amplifier linearization device includes: an amplifier including: an input terminal; an output terminal; and a first group of transistors coupled between the input terminal and the output terminal, the first group of transistors including one or A plurality of transistors; and a linearizer, comprising: a second set of transistors, coupled between the DC power supply and the input terminal of the amplifier, the second set of transistors including one or more transistors, The second set of transistors generates a desired nonlinear channel impedance in a specific voltage interval to cancel the nonlinear gain factor of the amplifier; and The first group of transistors and the second group of transistors have the same topological structure, and the second group of transistors is configured to receive the direct current transmitted from the direct current power source to the second group of transistors voltage. 如申請專利範圍第9項所述的放大器線性化裝置，其中所述第一組電晶體和所述第二組電晶體均包括串疊式拓撲結構或者均包括非串疊式拓撲結構。 The amplifier linearization device according to the ninth patent application, wherein the first group of transistors and the second group of transistors both include a series topology or both include a non-series topology. 如申請專利範圍第10項所述的放大器線性化裝置，其中，所述第一組電晶體和所述第二組電晶體均包括串疊式拓撲結構，並且其中，所述第一組電晶體中的相應的第一電晶體和第二電晶體包括共控制端子配置和共通道端子配置。 The amplifier linearization device according to claim 10, wherein the first group of transistors and the second group of transistors each include a tandem topology, and wherein, the first group of transistors The corresponding first transistor and second transistor in include a common control terminal configuration and a common channel terminal configuration. 如申請專利範圍第11項所述的放大器線性化裝置，其中，所述第二組電晶體中的第一電晶體和第二電晶體的通道在所述放大器的所述輸入端與所述直流電源之間彼此耦接。 The amplifier linearization device according to item 11 of the scope of patent application, wherein the channels of the first transistor and the second transistor in the second group of transistors are connected between the input end of the amplifier and the direct current The power supplies are coupled to each other. 如申請專利範圍第12項所述的放大器線性化裝置，其中，所述第一組電晶體中的所述第一電晶體和所述第二電晶體是場效應電晶體(FET)，分別包括共閘極配置和共源極配置。 The amplifier linearization device according to item 12 of the scope of patent application, wherein the first transistor and the second transistor in the first group of transistors are field-effect transistors (FET), which respectively include Common gate configuration and common source configuration. 如申請專利範圍第10項所述的放大器線性化裝置，其中，所述第一組電晶體和所述第二組電晶體均包括非串疊式拓撲結構，並且其中，所述第一組電晶體中的第一電晶體包括共通道端子配置。 The amplifier linearization device according to claim 10, wherein the first set of transistors and the second set of transistors both include a non-tandem topology, and wherein the first set of transistors The first transistor in the crystal includes a common channel terminal configuration. 如申請專利範圍第14項所述的放大器線性化裝置，其中，所述第二組電晶體中的第一電晶體的通道端子耦接至所述直流電源以及所述放大器的輸入端。 The amplifier linearization device according to item 14 of the scope of patent application, wherein the channel terminal of the first transistor in the second group of transistors is coupled to the DC power supply and the input terminal of the amplifier. 如申請專利範圍第15項所述的放大器線性化裝置，其中，所述第一組電晶體中的所述第一電晶體是包括共源極配置的場效應電晶體(FET)。 The amplifier linearization device according to the 15th patent application, wherein the first transistor in the first group of transistors is a field effect transistor (FET) including a common source configuration. 如申請專利範圍第9項所述的放大器線性化裝置，其中所述第二組電晶體耦接在所述放大器的所述輸入端與所述輸出端之間。 The amplifier linearization device according to the 9th patent application, wherein the second set of transistors are coupled between the input terminal and the output terminal of the amplifier.

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