TWI743851B - Pcie slot detection system - Google Patents

Pcie slot detection system Download PDF

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TWI743851B
TWI743851B TW109120941A TW109120941A TWI743851B TW I743851 B TWI743851 B TW I743851B TW 109120941 A TW109120941 A TW 109120941A TW 109120941 A TW109120941 A TW 109120941A TW I743851 B TWI743851 B TW I743851B
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detection
peripheral component
component interconnection
control chip
slot
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TW109120941A
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TW202201238A (en
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張天超
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英業達股份有限公司
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Abstract

A PCIe slot detection system is provided. Detection signal is transferred to PCIe control chip by PCIe interface to detect PCIe slot and generate first detection result information. First detection result information is transferred to detection application by PCIe slot. Detection signal is transferred to PCIe control chip by PCIe interface to detection logic control chip to control detection and set detection logic according to detection signal for detect PCIe slot and generate second detection result information. Second detection result information is transferred to detection application by PCIe slot. Therefore, the efficiency of detecting pins of PCIe slot individually may be achieved.

Description

快速周邊組件互連插槽檢測系統Rapid Peripheral Component Interconnect Slot Inspection System

一種檢測系統，尤其是指一種提供快速周邊組件互連插槽各個腳位進行檢測系統。A detection system, in particular, refers to a detection system that provides fast peripheral component interconnection sockets for each pin.

當前快速周邊組件互連插槽檢測通常是採用標準快速周邊組件互連網卡加以實現，採用標準快速周邊組件互連網卡檢測只能檢測到基本的電源特徵和標準快速周邊組件互連插槽的連接狀態，無法詳細對標準快速周邊組件互連插槽的各個角為分開檢測，也沒有輔助腳位檢測的功能，現有對於標準快速周邊組件互連插槽的檢測覆蓋率偏低。At present, rapid peripheral component interconnection slot detection is usually realized by using standard rapid peripheral component interconnection network card, and standard rapid peripheral component interconnection network card detection can only detect the basic power characteristics and the connection status of standard rapid peripheral component interconnection slot. It is impossible to separately detect the corners of the standard rapid peripheral component interconnection slot in detail, and there is no auxiliary pin detection function. The existing detection coverage rate for the standard rapid peripheral component interconnection slot is low.

綜上所述，可知先前技術中長期以來一直存在現有對標準快速周邊組件互連插槽檢測無法提供各個腳位檢測的問題，因此有必要提出改進的技術手段，來解決此一問題。In summary, it can be seen that the prior art has long been a problem that the existing standard fast peripheral component interconnection slot detection cannot provide individual pin detection. Therefore, it is necessary to propose improved technical means to solve this problem.

有鑒於先前技術存在現有對標準快速周邊組件互連插槽檢測無法提供各個腳位檢測的問題，本發明遂揭露一種快速周邊組件互連插槽檢測系統，其中：In view of the prior art problem that the existing standard rapid peripheral component interconnection slot detection cannot provide individual pin detection, the present invention discloses a rapid peripheral component interconnection slot detection system, in which:

本發明所揭露第一實施態樣的快速周邊組件互連插槽檢測系統，其包含：主機板以及檢測電路板，檢測電路板更包含：快速周邊組件互連控制晶片以及檢測邏輯控制晶片。The present invention discloses a first embodiment of the rapid peripheral component interconnection slot inspection system, which includes a main board and a test circuit board, and the test circuit board further includes: a rapid peripheral component interconnection control chip and a test logic control chip.

主機板具有中央處理器、記憶體、快速周邊組件互連（Peripheral Component Interconnect Express，PCIe）插槽，檢測程式儲存於記憶體中，中央處理器自記憶體加載並執行檢測程式以生成檢測訊號，檢測程式透過快速周邊組件互連插槽傳輸檢測訊號、第一檢測結果資訊以及第二檢測結果資訊。The motherboard has a central processing unit, a memory, and a Peripheral Component Interconnect Express (PCIe) slot. The detection program is stored in the memory. The central processing unit loads and executes the detection program from the memory to generate the detection signal. The detection program transmits the detection signal, the first detection result information, and the second detection result information through the fast peripheral component interconnection slot.

檢測電路板透過快速周邊組件互連介面插設於快速周邊組件互連插槽，檢測電路板的快速周邊組件互連控制晶片與快速周邊組件互連介面直接與透過開關形成電性連接，自快速周邊組件互連介面傳輸檢測訊號以對快速周邊組件互連插槽進行檢測並生成第一檢測結果資訊，透過快速周邊組件互連插槽傳輸第一檢測結果資訊至檢測程式；及檢測電路板的檢測邏輯控制晶片與快速周邊組件互連介面直接與透過開關形成電性連接，檢測邏輯控制晶片與快速周邊組件互連控制晶片直接與透過開關形成電性連接，自快速周邊組件互連介面傳輸檢測訊號以依據檢測訊號進行檢測控制以及進行檢測邏輯設定以對快速周邊組件互連插槽進行檢測並生成第二檢測結果資訊，透過快速周邊組件互連插槽傳輸第二檢測結果資訊至檢測程式。The test circuit board is inserted into the rapid peripheral component interconnection slot through the rapid peripheral component interconnection interface, and the rapid peripheral component interconnection control chip and the rapid peripheral component interconnection interface of the test circuit board are directly electrically connected with the switch through the switch. The peripheral component interconnection interface transmits detection signals to detect the rapid peripheral component interconnection slot and generate first test result information, and transmits the first test result information to the test program through the rapid peripheral component interconnection slot; and detects the circuit board The detection logic control chip and the fast peripheral component interconnection interface are directly electrically connected with the through switch, and the detection logic control chip and the fast peripheral component interconnection control chip are directly electrically connected with the through switch, and the detection is transmitted from the fast peripheral component interconnection interface. The signal is used to perform detection control and detection logic settings based on the detection signal to detect the fast peripheral component interconnection slot and generate second detection result information, and transmit the second detection result information to the testing program through the fast peripheral component interconnection slot.

本發明所揭露第二實施態樣的快速周邊組件互連插槽檢測系統，其包含：主機板、檢測電路板以及檢測裝置，檢測電路板更包含：快速周邊組件互連控制晶片、檢測邏輯控制晶片、第一UART轉RS-232介面晶片、第二UART轉RS-232介面晶片、快速周邊組件互連封包切換連接器以及檢測邏輯連接連接器。The second embodiment of the present invention discloses a rapid peripheral component interconnection slot detection system, which includes: a motherboard, a detection circuit board, and a detection device. The detection circuit board further includes: a rapid peripheral component interconnection control chip and a detection logic control Chip, first UART to RS-232 interface chip, second UART to RS-232 interface chip, fast peripheral component interconnection packet switching connector, and detection logic connection connector.

主機板具有快速周邊組件互連插槽，檢測電路板透過快速周邊組件互連介面插設於快速周邊組件互連插槽，檢測電路板的快速周邊組件互連控制晶片與快速周邊組件互連介面直接與透過開關形成電性連接，接收檢測訊號以對快速周邊組件互連插槽進行檢測並生成第一檢測結果資訊；檢測電路板的檢測邏輯控制晶片與快速周邊組件互連介面直接與透過開關形成電性連接，檢測邏輯控制晶片與快速周邊組件互連控制晶片直接與透過開關形成電性連接，接收檢測訊號以依據檢測訊號進行檢測控制以及進行檢測邏輯設定以對快速周邊組件互連插槽進行檢測並生成述第二檢測結果資訊；檢測電路板的快速周邊組件互連封包切換連接器與快速周邊組件互連控制晶片直接與透過第一UART轉RS-232介面晶片形成電性連接，快速周邊組件互連封包切換連接器傳輸檢測訊號至快速周邊組件互連控制晶片，快速周邊組件互連封包切換連接器對第一檢測結果資訊進行傳輸；及檢測電路板的檢測邏輯連接連接器與檢測邏輯控制晶片透過第二UART轉RS-232介面晶片形成電性連接，檢測邏輯連接連接器傳輸檢測訊號至檢測邏輯控制晶片，檢測邏輯連接連接器對第二檢測結果資訊進行傳輸。The motherboard has a fast peripheral component interconnection slot, the test circuit board is inserted into the fast peripheral component interconnection slot through the rapid peripheral component interconnection interface, and the rapid peripheral component interconnection control chip and the fast peripheral component interconnection interface of the test circuit board Directly form an electrical connection with the through switch, receive the detection signal to detect the fast peripheral component interconnection slot and generate the first detection result information; the detection logic control chip of the test circuit board and the fast peripheral component interconnect interface are directly connected with the through switch An electrical connection is formed. The detection logic control chip and the fast peripheral component interconnection control chip are directly electrically connected with the through switch. The detection signal is received to perform detection control based on the detection signal and the detection logic setting is performed to connect the fast peripheral component interconnection slot Perform inspection and generate the second inspection result information; the fast peripheral component interconnection packet switching connector of the testing circuit board and the fast peripheral component interconnection control chip directly form an electrical connection with the first UART to RS-232 interface chip, which is fast The peripheral component interconnection packet switching connector transmits the detection signal to the rapid peripheral component interconnection control chip, and the rapid peripheral component interconnection packet switching connector transmits the first inspection result information; and the inspection logic connection connector of the inspection circuit board and the inspection The logic control chip forms an electrical connection through the second UART to RS-232 interface chip, the detection logic connection connector transmits the detection signal to the detection logic control chip, and the detection logic connection connector transmits the second detection result information.

檢測裝置執行有檢測程式以生成檢測訊號，檢測裝置分別與快速周邊組件互連封包切換連接器以及檢測邏輯連接連接器形成電性連接，檢測程式分別透過快速周邊組件互連封包切換連接器以及檢測邏輯連接連接器傳輸檢測訊號，檢測程式透過快速周邊組件互連封包切換連接器傳輸第一檢測結果資訊，檢測程式透過檢測邏輯連接連接器傳輸第二檢測結果資訊。The detection device executes a detection program to generate a detection signal. The detection device forms an electrical connection with the fast peripheral component interconnection packet switching connector and the detection logic connection connector. The detection program respectively uses the fast peripheral component interconnection packet switching connector and detection The logical connection connector transmits the detection signal, the detection program transmits the first detection result information through the fast peripheral component interconnection packet switching connector, and the detection program transmits the second detection result information through the detection logical connection connector.

本發明所揭露的系統如上，與先前技術之間的差異在於快速周邊組件互連控制晶片自快速周邊組件互連介面傳輸檢測訊號以對快速周邊組件互連插槽進行檢測並生成第一檢測結果資訊，透過快速周邊組件互連插槽傳輸第一檢測結果資訊至檢測程式，檢測邏輯控制晶片自快速周邊組件互連介面傳輸檢測訊號以依據檢測訊號進行檢測控制以及進行檢測邏輯設定以對快速周邊組件互連插槽進行檢測並生成第二檢測結果資訊，透過快速周邊組件互連插槽傳輸第二檢測結果資訊至檢測程式。The system disclosed in the present invention is as above. The difference from the prior art is that the rapid peripheral component interconnection control chip transmits the detection signal from the rapid peripheral component interconnection interface to detect the rapid peripheral component interconnection slot and generate the first test result. Information, the first inspection result information is transmitted to the inspection program through the fast peripheral component interconnection slot, the inspection logic control chip transmits the inspection signal from the fast peripheral component interconnection interface to perform inspection control based on the inspection signal and the inspection logic setting to control the rapid peripheral The component interconnection slot performs detection and generates second detection result information, and transmits the second detection result information to the testing program through the fast peripheral component interconnection slot.

透過上述的技術手段，本發明可以達成快速周邊組件互連插槽腳位各別檢測的技術功效。Through the above-mentioned technical means, the present invention can achieve the technical effect of rapid peripheral component interconnection socket pin detection.

以下將配合圖式及實施例來詳細說明本發明的實施方式，藉此對本發明如何應用技術手段來解決技術問題並達成技術功效的實現過程能充分理解並據以實施。The following describes the implementation of the present invention in detail with the drawings and embodiments, so as to fully understand and implement the implementation process of how the present invention uses technical means to solve technical problems and achieve technical effects.

以下首先要說明本發明所揭露第一實施態樣的快速周邊組件互連插槽檢測系統，並請參考「第1圖」所示，「第1圖」繪示為本發明第一實施態樣快速周邊組件互連插槽檢測系統的系統方塊圖。The following first describes the rapid peripheral component interconnection slot detection system disclosed in the first embodiment of the present invention, and please refer to "Figure 1" which shows the first embodiment of the present invention. The system block diagram of the fast peripheral component interconnection slot inspection system.

本發明所揭露第一實施態樣的快速周邊組件互連插槽檢測系統，其包含：主機板10以及檢測電路板20，檢測電路板20更包含：快速周邊組件互連控制晶片21以及檢測邏輯控制晶片22。The first embodiment of the present invention discloses a rapid peripheral component interconnection slot inspection system, which includes: a motherboard 10 and a test circuit board 20. The test circuit board 20 further includes: a rapid peripheral component interconnection control chip 21 and a test logic Control wafer 22.

主機板10具有中央處理器11、記憶體12、快速周邊組件互連（Peripheral Component Interconnect Express，PCIe）插槽13，檢測程式儲存於記憶體12中，中央處理器11自記憶體12加載並執行檢測程式以生成檢測訊號。The motherboard 10 has a central processing unit 11, a memory 12, and a Peripheral Component Interconnect Express (PCIe) slot 13. The detection program is stored in the memory 12, and the central processing unit 11 is loaded and executed from the memory 12 Test program to generate test signal.

檢測電路板20透過快速周邊組件互連介面23插設於快速周邊組件互連插槽13，檢測電路板20的快速周邊組件互連控制晶片21與快速周邊組件互連介面23直接與透過開關24形成電性連接，檢測電路板20的檢測邏輯控制晶片22與快速周邊組件互連介面23直接與透過開關24形成電性連接，檢測邏輯控制晶片22與快速周邊組件互連控制晶片21直接與透過開關24形成電性連接。The test circuit board 20 is inserted into the rapid peripheral component interconnection slot 13 through the rapid peripheral component interconnection interface 23, and the rapid peripheral component interconnection control chip 21 and the rapid peripheral component interconnection interface 23 of the test circuit board 20 are directly connected through the switch 24 An electrical connection is formed. The detection logic control chip 22 of the detection circuit board 20 and the fast peripheral component interconnection interface 23 are directly electrically connected to the through switch 24, and the detection logic control chip 22 and the fast peripheral component interconnection control chip 21 are directly connected to the through switch 24. The switch 24 forms an electrical connection.

除此之外，檢測電路板20更包含：唯讀記憶體（Read-Only Memory ，ROM）25、EJTAG介面26、JLINK介面27、石英振盪器（crystal ）28。In addition, the detection circuit board 20 further includes: a read-only memory (ROM) 25, an EJTAG interface 26, a JLINK interface 27, and a crystal 28.

唯讀記憶體25與快速周邊組件互連控制晶片22形成電性連接， EJTAG介面26與快速周邊組件互連控制晶片22形成電性連接，JLINK介面27與檢測邏輯控制晶片24形成電性連接，石英振盪器28透過時脈產生器（Clock）29與快速周邊組件互連控制晶片22形成電性連接，石英振盪器28與檢測邏輯控制晶片24形成電性連接。The read-only memory 25 forms an electrical connection with the fast peripheral component interconnection control chip 22, the EJTAG interface 26 forms an electrical connection with the fast peripheral component interconnection control chip 22, and the JLINK interface 27 forms an electrical connection with the detection logic control chip 24. The quartz oscillator 28 is electrically connected to the fast peripheral component interconnection control chip 22 through a clock generator (Clock) 29, and the quartz oscillator 28 is electrically connected to the detection logic control chip 24.

檢測程式透過快速周邊組件互連插槽13即可傳輸檢測訊號至快速周邊組件互連控制晶片21，快速周邊組件互連控制晶片21依據檢測訊號對快速周邊組件互連插槽13進行檢測並生成第一檢測結果資訊，快速周邊組件互連控制晶片21透過快速周邊組件互連插槽13傳輸第一檢測結果資訊至檢測程式。The inspection program can transmit the inspection signal to the rapid peripheral component interconnection control chip 21 through the rapid peripheral component interconnection slot 13, and the rapid peripheral component interconnection control chip 21 detects and generates the rapid peripheral component interconnection slot 13 according to the inspection signal The first inspection result information, the rapid peripheral component interconnection control chip 21 transmits the first inspection result information to the inspection program through the rapid peripheral component interconnection slot 13.

檢測程式透過快速周邊組件互連插槽13即可傳輸檢測訊號至檢測邏輯控制晶片22，檢測邏輯控制晶片22依據檢測訊號進行檢測控制以及進行檢測邏輯設定以對快速周邊組件互連插槽13進行檢測並生成第二檢測結果資訊，檢測邏輯控制晶片22透過快速周邊組件互連插槽13傳輸第二檢測結果資訊至檢測程式。The inspection program can transmit the inspection signal to the inspection logic control chip 22 through the fast peripheral component interconnection slot 13, and the inspection logic control chip 22 performs inspection control according to the inspection signal and performs inspection logic settings to perform the inspection on the fast peripheral component interconnection slot 13. The second inspection result information is detected and generated, and the inspection logic control chip 22 transmits the second inspection result information to the inspection program through the fast peripheral component interconnection slot 13.

值得注意的是，快速周邊組件互連插槽13進行檢測包含電源腳位檢測、PCIe傳輸速度檢測、PCIe傳輸頻寬檢測、PCIe傳輸速度切換檢測、系統管理匯流排（System Management Bus，SMBus）檢測、喚醒（WAKE）檢測、JTAG檢測、PWRBRK檢測以及CLKREQ檢測。It is worth noting that the Fast Peripheral Component Interconnect slot 13 performs detection including power pin detection, PCIe transmission speed detection, PCIe transmission bandwidth detection, PCIe transmission speed switching detection, and System Management Bus (SMBus) detection. , Wake up (WAKE) detection, JTAG detection, PWRBRK detection and CLKREQ detection.

接著，以下說明本發明所揭露第二實施態樣的快速周邊組件互連插槽檢測系統，並請參考「第2圖」所示，「第2圖」繪示為本發明第二實施態樣快速周邊組件互連插槽檢測系統的系統方塊圖。Next, the following describes the rapid peripheral component interconnection slot detection system disclosed in the second embodiment of the present invention, and please refer to "Figure 2" which shows the second embodiment of the present invention. The system block diagram of the fast peripheral component interconnection slot inspection system.

本發明所揭露第二實施態樣的快速周邊組件互連插槽檢測系統，其包含：主機板10、檢測電路板20以及檢測裝置40，檢測電路板20更包含：快速周邊組件互連控制晶片21、檢測邏輯控制晶片22、第一UART轉RS-232介面晶片31、第二UART轉RS-232介面晶片32、快速周邊組件互連封包切換連接器33以及檢測邏輯連接連接器34。The second embodiment of the present invention discloses a rapid peripheral component interconnection slot detection system, which includes: a motherboard 10, a detection circuit board 20, and a detection device 40. The detection circuit board 20 further includes: a rapid peripheral component interconnection control chip 21. The detection logic control chip 22, the first UART to RS-232 interface chip 31, the second UART to RS-232 interface chip 32, the fast peripheral component interconnection packet switching connector 33, and the detection logic connection connector 34.

檢測電路板20透過快速周邊組件互連介面23插設於快速周邊組件互連插槽13，檢測電路板20的快速周邊組件互連控制晶片21與快速周邊組件互連介面23直接與透過開關24形成電性連接，檢測電路板20的檢測邏輯控制晶片22與快速周邊組件互連介面23直接與透過開關24形成電性連接，檢測邏輯控制晶片22與快速周邊組件互連控制晶片21直接與透過開關24形成電性連接，檢測電路板20的快速周邊組件互連封包切換連接器33與快速周邊組件互連控制晶片21直接與透過第一UART轉RS-232介面晶片31形成電性連接，檢測電路板20的檢測邏輯連接連接器34與檢測邏輯控制晶片22透過第二UART轉RS-232介面晶片32形成電性連接。The test circuit board 20 is inserted into the rapid peripheral component interconnection slot 13 through the rapid peripheral component interconnection interface 23, and the rapid peripheral component interconnection control chip 21 and the rapid peripheral component interconnection interface 23 of the test circuit board 20 are directly connected through the switch 24 An electrical connection is formed. The detection logic control chip 22 of the detection circuit board 20 and the fast peripheral component interconnection interface 23 are directly electrically connected to the through switch 24, and the detection logic control chip 22 and the fast peripheral component interconnection control chip 21 are directly connected to the through switch 24. The switch 24 forms an electrical connection, and the fast peripheral component interconnection packet switching connector 33 of the detection circuit board 20 and the fast peripheral component interconnection control chip 21 directly form an electrical connection with the first UART to RS-232 interface chip 31 to detect The detection logic connection connector 34 of the circuit board 20 and the detection logic control chip 22 are electrically connected through the second UART to RS-232 interface chip 32.

除此之外，檢測電路板20更包含：唯讀記憶體25、EJTAG介面26、JLINK介面27、石英振盪器28。In addition, the detection circuit board 20 further includes: a read-only memory 25, an EJTAG interface 26, a JLINK interface 27, and a quartz oscillator 28.

唯讀記憶體25與快速周邊組件互連控制晶片22形成電性連接， EJTAG介面26與快速周邊組件互連控制晶片22形成電性連接，JLINK介面27與檢測邏輯控制晶片24形成電性連接，石英振盪器28透過時脈產生器（Clock）29與快速周邊組件互連控制晶片22形成電性連接，石英振盪器28與檢測邏輯控制晶片24形成電性連接。The read-only memory 25 forms an electrical connection with the fast peripheral component interconnection control chip 22, the EJTAG interface 26 forms an electrical connection with the fast peripheral component interconnection control chip 22, and the JLINK interface 27 forms an electrical connection with the detection logic control chip 24. The quartz oscillator 28 is electrically connected to the fast peripheral component interconnection control chip 22 through a clock generator (Clock) 29, and the quartz oscillator 28 is electrically connected to the detection logic control chip 24.

檢測裝置30執行有檢測程式以生成檢測訊號，檢測裝置30分別與快速周邊組件互連封包切換連接器33以及檢測邏輯連接連接器34形成電性連接，檢測程式透過UART傳輸方式透過快速周邊組件互連封包切換連接器33傳輸檢測訊號至快速周邊組件互連控制晶片21，快速周邊組件互連控制晶片21依據檢測訊號對快速周邊組件互連插槽13進行檢測並生成第一檢測結果資訊，快速周邊組件互連控制晶片21透過快速周邊組件互連封包切換連接器33對第一檢測結果資訊進行傳輸。The detection device 30 executes a detection program to generate a detection signal. The detection device 30 is respectively electrically connected with the fast peripheral component interconnection packet switching connector 33 and the detection logic connection connector 34, and the detection program is transmitted through the fast peripheral component interconnection via UART transmission. The packet switching connector 33 transmits the detection signal to the fast peripheral component interconnection control chip 21. The fast peripheral component interconnection control chip 21 detects the fast peripheral component interconnection socket 13 according to the detection signal and generates the first detection result information, which is fast The peripheral component interconnection control chip 21 transmits the first inspection result information through the rapid peripheral component interconnection packet switching connector 33.

檢測程式透過UART傳輸方式透過檢測邏輯連接連接器34傳輸檢測訊號至檢測邏輯控制晶片22，檢測邏輯控制晶片22依據檢測訊號進行檢測控制以及進行檢測邏輯設定以對快速周邊組件互連插槽13進行檢測並生成第二檢測結果資訊，檢測邏輯控制晶片22透過檢測邏輯連接連接器34對第二檢測結果資訊傳輸至檢測程式。The inspection program transmits the inspection signal to the inspection logic control chip 22 through the inspection logic connection connector 34 through the UART transmission method. The inspection logic control chip 22 performs inspection control according to the inspection signal and performs inspection logic settings to perform the rapid peripheral component interconnection socket 13 The second detection result information is detected and generated, and the detection logic control chip 22 transmits the second detection result information to the detection program through the detection logic connection connector 34.

值得注意的是，快速周邊組件互連插槽13進行檢測包含電源腳位檢測、PCIe傳輸速度檢測、PCIe傳輸頻寬檢測、PCIe傳輸速度切換檢測、系統管理匯流排（System Management Bus，SMBus）檢測、喚醒（WAKE）檢測、JTAG檢測、PWRBRK檢測以及CLKREQ檢測。It is worth noting that the Fast Peripheral Component Interconnect slot 13 performs detection including power pin detection, PCIe transmission speed detection, PCIe transmission bandwidth detection, PCIe transmission speed switching detection, and System Management Bus (SMBus) detection. , Wake up (WAKE) detection, JTAG detection, PWRBRK detection and CLKREQ detection.

請參考「第3圖」所示，「第3圖」繪示為本發明快速周邊組件互連插槽檢測的電源腳位檢測示意圖。Please refer to "Figure 3". "Figure 3" is a schematic diagram of power pin detection for rapid peripheral component interconnection slot detection of the present invention.

檢測邏輯控制晶片22接收到的檢測訊號為電源腳位檢測時，檢測邏輯控制晶片22即會對快速周邊組件互連插槽13的電源腳位分別進行電壓的量測以生成第二檢測結果資訊，檢測程式會判斷第二檢測結果資訊中電源腳位所量測到的電壓是否符合PCIe所規範的電壓範圍，檢測程式即可檢測出快速周邊組件互連插槽13的電源腳位是否正常供電。When the detection signal received by the detection logic control chip 22 is power pin detection, the detection logic control chip 22 will measure the voltage of the power pins of the fast peripheral component interconnection socket 13 to generate the second detection result information. , The test program will determine whether the voltage measured by the power pin in the second test result information meets the voltage range specified by PCIe, and the test program can detect whether the power pin of the fast peripheral component interconnect slot 13 is normally powered .

檢測邏輯控制晶片22接收到的檢測訊號為電源腳位檢測時，檢測邏輯控制晶片22即會對快速周邊組件互連插槽13的電源腳位分別進行電壓的量測以生成第二檢測結果資訊，檢測程式會判斷第二檢測結果資訊中電源腳位所量測到的電壓是否符合PCIe所規範的電壓範圍，檢測程式即可檢測出快速周邊組件互連插槽13的電源腳位是否正常供電。When the detection signal received by the detection logic control chip 22 is power pin detection, the detection logic control chip 22 will measure the voltage of the power pins of the fast peripheral component interconnection socket 13 to generate the second detection result information. , The test program will determine whether the voltage measured by the power pin in the second test result information meets the voltage range specified by PCIe, and the test program can detect whether the power pin of the fast peripheral component interconnect slot 13 is normally powered .

快速周邊組件互連控制晶片21在檢測電路板20透過快速周邊組件互連介面21插設於快速周邊組件互連插槽13時偵測並將PCIe傳輸速度以及PCIe傳輸頻寬儲存於暫存器中，檢測邏輯控制晶片22自暫存器中取得PCIe傳輸速度以及PCIe傳輸頻寬以生成第二檢測結果，快速周邊組件互連控制晶片21依據檢測訊號控制PCIe傳輸速度的切換，並將PCIe傳輸速度切換後的PCIe的連接狀態生成為第一檢測結果，檢測程式即可檢測出快速周邊組件互連插槽13的PCIe傳輸速度、PCIe傳輸頻寬以及PCIe傳輸速度切換是否與PCIe的規範相符。The fast peripheral component interconnection control chip 21 detects and stores the PCIe transmission speed and PCIe transmission bandwidth in the register when the detection circuit board 20 is inserted into the fast peripheral component interconnection slot 13 through the fast peripheral component interconnection interface 21 In, the detection logic control chip 22 obtains the PCIe transmission speed and PCIe transmission bandwidth from the register to generate the second detection result. The fast peripheral component interconnection control chip 21 controls the switching of the PCIe transmission speed according to the detection signal, and transmits the PCIe The PCIe connection status after the speed switch is generated as the first detection result, and the detection program can detect whether the PCIe transmission speed, PCIe transmission bandwidth of the fast peripheral component interconnect slot 13 and the PCIe transmission speed switching comply with the PCIe specification.

請參考「第4A圖」以及「第4B圖」所示，「第4A圖」繪示為本發明快速周邊組件互連插槽檢測的系統管理匯流排Master模式檢測示意圖；「第4B圖」繪示為本發明快速周邊組件互連插槽檢測的系統管理匯流排Slave模式檢測示意圖。Please refer to "Figure 4A" and "Figure 4B". "Figure 4A" is a schematic diagram of the system management bus Master mode test for rapid peripheral component interconnect slot detection of the present invention; "Figure 4B" is drawn Shown is a schematic diagram of the system management bus Slave mode detection of the rapid peripheral component interconnection slot detection of the present invention.

在系統管理匯流排的Master模式檢測中，檢測邏輯控制晶片22依據檢測訊號設定為I2C Master檢測狀態，檢測邏輯控制晶片22獲得主機板10上I2C裝置的位址，檢測邏輯控制晶片22會讀取或者寫入I2C位址空間，檢測程式根據I2C位址空間讀取或者寫入的成功與否判定SMBus的可用性。In the Master mode inspection of the system management bus, the inspection logic control chip 22 is set to the I2C Master inspection state according to the inspection signal, the inspection logic control chip 22 obtains the address of the I2C device on the motherboard 10, and the inspection logic control chip 22 will read Or write to the I2C address space, and the detection program determines the availability of SMBus based on the success of reading or writing to the I2C address space.

在系統管理匯流排的Slave模式檢測中，僅能適用第一實施態樣，檢測程式訪問主機板的基板管理控制器（Baseboard Management Controller，BMC）或者是ICH上的SMBus控制器，藉由SMBus控制器訪問檢測邏輯控制晶片22所模擬的EEPROM，透過讀寫此EEPROM來驗證SMBus匯流排的可用性。In the Slave mode detection of the system management bus, only the first implementation mode can be applied. The detection program accesses the Baseboard Management Controller (BMC) of the motherboard or the SMBus controller on the ICH, which is controlled by SMBus The device accesses the EEPROM simulated by the detection logic control chip 22, and verifies the availability of the SMBus bus by reading and writing the EEPROM.

請參考「第5圖」所示，「第5圖」繪示為本發明快速周邊組件互連插槽檢測的喚醒檢測示意圖。Please refer to "Figure 5". "Figure 5" is a schematic diagram of the wake-up detection of the rapid peripheral component interconnection slot detection of the present invention.

喚醒檢測包含有IO模式和Function模式，Function模式的適應場景是主機板10透過BMC讀取喚醒狀態，或者主機板10有多於一個的PCIe插槽，並且各個PCIe插槽之間的喚醒連接在一起，由第一檢測邏輯控制晶片221發出喚醒訊號，由主機板10的BMC讀取喚醒狀態或是由第二檢測邏輯控制晶片222讀取喚醒狀態，或是由第二檢測邏輯控制晶片222發出喚醒訊號，由主機板10的BMC讀取喚醒狀態或是由第一檢測邏輯控制晶片221讀取喚醒狀態藉以進行檢測。Wake-up detection includes IO mode and Function mode. The application scenario of Function mode is that the motherboard 10 reads the wake-up status through the BMC, or the motherboard 10 has more than one PCIe slot, and the wake-up between each PCIe slot is connected in At the same time, the first detection logic control chip 221 sends out a wake-up signal, the BMC of the motherboard 10 reads the wake-up state or the second detection logic control chip 222 reads the wake-up state, or the second detection logic control chip 222 sends out a wake-up signal. For the wake-up signal, the BMC of the motherboard 10 reads the wake-up state or the first detection logic control chip 221 reads the wake-up state for detection.

請參考「第6圖」所示，「第6圖」繪示為本發明快速周邊組件互連插槽檢測的IO檢測模型示意圖。Please refer to "Figure 6". "Figure 6" is a schematic diagram of the IO detection model for rapid peripheral component interconnection slot detection of the present invention.

JTAG包括TMS、TDI、TDO以及TCK，JTAG、PWRBRK以及CLKREQ的訊號都採用IO檢測模型，IO檢測模型請參考「第6圖」所示，即任意一個被檢測的腳位，檢測邏輯控制晶片22的IO連接到此腳位上時，檢測邏輯控制晶片22可以控制連接在這個腳位上的兩個電阻分別設定為上拉電阻以及下拉電阻。檢測邏輯控制晶片22透過控制上拉狀態、下拉狀態以及無上下拉狀態，同時讀取IO的狀態訊號，可以確定被檢測的腳位是H/L/NC狀態。JTAG includes TMS, TDI, TDO, and TCK. The signals of JTAG, PWRBRK, and CLKREQ all use the IO detection model. Please refer to "Figure 6" for the IO detection model. That is, any one of the detected pins, the detection logic control chip 22 When the IO is connected to this pin, the detection logic control chip 22 can control the two resistors connected to this pin to be set as a pull-up resistor and a pull-down resistor, respectively. The detection logic control chip 22 can determine that the detected pin is in the H/L/NC state by controlling the pull-up state, the pull-down state, and the no-up-pull-down state, while reading the state signal of the IO.

綜上所述，可知本發明與先前技術之間的差異在於快速周邊組件互連控制晶片自快速周邊組件互連介面傳輸檢測訊號以對快速周邊組件互連插槽進行檢測並生成第一檢測結果資訊，透過快速周邊組件互連插槽傳輸第一檢測結果資訊至檢測程式，檢測邏輯控制晶片自快速周邊組件互連介面傳輸檢測訊號以依據檢測訊號進行檢測控制以及進行檢測邏輯設定以對快速周邊組件互連插槽進行檢測並生成第二檢測結果資訊，透過快速周邊組件互連插槽傳輸第二檢測結果資訊至檢測程式。In summary, it can be seen that the difference between the present invention and the prior art is that the rapid peripheral component interconnection control chip transmits the detection signal from the rapid peripheral component interconnection interface to detect the rapid peripheral component interconnection slot and generate the first inspection result. Information, the first inspection result information is transmitted to the inspection program through the fast peripheral component interconnection slot, the inspection logic control chip transmits the inspection signal from the fast peripheral component interconnection interface to perform inspection control based on the inspection signal and the inspection logic setting to control the rapid peripheral The component interconnection slot performs detection and generates second detection result information, and transmits the second detection result information to the testing program through the fast peripheral component interconnection slot.

藉由此一技術手段可以來解決先前技術所存在現有對標準快速周邊組件互連插槽檢測無法提供各個腳位檢測的問題，進而達成快速周邊組件互連插槽腳位各別檢測的技術功效。This technical method can solve the problem that the existing standard rapid peripheral component interconnection socket detection cannot provide individual pin detection in the existing technology, and then achieve the technical effect of the rapid peripheral component interconnection socket pin detection technology. .

雖然本發明所揭露的實施方式如上，惟所述的內容並非用以直接限定本發明的專利保護範圍。任何本發明所屬技術領域中具有通常知識者，在不脫離本發明所揭露的精神和範圍的前提下，可以在實施的形式上及細節上作些許的更動。本發明的專利保護範圍，仍須以所附的申請專利範圍所界定者為準。Although the embodiments disclosed in the present invention are as described above, the content described is not intended to directly limit the scope of patent protection of the present invention. Anyone with ordinary knowledge in the technical field to which the present invention belongs can make slight changes in the implementation form and details without departing from the spirit and scope disclosed by the present invention. The scope of patent protection of the present invention shall still be subject to those defined by the scope of the attached patent application.

10:主機板 11:中央處理器 12:記憶體 13:快速周邊組件互連插槽 20:檢測電路板 21:快速周邊組件互連控制晶片 22:檢測邏輯控制晶片 221:第一檢測邏輯控制晶片 222:第二檢測邏輯控制晶片 23:快速周邊組件互連介面 24:開關 25:唯讀記憶體 26:EJTAG介面 27:JLINK介面 28:石英振盪器 29:時脈產生器 31:第一UART轉RS-232介面晶片 32:第二UART轉RS-232介面晶片 33:快速周邊組件互連封包切換連接器 34:檢測邏輯連接連接器 10: Motherboard 11: Central Processing Unit 12: Memory 13: Fast peripheral component interconnection slot 20: Test the circuit board 21: Fast peripheral component interconnection control chip 22: Inspection logic control chip 221: The first detection logic control chip 222: The second detection logic control chip 23: Fast peripheral component interconnection interface 24: switch 25: Read-only memory 26: EJTAG interface 27: JLINK interface 28: Quartz oscillator 29: Clock generator 31: The first UART to RS-232 interface chip 32: The second UART to RS-232 interface chip 33: Fast peripheral component interconnection packet switching connector 34: Detect logical connection connector

第1圖繪示為本發明第一實施態樣快速周邊組件互連插槽檢測系統的系統方塊圖。 第2圖繪示為本發明第二實施態樣快速周邊組件互連插槽檢測系統的系統方塊圖。 第3圖繪示為本發明快速周邊組件互連插槽檢測的電源腳位檢測示意圖。 第4A圖繪示為本發明快速周邊組件互連插槽檢測的系統管理匯流排Master模式檢測示意圖。 第4B圖繪示為本發明快速周邊組件互連插槽檢測的系統管理匯流排Slave模式檢測示意圖。 第5圖繪示為本發明快速周邊組件互連插槽檢測的喚醒檢測示意圖。 第6圖繪示為本發明快速周邊組件互連插槽檢測的IO檢測模型示意圖。 FIG. 1 is a system block diagram of the rapid peripheral component interconnection slot detection system according to the first embodiment of the present invention. FIG. 2 is a system block diagram of the rapid peripheral component interconnection slot detection system according to the second embodiment of the present invention. FIG. 3 is a schematic diagram of power pin detection for rapid peripheral component interconnection slot detection of the present invention. FIG. 4A is a schematic diagram of the system management bus Master mode detection of the rapid peripheral component interconnection slot detection of the present invention. FIG. 4B is a schematic diagram of the system management bus Slave mode detection of the rapid peripheral component interconnection slot detection of the present invention. FIG. 5 is a schematic diagram of wake-up detection for rapid peripheral component interconnection slot detection of the present invention. Figure 6 is a schematic diagram of the IO detection model for rapid peripheral component interconnection slot detection of the present invention.

10:主機板 10: Motherboard

11:中央處理器 11: Central Processing Unit

12:記憶體 12: Memory

13:快速周邊組件互連插槽 13: Fast peripheral component interconnection slot

20:檢測電路板 20: Test the circuit board

21:快速周邊組件互連控制晶片 21: Fast peripheral component interconnection control chip

22:檢測邏輯控制晶片 22: Inspection logic control chip

23:快速周邊組件互連介面 23: Fast peripheral component interconnection interface

24:開關 24: switch

25:唯讀記憶體 25: Read-only memory

26:EJTAG介面 26: EJTAG interface

24:JLINK介面 24: JLINK interface

28:石英振盪器 28: Quartz oscillator

29:時脈產生器 29: Clock generator

Claims (10)

一種快速周邊組件互連插槽檢測系統，其包含：一主機板，所述主機板具有一中央處理器、一記憶體、一快速周邊組件互連(Peripheral Component Interconnect Express，PCIe)插槽，一檢測程式儲存於所述記憶體中，所述中央處理器自所述記憶體加載並執行所述檢測程式以生成一檢測訊號，所述檢測程式透過所述快速周邊組件互連插槽傳輸所述檢測訊號、一第一檢測結果資訊以及一第二檢測結果資訊；一檢測電路板，所述檢測電路板透過一快速周邊組件互連介面插設於所述快速周邊組件互連插槽，所述檢測電路板更包含：一快速周邊組件互連控制晶片，所述快速周邊組件互連控制晶片與所述快速周邊組件互連介面直接與透過開關形成電性連接，自所述快速周邊組件互連介面傳輸所述檢測訊號以對所述快速周邊組件互連插槽進行檢測並生成所述第一檢測結果資訊，透過所述快速周邊組件互連插槽傳輸所述第一檢測結果資訊至所述檢測程式；及一檢測邏輯控制晶片，所述檢測邏輯控制晶片與所述快速周邊組件互連介面直接與透過開關形成電性連接，所述檢測邏輯控制晶片與所述快速周邊組件互連控制晶片直接與透過開關形成電性連接，自所述快速周邊組件互連介面傳輸所述檢測訊號以依據所述檢測訊號進行檢測控制以及進行檢測邏輯設定以對所述快速周邊組件互連插槽進行檢測並 生成所述第二檢測結果資訊，透過所述快速周邊組件互連插槽傳輸所述第二檢測結果資訊至所述檢測程式。 A rapid peripheral component interconnection slot detection system, comprising: a motherboard with a central processing unit, a memory, a Peripheral Component Interconnect Express (PCIe) slot, The detection program is stored in the memory, and the central processing unit loads and executes the detection program from the memory to generate a detection signal, and the detection program transmits the detection signal through the fast peripheral component interconnection slot A detection signal, a first detection result information, and a second detection result information; a detection circuit board, the detection circuit board is inserted into the rapid peripheral component interconnection slot through a rapid peripheral component interconnection interface, the The test circuit board further includes: a rapid peripheral component interconnection control chip, the rapid peripheral component interconnection control chip and the rapid peripheral component interconnection interface directly form an electrical connection with a switch, from the rapid peripheral component interconnection The interface transmits the detection signal to detect the fast peripheral component interconnection slot and generates the first detection result information, and transmits the first detection result information to the fast peripheral component interconnection slot through the A detection program; and a detection logic control chip, the detection logic control chip and the fast peripheral component interconnection interface are directly electrically connected with a through switch, the detection logic control chip and the fast peripheral component interconnection control chip Directly form an electrical connection with a switch, and transmit the detection signal from the fast peripheral component interconnection interface to perform detection control according to the detection signal and perform detection logic settings to detect the fast peripheral component interconnection slot and The second detection result information is generated, and the second detection result information is transmitted to the detection program through the fast peripheral component interconnection slot. 如請求項1所述的快速周邊組件互連插槽檢測系統，其中對所述快速周邊組件互連插槽進行檢測包含電源腳位檢測、PCIe傳輸速度檢測、PCIe傳輸頻寬檢測、PCIe傳輸速度切換檢測、系統管理匯流排(System Management Bus，SMBus)檢測、喚醒(WAKE)檢測、JTAG檢測、PWRBRK檢測以及CLKREQ檢測。 The fast peripheral component interconnection slot detection system according to claim 1, wherein the detection of the fast peripheral component interconnection slot includes power pin detection, PCIe transmission speed detection, PCIe transmission bandwidth detection, PCIe transmission speed Switch detection, System Management Bus (SMBus) detection, WAKE detection, JTAG detection, PWRBRK detection and CLKREQ detection. 如請求項1所述的快速周邊組件互連插槽檢測系統，其中所述快速周邊組件互連控制晶片在所述檢測電路板透過所述快速周邊組件互連介面插設於所述快速周邊組件互連插槽時偵測並將PCIe傳輸速度以及PCIe傳輸頻寬儲存於暫存器中，所述檢測邏輯控制晶片自暫存器中取得PCIe傳輸速度以及PCIe傳輸頻寬以生成所述第二檢測結果。 The rapid peripheral component interconnection slot inspection system according to claim 1, wherein the rapid peripheral component interconnection control chip is inserted into the rapid peripheral component on the test circuit board through the rapid peripheral component interconnection interface When interconnecting slots, detect and store the PCIe transmission speed and PCIe transmission bandwidth in the register. The detection logic control chip obtains the PCIe transmission speed and PCIe transmission bandwidth from the register to generate the second Test results. 如請求項1所述的快速周邊組件互連插槽檢測系統，其中所述快速周邊組件互連控制晶片依據所述檢測訊號控制PCIe傳輸速度的切換，並將PCIe傳輸速度切換後的PCIe的連接狀態生成為所述第一檢測結果。 The fast peripheral component interconnection slot detection system according to claim 1, wherein the fast peripheral component interconnection control chip controls the switching of the PCIe transmission speed according to the detection signal, and connects the PCIe after the PCIe transmission speed is switched The state is generated as the first detection result. 如請求項1所述的快速周邊組件互連插槽檢測系統，其中所述檢測邏輯控制晶片依據所述檢測訊號將所述檢測邏輯控制晶片的輸入輸出腳位與所述快速周邊組件互連插槽需要檢測的腳位設定形成電性連接，且所述檢測邏輯控制晶片設定所述檢測邏輯控制晶片的輸入輸出腳位相連的二個電阻為上拉電阻以及下拉電阻，所述檢測邏輯控制晶片控制所述檢測邏輯控制晶片的輸入輸出腳位為上拉狀態、下拉狀態以及無上拉下拉狀態以對所述快速周邊組件互連插槽需要檢測的腳位進行檢測。 The fast peripheral component interconnection socket inspection system according to claim 1, wherein the detection logic control chip connects the input and output pins of the detection logic control chip to the fast peripheral component interconnection socket according to the detection signal The pin setting of the slot to be detected forms an electrical connection, and the detection logic control chip sets the two resistors connected to the input and output pins of the detection logic control chip as a pull-up resistor and a pull-down resistor, and the detection logic control chip The input and output pins of the detection logic control chip are controlled to be in a pull-up state, a pull-down state, and a pull-up-free state to detect the pins that need to be detected in the fast peripheral component interconnection slot. 一種外部連結標準插槽檢測系統，其包含：一主機板，所述主機板具有一快速周邊組件互連(Peripheral Component Interconnect Express，PCIe)插槽；一檢測電路板，所述檢測電路板透過一快速周邊組件互連介面插設於所述快速周邊組件互連插槽，所述檢測電路板更包含：一快速周邊組件互連控制晶片，所述快速周邊組件互連控制晶片與所述快速周邊組件互連介面直接與透過開關形成電性連接，接收一檢測訊號以對所述快速周邊組件互連插槽進行檢測並生成一第一檢測結果資訊；一檢測邏輯控制晶片，所述檢測邏輯控制晶片與所述快速周邊組件互連介面直接與透過開關形成電性連接，所述檢測邏輯控制晶片與所述快速周邊組件互連控制晶片直接與透過開關形成電性連接，接收所述檢測訊號以依據所述檢測訊號進行檢測控制以及進行檢測邏輯設定以對所述快速周邊組件互連插槽進行檢測並生成一述第二檢測結果資訊；一快速周邊組件互連封包切換(PCIe switch)連接器，所述快速周邊組件互連封包切換連接器與所述快速周邊組件互連控制晶片直接與透過一第一UART轉RS-232介面晶片形成電性連接，所述快速周邊組件互連封包切換連接器傳輸所述檢測訊號至所述快速周邊組件互連控制晶片，所述快速周邊組件互連封包切換連接器對所述第一檢測結果資訊進行傳輸；及 一檢測邏輯連接連接器，所述檢測邏輯連接連接器與所述檢測邏輯控制晶片透過一第二UART轉RS-232介面晶片形成電性連接，所述檢測邏輯連接連接器傳輸所述檢測訊號至所述檢測邏輯控制晶片，所述檢測邏輯連接連接器對所述第二檢測結果資訊進行傳輸；及一檢測裝置，所述檢測裝置執行有一檢測程式以生成所述檢測訊號，所述檢測裝置分別與所述快速周邊組件互連封包切換連接器以及所述檢測邏輯連接連接器形成電性連接，所述檢測程式分別透過所述快速周邊組件互連封包切換連接器以及所述檢測邏輯連接連接器傳輸所述檢測訊號，所述檢測程式透過所述快速周邊組件互連封包切換連接器傳輸所述第一檢測結果資訊，所述檢測程式透過所述檢測邏輯連接連接器傳輸所述第二檢測結果資訊。 An external connection standard slot detection system, which includes: a motherboard with a Peripheral Component Interconnect Express (PCIe) slot; a detection circuit board, the detection circuit board through a The rapid peripheral component interconnection interface is inserted into the rapid peripheral component interconnection slot, and the test circuit board further includes: a rapid peripheral component interconnection control chip, the rapid peripheral component interconnection control chip and the rapid peripheral component interconnection control chip The component interconnection interface is directly electrically connected with the through switch, receives a detection signal to detect the fast peripheral component interconnection slot and generates a first detection result information; a detection logic control chip, the detection logic control The chip and the fast peripheral component interconnection interface are directly electrically connected with the through switch, the detection logic control chip and the fast peripheral component interconnection control chip are directly electrically connected with the through switch, and receive the detection signal to Perform detection control and perform detection logic settings based on the detection signal to detect the fast peripheral component interconnection slot and generate a second detection result information; a fast peripheral component interconnection packet switch (PCIe switch) connector The fast peripheral component interconnection packet switching connector and the fast peripheral component interconnection control chip directly form an electrical connection with a first UART to RS-232 interface chip, and the fast peripheral component interconnection packet switching connection Transmitting the detection signal to the rapid peripheral component interconnection control chip, and the rapid peripheral component interconnection packet switching connector transmits the first detection result information; and A detection logic connection connector, the detection logic connection connector and the detection logic control chip are electrically connected through a second UART to RS-232 interface chip, and the detection logic connection connector transmits the detection signal to The detection logic control chip, the detection logic connection connector transmits the second detection result information; and a detection device, the detection device executes a detection program to generate the detection signal, and the detection device respectively An electrical connection is formed with the rapid peripheral component interconnection packet switching connector and the detection logic connection connector, and the detection program respectively passes through the rapid peripheral component interconnection packet switching connector and the detection logic connection connector The detection signal is transmitted, the detection program transmits the first detection result information through the fast peripheral component interconnection packet switching connector, and the detection program transmits the second detection result through the detection logic connection connector News. 如請求項6所述的快速周邊組件互連插槽檢測系統，其中對所述快速周邊組件互連插槽進行檢測包含電源腳位檢測、PCIe傳輸速度檢測、PCIe傳輸頻寬檢測、PCIe傳輸速度切換檢測、系統管理匯流排(System Management Bus，SMBus)檢測、喚醒(WAKE)檢測、JTAG檢測、PWRBRK檢測以及CLKREQ檢測。 The fast peripheral component interconnection slot detection system according to claim 6, wherein the detection of the fast peripheral component interconnection slot includes power pin detection, PCIe transmission speed detection, PCIe transmission bandwidth detection, PCIe transmission speed Switch detection, System Management Bus (SMBus) detection, WAKE detection, JTAG detection, PWRBRK detection and CLKREQ detection. 如請求項6所述的快速周邊組件互連插槽檢測系統，其中所述快速周邊組件互連控制晶片在所述檢測電路板透過所述快速周邊組件互連介面插設於所述快速周邊組件互連插槽時偵測並將PCIe傳輸速度以及PCIe傳輸頻寬儲 存於暫存器中，所述檢測邏輯控制晶片自暫存器中取得PCIe傳輸速度以及PCIe傳輸頻寬以生成所述第二檢測結果。 The rapid peripheral component interconnection slot inspection system according to claim 6, wherein the rapid peripheral component interconnection control chip is inserted into the rapid peripheral component on the test circuit board through the rapid peripheral component interconnection interface Detect and store PCIe transmission speed and PCIe transmission bandwidth when interconnecting slots Stored in a register, the detection logic control chip obtains PCIe transmission speed and PCIe transmission bandwidth from the register to generate the second detection result. 如請求項6所述的快速周邊組件互連插槽檢測系統，其中所述快速周邊組件互連控制晶片依據所述檢測訊號控制PCIe傳輸速度的切換，並將PCIe傳輸速度切換後的PCIe的連接狀態生成為所述第一檢測結果。 The fast peripheral component interconnection slot detection system according to claim 6, wherein the fast peripheral component interconnection control chip controls the switching of the PCIe transmission speed according to the detection signal, and connects the PCIe after the PCIe transmission speed is switched The state is generated as the first detection result. 如請求項6所述的快速周邊組件互連插槽檢測系統，其中所述檢測邏輯控制晶片依據所述檢測訊號將所述檢測邏輯控制晶片的輸入輸出腳位與所述快速周邊組件互連插槽需要檢測的腳位設定形成電性連接，且所述檢測邏輯控制晶片設定所述檢測邏輯控制晶片的輸入輸出腳位相連的二個電阻為上拉電阻以及下拉電阻，所述檢測邏輯控制晶片控制所述檢測邏輯控制晶片的輸入輸出腳位為上拉狀態、下拉狀態以及無上拉下拉狀態以對所述快速周邊組件互連插槽需要檢測的腳位進行檢測。 The fast peripheral component interconnection socket inspection system according to claim 6, wherein the detection logic control chip connects the input and output pins of the detection logic control chip to the fast peripheral component interconnection socket according to the detection signal The pin setting of the slot to be detected forms an electrical connection, and the detection logic control chip sets the two resistors connected to the input and output pins of the detection logic control chip as a pull-up resistor and a pull-down resistor, and the detection logic control chip The input and output pins of the detection logic control chip are controlled to be in a pull-up state, a pull-down state, and a pull-up-free state to detect the pins that need to be detected in the fast peripheral component interconnection slot.
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