TWI741581B - 微流體致動器之異質整合晶片 - Google Patents
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Abstract
一種微流體致動器之異質整合晶片,包含:一第一基板,具有一第一腔體;一第一絕緣層,設置於第一基板上;一第一導電層,設置於第一絕緣層上,並具有至少一電極墊片;一壓電層,設置於第一導電層上;一第二導電層,設置於壓電層上;一第二基板,接合於第一基板,藉以定義出一第二腔體,並具有一噴孔、一流體流道以及一第三腔體;一接合層,接合於第一基板與第二基板之間;一控制元件,設置於第二基板中;至少一穿孔槽,由至少一電極墊片貫穿至第二基板;以及至少一導電體,填充於至少一穿孔槽中。
Description
本案關於一種整合晶片,尤指一種使用微機電半導體製程製作之微流體致動器之異質整合晶片。
目前於各領域中無論是醫藥、電腦科技、列印、能源等工業,產品均朝精緻化及微小化方向發展,其中微型幫浦產品所包含之微流體致動器為其關鍵技術。
隨著科技的日新月異,流體輸送結構的應用上亦愈來愈多元化,舉凡工業應用、生醫應用、醫療保健、電子散熱、生活電子產品……等,甚至近來熱門的行動穿戴裝置亦可見它的踨影,可見傳統的流體致動器已漸漸有朝向裝置微小化、流量極大化的趨勢。
現有技術中已發展多種微機電半導體製程製出之微流體致動器,然而,如何整合微流體致動器本體與控制元件(如微控器、控制電路)之整合,仍為發展之重要內容。
本案之主要目的係提供一種微流體致動器之異質整合晶片,與以半導體製程等製作之MOS電路IC或微控制器等,以矽穿孔(TSV)封裝技術結合而成。
本案之一廣義實施態樣為一種微流體致動器之異質整合晶片,包含一第一基板、一第一絕緣層、一第一導電層、一壓電層、一第二導電層、一第二基板、一接合層、一控制元件、至少一穿孔槽以及至少一導電體。第一基板,具有第一腔體。第一絕緣層,設置於第一基板上。第一導電層,設置於第一絕緣層上,並具有至少一電極墊片。壓電層,設置於第一導電層上。第二導電層,設置於壓電層上。第二基板,接合於第一基板,藉以定義出第二腔體,並具有噴孔、流體流道以及第三腔體。接合層,接合於第一基板與第二基板之間。控制元件,設置於第二基板中。至少一穿孔槽,由至少一電極墊片貫穿至第二基板。至少一導電體,填充於至少一穿孔槽中。
本案之另一廣義實施態樣為一種微流體致動器之異質整合晶片,包含一第一基板、一第一絕緣層、一第一導電層、一壓電層、一第二導電層、一第二基板、一控制元件、至少一穿孔槽以及至少一導電體。第一基板,具有至少一第一腔體。第一絕緣層,設置於第一基板上。第一導電層,設置於第一絕緣層上,並具有至少一電極墊片。壓電層,設置於第一導電層上。第二導電層,設置於壓電層上,第一導電層、壓電層、第二導電層定義出至少一致動區。第二基板,接合於第一基板,藉以定義出至少一第二腔體,並具有至少一噴孔、至少一流體流道以及至少一第三腔體,第一基板之至少一第一腔體、第二基板之至少一第二腔體、至少一噴孔、至少一流體流道以及至少一第三腔體與至少一致動區位置相對應。控制元件,設置於第二基板中。至少一穿孔槽,由至少一電極墊片貫穿至第二基板。至少一導電體,填充於至少一穿孔槽中。
體現本案特徵與優點的實施例將在後段的說明中詳細敘述。應理解的是本案能夠在不同的態樣上具有各種的變化,其皆不脫離本案的範圍,且其中的說明及圖示在本質上當作說明之用,而非用以限制本案。
請參閱第1圖,於本案第一實施例中,本案微流體致動器之異質整合晶片10,係由一第一基板1a、一第一絕緣層1b、一第一導電層1c、一壓電層1d、一第二導電層1e、一接合層1f、一第二基板2a、一控制元件3、至少一穿孔槽4、至少一導電體5以及至少一佈線體6組合而成。
值得注意的是,於本案第一實施例中,微流體致動器之異質整合晶片10包含一保護層7,用以保護第二基板2a、控制元件3以及佈線體6,但不以此為限,於其他實施例中,保護層7之設置可依設計需求而增減。此外,於本案第一實施例中,微流體致動器之異質整合晶片10更包含一閥層8,閥層8內具有至少一閥區8a,閥區8a內具有一逆止閥,用以防止流體傳輸過程中逆流,但不以此為限,於其他實施例中,閥層8與閥區8a之設置可依設計需求而變更。
另外值得注意的是,於本案第一實施例中,微流體致動器之異質整合晶片10包含單一個致動單元9,但不以此為限,於其他實施例中,微流體致動器之異質整合晶片10可由複數個致動單元9串聯、並聯、串並聯組合而成。
請參閱第2A圖至第2D圖,第一基板1a包含至少一第一腔體11a,於下列實施例中的第一腔體11a之數量係使用一個做舉例說明,但不以此為限。第一導電層1c、壓電層1d、第二導電層1e利用微影及蝕刻製程定義出至少一致動區M,於下列實施例中的至少一致動區M之數量係使用一個做舉例說明,但不以此為限。於本案第一實施例中,第一基板1a包含一第一腔體11a,利用微影及蝕刻製程製出。值得注意的是,於本案第一實施例中,第一基板1a為一矽基材,但不以此為限,於其他實施例中,第一基板1a之材料可依設計需求而變更。第一絕緣層1b設置於第一基板1a上。值得注意的是,於本案第一實施例中,第一絕緣層1b為一氮化矽材料,但不以此為限,於其他實施例中,第一絕緣層1b之材料可依設計需求而變更。第一導電層1c設置於第一絕緣層1b上,並具有至少一電極墊片(S'、D'、G'),於本案第一實施例中,第一導電層1c具有三個電極墊片(S'、D'、G'),但不以此為限。值得注意的是,於本案第一實施例中,第一導電層1c為一導電材料,如鈦/白金(Ti/Pt),但不以此為限,於其他實施例中,第一導電層1c之材料可依設計需求而變更。壓電層1d設置於第一導電層1c上。值得注意的是,於本案第一實施例中,壓電層1d為一壓電材料,如鋯鈦酸鉛(PZT)之薄膜或塊材,但不以此為限,於其他實施例中,壓電層1d之材料可依設計需求而變更。第二導電層1e設置於壓電層1d上。值得注意的是,於本案第一實施例中,第二導電層1e為一導電材料,如鈦/鋁(Ti/Al)或鉻/金(Cr/Au)……等,但不以此為限,於其他實施例中,第二導電層1e之材料可依設計需求而變更。第一導電層1c、壓電層1d、第二導電層1e利用微影及蝕刻製程定義出一致動區M。致動區M與第一腔體11a之位置相對應。接合層1f設置於第一基板1a相反於第一絕緣層1b之一面。值得注意的是,於本案第一實施例中,接合層1f為乾膜光阻(dry film photoresist)材料,但不以此為限,於其他實施例中,接合層1f之材料可依設計需求而變更。
請參閱第3A圖至第3F圖,第二基板2a包含至少一流體流道21a、至少一第二腔體22a、至少一第三腔體23a以及至少一噴孔24a,於下列實施例中之至少一流體流道21a、至少一第二腔體22a、至少一第三腔體23a以及至少一噴孔24a之數量係使用一個做舉例說明,但不以此為限。至少一流體流道21a、至少一第二腔體22a、至少一第三腔體23a以及至少一噴孔24a亦可為多個之組合。於本案第一實施例中,第二基板2a包含一流體流道21a、一第二腔體22a、一第三腔體23a以及一噴孔24a。流體流道21a、第二腔體22a以及第三腔體23a係利用微影及蝕刻製程製出。噴孔24a係利用雷射蝕刻製出。流體流道21a連通於噴孔24a以及第一基板1a之第一腔體11a之間。第二腔體22a連通於第三腔體23a以及第一基板1a之第一腔體11a之間。值得注意的是,於本案第一實施例中,第二基板2a為一矽基材,但不以此為限,於其他實施例中,第二基板2a之材料可依設計需求而變更。在進行流體流道21a以及第三腔體23a之微影蝕刻製程時,先於第二基板2a上設置一第一遮罩層2b,藉以定義出蝕刻之位置。值得注意的是,於本案第一實施例中,第一遮罩層2b為乾膜光阻(dry film photoresist)材料,但不以此為限,於其他實施例中,第一遮罩層2b之材料可依設計需求而變更。在進行第二腔體22a之微影蝕刻製程時,先於第二基板2a上設置一第二遮罩層2c,第二遮罩層2c具有一遮罩區21c,藉以定義出蝕刻之位置。值得注意的是,於本案第一實施例中,第二遮罩層2c為乾膜光阻(dry film photoresist)材料,但不以此為限,於其他實施例中,第二遮罩層2c之材料可依設計需求而變更。
請參閱第4圖,於本案第一實施例中,第一基板1a與第二基板2a透過接合層1f相互接合。
請回到第1圖,於本案第一實施例中,控制元件3係為一金屬氧化物半導體場效電晶體,控制元件3設置於第二基板2a中。至少一穿孔槽4由至少一電極墊片(S'、D'、G')貫穿至第二基板2a。於本案第一實施例中,微流體致動器之異質整合晶片10包含三個穿孔槽4,與電極墊片(S'、D'、G')之數量相對應,但不以此為限。至少一導電體5填充於至少一穿孔槽4中,於本案第一實施例中,微流體致動器之異質整合晶片10包含三個導電體5,分別填充三個穿孔槽4中,但不以此限。至少一佈線體6電性連接於控制元件3與至少一導電體5之間,於本案第一實施例中,微流體致動器之異質整合晶片10包含三個佈線體6,電性連接於控制元件3與三個導電體5之間,但不以此為限。又,佈線體6係於第二基板2a上電性連接於控制元件3與至少一導電體5之間,理應於同一平面,圖示係為了方便示意控制元件3與佈線體6之電性連接關係,且佈線體6不會影響噴孔24a之流體流出,於噴孔24a處以虛線示意。於本案第一實施例中,至少一穿孔槽4以及至少一導電體5之結構係為矽穿孔(TSV)技術,但不以此為限。於本案第一實施例中,保護層7用以保護第二基板2a、控制元件3以及佈線體6,且保護層7不會影響噴孔24a之流體流出,於噴孔24a處以虛線示意,但不以此為限,於其他實施例中,保護層7之設置可依設計需求而增減,但不以此為限。於本案第一實施例中,閥層8,具有至少一閥區8a,閥區8a內具有一逆止閥,用以防止流體傳輸過程中逆流,且閥區8a不會影響噴孔24a之流體流出,於噴孔24a處以虛線示意,但不以此為限,於其他實施例中,閥區8a之設置可依設計需求而變更,但不以此為限。
請參閱第4圖、第5A圖及第5B圖,於本案第一實施例中,第一腔體11a具有一第一深度(P1),介於50μm與200μm之間,但不以此為限,並可依設計需求而變更。於本案第一實施例中,接合層1f具有一第二深度(Q1),係為14μm,但不以此為限,於其他實施例中,接合層1f之第二深度(Q1)可介於10μm與35μm之間,並可依設計需求而變更。於本案第一實施例中,由接合層1f底部至第二基板2a底部之深度定義為一第三深度(R1),介於370μm與525μm之間,但不以此為限。值得注意的是,於本案實施例中,第一深度(P1)、第二深度(Q1)及第三深度(R1)係可依設計需求而相互變更;為配合流體之特性,不同的流體具備不同的黏滯性及壓縮性,可依此調整第一深度(P1)之深度,以提升流體輸送效率。
請參閱第6圖,於本案第一實施例中,微流體致動器之異質整合晶片10致動時,流體會自第三腔體23a經由第二腔體22a匯集至第一腔體11a,接著再由第一腔體11a經由流體流道21a流至噴孔24a後,由噴孔24a排出至微流體致動器之異質整合晶片10之外。
請參閱第7圖及第8圖,本案第二實施例與第一實施例大致相同,主要差異在於,微流體致動器之異質整合晶片100包含複數個致動單元9。於本案第二實施例中,致動單元9係藉由串並聯組合而成,但不以此為限。微流體致動器之異質整合晶片100致動時,流體分別由各致動單元9之第三腔體23a經由第二腔體22a匯集至第一腔體11a,再由第一腔體11a經由流體流道21a流至噴孔24a後,由噴孔24a排出至微流體致動器之異質整合晶片100之外。於本案第二實施例中,保護層7不會影響噴孔24a之流體流出,於噴孔24a處以虛線示意,但不以此為限,於其他實施例中,保護層7之設置可依設計需求而增減,但不以此為限。於本案第二實施例中,具有至少二閥區8a,閥區8a內具有一逆止閥,用以防止流體傳輸過程中逆流,且閥區8a不會影響噴孔24a之流體流出,於噴孔24a處以虛線示意,但不以此為限,於其他實施例中,閥區8a之設置可依設計需求而變更,但不以此為限。
請參閱第9圖,本案第三實施例與第一實施例大致相同,主要差異在於,微流體致動器之異質整合晶片10'還包含一過濾結構26a,設置於第二基板2a之第二腔體22a內,供以過濾流體。
請參閱第10A圖至第10C圖,於本案第三實施例中,過濾結構26a具有不同結構態樣,可為導槽狀(如第10A圖)、方柱狀(如第10B圖)、圓柱狀(如第10C圖)其中之一,但不以此為限,於其他實施例中,過濾結構26a之結構態樣可依設計需求而變更。
請參閱第11圖,本案第四實施例與第一實施例大致相同,主要差異在於,微流體致動器之異質整合晶片10''不包含接合層1f。第一基板1a與第二基板2a之接合係以卡榫接合方式來接合。值得注意的是,於本案實施例中,卡榫接合方式係為自體對準接合,與傳統需以定位點對位之接合方式不同,即,透過卡榫第一基板1a與第二基板2a可相互自行對準並接合。於本案第四實施例中,保護層7不會影響噴孔24a之流體流出,於噴孔24a處以虛線示意,但不以此為限,於其他實施例中,保護層7之設置可依設計需求而增減,但不以此為限。於本案第四實施例中,具有至少一閥區8a,閥區8a內具有一逆止閥,用以防止流體傳輸過程中逆流,且閥區8a不會影響噴孔24a之流體流出,於噴孔24a處以虛線示意,但不以此為限,於其他實施例中,閥區8a之設置可依設計需求而變更,但不以此為限。
請參閱第12A圖至第12C圖,於本案第四實施例中,第一基板1a具有至少一接合凹槽1g,以及第二基板2a具有至少一接合凸件25a。接合凹槽1g與接合凸件25a之形狀相互對應,以使第一基板1a與第二基板2a得利用卡榫接合方式來接合。如第12A圖所示,接合凸件25a之形狀為正方體,如第12B圖所示,接合凸件25a之形狀為四邊體,如第12C圖所示,接合凸件25a之形狀為長方體,但不以此為限,於其他實施例中,接合凹槽1g與接合凸件25a之形狀可依設計需求而變更。
本案提供一微流體致動器之異質整合晶片,使用微機電半導體製程,並輔以矽穿孔(TSV)封裝技術製作而成,微流體致動器與控制元件在相對兩面,並且可藉由控制微流體致動器之晶片整合來達成流體輸送目的,極具產業之利用價值,爰依法提出申請。
本案得由熟知此技術之人士任施匠思而為諸般修飾,然皆不脫如附申請專利範圍所欲保護者。
10、10'、10''、100、100a、100b、100c:微流體致動器之異質整合晶片
1a:第一基板
1b:第一絕緣層
1c:第一導電層
1d:壓電層
1e:第二導電層
1f:接合層
1g:接合凹槽
11a:第一腔體
2a:第二基板
21a:流體流道
22a:第二腔體
23a:第三腔體
24a:噴孔
25a:接合凸件
26a:過濾結構
2b:第一遮罩層
2c:第二遮罩層
21c:遮罩區
3:控制元件
4:穿孔槽
5:導電體
6:佈線體
7:保護層
8:閥層
8a:閥區
9:致動單元
D:汲極區
D':汲極電極墊片
G:閘極區
G':閘極電極墊片
M:致動區
P1:第一深度
Q1:第二深度
R1:第三深度
S:源極區
S':源極電極墊片
第1圖為本案微流體致動器之異質整合晶片之第一實施例之剖面示意圖。
第2A圖至第3F圖為本案第一實施例之製造步驟分解示意圖。
第4圖為本案第一實施例之微流體致動結構之剖面示意圖。
第5A圖及第5B圖為本案第一實施例之不同深度態樣示意圖。
第6圖為本案第一實施例之流體流動示意圖。
第7圖為本案微流體致動器之異質整合晶片之第二實施例之部分立體俯視圖。
第8圖為本案第二實施例之流體流動示意圖。
第9圖為本案微流體致動器之異質整合晶片之第三實施例之剖面示意圖。
第10A圖至第10C圖為本案第三實施例之不同結構態樣之局部立體示意圖。
第11圖為本案微流體致動器之異質整合晶片之第四實施例之剖面示意圖。
第12A圖至第12C圖為本案第四實施例之不同接合態樣之局部立體***示意圖。
10:微流體致動器之異質整合晶片
1a:第一基板
1b:第一絕緣層
1c:第一導電層
1d:壓電層
1e:第二導電層
1f:接合層
11a:第一腔體
2a:第二基板
21a:流體流道
22a:第二腔體
23a:第三腔體
24a:噴孔
3:控制元件
4:穿孔槽
5:導電體
6:佈線體
7:保護層
8:閥層
8a:閥區
9:致動單元
D:汲極區
D':汲極電極墊片
G:閘極區
G':閘極電極墊片
M:致動區
S:源極區
S':源極電極墊片
Claims (13)
- 一種微流體致動器之異質整合晶片,包含:一第一基板,具有一第一腔體;一第一絕緣層,設置於該第一基板上;一第一導電層,設置於該第一絕緣層上,並具有至少一電極墊片;一壓電層,設置於該第一導電層上;一第二導電層,設置於該壓電層上;一第二基板,接合於該第一基板,藉以定義出一第二腔體,並具有一噴孔、一流體流道以及一第三腔體;一接合層,接合於該第一基板與該第二基板之間;一控制元件,設置於該第二基板中;至少一穿孔槽,由該至少一電極墊片貫穿至該第二基板;至少一導電體,填充於該至少一穿孔槽中;以及至少一佈線體,電性連接於該控制元件與該至少一導電體之間。
- 如請求項1所述之微流體致動器之異質整合晶片,其中該第一基板與該第二基板分別為一矽基板。
- 如請求項1所述之微流體致動器之異質整合晶片,其中該第一絕緣層係為一氮化矽材料。
- 如請求項1所述之微流體致動器之異質整合晶片,其中該控制元件係為一金屬氧化物半導體場效電晶體。
- 如請求項1所述之微流體致動器之異質整合晶片,其中該第一腔體之一第一深度介於50μm~200μm之間。
- 如請求項1所述之微流體致動器之異質整合晶片,其中該接合層之一第二深度介於10μm~35μm之間。
- 如請求項1所述之微流體致動器之異質整合晶片,其中該接合層底部至該第二基板底部之一第三深度介於370μm~525μm之間。
- 如請求項1所述之微流體致動器之異質整合晶片,其中該第二基板具有至少一接合凸件。
- 如請求項8所述之微流體致動器之異質整合晶片,其中該至少一接合凸件之形狀為正方體、長方體、四邊體其中之一。
- 如請求項9所述之微流體致動器之異質整合晶片,其中該第一基板具有至少一接合凹槽,該至少一接合凹槽與該第二基板之該至少一接合凸件之形狀相對應。
- 如請求項1所述之微流體致動器之異質整合晶片,更包含一過濾結構,設置於該第二腔體內。
- 如請求項11所述之微流體致動器之異質整合晶片,該過濾結構之形狀係為導槽狀、方柱狀、圓柱狀其中之一。
- 一種微流體致動器之異質整合晶片,包含:一第一基板,具有至少一第一腔體;一第一絕緣層,設置於該第一基板上;一第一導電層,設置於該第一絕緣層上,並具有至少一電極墊片;一壓電層,設置於該第一導電層上;一第二導電層,設置於該壓電層上,該第一導電層、該壓電層、該第二導電層定義出至少一致動區; 一第二基板,接合於該第一基板,藉以定義出至少一第二腔體,並具有至少一噴孔、至少一流體流道以及至少一第三腔體,該第一基板之該至少一第一腔體、該第二基板之該至少一第二腔體、該至少一噴孔、該至少一流體流道以及該至少一第三腔體與該至少一致動區位置相對應;一控制元件,設置於該第二基板中;至少一穿孔槽,由該至少一電極墊片貫穿至該第二基板;至少一導電體,填充於該至少一穿孔槽中;以及至少一佈線體,電性連接於該控制元件與該至少一導電體之間。
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