TWI738386B - Gate on array driving circuit - Google Patents
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本發明是關於一種閘極陣列驅動電路，特別是關於一種藉由穩壓電晶體的設置，減少穩壓節點電壓準位偏移造成錯誤輸出問題的閘極陣列驅動電路。 The present invention relates to a gate array drive circuit, in particular to a gate array drive circuit that reduces the problem of wrong output caused by the voltage level deviation of the voltage stabilizing node through the setting of a voltage stabilizing transistor.
現有顯示面板的驅動電路，會以閘極陣列驅動電路(GOA)來取代閘極控制晶片來達到節省成本的目的，但由於顯示面板的尺寸逐漸擴大，所需的閘極陣列驅動電路也相應提升。然而，因應顯示面板窄邊框的設計，能提供設置閘極陣列驅動電路的空間反而逐漸縮減。為縮減周邊區域的寬度，閘極陣列驅動電路需進一步簡化以達到上述要求。 Existing display panel drive circuits will replace gate control chips with gate array drive circuits (GOA) to achieve cost savings. However, as the size of display panels is gradually expanding, the required gate array drive circuits have also increased accordingly . However, due to the design of the narrow frame of the display panel, the space provided for the arrangement of the gate array driving circuit is gradually reduced. In order to reduce the width of the peripheral area, the gate array driving circuit needs to be further simplified to meet the above requirements.
在各種電路簡化的設計中，通常會減少當中電晶體的數量來達到設置區域的縮減，但簡化後的電路仍須滿足元件電性，以免影響到顯示面板的顯示品質。在簡化的閘極陣列驅動電路當中，對於操作節點的電壓控制，包含上拉電路的控制及下拉電路的維持，都有一定的要求，若是無法達到上述特性，這樣的簡化電路將無法達到要求的顯示效果。 In the design of various circuit simplifications, the number of intermediate transistors is usually reduced to achieve the reduction of the setting area, but the simplified circuit must still meet the electrical properties of the components, so as not to affect the display quality of the display panel. In the simplified gate array drive circuit, there are certain requirements for the voltage control of the operating node, including the control of the pull-up circuit and the maintenance of the pull-down circuit. If the above characteristics cannot be achieved, such a simplified circuit will not be able to meet the requirements. display effect.
綜觀前所述，習知的閘極陣列驅動電路的設計上仍然具有相當之缺陷，因此，本發明藉由設計一種閘極陣列驅動電路，針對現有技術之缺失加以改善，以解決現有技術的問題，進而增進產業上之實施利用。 In summary, the design of the conventional gate array drive circuit still has considerable defects. Therefore, the present invention addresses the defects of the prior art by designing a gate array drive circuit to solve the problems of the prior art. , And further enhance the implementation and utilization in industry.
有鑑於上述習知技術之問題，本發明之目的在於提供一種閘極陣列驅動電路，其藉由穩壓電晶體的設置，解決現有簡化電路當中穩壓節點隨時間漏電而造成電壓準位偏移的問題。 In view of the above-mentioned problems of the prior art, the purpose of the present invention is to provide a gate array driving circuit, which solves the voltage level deviation caused by the leakage of the voltage stabilizing node over time in the existing simplified circuit through the arrangement of the stabilizing transistor. The problem.
根據上述目的，本發明之實施例提出一種閘極陣列驅動電路，其包含上拉電路、上拉控制電路、下拉電路以及下拉控制電路。其中，上拉電路耦接於操作節點及時脈訊號源，上拉電路依據時脈訊號源之時脈訊號與操作節點的電壓，輸出閘極驅動訊號。上拉控制電路耦接於高電壓源及操作節點，上拉控制電路接收第一驅動訊號以上拉操作節點的電壓。下拉電路耦接於低電壓源及上拉電路。下拉控制電路耦接於上拉控制電路、下拉電路及低電壓源，下拉控制電路包含穩壓電晶體及第一電容，穩壓電晶體的第一端耦接穩壓節點，穩壓電晶體的第二端耦接低電壓源，穩壓電晶體的控制端耦接反向時脈訊號源，第一電容的一端耦接穩壓節點，另一端耦接時脈訊號源，穩壓電晶體接收反向時脈訊號，開啟穩壓電晶體將穩壓節點補償至預設低準位。 According to the above objective, an embodiment of the present invention provides a gate array driving circuit, which includes a pull-up circuit, a pull-up control circuit, a pull-down circuit, and a pull-down control circuit. Wherein, the pull-up circuit is coupled to the clock signal source of the operating node, and the pull-up circuit outputs the gate driving signal according to the clock signal of the clock signal source and the voltage of the operating node. The pull-up control circuit is coupled to the high voltage source and the operation node, and the pull-up control circuit receives the first driving signal to pull up the voltage of the operation node. The pull-down circuit is coupled to the low voltage source and the pull-up circuit. The pull-down control circuit is coupled to the pull-up control circuit, the pull-down circuit, and the low-voltage source. The pull-down control circuit includes a voltage stabilizing transistor and a first capacitor. The first end of the voltage stabilizing transistor is coupled to the voltage stabilizing node. The second end is coupled to the low-voltage source, the control end of the stabilized transistor is coupled to the reverse clock signal source, one end of the first capacitor is coupled to the stabilized node, the other end is coupled to the clock signal source, and the stabilized transistor receives Reverse clock signal, turn on the voltage regulator transistor to compensate the voltage regulator node to the preset low level.
在本發明的實施例中，下拉控制電路可包含第一電晶體、第二電晶體以及第三電晶體。其中，第一電晶體的第一端耦接上拉控制電路，第一電晶體的第二端耦接低電壓源，第一電晶體的控制端接收第二驅動訊號。第二電晶體的第一端耦接第一電容的一端，第二電晶體的第二端耦接低電壓源，第二 電晶體的控制端耦接上拉控制電路。第三電晶體的第一端耦接操作節點，第三電晶體的第二端耦接低電壓源，第三電晶體的控制端耦接穩壓節點。 In an embodiment of the present invention, the pull-down control circuit may include a first transistor, a second transistor, and a third transistor. Wherein, the first end of the first transistor is coupled to the pull-up control circuit, the second end of the first transistor is coupled to the low voltage source, and the control end of the first transistor receives the second driving signal. The first end of the second transistor is coupled to one end of the first capacitor, the second end of the second transistor is coupled to the low voltage source, and the second The control terminal of the transistor is coupled to the pull-up control circuit. The first end of the third transistor is coupled to the operating node, the second end of the third transistor is coupled to the low voltage source, and the control end of the third transistor is coupled to the voltage stabilizing node.
在本發明的實施例中，上拉控制電路可包含第四電晶體，第四電晶體的第一端耦接高電壓源，第四電晶體的第二端耦接操作節點，第四電晶體的控制端接收第一驅動訊號。 In an embodiment of the present invention, the pull-up control circuit may include a fourth transistor, the first end of the fourth transistor is coupled to the high voltage source, the second end of the fourth transistor is coupled to the operating node, and the fourth transistor is The control terminal receives the first driving signal.
在本發明的實施例中，下拉電路可包含第五電晶體以及第六電晶體。其中，第五電晶體的第一端耦接上拉電路，第五電晶體的第二端耦接低電壓源，第五電晶體的控制端耦接反向時脈訊號源。第六電晶體的第一端耦接上拉電路，第六電晶體的第二端耦接低電壓源，第六電晶體的控制端耦接穩壓節點。 In the embodiment of the present invention, the pull-down circuit may include a fifth transistor and a sixth transistor. Wherein, the first end of the fifth transistor is coupled to the pull-up circuit, the second end of the fifth transistor is coupled to the low voltage source, and the control end of the fifth transistor is coupled to the reverse clock signal source. The first end of the sixth transistor is coupled to the pull-up circuit, the second end of the sixth transistor is coupled to the low voltage source, and the control end of the sixth transistor is coupled to the voltage stabilizing node.
在本發明的實施例中，上拉電路可包含第七電晶體以及第二電容。其中，第七電晶體的第一端耦接時脈訊號源，第七電晶體的第二端耦接輸出端，第七電晶體的控制端耦接操作節點。第二電容的一端耦接第七電晶體的控制端，另一端耦接第七電晶體的第二端。 In an embodiment of the present invention, the pull-up circuit may include a seventh transistor and a second capacitor. Wherein, the first terminal of the seventh transistor is coupled to the clock signal source, the second terminal of the seventh transistor is coupled to the output terminal, and the control terminal of the seventh transistor is coupled to the operating node. One end of the second capacitor is coupled to the control end of the seventh transistor, and the other end is coupled to the second end of the seventh transistor.
在本發明的實施例中，上拉電路可包含第八電晶體，第八電晶體的第一端耦接時脈訊號源，第八電晶體的第二端耦接下拉電路，第八電晶體的控制端耦接操作節點。下拉電路可包含第九電晶體，第九電晶體的第一端耦接上拉電路，第九電晶體的第二端耦接低電壓源，第九電晶體的控制端耦接穩壓節點。 In an embodiment of the present invention, the pull-up circuit may include an eighth transistor, the first end of the eighth transistor is coupled to the clock signal source, the second end of the eighth transistor is coupled to the pull-down circuit, and the eighth transistor The control terminal is coupled to the operating node. The pull-down circuit may include a ninth transistor, the first end of the ninth transistor is coupled to the pull-up circuit, the second end of the ninth transistor is coupled to the low voltage source, and the control end of the ninth transistor is coupled to the voltage stabilizing node.
在本發明的實施例中，低電壓源可包含第一低電壓源及第二低電壓源，下拉控制電路耦接第一低電壓源，下拉電路耦接第二低電壓源。 In an embodiment of the present invention, the low-voltage source may include a first low-voltage source and a second low-voltage source, the pull-down control circuit is coupled to the first low-voltage source, and the pull-down circuit is coupled to the second low-voltage source.
承上所述，依本發明實施例所揭露的閘極陣列驅動電路，可在設置穩壓電晶體後，藉由反向時脈訊號開啟來補償穩壓節點的電壓準位，使得原本因為漏電而使得電壓準位偏移的問題能拉回至預設的低準位，進而使得操作節點在耦合電壓後不會產生過大的紋波，即避免多個脈波產生錯誤的閘極驅動訊號。 In summary, the gate array drive circuit disclosed in the embodiment of the present invention can compensate the voltage level of the voltage stabilizing node by turning on the reverse clock signal after the voltage stabilizing transistor is set, which causes the original leakage current The problem of voltage level deviation can be pulled back to the preset low level, so that the operating node will not generate excessive ripple after the voltage is coupled, that is, avoid multiple pulses from generating erroneous gate driving signals.
1,2,3,4:閘極陣列驅動電路 1,2,3,4: Gate array drive circuit
11,21,31,41:上拉電路 11, 21, 31, 41: pull-up circuit
12,22,32,42:上拉控制電路 12, 22, 32, 42: pull-up control circuit
13,23,33,43:下拉電路 13,23,33,43: pull-down circuit
14,24,34,44:下拉控制電路 14,24,34,44: pull-down control circuit
C1:第一電容 C1: The first capacitor
C2:第二電容 C2: second capacitor
CK:時脈訊號源 CK: Clock signal source
Gn:輸出端 Gn: output
M1~M9:第一電晶體~第九電晶體 M1~M9: The first transistor ~ the ninth transistor
MS:穩壓電晶體 MS: Regulated Transistor
NS:穩壓節點 NS: Voltage stabilizing node
Qn:操作節點 Qn: Operation node
S(n-4):第一驅動訊號 S(n-4): the first drive signal
S(n+4):第二驅動訊號 S(n+4): second drive signal
S(n):同級驅動訊號 S(n): same level drive signal
VGHD:高電壓源 VGHD: High voltage source
VSS:低電壓源 VSS: Low voltage source
VSSQ:第一低電壓源 VSSQ: the first low voltage source
VSSG:第二低電壓源 VSSG: second low voltage source
XCK:反向時脈訊號源 XCK: Reverse clock signal source
為使本發明之技術特徵、內容與優點及其所能達成之功效更為顯而易見，茲將本發明配合附圖，並以實施例之表達形式詳細說明如下： 第1圖為本發明實施例之閘極陣列驅動電路之示意圖。 In order to make the technical features, content and advantages of the present invention and its achievable effects more obvious, the present invention is described in detail in the form of embodiments with the accompanying drawings as follows: Figure 1 is a schematic diagram of a gate array driving circuit according to an embodiment of the present invention.
第2圖為本發明另一實施例之閘極陣列驅動電路之示意圖。 FIG. 2 is a schematic diagram of a gate array driving circuit according to another embodiment of the present invention.
第3圖為本發明又一實施例之閘極陣列驅動電路之示意圖。 FIG. 3 is a schematic diagram of a gate array driving circuit according to another embodiment of the present invention.
第4圖為本發明再一實施例之閘極陣列驅動電路之示意圖。 FIG. 4 is a schematic diagram of a gate array driving circuit according to still another embodiment of the present invention.
第5圖為本發明實施例之閘極陣列驅動電路之測試圖。 FIG. 5 is a test diagram of the gate array driving circuit according to the embodiment of the present invention.
為利瞭解本發明之技術特徵、內容與優點及其所能達成之功效，茲將本發明配合附圖，並以實施例之表達形式詳細說明如下，而其中所使用之圖式，其主旨僅為示意及輔助說明書之用，未必為本發明實施後之真實比例與精準配置，故不應就所附之圖式的比例與配置關係解讀、侷限本發明於實際實施上的權利範圍，合先敘明。 In order to understand the technical features, content and advantages of the present invention as well as the effects that can be achieved, the present invention is described in detail with the accompanying drawings and in the form of embodiment expressions as follows, and the figures used therein are only For the purpose of illustration and supplementary description, it is not necessarily the true scale and precise configuration after the implementation of the invention. Therefore, the scale and configuration relationship of the attached drawings should not be interpreted, and the scope of rights of the invention in actual implementation should not be interpreted. Narrate.
在附圖中，為了清楚起見，放大了層、膜、面板、區域、導光件等的厚度或寬度。在整個說明書中，相同的附圖標記表示相同的元件。應當理解，當諸如層、膜、區域或基板的元件被稱為在另一元件「上」或「連接到」另一元件時，其可以直接在另一元件上或與另一元件連接，或者中間元件可以也存在。相反地，當元件被稱為「直接在另一元件上」或「直接連接到」另一元件時，不存在中間元件。如本文所使用的「連接」，其可以指物理及/或電性的連接。再者，「電性連接」或「耦合」係可為二元件間存在其它元件。此外，應當理解，儘管術語「第一」、「第二」、「第三」在本文中可以用於描述各種元件、部件、區域、層及/或部分，其係用於將一個元件、部件、區域、層及/或部分與另一個元件、部件、區域、層及/或部分區分開。因此，僅用於描述目的，而不能將其理解為指示或暗示相對重要性或者其順序關係。 In the drawings, the thickness or width of layers, films, panels, regions, light guides, etc., are exaggerated for clarity. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements can also be present. Conversely, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connection" can refer to a physical and/or electrical connection. Furthermore, "electrical connection" or "coupling" can mean that there are other elements between the two elements. In addition, it should be understood that although the terms "first", "second", and "third" may be used herein to describe various elements, components, regions, layers and/or parts, they are used to refer to an element, component , Region, layer and/or part are distinguished from another element, component, region, layer and/or part. Therefore, it is only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or its sequence relationship.
除非另有定義，本文所使用的所有術語(包括技術和科學術語)具有與本發明所屬技術領域的通常知識者通常理解的含義。將進一步理解的是，諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的含義，並且將不被解釋為理想化的或過度正式的意義，除非本文中明確地如此定義。 Unless otherwise defined, all terms (including technical and scientific terms) used herein have meanings commonly understood by ordinary knowledge in the technical field to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.
請參閱第1圖，其為本發明實施例之閘極陣列驅動電路之示意圖。如圖所示，閘極陣列驅動電路1包含上拉電路11、上拉控制電路12、下拉電路13以及下拉控制電路14。上拉電路11耦接於操作節點Qn及時脈訊號源CK，上拉電路11依據時脈訊號源CK之時脈訊號與操作節點Qn的電壓，於輸出端Gn輸出閘極驅動訊號。顯示面板的各個像素可分別耦接閘極陣列驅動電路1的輸出端Gn，依據時脈訊號的時序，依序提供閘極驅動訊號來驅動各個像素陣列當中的
像素驅動電路。在本實施例當中，決定操作節點Qn的電壓的是耦接上拉電路11的上拉控制電路12，上拉控制電路12耦接於高電壓源VGHD及操作節點Qn，上拉控制電路12接收第一驅動訊號S(n-4)以上拉操作節點Qn的電壓。
Please refer to FIG. 1, which is a schematic diagram of a gate array driving circuit according to an embodiment of the present invention. As shown in the figure, the gate
另外，在非閘極陣列驅動電路1開啟的時間，若操作節點Qn因為漏電流的關係而使上拉電路11錯誤啟動，造成閘極驅動訊號的錯誤輸出，將會影響顯示面板中像素的顯示結果。因此，設置下拉電路13及下拉控制電路14來維持正確的驅動訊號輸出，下拉電路13耦接於低電壓源VSS，且耦接於上拉電路11，下拉電路13能下拉輸出端Gn的電壓。下拉控制電路14耦接於上拉控制電路12、下拉電路13及低電壓源VSS，下拉控制電路14能下拉操作節點Qn及輸出端Gn的電壓。下拉控制電路14包含穩壓電晶體MS及第一電容C1，穩壓電晶體MS的第一端耦接至穩壓節點NS，第二端耦接低電壓源VSS，控制端耦接反向時脈訊號源XCK，第一電容C1的一端耦接穩壓節點NS，另一端耦接時脈訊號源CK。
穩壓節點NS耦接於操作節點Qn，當接收反向時脈訊號源XCK的反向時脈訊號而開啟穩壓電晶體MS時，可將穩壓節點NS補償至預設低準位，使得下拉電路13在維持操作節點Qn的電壓時，不會因為漏電準位逐漸偏低而使得下拉能力變差。
In addition, during the time when the non-gate
在本實施例中，下拉控制電路14包含第一電晶體M1、第二電晶體M2以及第三電晶體M3。其中，第一電晶體M1的第一端耦接上拉控制電路12，第一電晶體M1的第二端耦接低電壓源VSS，第一電晶體M1的控制端接收第二驅動訊號S(n+4)，第一電晶體M1響應第二驅動訊號S(n+4)來下拉操作節點Qn的電壓。第二驅動訊號S(n+4)與第一驅動訊號S(n-4)分別為後四級與前四級的控制訊號。第二電晶體M2的第一端耦接第一電容C1的一端，第二電晶體M2的第二端耦接低電壓源VSS，第二電晶體M2的控制端耦接上拉控制電路12。第三電晶體
M3的第一端耦接操作節點Qn，第三電晶體M3的第二端耦接低電壓源VSS，第三電晶體M3的控制端耦接穩壓節點NS，第三電晶體M3響應穩壓節點NS的電壓來下拉操作節點Qn的電壓。其中，穩壓節點NS的電壓由第二電晶體M2、第一電容C1及穩壓電晶體MS來控制。穩壓電晶體MS的設置藉由反向時脈訊號將第三電晶體M3的控制端補償回復至正確的低準位，在下個時序耦合時能維持正確的電壓，讓第三電晶體M3能穩定地將操作節點Qn的電壓下拉，避免操作節點Qn產生紋波(ripple)現象而發出錯誤的閘極驅動訊號。
In this embodiment, the pull-
與下拉控制電路14耦接的上拉控制電路12，則包含第四電晶體M4，第四電晶體M4的第一端耦接高電壓源VGHD，第四電晶體M4的第二端耦接操作節點Qn，第四電晶體M4的控制端接收第一驅動訊號S(n-4)。與下拉控制電路14耦接的下拉電路13，則包含第五電晶體M5以及第六電晶體M6。其中，第五電晶體M5的第一端耦接上拉電路11，第五電晶體M5的第二端耦接低電壓源VSS，第五電晶體M5的控制端耦接反向時脈訊號源XCK。第六電晶體M6的第一端耦接上拉電路11，第六電晶體M6的第二端耦接低電壓源VSS，第六電晶體M6的控制端耦接穩壓節點NS。與下拉電路13耦接的上拉電路11，則包含第七電晶體M7以及第二電容C2。其中，第七電晶體M7的第一端耦接時脈訊號源CK，第七電晶體M7的第二端耦接輸出端Gn，第七電晶體M7的控制端耦接操作節點Qn。第二電容C2的一端耦接第七電晶體M7的控制端，另一端耦接第七電晶體M7的第二端。
The pull-up
請參閱第2圖，其為本發明另一實施例之閘極陣列驅動電路之示意圖。如圖所示，閘極陣列驅動電路2包含上拉電路21、上拉控制電路22、下拉電路23以及下拉控制電路24。上拉電路21耦接於操作節點Qn及時脈訊號源CK，
上拉電路21依據時脈訊號源CK之時脈訊號與操作節點Qn的電壓，於輸出端Gn輸出閘極驅動訊號。上拉控制電路22耦接於高電壓源VGHD及操作節點Qn，上拉控制電路12接收第一驅動訊號S(n-4)以上拉操作節點Qn的電壓。下拉電路23耦接於上拉電路21，下拉電路23能下拉輸出端Gn的電壓。下拉控制電路24耦接於上拉控制電路22及下拉電路23，下拉控制電路24能下拉操作節點Qn及輸出端Gn的電壓，下拉控制電路24還包含穩壓電晶體MS及第一電容C1。
Please refer to FIG. 2, which is a schematic diagram of a gate array driving circuit according to another embodiment of the present invention. As shown in the figure, the gate
除此之外，下拉控制電路14包含第一電晶體M1、第二電晶體M2以及第三電晶體M3，第一電晶體M1響應第二驅動訊號S(n+4)來下拉操作節點Qn的電壓，第三電晶體M3響應穩壓節點NS的電壓來下拉操作節點Qn的電壓。上拉控制電路12包含第四電晶體M4，下拉電路13包含第五電晶體M5以及第六電晶體M6，上拉電路11包含第七電晶體M7以及第二電容C2。本實施例中，閘極陣列驅動電路2與前一實施例同樣為八個電晶體兩個電容(8T2C)之驅動電路，與前述實施例相同或相似的元件以相同符號表示，其技術內容不再重複描述。
In addition, the pull-
與前述實施例不同之處，本實施例中下拉控制電路14耦接於第一低電壓源VSSQ，下拉電路13耦接第二低電壓源VSSG。更詳細地，穩壓電晶體MS的第二端、第一電晶體M1的第二端、第二電晶體M2的第二端及第三電晶體M3的第二端耦接第一低電壓源VSSQ，而第五電晶體M5的第二端及第六電晶體M6的第二端耦接第二低電壓源VSSG。通過不同低電壓源的設置，可是下拉控制電路14與下拉電路13的操作更為穩定。
Different from the previous embodiment, in this embodiment, the pull-
請參閱第3圖，其為本發明又一實施例之閘極陣列驅動電路之示意圖。如圖所示，閘極陣列驅動電路3包含上拉電路31、上拉控制電路32、下拉電路33以及下拉控制電路34。上拉電路31耦接於操作節點Qn及時脈訊號源CK，
上拉電路31依據時脈訊號源CK之時脈訊號與操作節點Qn的電壓，於輸出端Gn輸出閘極驅動訊號。上拉控制電路32耦接於高電壓源VGHD及操作節點Qn，上拉控制電路32接收第一驅動訊號S(n-4)以上拉操作節點Qn的電壓。下拉電路33耦接於上拉電路31，下拉電路33能下拉輸出端Gn的電壓。下拉控制電路34耦接於上拉控制電路32及下拉電路33，下拉控制電路34能下拉操作節點Qn及輸出端Gn的電壓，下拉控制電路34還包含穩壓電晶體MS及第一電容C1。穩壓電晶體MS的第一端耦接至穩壓節點NS，第二端耦接低電壓源VSS，控制端耦接反向時脈訊號源XCK，第一電容C1的一端耦接穩壓節點NS，另一端耦接時脈訊號源CK。穩壓節點NS耦接於操作節點Qn，當接收反向時脈訊號源XCK的反向時脈訊號而開啟穩壓電晶體MS時，可將穩壓節點NS補償至預設低準位，使得下拉電路33在維持操作節點Qn的電壓時，不會因為漏電準位逐漸偏低而使得下拉能力變差。
Please refer to FIG. 3, which is a schematic diagram of a gate array driving circuit according to another embodiment of the present invention. As shown in the figure, the gate
在本實施例中，下拉控制電路34包含第一電晶體M1、第二電晶體M2以及第三電晶體M3。其中，第一電晶體M1的第一端耦接上拉控制電路32，第一電晶體M1的第二端耦接低電壓源VSS，第一電晶體M1的控制端接收第二驅動訊號S(n+4)，第一電晶體M1響應第二驅動訊號S(n+4)來下拉操作節點Qn的電壓。第二驅動訊號S(n+4)與第一驅動訊號S(n-4)分別為後四級與前四級的控制訊號。第二電晶體M2的第一端耦接第一電容C1的一端，第二電晶體M2的第二端耦接低電壓源VSS，第二電晶體M2的控制端耦接上拉控制電路32。第三電晶體M3的第一端耦接操作節點Qn，第三電晶體M3的第二端耦接低電壓源VSS，第三電晶體M3的控制端耦接穩壓節點NS，第三電晶體M3響應穩壓節點NS的電壓來下拉操作節點Qn的電壓。其中，穩壓節點NS的電壓由第二電晶體M2、第一電容
C1及穩壓電晶體MS來控制。穩壓電晶體MS的設置藉由反向時脈訊號將第三電晶體M3的控制端補償回復至正確的低準位，在下個時序耦合時能維持正確的電壓，讓第三電晶體M3能穩定地將操作節點Qn的電壓下拉，避免操作節點Qn產生紋波(ripple)現象而發出錯誤的閘極驅動訊號。
In this embodiment, the pull-
與下拉控制電路34耦接的上拉控制電路32，則包含第四電晶體M4，第四電晶體M4的第一端耦接高電壓源VGHD，第四電晶體M4的第二端耦接操作節點Qn，第四電晶體M4的控制端接收第一驅動訊號S(n-4)。與下拉控制電路34耦接的下拉電路33，則包含第五電晶體M5以及第六電晶體M6。其中，第五電晶體M5的第一端耦接上拉電路31，第五電晶體M5的第二端耦接低電壓源VSS，第五電晶體M5的控制端耦接反向時脈訊號源XCK。第六電晶體M6的第一端耦接上拉電路31，第六電晶體M6的第二端耦接低電壓源VSS，第六電晶體M6的控制端耦接穩壓節點NS。與下拉電路33耦接的上拉電路31，則包含第七電晶體M7以及第二電容C2。其中，第七電晶體M7的第一端耦接時脈訊號源CK，第七電晶體M7的第二端耦接輸出端Gn，第七電晶體M7的控制端耦接操作節點Qn。第二電容C2的一端耦接第七電晶體M7的控制端，另一端耦接第七電晶體M7的第二端。
The pull-up
與第1圖之實施例不同之處，本實施例的閘極陣列驅動電路3當中，上拉電路31包含第八電晶體M8，第八電晶體M8的第一端耦接時脈訊號源CK，第八電晶體M8的第二端耦接下拉電路33，第八電晶體M8的控制端耦接操作節點Qn。其中，第八電晶體M8的第二端耦接第五電晶體M5的第一端及第六電晶體M6的第一端，且第八電晶體M8的第二端及第五電晶體M5的第一端還耦接同級驅動訊號S(n)。除此之外，下拉電路33包含第九電晶體M9，第九電晶體
M9的第一端耦接上拉電路，第九電晶體M9的第二端耦接低電壓源VSS，第九電晶體M9的控制端耦接穩壓節點NS。其中，第九電晶體M9的第一端耦接第七電晶體M7的第二端及第二電容C2的第二端。
Different from the embodiment in FIG. 1, in the gate
請參閱第4圖，其為本發明再一實施例之閘極陣列驅動電路之示意圖。如圖所示，閘極陣列驅動電路4包含上拉電路41、上拉控制電路42、下拉電路43以及下拉控制電路44。上拉電路41耦接於操作節點Qn及時脈訊號源CK，上拉電路41依據時脈訊號源CK之時脈訊號與操作節點Qn的電壓，於輸出端Gn輸出閘極驅動訊號。上拉控制電路42耦接於高電壓源VGHD及操作節點Qn，上拉控制電路42接收第一驅動訊號S(n-4)以上拉操作節點Qn的電壓。下拉電路43耦接於上拉電路41，下拉電路43能下拉輸出端Gn的電壓。下拉控制電路44耦接於上拉控制電路42及下拉電路43，下拉控制電路44能下拉操作節點Qn及輸出端Gn的電壓，下拉控制電路44還包含穩壓電晶體MS及第一電容C1。
Please refer to FIG. 4, which is a schematic diagram of a gate array driving circuit according to still another embodiment of the present invention. As shown in the figure, the gate
除此之外，下拉控制電路44包含第一電晶體M1、第二電晶體M2以及第三電晶體M3，第一電晶體M1響應第二驅動訊號S(n+4)來下拉操作節點Qn的電壓，第三電晶體M3響應穩壓節點NS的電壓來下拉操作節點Qn的電壓。上拉控制電路42包含第四電晶體M4，下拉電路43包含第五電晶體M5、第六電晶體M6以及第九電晶體M9，上拉電路41包含第七電晶體M7、第八電晶體M8以及第二電容C2。本實施例中，閘極陣列驅動電路4與第3圖的實施例同樣為十個電晶體兩個電容(10T2C)之驅動電路，與前述實施例相同或相似的元件以相同符號表示，其技術內容不再重複描述。
In addition, the pull-down control circuit 44 includes a first transistor M1, a second transistor M2, and a third transistor M3. The first transistor M1 responds to the second drive signal S(n+4) to pull down the operating node Qn The third transistor M3 responds to the voltage of the voltage stabilizing node NS to pull down the voltage of the operating node Qn. The pull-up
與前述實施例不同之處，本實施例中下拉控制電路44耦接於第一低電壓源VSSQ，下拉電路43耦接第二低電壓源VSSG。更詳細地，穩壓電晶體
MS的第二端、第一電晶體M1的第二端、第二電晶體M2的第二端及第三電晶體M3的第二端耦接第一低電壓源VSSQ，而第五電晶體M5的第二端、第六電晶體M6的第二端及第九電晶體M9的第二端耦接第二低電壓源VSSG。通過不同低電壓源的設置，可是下拉控制電路44與下拉電路43的操作更為穩定。
Different from the previous embodiment, in this embodiment, the pull-down control circuit 44 is coupled to the first low voltage source VSSQ, and the pull-
請參閱第5圖，其為本發明實施例之閘極陣列驅動電路之測試圖。在本實施例中，是以第4圖之閘極陣列驅動電路4為例進行模擬測試，但本揭露之閘極陣列驅動電路不以此為限，以不同電晶體及電容配置所形成的閘極陣列驅動電路也具有相同或類似的測試結果。如圖所示，以設置穩壓電晶體的驅動電路與未設置穩壓電晶體的驅動電路進行比較，當完成本身的工作週期後，未設置穩壓電晶體的驅動電路，在穩壓節點NS的部分，會隨時間漏電而偏移使得準位降到9.3V，操作節點Qn的部分，這樣的偏移使得操作節點Qn在耦合穩壓節點NS的電壓後，可能產生-1.48V的紋波(ripple)，由於下拉的準位不足，使得過高的紋波可能造成上拉電路錯誤啟動而送出錯誤的閘極驅動訊號。
Please refer to FIG. 5, which is a test diagram of the gate array driving circuit according to the embodiment of the present invention. In this embodiment, the gate
相對地，依據本揭露設置的穩壓電晶體，在接受到反向時脈訊號的高頻訊號啟動後，會將穩壓節點NS的準位偏移拉回如圖所示的12V，使得穩壓節點NS具備穩定的下拉能力，即操作節點Qn在耦合穩壓節點NS的電壓後，產生較低的紋波，如圖所示的-2.35V，避免輸出多個脈波而產生錯充的問題。 In contrast, the stabilized voltage transistor set according to the present disclosure, after receiving the high-frequency signal of the reverse clock signal, will pull the level offset of the stabilized node NS back to 12V as shown in the figure, so as to stabilize The voltage node NS has a stable pull-down capability, that is, the operating node Qn generates a lower ripple after coupling the voltage of the voltage stabilization node NS, as shown in the figure-2.35V, to avoid outputting multiple pulses and causing incorrect charging problem.
以上所述僅為舉例性，而非為限制性者。任何未脫離本發明之精神與範疇，而對其進行之等效修改或變更，均應包含於後附之申請專利範圍中。 The above descriptions are merely illustrative and not restrictive. Any equivalent modifications or alterations that do not depart from the spirit and scope of the present invention should be included in the scope of the appended patent application.
1:閘極陣列驅動電路 1: Gate array drive circuit
11:上拉電路 11: pull-up circuit
12:上拉控制電路 12: Pull-up control circuit
13:下拉電路 13: pull-down circuit
14:下拉控制電路 14: pull-down control circuit
C1:第一電容 C1: The first capacitor
C2:第二電容 C2: second capacitor
CK:時脈訊號源 CK: Clock signal source
Gn:輸出端 Gn: output
M1~M7:第一電晶體~第七電晶體 M1~M7: The first transistor ~ the seventh transistor
MS:穩壓電晶體 MS: Regulated Transistor
NS:穩壓節點 NS: Voltage stabilizing node
Qn:操作節點 Qn: Operation node
S(n-4):第一驅動訊號 S(n-4): the first drive signal
S(n+4):第二驅動訊號 S(n+4): second drive signal
VGHD:高電壓源 VGHD: High voltage source
VSS:低電壓源 VSS: Low voltage source
XCK:反向時脈訊號源 XCK: Reverse clock signal source
Claims (7)
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| US20190197973A1 (en) * | 2017-12-26 | 2019-06-27 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Gate driver and driving circuit |
| US10593416B2 (en) * | 2018-01-02 | 2020-03-17 | Boe Technology Group Co., Ltd. | Shift register, driving method, gate driving circuit and display device |
| US20200184872A1 (en) * | 2018-12-07 | 2020-06-11 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Shift register circuit, gate driving circuit and method for driving the same, and display apparatus |
-
2020
- 2020-06-17 TW TW109120475A patent/TWI738386B/en active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10002675B2 (en) * | 2016-02-03 | 2018-06-19 | Boe Technology Group Co., Ltd. | Shift register unit, gate driving circuit and driving method, and display apparatus |
| US20190197973A1 (en) * | 2017-12-26 | 2019-06-27 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Gate driver and driving circuit |
| US10593416B2 (en) * | 2018-01-02 | 2020-03-17 | Boe Technology Group Co., Ltd. | Shift register, driving method, gate driving circuit and display device |
| US20200184872A1 (en) * | 2018-12-07 | 2020-06-11 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Shift register circuit, gate driving circuit and method for driving the same, and display apparatus |
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| Publication number | Publication date |
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| TW202201397A (en) | 2022-01-01 |
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