TWI737377B

TWI737377B - Semiconductor structure and method of fabricating the same

Info

Publication number: TWI737377B
Application number: TW109122239A
Authority: TW
Inventors: 浦士杰; 陳輝煌; 戴執中
Original assignee: 力晶積成電子製造股份有限公司
Priority date: 2020-07-01
Filing date: 2020-07-01
Publication date: 2021-08-21
Also published as: TW202203323A; CN113889479A

Abstract

A method of fabricating a semiconductor structure, including the steps of forming a floating gate and a logic gate on a substrate, forming a first source and a first drain respectively at two sides of the floating gate, forming a coupling dielectric and a polysilicon layer sequentially on the substrate, the floating gate and the logic gate after the first source and the first drain are formed, patterning the polysilicon layer to form a control gate covering the floating gate, and forming light-doped drains, a second source and a second drain at two sides of the logic gate after the control gate is formed.

Description

半導體結構及其製作方法 Semiconductor structure and manufacturing method thereof

本發明與一種半導體結構的製作方法有關，更具體言之，其係關於一種整合非揮發性記憶體單元區域以及邏輯區域的半導體製作方法及其衍生出之相關結構，其可以減少非揮發性記憶體單元區域的製程對邏輯區域在熱預算(thermal budget)方面的影響。 The present invention relates to a manufacturing method of a semiconductor structure, more specifically, it relates to a semiconductor manufacturing method that integrates non-volatile memory cell regions and logic regions and related structures derived therefrom, which can reduce non-volatile memory The influence of the manufacturing process of the bulk cell area on the thermal budget of the logic area.

許多半導體裝置中會含有或是將非揮發性記憶體(non-volatile memory,NVM)單元與其他類型的電晶體嵌入在同一積體電路上。這些不同類型的電晶體可能會具有不同的製程，需要加以整合。例如，如果要將NVM製程與金屬氧化物半導體(MOS)製程整合，此MOS製程可以被修改成包含製作NVM記憶體單元所需製程步驟。 Many semiconductor devices contain or embed non-volatile memory (NVM) units and other types of transistors on the same integrated circuit. These different types of transistors may have different manufacturing processes and need to be integrated. For example, if the NVM process is to be integrated with the metal oxide semiconductor (MOS) process, the MOS process can be modified to include the process steps required to fabricate the NVM memory cell.

NVM一般會內嵌在具有MOS邏輯電路系統的系統晶片(SoC)中。NVM可包含由多晶矽構成的浮動閘，或是使用由奈米晶體、氮化矽、氮氧化矽構成的電荷儲存層，其可與類比或邏輯電路系統中使用的多種類型的MOS電晶體整合在一起，諸如邏輯開關電晶體、高壓開關電晶體、驅動器、或是靜態隨機存取記憶(SRAM)單元等。 NVM is generally embedded in a system-on-chip (SoC) with a MOS logic circuit system. NVM can include floating gates made of polysilicon, or use charge storage layers made of nanocrystals, silicon nitride, and silicon oxynitride. It can be integrated with multiple types of MOS transistors used in analog or logic circuit systems. , Such as logic switching transistors, high-voltage switching transistors, drivers, or static random access memory (SRAM) units.

因為NVM單元與MOS邏輯電晶體的需求不同，其整合並不容易。NVM單元係用來儲存電荷，而邏輯電晶體一般是為了高速運作，NVM單元中需要電荷儲存層以及不同功能閘的特點使得其要與邏輯電晶體整合變得困難，特別是在需要多種不同類型的邏輯電晶體的情況下。 Because the requirements of NVM cells and MOS logic transistors are different, its integration is not easy. NVM cells are used to store charges, and logic transistors are generally used for high-speed operation. NVM cells need The characteristics of the charge storage layer and different functional gates make it difficult to integrate with logic transistors, especially when multiple different types of logic transistors are required.

NVM與MOS電晶體的整合會導入額外的濕蝕刻、退火、氧化等製程，其可能會改變邏輯井的輪廓以及主動區與溝渠區的邊界，使得邏輯元件無法達到其標準流程下應有的電性目標。特別是當現今的半導體製程進入了深次微米或是奈米的通道尺度，其必須要更加小心精確地控制相關製程的熱預算(thermal budget)，才能使得裝置達到預期的效能與可靠度。目前，要製作100nm以下的記憶體節點會有更高的熱預算需求，其可能需要多次的學習週期來調整佈植製程的參數才能大致達到其原有的邏輯電性表現。 The integration of NVM and MOS transistors will introduce additional wet etching, annealing, oxidation and other processes, which may change the outline of the logic well and the boundary between the active area and the trench area, making the logic element unable to meet the electrical requirements of its standard process. Sexual goals. Especially when the current semiconductor manufacturing process has entered the deep sub-micron or nanometer channel scale, it is necessary to more carefully and accurately control the thermal budget of the related process in order to make the device achieve the expected performance and reliability. At present, the production of memory nodes below 100nm will have a higher thermal budget requirement, and it may require multiple learning cycles to adjust the parameters of the deployment process to roughly achieve its original logic and electrical performance.

故此，目前業界仍須積極開發能有效整合NVM與MOS的製程，並同時維持元件原有的效能與可靠度。 Therefore, the industry still needs to actively develop a process that can effectively integrate NVM and MOS while maintaining the original performance and reliability of the device.

有鑑於前述目前NVM與MOS製程整合的現況，本發明特此提出了一種新穎的半導體製程以及其衍生出之相關結構，其可以減少非揮發性記憶體單元區域的製程對邏輯區域在熱預算(thermal budget)方面的影響。 In view of the aforementioned current integration of NVM and MOS processes, the present invention hereby proposes a novel semiconductor process and related structures derived from it, which can reduce the thermal budget of the non-volatile memory cell area to the logic area. budget).

本發明的其一面向為提出一種半導體結構，其結構包含一基底，具有一記憶體單元區域與一邏輯區域、一記憶體單元位於該記憶體單元區域上，該記憶體單元包含一浮動閘位於該基底上、第一源極與第一汲極分別位於該浮動閘兩側、一控制閘覆蓋該浮動閘且與該第一源極以及該第一汲極部分重疊、一耦合介電層位於該浮動閘與該控制閘之間、以及第一間隔壁，位於該控制閘的側壁上，一金屬氧化物半導體場效電晶體位於該邏輯區域上，該金屬氧化物半導體場效電晶體包含一邏輯閘位於該基底上、兩輕摻雜汲極分別位於該邏輯閘兩側、第二源極與第二汲極位於該兩輕摻雜汲極外側、偏移間隔壁分別位於該邏輯閘的兩側、以及第二間隔壁位於該偏移間隔壁的側壁上，其中該記憶體單元的該第一間隔壁與該金屬氧化物半導體場效電晶體的該第二間隔壁的材質相同且在同一製程中形成。 One aspect of the present invention is to provide a semiconductor structure. The structure includes a substrate with a memory cell region and a logic region, a memory cell is located on the memory cell region, and the memory cell includes a floating gate located on On the substrate, the first source and the first drain are respectively located on both sides of the floating gate, a control gate covers the floating gate and partially overlaps the first source and the first drain, and a coupling dielectric layer is located Between the floating gate and the control gate and the first partition wall is located on the sidewall of the control gate, a metal oxide semiconductor field effect transistor is located on the logic area, and the metal oxide semiconductor field effect transistor includes a The logic gate is located on the substrate, the two lightly doped drains are respectively located on both sides of the logic gate, the second source and the second drain are located outside the two lightly doped drains, and the offset spacers are located respectively Both sides of the logic gate and the second partition wall are located on the sidewall of the offset partition wall, wherein the first partition wall of the memory cell and the second partition wall of the metal oxide semiconductor field effect transistor are The material is the same and formed in the same manufacturing process.

本發明的另一面向為提出一種半導體結構的製作方法，其步驟包含在一基底上形成一浮動閘與一邏輯閘、在該浮動閘的兩側分別形成第一源極與第一汲極、在形成該第一源極與該第一汲極後，在該基底、該浮動閘、以及該邏輯閘上依序形成一耦合介電層與一多晶矽層、圖案化該多晶矽層以形成覆蓋該浮動閘的控制閘、以及在形成該控制閘後，在該邏輯閘的兩側形成輕摻雜汲極、第二源極、以及第二汲極。 Another aspect of the present invention is to provide a method for fabricating a semiconductor structure. The steps include forming a floating gate and a logic gate on a substrate, forming a first source and a first drain on both sides of the floating gate, After forming the first source and the first drain, a coupling dielectric layer and a polysilicon layer are sequentially formed on the substrate, the floating gate, and the logic gate, and the polysilicon layer is patterned to cover the The control gate of the floating gate, and after the control gate is formed, a lightly doped drain, a second source, and a second drain are formed on both sides of the logic gate.

本發明的這類目的與其他目的在閱者讀過下文中以多種圖示與繪圖來描述的較佳實施例之細節說明後應可變得更為明瞭顯見。 Such objects and other objects of the present invention should become more apparent after readers have read the detailed description of the preferred embodiments described below with various illustrations and drawings.

10:半導體結構 10: Semiconductor structure

20:記憶體單元 20: Memory unit

30:金屬氧化物半導體場效電晶體 30: Metal Oxide Semiconductor Field Effect Transistor

100:基底 100: base

100a:記憶體單元區域 100a: Memory cell area

100b:邏輯區域 100b: logical area

102:元件隔離層 102: component isolation layer

104:浮動閘 104: Floating Gate

106:邏輯閘 106: Logic Gate

108:閘極氧化層 108: gate oxide layer

110:光阻 110: photoresist

112:耦合介電層 112: coupling dielectric layer

114:多晶矽層 114: polysilicon layer

115:偏移間隔壁 115: Offset partition wall

116:控制閘 116: control gate

118:間隔層 118: Interval layer

120:主間隔壁 120: main partition

122:光阻 122: photoresist

D:汲極 D: Dip pole

LDD:輕摻雜汲極 LDD: Lightly doped drain

P1,P2:離子佈植製程 P1, P2: ion implantation process

S:源極 S: source

S1-S8:步驟 S1-S8: steps

本說明書含有附圖併於文中構成了本說明書之一部分，俾使閱者對本發明實施例有進一步的瞭解。該些圖示係描繪了本發明一些實施例並連同本文描述一起說明了其原理。在該些圖示中：第1-7圖為根據本發明較佳實施例中一半導體製作流程的截面示意圖；以及第8圖為根據本發明較佳實施例中一半導體製作方法的流程圖。 This specification contains drawings and constitutes a part of this specification in the text, so that readers can have a further understanding of the embodiments of the present invention. These figures depict some embodiments of the present invention and together with the description herein, explain the principles. In these figures: Figures 1-7 are schematic cross-sectional views of a semiconductor manufacturing process according to a preferred embodiment of the present invention; and Figure 8 is a flowchart of a semiconductor manufacturing method according to a preferred embodiment of the present invention.

須注意本說明書中的所有圖示皆為圖例性質，為了清楚與方便圖示說明之故，圖示中的各部件在尺寸與比例上可能會被誇大或縮小地呈現，一般而言，圖中相同的參考符號會用來標示修改後或不同實施例中對應或類似的元件特徵。 It should be noted that all the illustrations in this manual are illustrations in nature. For clarity and convenience of illustration, the parts in the illustrations may be exaggerated or reduced in size and proportion. Generally speaking, the figures The same reference symbols will be used to indicate corresponding or similar element features in modified or different embodiments.

現在下文將詳細說明本發明的示例性實施例，其會參照附圖示出所描述之特徵以便閱者理解並實現技術效果。閱者將可理解文中之描述僅透過例示之方式來進行，而非意欲要限制本案。本案的各種實施例和實施例中彼此不衝突的各種特徵可以以各種方式來加以組合或重新設置。在不脫離本發明的精神與範疇的情況下，對本案的修改、等同物或改進對於本領域技術人員來說是可以理解的，並且旨在包含在本案的範圍內。 Now, exemplary embodiments of the present invention will be described in detail below, which will illustrate the described features with reference to the accompanying drawings so that readers can understand and achieve technical effects. Readers will understand that the description in the text is only done by way of example, and is not intended to limit the case. The various embodiments of this case and various features in the embodiments that do not conflict with each other can be combined or re-arranged in various ways. Without departing from the spirit and scope of the present invention, modifications, equivalents or improvements to this case are understandable to those skilled in the art, and are intended to be included in the scope of this case.

閱者應能容易理解，本案中的「在…上」、「在…之上」和「在…上方」的含義應當以廣義的方式被解讀，以使得「在…上」不僅表示「直接在」某物「上」而且還包括在某物「上」且其間有居間特徵或層的含義，並且「在…之上」或「在…上方」不僅表示「在」某物「之上」或「上方」的含義，而且還可以包括其「在」某物「之上」或「上方」且其間沒有居間特徵或層(即，直接在某物上)的含義。 Readers should be able to easily understand that the meanings of "on", "on" and "on" in this case should be interpreted in a broad way, so that "on" not only means "directly on" "Something is "on" but also includes something "on" with the meaning of intervening features or layers in between, and "on" or "above" not only means "on" or "on" something The meaning of "above" can also include the meaning of "above" or "above" something without intervening features or layers (that is, directly on something).

此外，諸如「在…之下」、「在…下方」、「下部」、「在…之上」、「上部」等空間相關術語在本文中為了描述方便可以用於描述一個元件或特徵與另一個或多個元件或特徵的關係，如在附圖中示出的。 In addition, space-related terms such as "below", "below", "lower", "above", "upper" and other space-related terms may be used herein to describe one element or feature and another for convenience of description. The relationship of one or more elements or features is as shown in the drawings.

如本文中使用的，術語「基底」是指向其上增加後續材料的材料。可以對基底自身進行圖案化。增加在基底的頂部上的材料可以被圖案化或可以保持不被圖案化。此外，基底可以包括廣泛的半導體材料，例如矽、鍺、砷化鎵、磷化銦等。或者，基底可以由諸如玻璃、塑膠或藍寶石晶圓的非導電材料製成。 As used herein, the term "substrate" refers to a material on which subsequent materials are added. The substrate itself can be patterned. The material added on the top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

如本文中使用的，術語「層」是指包括具有厚度的區域的材料部分。層可以在下方或上方結構的整體之上延伸，或者可以具有小於下方或上方結構範圍的範圍。此外，層可以是厚度小於連續結構的厚度的均質或非均質連續結構的區域。例如，層可以位於在連續結構的頂表面和底表面之間或在頂表面和底表面處的任何水平面對之間。層可以水準、豎直和/或沿傾斜表面延伸。基底可以是層，其中可以包括一個或多個層，和/或可以在其上、其上方和/或其下方具有一個或多個層。層可以包括多個層。例如，互連層可以包括一個或多個導體和接觸層(其中形成觸點、互連線和/或通孔)和一個或多個介電層。 As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer may extend over the entirety of the lower or upper structure, or may have a range smaller than the range of the lower or upper structure. In addition, the layer can be a homogeneous or heterogeneous continuous junction with a thickness less than the thickness of the continuous structure. Structured area. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any horizontal faces at the top and bottom surfaces. The layers can extend horizontally, vertically, and/or along inclined surfaces. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers on, above, and/or below it. The layer may include multiple layers. For example, the interconnect layer may include one or more conductor and contact layers (where contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

現在下文的實施例將根據第8圖所示的流程圖來說明本發明的半導體製作方法，其方法在各個不同的階段與步驟可以分別從對應的第1圖至第7圖的截面結構來獲得更清楚的細節與了解。須注意本發明提出了一種整合NVM與MOS製程的方法與結構，其涉及到半導體電路上記憶體單元區域與邏輯區域兩種不同部位，故圖示中會以兩個不同區域來表示並說明其在製程方面的整合性以及在結構上的關聯性。在一些其他例子中，邏輯區域還可能會細分成高電壓區域、中電壓區域、低電壓區域等，或是額外包含類比電路區域。為圖示簡明之故，在本發明實施例中僅以一邏輯區域來代表。本發明方法特別適用於深次微米(小於100奈米結點)或是奈米通道尺度的元件之製作，其可有效改進製程在熱預算(thermal budget)方面對於元件的影響，以提升元件的可靠度與性能，不需增加額外的製程步驟。 Now the following embodiments will illustrate the semiconductor manufacturing method of the present invention according to the flowchart shown in Figure 8. The method can be obtained from the corresponding cross-sectional structure of Figure 1 to Figure 7 at various stages and steps. Clearer details and understanding. It should be noted that the present invention proposes a method and structure for integrating NVM and MOS processes, which involves two different parts of the memory cell area and the logic area on the semiconductor circuit. Therefore, two different areas are shown and explained in the figure. Integration in manufacturing process and relevance in structure. In some other examples, the logic area may be subdivided into a high voltage area, a medium voltage area, a low voltage area, etc., or may additionally include an analog circuit area. For the sake of simplicity of the illustration, only a logical area is represented in the embodiment of the present invention. The method of the present invention is particularly suitable for the fabrication of deep sub-micron (less than 100 nanometer junctions) or nanochannel-scale components. It can effectively improve the impact of the process on the thermal budget of the component, so as to improve the component’s thermal budget. Reliability and performance, no additional process steps are required.

首先請參照第1圖，本發明整個半導體製程從一基底100開始進行。基底100可為一p型摻雜的單晶矽基底，其上可劃分有一記憶體單元區域100a與一邏輯區域100b。記憶體單元區域100a上預定用來形成非揮發性記憶體(NVM)單元等記憶體元件，邏輯區域100b上預定用來形成金屬氧化物半導體場效電晶體(MOSFET)等邏輯元件。基底100中形成有元件隔離層102，如氧化矽材質的淺溝渠絕緣結構(STI)或是場氧化層(FOX)等結構，來界定出其上個別元件的主動區域範圍。在進行元件的製作之前，基底100的記憶體單元區域100a與邏輯區域100b可先透過離子佈植製程在其中形成p型井與/或n型井，可控制元件的臨界電壓。為圖示簡明之故，圖中將不示出這些井區。 First, referring to FIG. 1, the entire semiconductor manufacturing process of the present invention starts from a substrate 100. The substrate 100 may be a p-type doped single crystal silicon substrate, on which a memory cell region 100a and a logic region 100b can be divided. The memory cell area 100a is intended to form memory elements such as non-volatile memory (NVM) cells, and the logic area 100b is intended to form logic elements such as metal oxide semiconductor field effect transistors (MOSFET). A device isolation layer 102 is formed in the substrate 100, such as a shallow trench insulation structure (STI) made of silicon oxide or a field oxide layer (FOX), to define the active area of individual devices thereon. Before the device is fabricated, the memory cell region 100a and the logic region 100b of the substrate 100 can be formed into p-type wells and/or n-type wells through an ion implantation process, and the threshold voltage of the device can be controlled. For the sake of brevity, these well areas will not be shown in the figure.

復參照第1圖。在步驟S1中，基底100的記憶體單元區域100a與邏輯區域100b上會先透過光刻製程分別形成浮動閘104與邏輯閘106以及介於該兩閘極結構與基底100之間的閘極氧化層108。在本發明實施例中，浮動閘104與邏輯閘106的材質可為多晶矽，如摻有磷的n型摻雜多晶矽，該兩者可以使用同一多晶矽層在同一道光刻製程中形成。在實作中，記憶體單元區域100a的每一單元區域上都會形成浮動閘，而邏輯區域100b上則可能同時有NMOS與PMOS兩種元件構成的CMOS電路結構。為圖示簡明之故，圖中分別以一浮動閘104與一邏輯閘106來代表之。記憶體單元區域100a與邏輯區域100b的閘極氧化層108可能在不同的製程中形成且具有不同的組成與厚度。例如浮動閘104下方的閘極氧化層可為一穿隧氧化層，其厚度可能與邏輯閘106下方的閘極氧化層108厚度不同。閘極氧化層108可為熱氧化層或是高介電常數層。 Refer to Figure 1 again. In step S1, the floating gate 104 and the logic gate 106 are formed on the memory cell region 100a and the logic region 100b of the substrate 100, respectively, and the gate oxide between the two gate structures and the substrate 100 is formed through a photolithography process. Layer 108. In the embodiment of the present invention, the material of the floating gate 104 and the logic gate 106 can be polysilicon, such as n-type doped polysilicon doped with phosphorus, and the two can be formed by using the same polysilicon layer in the same photolithography process. In practice, floating gates are formed on each cell region of the memory cell region 100a, and the logic region 100b may have a CMOS circuit structure composed of both NMOS and PMOS elements. For the sake of simplicity of the illustration, a floating gate 104 and a logic gate 106 are respectively represented in the figure. The gate oxide layer 108 of the memory cell region 100a and the logic region 100b may be formed in different processes and have different compositions and thicknesses. For example, the gate oxide layer under the floating gate 104 may be a tunnel oxide layer, and its thickness may be different from the thickness of the gate oxide layer 108 under the logic gate 106. The gate oxide layer 108 can be a thermal oxide layer or a high dielectric constant layer.

復參照第1圖。基底100上形成浮動閘104與邏輯閘106等結構後，接著在步驟S2中，在邏輯區域100b上覆蓋一層光阻110，並以光阻110為遮罩進行一離子佈植製程P1，例如以預定的斜角在基底100中摻雜砷離子或磷離子，以在記憶體單元區域100a的基底100中形成源極S與汲極D，被光阻110覆蓋的邏輯區域100b則不會形成源極與汲極。如第2圖所示，記憶體單元區域100a中的源極S與汲極D會自對準地形成在浮動閘104兩側。源極S與汲極D形成後可以進行一灰化製程將光阻110剝除，並進行一退火製程來擴散源極S與汲極D區域並去除其中的缺陷。 Refer to Figure 1 again. After the floating gate 104 and the logic gate 106 are formed on the substrate 100, then in step S2, a layer of photoresist 110 is covered on the logic area 100b, and an ion implantation process P1 is performed using the photoresist 110 as a mask, for example, The substrate 100 is doped with arsenic or phosphorous ions at a predetermined oblique angle to form a source S and a drain D in the substrate 100 of the memory cell region 100a. The logic region 100b covered by the photoresist 110 does not form a source. Pole and drain pole. As shown in FIG. 2, the source S and the drain D in the memory cell region 100a are formed on both sides of the floating gate 104 in a self-aligned manner. After the source S and the drain D are formed, an ashing process can be performed to remove the photoresist 110, and an annealing process can be performed to diffuse the source S and drain D regions and remove defects therein.

現在請參照第2圖。在記憶體單元區域100a的源極S與汲極D形成後，接下來在步驟S3中，在基底100上依序形成一層較薄的耦合介電層(或稱為電極間介電層)112以及一層較厚的多晶矽層114。耦合介電層112會共形地覆蓋在浮動閘104與邏輯閘106的表面，其材質可為氧化矽、氮化矽、或是其組合而成的ONO(氧化矽-氮化矽-氧化矽)複層結構。多晶矽層114係共形地覆蓋在耦合介電層112上，其材質可和浮動閘104以及邏輯閘106相同，如摻有磷的n型摻雜多晶矽。在後續製程中多晶矽層114會形成為NVM記憶元件的控制閘。 Please refer to Figure 2 now. After the source S and the drain D of the memory cell region 100a are formed, then in step S3, a thin coupling dielectric layer (or inter-electrode dielectric layer) 112 is sequentially formed on the substrate 100 And a thicker polysilicon layer 114. The coupling dielectric layer 112 will conformally cover the surfaces of the floating gate 104 and the logic gate 106. The material can be silicon oxide, silicon nitride, or a combination of ONO (silicon oxide-silicon nitride-silicon oxide). ) Multi-layer structure. The polysilicon layer 114 conformally covers the coupling medium On the electrical layer 112, the material can be the same as the floating gate 104 and the logic gate 106, such as n-type doped polysilicon doped with phosphorus. In the subsequent process, the polysilicon layer 114 will be formed as a control gate for the NVM memory device.

接下來請參照第3圖。在耦合介電層112與多晶矽層114形成後，接著在步驟S4中，進行一光刻製程圖案化多晶矽層114，形成位於浮動閘104上方的控制閘116。此步驟可包含在控制閘116以外區域的多晶矽層114上覆蓋一層光阻(未圖示)，之後再進行一乾蝕刻製程移除未被該光阻覆蓋的多晶矽層114，如此形成控制閘116。該光阻在控制閘116形成後會被去除。須注意在此步驟中，多晶矽層114下方的耦合介電層112並不會被移除。 Please refer to Figure 3 next. After the coupling dielectric layer 112 and the polysilicon layer 114 are formed, then in step S4, a photolithography process is performed to pattern the polysilicon layer 114 to form the control gate 116 above the floating gate 104. This step may include covering a layer of photoresist (not shown) on the polysilicon layer 114 outside the control gate 116, and then performing a dry etching process to remove the polysilicon layer 114 not covered by the photoresist, thus forming the control gate 116. The photoresist is removed after the control gate 116 is formed. It should be noted that in this step, the coupling dielectric layer 112 under the polysilicon layer 114 is not removed.

對一般的先前技術而言，其NVM記憶元件的控制閘之製作，包括多晶矽層114的形成與圖案化，大多是在邏輯區域100b上的電晶體的輕微摻雜汲極(LDD)、源極、以及汲極等部位形成之後才開始進行的。對於深次微米或是奈米通道尺度這種極微小的元件製作而言，此製作控制閘的製程會增加整體製程的熱預算，其製程所導致的熱循環會影響在控制閘之前就已經形成的邏輯區域100b上的輕微摻雜汲極、源極、以及汲極等摻雜部位的性質，使得其構成的邏輯元件失去應有的效能與可靠度，特別是對於低電壓元件，此熱循環的負面影響特別顯著。對此，在本發明實施例中，從第3圖可以看到，本發明製程特別將NVM記憶元件的控制閘116製程設計成在邏輯區域100b上的輕微摻雜汲極、源極、以及汲極等部位的製程之前，如此控制閘116的相關製程所帶來的熱循環就不會影響到後續邏輯區域100b上輕微摻雜汲極、源極、以及汲極的特性，其有效地解決先前技術的熱預算問題。 For the general prior art, the fabrication of the control gate of the NVM memory device, including the formation and patterning of the polysilicon layer 114, is mostly the lightly doped drain (LDD) and source of the transistor on the logic region 100b. , And the drain and other parts are formed after the beginning. For the production of extremely small components such as deep sub-micron or nano-channel scales, the process of making the control gate will increase the thermal budget of the overall process, and the thermal cycle caused by the process will affect the formation before the control gate The nature of the lightly doped drain, source, and drain on the logic region 100b of the logic region 100b makes the logic device constituted lose its due performance and reliability, especially for low-voltage devices, this thermal cycle The negative impact of is particularly significant. In this regard, in the embodiment of the present invention, it can be seen from FIG. 3 that the process of the present invention specifically designs the control gate 116 of the NVM memory device to slightly doped drain, source, and drain on the logic region 100b. Before the process of the pole position, the thermal cycle caused by the related process of controlling the gate 116 in this way will not affect the characteristics of the lightly doped drain, source, and drain on the subsequent logic region 100b, which effectively solves the previous problem. Technical thermal budget issues.

接下來請參照第4圖。在控制閘116形成後，接著在步驟S5中，進行一蝕刻製程移除基底100上裸露的耦合介電層112。該蝕刻製程可為一非等向性乾蝕刻製程，如此在基底100表面上的耦合介電層112移除後，邏輯區域100b上剩餘的耦合介電層112會在邏輯閘106的側壁上形成偏移間隔壁(offset spacer)115，其可用於後續輕摻雜汲極之製作。記憶體單元區域100a上剩餘的耦合介電層112即作為控制閘116與浮動閘104、源極S、以及汲極D之間的耦合介電層112(包含浮動閘104的間隔壁)，浮動閘104兩旁的間隔壁可以提供較為平緩的表面起伏，使得其上的控制閘116達到較佳的階梯覆蓋效果。在本發明方法實施例中，記憶體單元的耦合介電層112與邏輯元件的偏移間隔壁是以相同的材料層在同一製程中製作完成，其可減少製程中所需的材料層形成步驟以及其所衍生出之熱循環影響。 Please refer to Figure 4 next. After the control gate 116 is formed, then in step S5, an etching process is performed to remove the exposed coupling dielectric layer 112 on the substrate 100. The etching process can be an anisotropic dry etching process, so that after the coupling dielectric layer 112 on the surface of the substrate 100 is removed, the remaining coupling dielectric layer 112 on the logic region 100b is formed on the sidewall of the logic gate 106 Offset spacer 115, which can Used for subsequent production of lightly doped drain. The remaining coupling dielectric layer 112 on the memory cell region 100a serves as the coupling dielectric layer 112 (including the partition wall of the floating gate 104) between the control gate 116 and the floating gate 104, the source S, and the drain D. The partition walls on both sides of the gate 104 can provide a relatively smooth surface undulation, so that the control gate 116 thereon achieves a better step coverage effect. In the embodiment of the method of the present invention, the coupling dielectric layer 112 of the memory cell and the offset spacer of the logic element are fabricated with the same material layer in the same manufacturing process, which can reduce the material layer forming steps required in the manufacturing process. And the thermal cycle influence derived from it.

接下來請參照第5圖。在偏移間隔壁115形成後，接著在步驟S6中，進行一離子佈植製程，例如以斜角度摻雜磷、硼等離子(用於NMOS)或是二氟化硼離子(用於PMOS)，在邏輯區域100b的邏輯閘106兩旁的基底100中形成輕摻雜汲極LDD。偏移間隔壁115的存在可以保護邏輯閘106，並增加所形成的輕摻雜汲極LDD的延伸距離以改善邏輯元件的短通道效應問題。須注意此製程可能包含在未預定要形成輕摻雜汲極LDD的區域上(如記憶體單元區域100a)上形成佈植遮罩。為了圖示簡明之故，此處不予以示出。同樣地，輕摻雜汲極LDD形成後可進行依退火製程來擴散輕摻雜汲極LDD區域並去除其中的缺陷。 Please refer to Figure 5 next. After the offset spacer 115 is formed, then in step S6, an ion implantation process is performed, such as doping phosphorous, boron plasma (for NMOS) or boron difluoride ion (for PMOS) at an oblique angle, A lightly doped drain LDD is formed in the substrate 100 on both sides of the logic gate 106 of the logic region 100b. The existence of the offset spacer 115 can protect the logic gate 106 and increase the extension distance of the formed lightly doped drain LDD to improve the short channel effect of the logic element. It should be noted that this process may include forming an implant mask on a region where the lightly doped drain LDD is not scheduled to be formed (such as the memory cell region 100a). For the sake of brevity, it is not shown here. Similarly, after the lightly doped drain LDD is formed, an annealing process can be performed to diffuse the lightly doped drain LDD region and remove defects therein.

復參照第5圖。在邏輯區域100b上的輕摻雜汲極LDD形成後，接著在整個基底100的表面上形成一層間隔層118。間隔層118的材質可為氧化矽、氮氧化矽、或是由氧化矽與氮化矽組成的ONO複層結構，其共形地覆蓋在控制閘116、邏輯閘106與偏移間隔壁115等部位的表面上。間隔層118在後續製程可形成記憶體元件與邏輯元件的主間隔壁。 Refer to Figure 5 again. After the lightly doped drain LDD is formed on the logic region 100b, a spacer layer 118 is then formed on the entire surface of the substrate 100. The material of the spacer layer 118 can be silicon oxide, silicon oxynitride, or an ONO multi-layer structure composed of silicon oxide and silicon nitride, which conformally covers the control gate 116, the logic gate 106, the offset spacer 115, etc. On the surface of the site. The spacer layer 118 can form a main spacer between the memory device and the logic device in a subsequent process.

接下來請參照第6圖。在間隔層118形成後，接著在步驟S7中，進行一蝕刻製程移除部分的間隔層118。該蝕刻製程可為一非等向性乾蝕刻製程，如此在基底100表面上的間隔層118移除後，剩餘的間隔層118會分別在控制閘116的側壁以及邏輯閘106的偏移間隔壁115的側壁上形成主間隔壁120。主間隔壁120可以保護控制閘116與邏輯閘106，並可用於後續製程中邏輯區域100b上源極與汲極之製作。 Please refer to Figure 6 next. After the spacer layer 118 is formed, then in step S7, an etching process is performed to remove part of the spacer layer 118. The etching process can be an anisotropic dry etching process, so that after the spacer layer 118 on the surface of the substrate 100 is removed, the remaining spacer layer 118 will be on the sidewalls of the control gate 116 and the offset spacer wall of the logic gate 106, respectively. The main partition wall 120 is formed on the side wall of 115. The main partition wall 120 can protect the control gate 116 and the logic gate 106, and can be used for the source and drain on the logic region 100b in the subsequent process The production.

復參照第6圖。在主間隔壁120形成後，接著在步驟S8中，在記憶體單元區域100a上覆蓋一層光阻122，並以光阻122為遮罩進行一離子佈植製程P2，例如以斜角度摻雜砷離子(用於NMOS)或是二氟化硼離子(用於PMOS)，以在邏輯區域100b的基底100中形成源極S與汲極D，被光阻122覆蓋的記憶體單元區域100a則不會形成摻雜區。如第7圖所示，邏輯區域100b中的源極S與汲極D會自對準地形成在邏輯閘106的輕摻雜汲極LDD的兩側。源極S與汲極D形成後可以進行一灰化製程將光阻122剝除，並進行一退火製程來擴散源極S與汲極D區域並去除其中的缺陷。如此，即完成本發明本發明製作方法中NVM元件以及MOS元件之製作。 Refer to Figure 6 again. After the main partition wall 120 is formed, then in step S8, a layer of photoresist 122 is covered on the memory cell region 100a, and an ion implantation process P2 is performed using the photoresist 122 as a mask, such as doping arsenic at an oblique angle Ion (for NMOS) or boron difluoride ion (for PMOS) to form source S and drain D in the substrate 100 of the logic region 100b, while the memory cell region 100a covered by the photoresist 122 does not Doped regions will be formed. As shown in FIG. 7, the source S and the drain D in the logic region 100b are formed on both sides of the lightly doped drain LDD of the logic gate 106 in a self-aligned manner. After the source S and the drain D are formed, an ashing process can be performed to remove the photoresist 122, and an annealing process can be performed to diffuse the source S and drain D regions and remove defects therein. In this way, the manufacturing of the NVM device and the MOS device in the manufacturing method of the present invention is completed.

在完成上述NVM元件以及MOS元件之製作後，後續還可包含金屬矽化製程、在基底上形成層間介電層(ILD)覆蓋NVM元件以及MOS元件以及形成接觸件連接NVM元件與MOS元件的源極與汲極等常規製程。由於該些步驟並非本發明之重點，說明書中將不予說明與示出。 After the NVM device and the MOS device are fabricated, the subsequent steps may include a metal silicidation process, forming an interlayer dielectric layer (ILD) on the substrate to cover the NVM device and the MOS device, and forming contacts to connect the source of the NVM device and the MOS device Conventional processes such as dip poles. Since these steps are not the focus of the present invention, they will not be described and shown in the specification.

須注意在本發明方法實施例中，其製程特別將NVM記憶元件的控制閘116製程設計成在邏輯區域100b上的輕微摻雜汲極LDD、源極S、以及汲極D等部位的製程之前，如此控制閘116的相關製程所帶來的熱循環就不會影響到後續邏輯區域100b上輕微摻雜汲極LDD、源極S、以及汲極D的特性，其可有效地解決先前技術的熱預算問題。此外，對於本發明實施例中的NVM元件以及MOS元件來說，這兩種元件的閘極主間隔壁120都是使用同樣的材料層在同一道蝕刻製程中形成，可減少製作所需的成本與步驟，使為本發明的優點所在。 It should be noted that in the method embodiment of the present invention, the manufacturing process of the control gate 116 of the NVM memory device is specifically designed to be before the manufacturing process of the lightly doped drain LDD, source S, and drain D on the logic region 100b. Therefore, the thermal cycle caused by the related manufacturing process of the control gate 116 will not affect the characteristics of the lightly doped drain LDD, source S, and drain D on the subsequent logic region 100b, which can effectively solve the problem of the prior art Thermal budget issues. In addition, for the NVM devices and MOS devices in the embodiments of the present invention, the gate main spacers 120 of these two devices are formed by using the same material layer in the same etching process, which can reduce the manufacturing cost. And the steps are the advantages of the present invention.

現在請參照第7圖。根據上述實施例所說明之方法，本發明提出了一種新穎的半導體結構10，其結構包含一基底100，具有一記憶體單元區域100a與一邏輯區域100b。一記憶體單元20位於記憶體單元區域100a上，其包含一浮動閘 104位於基底100a上、第一源極S與第一汲極D分別位於浮動閘104的兩側、一控制閘116覆蓋在浮動閘104上並且與第一源極S以及該第一汲極S部分重疊、一耦合介電層112位於浮動閘104與控制閘116之間、以及第一間隔壁120位於控制閘116的側壁上。與習知技術不同的是，由於控制閘116覆蓋在浮動閘104上並有部分與兩側的第一源極S以及該第一汲極S重疊，記憶體單元20的第一間隔壁120只會與控制閘116接觸而不與浮動閘104接觸。半導體結構10還包含一金屬氧化物半導體場效電晶體30位於邏輯區域100b上，其包含一邏輯閘106位於基底100上、兩輕摻雜汲極LDD分別位於邏輯閘106的兩側、第二源極S與第二汲極D分別位於兩輕摻雜汲極LDD的外側、偏移間隔壁115位於邏輯閘106的兩側、以及第二間隔壁120位於偏移間隔壁115的側壁上。在此結構實施例中，記憶體單元20的第一間隔壁120與金屬氧化物半導體場效電晶體30的第二間隔壁120的材質相同且是在同一製程中形成。再者，記憶體單元20的耦合介電層112與金屬氧化物半導體場效電晶體30的偏移間隔壁115的材質相同且可以是在同一製程中形成。此外，記憶體單元20的浮動閘104與金屬氧化物半導體場效電晶體30的邏輯閘106的材質相同且可以是在同一製程中形成。 Please refer to Figure 7 now. According to the method described in the above embodiments, the present invention proposes a novel semiconductor structure 10, which includes a substrate 100 with a memory cell region 100a and a logic region 100b. A memory cell 20 is located on the memory cell area 100a, which includes a floating gate 104 is located on the substrate 100a, the first source S and the first drain D are respectively located on both sides of the floating gate 104, a control gate 116 covers the floating gate 104 and is connected to the first source S and the first drain S Partly overlapping, a coupling dielectric layer 112 is located between the floating gate 104 and the control gate 116, and the first partition wall 120 is located on the sidewall of the control gate 116. Different from the prior art, since the control gate 116 covers the floating gate 104 and partially overlaps the first source S and the first drain S on both sides, the first partition wall 120 of the memory cell 20 is only It will contact the control gate 116 but not the floating gate 104. The semiconductor structure 10 further includes a metal oxide semiconductor field effect transistor 30 on the logic region 100b, which includes a logic gate 106 on the substrate 100, two lightly doped drain LDDs on both sides of the logic gate 106, and a second The source S and the second drain D are respectively located outside the two lightly doped drains LDD, the offset spacer 115 is located on both sides of the logic gate 106, and the second spacer 120 is located on the sidewall of the offset spacer 115. In this structural embodiment, the first partition wall 120 of the memory cell 20 and the second partition wall 120 of the metal oxide semiconductor field effect transistor 30 are made of the same material and are formed in the same manufacturing process. Furthermore, the coupling dielectric layer 112 of the memory cell 20 and the offset spacer 115 of the metal oxide semiconductor field effect transistor 30 are made of the same material and can be formed in the same manufacturing process. In addition, the floating gate 104 of the memory cell 20 and the logic gate 106 of the metal oxide semiconductor field effect transistor 30 are made of the same material and can be formed in the same manufacturing process.

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

10:半導體結構 10: Semiconductor structure

20:記憶體單元 20: Memory unit

100:基底 100: base

100a:記憶體單元區域 100a: Memory cell area

100b:邏輯區域 100b: logical area

102:元件隔離層 102: component isolation layer

104:浮動閘 104: Floating Gate

106:邏輯閘 106: Logic Gate

108:閘極氧化層 108: gate oxide layer

112:耦合介電層 112: coupling dielectric layer

115:偏移間隔壁 115: Offset partition wall

116:控制閘 116: control gate

120:主間隔壁 120: main partition

D:汲極 D: Dip pole

LDD:輕摻雜汲極 LDD: Lightly doped drain

S:源極 S: source

Claims

一種半導體結構，包含：一基底，具有一記憶體單元區域與一邏輯區域；一記憶體單元，位於該記憶體單元區域上，該記憶體單元包含：一浮動閘，位於該基底上；第一源極與第一汲極，分別位於該浮動閘兩側；一控制閘，覆蓋該浮動閘且與該第一源極以及該第一汲極部分重疊；一耦合介電層，位於該浮動閘與該控制閘之間；以及第一間隔壁，位於該控制閘的側壁上；一金屬氧化物半導體場效電晶體，位於該邏輯區域上，該金屬氧化物半導體場效電晶體包含：一邏輯閘，位於該基底上；兩輕摻雜汲極，分別位於該邏輯閘兩側；第二源極與第二汲極，分別位於該兩輕摻雜汲極的外側；偏移間隔壁，位於該邏輯閘的兩側，其中該偏移間隔壁與該耦合介電層的材質相同且在同一製程中形成；以及第二間隔壁，位於該偏移間隔壁的側壁上；其中該記憶體單元的該第一間隔壁與該金屬氧化物半導體場效電晶體的該第二間隔壁的材質相同且在同一製程中形成。 A semiconductor structure includes: a substrate having a memory cell area and a logic area; a memory cell located on the memory cell area, the memory cell including: a floating gate located on the substrate; first The source and the first drain are respectively located on both sides of the floating gate; a control gate covers the floating gate and partially overlaps the first source and the first drain; a coupling dielectric layer is located on the floating gate Between and the control gate; and a first partition wall located on the sidewall of the control gate; a metal oxide semiconductor field effect transistor located on the logic area, and the metal oxide semiconductor field effect transistor includes: a logic The gate is located on the substrate; two lightly doped drains are respectively located on both sides of the logic gate; the second source and the second drain are respectively located outside the two lightly doped drains; the offset spacer is located On both sides of the logic gate, the offset spacer and the coupling dielectric layer are made of the same material and formed in the same manufacturing process; and a second spacer is located on the sidewall of the offset spacer; wherein the memory cell The first spacer and the second spacer of the metal oxide semiconductor field effect transistor are made of the same material and are formed in the same manufacturing process.

根據申請專利範圍第1項所述之半導體結構，其中該第一間隔壁與該第二間隔壁的材質為氧化矽、氮氧化矽或是氧化矽-氮化矽-氧化矽複層結構。 According to the semiconductor structure described in claim 1, wherein the material of the first partition wall and the second partition wall is silicon oxide, silicon oxynitride, or a silicon oxide-silicon nitride-silicon oxide composite structure.

根據申請專利範圍第1項所述之半導體結構，該偏移間隔壁與該耦合介電層的材質為氧化矽、氮化矽、或是氧化矽-氮化矽-氧化矽複層結構。 According to the semiconductor structure described in item 1 of the scope of patent application, the offset spacer and the coupling The material of the composite dielectric layer is silicon oxide, silicon nitride, or a silicon oxide-silicon nitride-silicon oxide composite layer structure.

根據申請專利範圍第1項所述之半導體結構，其中該浮動閘與該邏輯閘的材質相同且在同一製程中形成。 According to the semiconductor structure described in item 1 of the scope of patent application, the floating gate and the logic gate are made of the same material and formed in the same manufacturing process.

根據申請專利範圍第4項所述之半導體結構，該浮動閘與該邏輯閘的材質為多晶矽。 According to the semiconductor structure described in item 4 of the scope of patent application, the material of the floating gate and the logic gate is polysilicon.

一種半導體結構的製作方法，包含：在一基底上同時形成一浮動閘與一邏輯閘；在該浮動閘的兩側分別形成第一源極與第一汲極；在形成該第一源極與該第一汲極後，在該基底、該浮動閘、以及該邏輯閘上依序形成一耦合介電層與一多晶矽層；圖案化該多晶矽層，以形成覆蓋該浮動閘的控制閘；以及在形成該控制閘後，在該邏輯閘的兩側形成輕摻雜汲極、第二源極、以及第二汲極。 A method for manufacturing a semiconductor structure includes: simultaneously forming a floating gate and a logic gate on a substrate; forming a first source and a first drain on both sides of the floating gate; forming the first source and After the first drain, a coupling dielectric layer and a polysilicon layer are sequentially formed on the substrate, the floating gate, and the logic gate; the polysilicon layer is patterned to form a control gate covering the floating gate; and After the control gate is formed, a lightly doped drain, a second source, and a second drain are formed on both sides of the logic gate.

根據申請專利範圍第6項所述之半導體結構，更包含：在形成該控制閘後，對該耦合介電層進行一非等向性蝕刻製程，以形成位於該邏輯閘兩側的偏移間隔壁；以及在形成該偏移間隔壁後，在該邏輯閘的兩側形成該輕摻雜汲極。 According to the semiconductor structure described in item 6 of the scope of the patent application, it further includes: after forming the control gate, performing an anisotropic etching process on the coupling dielectric layer to form offset spaces located on both sides of the logic gate Barriers; and after forming the offset barriers, forming the lightly doped drain on both sides of the logic gate.

根據申請專利範圍第7項所述之半導體結構，更包含：在形成該輕摻雜汲極後，在該控制閘與該浮動閘上形成一間隔層；以及對該間隔層進行一非等向性蝕刻製程，以形成位於該控制閘的側壁上以及該偏移間隔壁的側壁上的間隔壁。 The semiconductor structure according to item 7 of the scope of patent application, further comprising: forming a spacer layer on the control gate and the floating gate after forming the lightly doped drain; and An anisotropic etching process is performed on the spacer layer to form spacers on the sidewalls of the control gate and the sidewalls of the offset spacers.

根據申請專利範圍第8項所述之半導體結構，更包含在形成該間隔壁後在該邏輯閘的兩側形成該第二源極與第二汲極。 According to the semiconductor structure described in item 8 of the scope of patent application, it further includes forming the second source electrode and the second drain electrode on both sides of the logic gate after forming the partition wall.

根據申請專利範圍第6項所述之半導體結構，其中該浮動閘與該邏輯閘的材質相同且在同一製程中形成。 According to the semiconductor structure described in item 6 of the scope of patent application, the floating gate and the logic gate are made of the same material and formed in the same manufacturing process.