TWI732626B - Display panel and manufacturing method thereof - Google Patents

Display panel and manufacturing method thereof Download PDF

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TWI732626B
TWI732626B TW109123745A TW109123745A TWI732626B TW I732626 B TWI732626 B TW I732626B TW 109123745 A TW109123745 A TW 109123745A TW 109123745 A TW109123745 A TW 109123745A TW I732626 B TWI732626 B TW I732626B
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layer
conductive layer
scan line
insulating layer
electrode
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TW202203178A (en
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甘政祐
黃國有
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友達光電股份有限公司
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Priority to CN202011640199.6A priority patent/CN112768472B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

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  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
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Abstract

A display panel includes a semiconductor layer, a gate insulating layer, a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer. The gate insulating layer is located on the semiconductor layer. The first conductive layer is located on the gate insulating layer, and includes a first scan line and a gate. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer, and includes a data line, a source, a drain, and a first connecting electrode. The second insulating layer is located on the second conductive layer. The third conductive layer is located on the second insulating layer and includes a second scan line. The first connecting electrode is connected to the first scan line. The second scan line is connected to the first connecting electrode.

Description

顯示面板及其製造方法Display panel and manufacturing method thereof

本發明是有關於一種顯示面板及其製造方法。 The invention relates to a display panel and a manufacturing method thereof.

隨著科技的進步，許多汽車都會搭載顯示裝置，除了可以顯示行車資訊(例如：衛星導航畫面)給駕駛者看以外，還能顯示具有娛樂性質的畫面(例如：遊戲或電影畫面)給副駕駛觀賞。 With the advancement of technology, many cars will be equipped with display devices. In addition to displaying driving information (such as satellite navigation screens) to the driver, they can also display entertainment screens (such as game or movie screens) to the co-pilot. Watch.

一般的液晶顯示裝置都包括了橫向延伸的掃描線以及縱向延伸的資料線，藉由掃描線以及資料線可以控制液晶顯示裝置中之子畫素上的訊號。一些汽車用的顯示裝置的橫向的延伸長度較長，因此具備了長度較長的掃描線。然而，若掃描線的長度太長，容易因為掃描線的電阻過大而導致畫面品質下降，因此，目前亟需一種可以解決前述問題的方法。 A general liquid crystal display device includes horizontally extending scan lines and longitudinally extending data lines. The scan lines and data lines can control the signals on the sub-pixels in the liquid crystal display device. Some display devices used in automobiles have a long horizontal extension, and therefore have a long scan line. However, if the length of the scan line is too long, the resistance of the scan line is likely to be too large and the picture quality is degraded. Therefore, there is an urgent need for a method that can solve the aforementioned problems.

本發明提供一種顯示面板，可以改善掃描線的電阻過大 的問題。 The present invention provides a display panel, which can improve the resistance of scan lines from being too large The problem.

本發明提供一種顯示面板的製造方法，可以降低掃描線的電阻。 The present invention provides a method for manufacturing a display panel, which can reduce the resistance of scan lines.

本發明的至少一實施例提供一種顯示面板，包括半導體層、閘極絕緣層、第一導電層、第一絕緣層、第二導電層、第二絕緣層以及第三導電層。半導體層位於基板上。閘極絕緣層位於半導體層上。第一導電層位於閘極絕緣層上，且包括第一掃描線以及閘極。閘極連接第一掃描線，且重疊於半導體層。第一絕緣層位於第一導電層上。第二導電層位於第一絕緣層上，且包括資料線、源極、汲極以及第一連接電極。源極以及汲極分別電性連接半導體層。源極連接資料線。第一連接電極重疊於第一掃描線。第二絕緣層位於第二導電層上。第三導電層位於第二絕緣層上，且包括第二掃描線。第一連接電極透過貫穿第一絕緣層的第一開口而連接至第一掃描線。第二掃描線透過貫穿第二絕緣層的第二開口而連接至第一連接電極。 At least one embodiment of the present invention provides a display panel including a semiconductor layer, a gate insulating layer, a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer. The semiconductor layer is located on the substrate. The gate insulating layer is located on the semiconductor layer. The first conductive layer is located on the gate insulating layer and includes a first scan line and a gate. The gate is connected to the first scan line and overlaps the semiconductor layer. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer and includes a data line, a source electrode, a drain electrode, and a first connection electrode. The source electrode and the drain electrode are respectively electrically connected to the semiconductor layer. The source is connected to the data line. The first connection electrode overlaps the first scan line. The second insulating layer is located on the second conductive layer. The third conductive layer is located on the second insulating layer and includes a second scan line. The first connection electrode is connected to the first scan line through a first opening penetrating the first insulating layer. The second scan line is connected to the first connection electrode through a second opening penetrating the second insulating layer.

本發明的至少一實施例提供一種顯示面板的製造方法，包括：形成半導體層於基板上；形成閘極絕緣層於半導體層上；形成第一導電層於閘極絕緣層上，且第一導電層包括第一掃描線以及閘極，閘極連接第一掃描線，且閘極重疊於半導體層；形成第一絕緣層於第一導電層上，第一絕緣層具有重疊於第一掃描線的第一開口；形成第二導電層於第一絕緣層上，且第二導電層包括資料線、源極、汲極以及第一連接電極，源極以及汲極分別電 性連接半導體層，且源極連接資料線，第一連接電極重疊於第一掃描線，且第一連接電極透過第一開口而連接至第一掃描線；形成第二絕緣層於第二導電層上，第二絕緣層具有重疊於第一連接電極的第二開口；形成第三導電層於第二絕緣層上，且第三導電層包括第二掃描線，第二掃描線透過第二開口而連接至第一連接電極。 At least one embodiment of the present invention provides a method for manufacturing a display panel, including: forming a semiconductor layer on a substrate; forming a gate insulating layer on the semiconductor layer; forming a first conductive layer on the gate insulating layer, and the first conductive layer The layer includes a first scan line and a gate electrode, the gate electrode is connected to the first scan line, and the gate electrode overlaps the semiconductor layer; a first insulating layer is formed on the first conductive layer, and the first insulating layer has an overlapped first scan line A first opening; a second conductive layer is formed on the first insulating layer, and the second conductive layer includes a data line, a source electrode, a drain electrode, and a first connection electrode, the source electrode and the drain electrode are respectively electrically connected The source is connected to the semiconductor layer, the source is connected to the data line, the first connection electrode overlaps the first scan line, and the first connection electrode is connected to the first scan line through the first opening; a second insulating layer is formed on the second conductive layer The second insulating layer has a second opening overlapping the first connecting electrode; a third conductive layer is formed on the second insulating layer, and the third conductive layer includes a second scan line, and the second scan line passes through the second opening. Connect to the first connection electrode.

10、20、30:顯示面板 10, 20, 30: display panel

100:基板 100: substrate

110:遮光層 110: shading layer

120:緩衝層 120: buffer layer

130:半導體層 130: semiconductor layer

140:閘極絕緣層 140: gate insulating layer

150:第一導電層 150: first conductive layer

152:第一掃描線 152: first scan line

154:閘極 154: Gate

160:第一絕緣材料層 160: first insulating material layer

160’:第一絕緣層 160’: First insulating layer

170:第二導電層 170: second conductive layer

172:資料線 172: Data Line

174:源極 174: Source

176:汲極 176: Dip pole

178a:第一連接電極 178a: first connecting electrode

178b:第二連接電極 178b: second connecting electrode

180:第二絕緣層 180: second insulating layer

190:第三導電層 190: third conductive layer

192:第二掃描線 192: second scan line

194a:第一觸控訊號線 194a: The first touch signal line

194b:第二觸控訊號線 194b: The second touch signal line

194a-1、194b-1:分支部 194a-1, 194b-1: branch

196:連接電極 196: Connect the electrodes

200:平坦層 200: flat layer

210:共用電極 210: Common electrode

220:絕緣層 220: insulating layer

230:畫素電極 230: pixel electrode

E1、E2:延伸方向 E1, E2: extension direction

H1:第一開口 H1: First opening

H2:第二開口 H2: second opening

H3:第三開口 H3: Third opening

H4:第四開口 H4: Fourth opening

H5:第五開口 H5: Fifth opening

O1、O2、O3:開口 O1, O2, O3: opening

st:狹縫 st: slit

T:開關元件 T: switching element

圖1A至圖1E是依照本發明的一實施例的一種顯示面板的製造方法的上視示意圖。 1A to 1E are schematic top views of a method for manufacturing a display panel according to an embodiment of the invention.

圖2A至圖2E是依照本發明的一實施例的一種顯示面板的製造方法的剖面示意圖。 2A to 2E are schematic cross-sectional views of a method for manufacturing a display panel according to an embodiment of the invention.

圖3A至圖3C是依照本發明的一實施例的一種顯示面板的製造方法的剖面示意圖。 3A to 3C are schematic cross-sectional views of a method for manufacturing a display panel according to an embodiment of the invention.

圖4是依照本發明的一實施例的一種顯示面板的上視示意圖。 FIG. 4 is a schematic top view of a display panel according to an embodiment of the invention.

圖5是依照本發明的一實施例的一種顯示面板的上視示意圖。 FIG. 5 is a schematic top view of a display panel according to an embodiment of the invention.

圖1A至圖1E是依照本發明的一實施例的一種顯示面板 的製造方法的上視示意圖。圖2A至圖2E是依照本發明的一實施例的一種顯示面板的製造方法的剖面示意圖。圖3A至圖3C是依照本發明的一實施例的一種顯示面板的製造方法的剖面示意圖。 1A to 1E are a display panel according to an embodiment of the present invention Schematic view of the top view of the manufacturing method. 2A to 2E are schematic cross-sectional views of a method for manufacturing a display panel according to an embodiment of the invention. 3A to 3C are schematic cross-sectional views of a method for manufacturing a display panel according to an embodiment of the invention.

請參考圖1A與圖2A，形成半導體層130於基板100上。在本實施例中，基板100的材料可為玻璃、石英、有機聚合物、或是不透光/反射材料(例如：導電材料、金屬、晶圓、陶瓷或其它可適用的材料)或是其它可適用的材料。若使用導電材料或金屬時，則在基板100上覆蓋一層絕緣層(未繪示)，以避免短路問題。半導體層130為單層或多層結構，且材料包括非晶矽、多晶矽、微晶矽、單晶矽、有機半導體材料、氧化物半導體材料(例如：銦鋅氧化物、銦鎵鋅氧化物、或是其它合適的材料、或上述之組合)或其它合適的材料或含有摻雜物(dopant)於上述材料中、或上述之組合。在本實施例中，半導體層130的形狀類似L形，但本發明不以此為限。在其他實施例中，半導體層130為其他幾何形狀。 Please refer to FIG. 1A and FIG. 2A to form a semiconductor layer 130 on the substrate 100. In this embodiment, the material of the substrate 100 can be glass, quartz, organic polymer, or opaque/reflective material (for example, conductive material, metal, wafer, ceramic or other applicable materials) or other materials. Applicable materials. If conductive materials or metals are used, an insulating layer (not shown) is covered on the substrate 100 to avoid short circuit problems. The semiconductor layer 130 has a single-layer or multi-layer structure, and the material includes amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (for example: indium zinc oxide, indium gallium zinc oxide, or It is other suitable materials, or a combination of the above) or other suitable materials or contains a dopant in the above materials, or a combination of the above. In this embodiment, the shape of the semiconductor layer 130 is similar to an L shape, but the invention is not limited to this. In other embodiments, the semiconductor layer 130 has other geometric shapes.

在本實施例中，形成半導體層130之前，選擇性地於基板100上形成遮光層110以及緩衝層120。半導體層130部分重疊於遮光層110，且半導體層130與遮光層110之間夾有緩衝層120。 In this embodiment, before forming the semiconductor layer 130, the light shielding layer 110 and the buffer layer 120 are selectively formed on the substrate 100. The semiconductor layer 130 partially overlaps the light shielding layer 110, and a buffer layer 120 is sandwiched between the semiconductor layer 130 and the light shielding layer 110.

請參考圖1B與圖2B，形成閘極絕緣層140於半導體層130上。形成第一導電層150於閘極絕緣層140上。第一導電層150包括第一掃描線152以及閘極154，閘極154連接第一掃描線152，且閘極154重疊於半導體層130。 Please refer to FIG. 1B and FIG. 2B to form a gate insulating layer 140 on the semiconductor layer 130. A first conductive layer 150 is formed on the gate insulating layer 140. The first conductive layer 150 includes a first scan line 152 and a gate electrode 154, the gate electrode 154 is connected to the first scan line 152, and the gate electrode 154 overlaps the semiconductor layer 130.

在本實施例中，每個半導體層130有兩個位置重疊於第一導電層150，而第一導電層150重疊於半導體層130的位置為閘極154。在本實施例中，第一掃描線152沿著延伸方向E1延伸，部分閘極154自第一掃描線152的側邊朝外延伸，另一部分閘極154位於第一掃描線152的延伸方向E1上。 In this embodiment, each semiconductor layer 130 overlaps the first conductive layer 150 at two positions, and the position where the first conductive layer 150 overlaps the semiconductor layer 130 is the gate 154. In this embodiment, the first scan line 152 extends along the extension direction E1, a part of the gate electrode 154 extends outward from the side of the first scan line 152, and another part of the gate electrode 154 is located in the extension direction E1 of the first scan line 152. on.

在一些實施例中，第一導電層150為單層或多層結構。在一些實施例中，第一導電層150為耐高溫金屬，且材料包括鎢、鉬、鋁上述金屬的合金或上述金屬之組合。 In some embodiments, the first conductive layer 150 has a single-layer or multi-layer structure. In some embodiments, the first conductive layer 150 is a high temperature resistant metal, and the material includes tungsten, molybdenum, aluminum alloys of the foregoing metals, or a combination of the foregoing metals.

在一些實施例中，在形成第一導電層150後，會對半導體層130進行離子摻雜製程。 In some embodiments, after the first conductive layer 150 is formed, the semiconductor layer 130 is subjected to an ion doping process.

形成第一絕緣材料層160於第一導電層150上。在一些實施例中，加熱第一絕緣材料層160，使第一絕緣材料層160中的氫離子擴散至半導體層130，藉此修復半導體層130在離子摻雜製程中所受到的損傷。在一些實施例中，第一導電層150在前述加熱製程中保護半導體層130，使氫離子不容易擴散至重疊於第一導電層150的部分半導體層130。在一些實施例中，前述加熱製程的溫度約為攝氏500度至攝氏800度。在本實施例中，由於第一導電層150為耐高溫金屬，因此，第一導電層150不容易在加熱製程中受損。 A first insulating material layer 160 is formed on the first conductive layer 150. In some embodiments, the first insulating material layer 160 is heated to diffuse the hydrogen ions in the first insulating material layer 160 to the semiconductor layer 130, thereby repairing damage to the semiconductor layer 130 during the ion doping process. In some embodiments, the first conductive layer 150 protects the semiconductor layer 130 during the aforementioned heating process, so that hydrogen ions are not easily diffused to a portion of the semiconductor layer 130 overlapping the first conductive layer 150. In some embodiments, the temperature of the aforementioned heating process is about 500 degrees Celsius to 800 degrees Celsius. In this embodiment, since the first conductive layer 150 is made of high-temperature resistant metal, the first conductive layer 150 is not easily damaged during the heating process.

請參考圖1C、圖2C與圖3A，圖案化第一絕緣材料層160以形成位於第一導電層150上的第一絕緣層160’。第一絕緣層160’具有重疊於第一掃描線152的第一開口H1，第一開口H1暴露出 第一掃描線152。 1C, 2C, and 3A, the first insulating material layer 160 is patterned to form a first insulating layer 160' on the first conductive layer 150. The first insulating layer 160' has a first opening H1 overlapping the first scan line 152, and the first opening H1 exposes First scan line 152.

形成第二導電層170於第一絕緣層160’上。第二導電層170包括資料線172、源極174、汲極176以及第一連接電極178a。源極174以及汲極176分別電性連接半導體層130。舉例來說，源極174以及汲極176透過分別透過開口O1以及開口O2而電性連接至半導體層130，其中開口O1以及開口O2貫穿閘極絕緣層140以及第一絕緣層160’。源極174連接資料線172，且汲極176分離於資料線172。資料線172沿著延伸方向E2延伸。延伸方向E2交錯於延伸方向E1。 A second conductive layer 170 is formed on the first insulating layer 160'. The second conductive layer 170 includes a data line 172, a source electrode 174, a drain electrode 176, and a first connection electrode 178a. The source electrode 174 and the drain electrode 176 are electrically connected to the semiconductor layer 130 respectively. For example, the source electrode 174 and the drain electrode 176 are electrically connected to the semiconductor layer 130 through the opening O1 and the opening O2, respectively, wherein the opening O1 and the opening O2 penetrate the gate insulating layer 140 and the first insulating layer 160'. The source electrode 174 is connected to the data line 172, and the drain electrode 176 is separated from the data line 172. The data line 172 extends along the extension direction E2. The extension direction E2 is staggered with the extension direction E1.

在本實施例中，開關元件T包括半導體層130、閘極154、源極174以及汲極176。 In this embodiment, the switching element T includes a semiconductor layer 130, a gate electrode 154, a source electrode 174, and a drain electrode 176.

第一連接電極178a重疊於第一掃描線152，且第一連接電極178a透過第一開口H1而連接至第一掃描線152，其中第一開口H1貫穿第一絕緣層160’。在本實施例中，第二導電層170還包括分離於第一連接電極178a的第二連接電極178b。第二連接電極178b跨過第一掃描線152。在本實施例中，第二連接電極178b位於第一連接電極178a以及資料線172之間。 The first connection electrode 178a overlaps the first scan line 152, and the first connection electrode 178a is connected to the first scan line 152 through the first opening H1, wherein the first opening H1 penetrates the first insulating layer 160'. In this embodiment, the second conductive layer 170 further includes a second connection electrode 178b separated from the first connection electrode 178a. The second connection electrode 178b crosses the first scan line 152. In this embodiment, the second connection electrode 178b is located between the first connection electrode 178a and the data line 172.

在一些實施例中，第二導電層170為單層或多層結構，且材料包括銀、銅、鋁、上述金屬的合金或上述金屬之組合。 In some embodiments, the second conductive layer 170 has a single-layer or multi-layer structure, and the material includes silver, copper, aluminum, alloys of the foregoing metals, or combinations of the foregoing metals.

形成第二絕緣層180於第二導電層170上，第二絕緣層180具有重疊於第一連接電極178a的第二開口H2。在本實施例中，第二絕緣層180還包括第三開口H3、第四開口H4以及第五開口 H5。第三開口H3以及第四開口H4重疊於第二連接電極178b。第五開口H5重疊於汲極174。 A second insulating layer 180 is formed on the second conductive layer 170, and the second insulating layer 180 has a second opening H2 overlapping the first connection electrode 178a. In this embodiment, the second insulating layer 180 further includes a third opening H3, a fourth opening H4, and a fifth opening. H5. The third opening H3 and the fourth opening H4 overlap the second connection electrode 178b. The fifth opening H5 overlaps the drain electrode 174.

請參考圖1D、圖2D以及圖3B，形成第三導電層190於第二絕緣層180上。第三導電層190包括第二掃描線192、第一觸控訊號線194a以及第二觸控訊號線194b。第二掃描線192透過第二絕緣層180的第二開口H2而連接至第一連接電極178a。藉由第一連接電極178a的設置，第二掃描線192電性連接至第一掃描線152，並改善掃描線的電阻值過大的問題。 Please refer to FIG. 1D, FIG. 2D, and FIG. 3B to form a third conductive layer 190 on the second insulating layer 180. The third conductive layer 190 includes a second scan line 192, a first touch signal line 194a, and a second touch signal line 194b. The second scan line 192 is connected to the first connection electrode 178a through the second opening H2 of the second insulating layer 180. With the arrangement of the first connection electrode 178a, the second scan line 192 is electrically connected to the first scan line 152, and the problem of excessive resistance of the scan line is improved.

在本實施例中，第二掃描線192沿著延伸方向E1延伸，且平行於第一掃描線152。在本實施例中，部分資料線172位於第二掃描線192與第一掃描線152之間。 In this embodiment, the second scan line 192 extends along the extension direction E1 and is parallel to the first scan line 152. In this embodiment, part of the data line 172 is located between the second scan line 192 and the first scan line 152.

第一觸控訊號線194a以及第二觸控訊號線194b分別位於第二掃描線192的兩側。第一觸控訊號線194a透過貫穿第二絕緣層180的第三開口H3而連接至第二連接電極178b。第二觸控訊號線194b透過貫穿第二絕緣層180的第四開口H4而連接至第二連接電極178b。第一觸控訊號線194a透過第二連接電極178b而電性連接至第二觸控訊號線194b，因此，第一觸控訊號線194a以及第二觸控訊號線194b不會與第二掃描線192短路。 The first touch signal line 194a and the second touch signal line 194b are located on both sides of the second scan line 192, respectively. The first touch signal line 194a is connected to the second connection electrode 178b through the third opening H3 passing through the second insulating layer 180. The second touch signal line 194b is connected to the second connection electrode 178b through the fourth opening H4 passing through the second insulating layer 180. The first touch signal line 194a is electrically connected to the second touch signal line 194b through the second connection electrode 178b. Therefore, the first touch signal line 194a and the second touch signal line 194b are not connected to the second scan line 192 short circuit.

第一觸控訊號線194a以及第二觸控訊號線194b沿著延伸方向E2延伸，且平行於資料線172。在本實施例中，第一觸控訊號線194a部分重疊於閘極154以及半導體層130，且第一觸控訊號線194a以及第二觸控訊號線194b不重疊於資料線172。 The first touch signal line 194a and the second touch signal line 194b extend along the extension direction E2 and are parallel to the data line 172. In this embodiment, the first touch signal line 194a partially overlaps the gate electrode 154 and the semiconductor layer 130, and the first touch signal line 194a and the second touch signal line 194b do not overlap the data line 172.

在本實施例中，第三導電層190還包括連接電極196，連接電極196重疊於汲極174，且透過第二絕緣層180的第五開口H5而電性連接至汲極174。 In this embodiment, the third conductive layer 190 further includes a connecting electrode 196 overlapping the drain electrode 174 and electrically connected to the drain electrode 174 through the fifth opening H5 of the second insulating layer 180.

在一些實施例中，第三導電層190為單層或多層結構。在一些實施例中，第三導電層190的材料不同於第一導電層150的材料，第三導電層190為低電阻的金屬，且材料包括銀、銅、鋁、上述金屬的合金或上述金屬之組合。在一些實施例中，第二掃描線192的電阻值低於第一掃描線152的電阻值。在一些實施例中，第二導電層170的材料與第三導電層190的材料相同。 In some embodiments, the third conductive layer 190 has a single-layer or multi-layer structure. In some embodiments, the material of the third conductive layer 190 is different from the material of the first conductive layer 150, and the third conductive layer 190 is a low-resistance metal, and the material includes silver, copper, aluminum, alloys of the foregoing metals, or the foregoing metals.的组合。 The combination. In some embodiments, the resistance value of the second scan line 192 is lower than the resistance value of the first scan line 152. In some embodiments, the material of the second conductive layer 170 is the same as the material of the third conductive layer 190.

在本實施例中，第一觸控訊號線194a、第二觸控訊號線194b以及第二掃描線192皆屬於相同導電層，因此，第一觸控訊號線194a、第二觸控訊號線194b以及第二掃描線192的圖形可以藉由同一個光罩所定義，藉此降低製造成本。 In this embodiment, the first touch signal line 194a, the second touch signal line 194b, and the second scan line 192 all belong to the same conductive layer. Therefore, the first touch signal line 194a and the second touch signal line 194b And the pattern of the second scan line 192 can be defined by the same mask, thereby reducing the manufacturing cost.

請參考圖1E、圖2E以及圖3C，形成平坦層200於第三導電層190。平坦層200例如為有機材料或無機材料。 Please refer to FIG. 1E, FIG. 2E, and FIG. 3C to form a flat layer 200 on the third conductive layer 190. The flat layer 200 is, for example, an organic material or an inorganic material.

形成共用電極210於平坦層200上。形成絕緣層220於共用電極210上。形成畫素電極230於絕緣層220上。在本實施例中，畫素電極230透過開口O3而電性連接至連接電極196，其中開口O3貫穿絕緣層220以及平坦層200。在本實施例中，畫素電極230透過連接電極196而電性連接至汲極176，但本發明不以此為限。在其他實施例中，第三導電層190不包括連接電極196，而畫素電極230直接電性連接至汲極176。 A common electrode 210 is formed on the flat layer 200. An insulating layer 220 is formed on the common electrode 210. The pixel electrode 230 is formed on the insulating layer 220. In this embodiment, the pixel electrode 230 is electrically connected to the connection electrode 196 through the opening O3, wherein the opening O3 penetrates the insulating layer 220 and the flat layer 200. In this embodiment, the pixel electrode 230 is electrically connected to the drain electrode 176 through the connection electrode 196, but the invention is not limited to this. In other embodiments, the third conductive layer 190 does not include the connection electrode 196, and the pixel electrode 230 is directly electrically connected to the drain electrode 176.

在一些實施例中，藉由第三導電層190的設置可以提升畫素結構的製程穩定性，舉例來說，藉由連接電極196的設置，畫素電極230不用直接與汲極176接觸就能夠電性連接至汲極176，也就是說不需要形成同時貫穿第二絕緣層180與平坦層200的開口就可以使畫素電極230電性連接至汲極176，藉此提升製程的良率。 In some embodiments, the processing stability of the pixel structure can be improved by the arrangement of the third conductive layer 190. For example, by the arrangement of the connecting electrode 196, the pixel electrode 230 can be able to be directly contacted without directly contacting the drain electrode 176. It is electrically connected to the drain electrode 176, that is, it is not necessary to form an opening that penetrates the second insulating layer 180 and the flat layer 200 at the same time to make the pixel electrode 230 electrically connected to the drain electrode 176, thereby improving the yield of the process.

在本實施例中，每個共用電極210重疊於多個畫素電極230，畫素電極230相較於共用電極210更遠離基板100，且每個畫素電極230具有重疊於共用電極210的多個狹縫st。在其他實施例中，共用電極210相較於畫素電極230更遠離基板100，且共用電極210具有重疊於畫素電極230的多個狹縫st。畫素電極230與共用電極210的材料包括透明導電材料，例如是銦錫氧化物、銦鋅氧化物、鋁錫氧化物、鋁鋅氧化物、銦鍺鋅氧化物、或其它合適的氧化物、或者是上述至少二者之堆疊層。在其他實施例中，顯示面板為反射式顯示面板，且畫素電極230與共用電極210的材料包括具有高反射率的金屬材料。 In this embodiment, each common electrode 210 overlaps a plurality of pixel electrodes 230, and the pixel electrode 230 is farther away from the substrate 100 than the common electrode 210, and each pixel electrode 230 has a large amount of overlap with the common electrode 210. A slit st. In other embodiments, the common electrode 210 is farther away from the substrate 100 than the pixel electrode 230, and the common electrode 210 has a plurality of slits st overlapping the pixel electrode 230. The material of the pixel electrode 230 and the common electrode 210 includes a transparent conductive material, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, or other suitable oxides, Or a stacked layer of at least two of the above. In other embodiments, the display panel is a reflective display panel, and the material of the pixel electrode 230 and the common electrode 210 includes a metal material with high reflectivity.

在一些實施例中，第一觸控訊號線194a以及第二觸控訊號線194b電性連接至對應的共用電極210，並用於傳遞或接收共用電極210上的觸控訊號。舉例來說，共用電極210透過貫穿平坦層200的開口(未繪出)而電性連接至對應的第一觸控訊號線194a或第二觸控訊號線194b。在一些實施例中，每個共用電極210電性連接至多個第一觸控訊號線194a及/或多個第二觸控訊號線 194b。 In some embodiments, the first touch signal line 194a and the second touch signal line 194b are electrically connected to the corresponding common electrode 210, and are used to transmit or receive the touch signal on the common electrode 210. For example, the common electrode 210 is electrically connected to the corresponding first touch signal line 194a or the second touch signal line 194b through an opening (not shown) penetrating the planarization layer 200. In some embodiments, each common electrode 210 is electrically connected to a plurality of first touch signal lines 194a and/or a plurality of second touch signal lines 194b.

在一些實施例中，顯示面板10還包括對向基板(未繪出)，基板100與對向基板之間夾有液晶層。畫素電極230與共用電極210之間的電場可以控制液晶分子的轉動。 In some embodiments, the display panel 10 further includes a counter substrate (not shown), and a liquid crystal layer is sandwiched between the substrate 100 and the counter substrate. The electric field between the pixel electrode 230 and the common electrode 210 can control the rotation of the liquid crystal molecules.

基於上述，第一連接電極178a連接至第一掃描線152，且第二掃描線192連接至第一連接電極178a，藉此能降低顯示面板的掃描線的電阻值。 Based on the above, the first connection electrode 178a is connected to the first scan line 152, and the second scan line 192 is connected to the first connection electrode 178a, thereby reducing the resistance value of the scan line of the display panel.

圖4是依照本發明的一實施例的一種顯示面板的上視示意圖。在此必須說明的是，圖4的實施例沿用圖1A至圖3C的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 FIG. 4 is a schematic top view of a display panel according to an embodiment of the invention. It must be noted here that the embodiment of FIG. 4 uses the element numbers and part of the content of the embodiment of FIGS. 1A to 3C, wherein the same or similar reference numbers are used to represent the same or similar elements, and the same technical content is omitted. Description. For the description of the omitted parts, reference may be made to the foregoing embodiment, which will not be repeated here.

請參考圖4，圖4的顯示面板20與圖1E的顯示面板10的差異在於顯示面板20，顯示面板20的半導體層130的形狀類似U形，但本發明不以此為限。在其他實施例中，半導體層130為其他幾何形狀。 Please refer to FIG. 4, the difference between the display panel 20 of FIG. 4 and the display panel 10 of FIG. 1E lies in the display panel 20. The shape of the semiconductor layer 130 of the display panel 20 is similar to a U shape, but the present invention is not limited thereto. In other embodiments, the semiconductor layer 130 has other geometric shapes.

在本實施例中，第二掃描線192透過第二絕緣層的第二開口H2而連接至第一連接電極178a。藉由第一連接電極178a的設置，第二掃描線192電性連接至第一掃描線152(重疊於第二掃描線192)，並改善掃描線的電阻值過大的問題。 In this embodiment, the second scan line 192 is connected to the first connection electrode 178a through the second opening H2 of the second insulating layer. With the arrangement of the first connection electrode 178a, the second scan line 192 is electrically connected to the first scan line 152 (overlaps the second scan line 192), and the problem of excessive resistance of the scan line is improved.

在本實施例中，第一觸控訊號線194a透過貫穿第二絕緣層的第三開口H3而連接至第二連接電極178b。第二觸控訊號線 194b透過貫穿第二絕緣層的第四開口H4而連接至第二連接電極178b。第一觸控訊號線194a透過第二連接電極178b而電性連接至第二觸控訊號線194b，因此，第一觸控訊號線194a以及第二觸控訊號線194b不會與第二掃描線192短路。 In this embodiment, the first touch signal line 194a is connected to the second connection electrode 178b through the third opening H3 penetrating the second insulating layer. The second touch signal line 194b is connected to the second connection electrode 178b through the fourth opening H4 penetrating the second insulating layer. The first touch signal line 194a is electrically connected to the second touch signal line 194b through the second connection electrode 178b. Therefore, the first touch signal line 194a and the second touch signal line 194b are not connected to the second scan line 192 short circuit.

圖5是依照本發明的一實施例的一種顯示面板的上視示意圖。在此必須說明的是，圖5的實施例沿用圖4的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 FIG. 5 is a schematic top view of a display panel according to an embodiment of the invention. It must be noted here that the embodiment of FIG. 5 uses the element numbers and part of the content of the embodiment of FIG. 4, wherein the same or similar reference numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiment, which will not be repeated here.

圖5的顯示面板30與圖4的顯示面板20的差異在於顯示面板30的第一觸控訊號線194a及第二觸控訊號線194b重疊於資料線172，藉此節省佈線空間。 The difference between the display panel 30 of FIG. 5 and the display panel 20 of FIG. 4 is that the first touch signal line 194a and the second touch signal line 194b of the display panel 30 overlap the data line 172, thereby saving wiring space.

在本實施例中，資料線172位於第二連接電極178b以及汲極176之間。第一觸控訊號線194a在靠近第二掃描線192處具有沿著延伸方向E1的分支部194a-1，分支部194a-1重疊於第三開口H3。第二觸控訊號線194b在靠近第二掃描線192處具有沿著延伸方向E1的分支部194b-1，分支部194b-1重疊於第四開口H4。第二掃描線192位於分支部194a-1與分支部194b-1之間。 In this embodiment, the data line 172 is located between the second connection electrode 178b and the drain electrode 176. The first touch signal line 194a has a branch portion 194a-1 along the extension direction E1 near the second scan line 192, and the branch portion 194a-1 overlaps the third opening H3. The second touch signal line 194b has a branch portion 194b-1 along the extension direction E1 near the second scan line 192, and the branch portion 194b-1 overlaps the fourth opening H4. The second scan line 192 is located between the branch portion 194a-1 and the branch portion 194b-1.

綜上所述，第一連接電極連接至第一掃描線，且第二掃描線連接至第一連接電極，藉此能降低顯示面板的掃描線的電阻值。 In summary, the first connection electrode is connected to the first scan line, and the second scan line is connected to the first connection electrode, thereby reducing the resistance of the scan line of the display panel.

10:顯示面板 10: Display panel

172:資料線 172: Data Line

178a:第一連接電極 178a: first connecting electrode

178b:第二連接電極 178b: second connecting electrode

192:第二掃描線 192: second scan line

194a:第一觸控訊號線 194a: The first touch signal line

194b:第二觸控訊號線 194b: The second touch signal line

196:連接電極 196: Connect the electrodes

210:共用電極 210: Common electrode

230:畫素電極 230: pixel electrode

H1:第一開口 H1: First opening

H2:第二開口 H2: second opening

H3:第三開口 H3: Third opening

H4:第四開口 H4: Fourth opening

O3:開口 O3: opening

st:狹縫 st: slit

Claims (11)

一種顯示面板，包括： 一半導體層，位於一基板上； 一閘極絕緣層，位於該半導體層上； 一第一導電層，位於該閘極絕緣層上，且包括： 一第一掃描線；以及 一閘極，連接該第一掃描線，且重疊於該半導體層； 一第一絕緣層，位於該第一導電層上； 一第二導電層，位於該第一絕緣層上，且包括： 一資料線； 一源極以及一汲極，分別電性連接該半導體層，且該源極連接該資料線；以及 一第一連接電極，重疊於該第一掃描線； 一第二絕緣層，位於該第二導電層上； 一第三導電層，位於該第二絕緣層上，且包括： 一第二掃描線，該第一連接電極透過貫穿該第一絕緣層的一第一開口而連接至該第一掃描線，且該第二掃描線透過貫穿該第二絕緣層的一第二開口而連接至該第一連接電極。 A display panel including: A semiconductor layer on a substrate; A gate insulating layer located on the semiconductor layer; A first conductive layer is located on the gate insulating layer and includes: A first scan line; and A gate connected to the first scan line and overlapped with the semiconductor layer; A first insulating layer on the first conductive layer; A second conductive layer is located on the first insulating layer and includes: A data line; A source electrode and a drain electrode are respectively electrically connected to the semiconductor layer, and the source electrode is connected to the data line; and A first connection electrode overlapping the first scan line; A second insulating layer on the second conductive layer; A third conductive layer is located on the second insulating layer and includes: A second scan line, the first connection electrode is connected to the first scan line through a first opening penetrating the first insulating layer, and the second scan line is penetrating a second opening penetrating the second insulating layer And connected to the first connection electrode. 如請求項1所述的顯示面板，其中該第二導電層更包括分離於該第一連接電極的一第二連接電極，且該第三導電層更包括： 一第一觸控訊號線以及一第二觸控訊號線，分別位於該第二掃描線的兩側，且該第一觸控訊號線透過該第二連接電極而電性連接至該第二觸控訊號線。 The display panel according to claim 1, wherein the second conductive layer further includes a second connection electrode separated from the first connection electrode, and the third conductive layer further includes: A first touch signal line and a second touch signal line are respectively located on both sides of the second scan line, and the first touch signal line is electrically connected to the second contact through the second connecting electrode Control signal line. 如請求項2所述的顯示面板，其中該第一觸控訊號線以及該第二觸控訊號線重疊於該資料線。The display panel according to claim 2, wherein the first touch signal line and the second touch signal line overlap the data line. 如請求項2所述的顯示面板，其中該第一觸控訊號線透過貫穿該第二絕緣層的一第三開口而連接至該第二連接電極，且該第二觸控訊號線透過貫穿該第二絕緣層的一第四開口而連接至該第二連接電極。The display panel according to claim 2, wherein the first touch signal line is connected to the second connection electrode through a third opening penetrating the second insulating layer, and the second touch signal line is penetrating through the second connection electrode A fourth opening of the second insulating layer is connected to the second connection electrode. 如請求項2所述的顯示面板，其中該第一觸控訊號線部分重疊於該閘極以及該半導體層。The display panel according to claim 2, wherein the first touch signal line partially overlaps the gate electrode and the semiconductor layer. 如請求項1所述的顯示面板，其中該第一導電層的材料不同於該第三導電層的材料，且該第二掃描線的電阻值小於該第一掃描線的電阻值。The display panel according to claim 1, wherein the material of the first conductive layer is different from the material of the third conductive layer, and the resistance value of the second scan line is smaller than the resistance value of the first scan line. 如請求項1所述的顯示面板，其中該第二導電層的材料與該第三導電層的材料相同。The display panel according to claim 1, wherein the material of the second conductive layer is the same as the material of the third conductive layer. 如請求項1所述的顯示面板，其中部分該資料線位於該第二掃描線與該第一掃描線之間。The display panel according to claim 1, wherein part of the data line is located between the second scan line and the first scan line. 一種顯示面板的製造方法，包括： 形成一半導體層於一基板上； 形成一閘極絕緣層於該半導體層上； 形成一第一導電層於該閘極絕緣層上，且該第一導電層包括： 一第一掃描線；以及 一閘極，連接該第一掃描線，且重疊於該半導體層； 形成一第一絕緣層於該第一導電層上，該第一絕緣層具有重疊於該第一掃描線的一第一開口； 形成一第二導電層於該第一絕緣層上，且該第二導電層包括： 一資料線； 一源極以及一汲極，分別電性連接該半導體層，且該源極連接該資料線；以及 一第一連接電極，重疊於該第一掃描線，且透過該第一開口而連接至該第一掃描線； 形成一第二絕緣層於該第二導電層上，該第二絕緣層具有重疊於該第一連接電極的一第二開口； 形成一第三導電層於該第二絕緣層上，且該第三導電層包括： 一第二掃描線，透過該第二開口而連接至該第一連接電極。 A method for manufacturing a display panel includes: Forming a semiconductor layer on a substrate; Forming a gate insulating layer on the semiconductor layer; A first conductive layer is formed on the gate insulating layer, and the first conductive layer includes: A first scan line; and A gate connected to the first scan line and overlapped with the semiconductor layer; Forming a first insulating layer on the first conductive layer, the first insulating layer having a first opening overlapping the first scan line; A second conductive layer is formed on the first insulating layer, and the second conductive layer includes: A data line; A source electrode and a drain electrode are respectively electrically connected to the semiconductor layer, and the source electrode is connected to the data line; and A first connection electrode overlapping the first scan line and connected to the first scan line through the first opening; Forming a second insulating layer on the second conductive layer, the second insulating layer having a second opening overlapping the first connecting electrode; A third conductive layer is formed on the second insulating layer, and the third conductive layer includes: A second scan line is connected to the first connection electrode through the second opening. 如請求項9所述的顯示面板的製造方法，更包括： 形成一第一絕緣材料層於該第一導電層上； 加熱該第一絕緣材料層，使該第一絕緣材料層中的氫離子擴散至該半導體層；以及 圖案化該第一絕緣材料層以形成該第一絕緣層。 The manufacturing method of the display panel as described in claim 9 further includes: Forming a first insulating material layer on the first conductive layer; Heating the first insulating material layer to diffuse hydrogen ions in the first insulating material layer to the semiconductor layer; and The first insulating material layer is patterned to form the first insulating layer. 如請求項9所述的顯示面板的製造方法，其中該第二導電層更包括分離於該第一連接電極的一第二連接電極，且該第三導電層更包括： 一第一觸控訊號線以及一第二觸控訊號線，分別位於該第二掃描線的兩側，且該第一觸控訊號線透過該第二連接電極而電性連接至該第二觸控訊號線。 The method for manufacturing a display panel according to claim 9, wherein the second conductive layer further includes a second connection electrode separated from the first connection electrode, and the third conductive layer further includes: A first touch signal line and a second touch signal line are respectively located on both sides of the second scan line, and the first touch signal line is electrically connected to the second contact through the second connecting electrode Control signal line.
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