TWI731844B - Layered body - Google Patents
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- TWI731844B TWI731844B TW104137226A TW104137226A TWI731844B TW I731844 B TWI731844 B TW I731844B TW 104137226 A TW104137226 A TW 104137226A TW 104137226 A TW104137226 A TW 104137226A TW I731844 B TWI731844 B TW I731844B
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- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 164
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 164
- 229910004298 SiO 2 Inorganic materials 0.000 claims abstract description 74
- 229910052751 metal Inorganic materials 0.000 claims description 143
- 239000002184 metal Substances 0.000 claims description 143
- 229910052719 titanium Inorganic materials 0.000 claims description 21
- 229910052738 indium Inorganic materials 0.000 claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- 229910052718 tin Inorganic materials 0.000 claims description 9
- 229910052733 gallium Inorganic materials 0.000 claims description 8
- 229910052732 germanium Inorganic materials 0.000 claims description 8
- 229910052725 zinc Inorganic materials 0.000 claims description 8
- 229910052684 Cerium Inorganic materials 0.000 claims description 7
- 229910052779 Neodymium Inorganic materials 0.000 claims description 7
- 229910052772 Samarium Inorganic materials 0.000 claims description 6
- 229910052727 yttrium Inorganic materials 0.000 claims description 6
- 239000010408 film Substances 0.000 description 119
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- 238000010586 diagram Methods 0.000 description 24
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- 239000010931 gold Substances 0.000 description 20
- 238000000137 annealing Methods 0.000 description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
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- 239000000463 material Substances 0.000 description 17
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- 229910052760 oxygen Inorganic materials 0.000 description 13
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- 239000011787 zinc oxide Substances 0.000 description 4
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- 239000007769 metal material Substances 0.000 description 2
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- 229910052758 niobium Inorganic materials 0.000 description 2
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- 241001175904 Labeo bata Species 0.000 description 1
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 125000005843 halogen group Chemical group 0.000 description 1
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- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
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- AHLBNYSZXLDEJQ-FWEHEUNISA-N orlistat Chemical compound CCCCCCCCCCC[C@H](OC(=O)[C@H](CC(C)C)NC=O)C[C@@H]1OC(=O)[C@H]1CCCCCC AHLBNYSZXLDEJQ-FWEHEUNISA-N 0.000 description 1
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- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 1
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- 229910052594 sapphire Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Laminated Bodies (AREA)
Abstract
本發明係一種積層體，其包含Si層及金屬氧化物層，且上述Si層之上述金屬氧化物層側之面上之SiO2層的膜厚為0.0nm~15.0nm。 The present invention is a laminated body comprising a Si layer and a metal oxide layer, and the thickness of the SiO 2 layer on the surface of the Si layer on the side of the metal oxide layer is 0.0 nm to 15.0 nm.
Description
本發明係關於一種積層體、包含其之元件、包含該元件之電路、電器機器及車輛。 The present invention relates to a laminated body, a component including the same, a circuit including the component, an electrical appliance, and a vehicle.
作為實現大電流、高耗電之肖特基勢壘二極體，揭示有使SiC或GaN於廉價之Si晶圓基板磊晶成長之例(例如專利文獻1~3)。 As a Schottky barrier diode that realizes high current and high power consumption, an example of epitaxial growth of SiC or GaN on an inexpensive Si wafer substrate is disclosed (for example, Patent Documents 1 to 3).
關於SiC，作為功率半導體較佳之結晶結構被視為4H-SiC，但由於晶格之失配較大，故而於Si上磊晶成長極為困難。若為3C-SiC，則可藉由對Si晶圓實施微細加工或使用Si(211)面而磊晶成長，但難以獲得可應用於功率裝置之程度之厚膜。 Regarding SiC, the crystal structure that is preferable as a power semiconductor is regarded as 4H-SiC, but due to the large mismatch of the crystal lattice, it is extremely difficult to grow epitaxially on Si. In the case of 3C-SiC, it is possible to perform epitaxial growth by micromachining Si wafers or using Si(211) planes, but it is difficult to obtain a thick film that can be applied to power devices.
另一方面，GaN雖於與Si晶格失配之方面未達SiC之程度，但若不介隔AlN等之緩衝層，則結晶成長較困難。晶格常數接近之藍寶石基板雖亦為有力候補，但無法使電流縱向流動，從而無法用於大電流用途。 On the other hand, although GaN is not as good as SiC in terms of lattice mismatch with Si, it is difficult to grow crystals without interposing a buffer layer such as AlN. Although a sapphire substrate with a close lattice constant is also a strong candidate, it cannot allow current to flow longitudinally, and thus cannot be used for high current applications.
因此，為了使用Si等之導電性基板，必須經由於基板上積層緩衝層進而使GaN結晶成長之步驟。然而，即便如此亦難以獲得完全之結晶。 Therefore, in order to use a conductive substrate such as Si, it is necessary to build a buffer layer on the substrate to grow GaN crystals. However, even so, it is difficult to obtain complete crystals.
專利文獻1：日本專利特開2009-164638號公報 Patent Document 1: Japanese Patent Laid-Open No. 2009-164638
專利文獻2：日本專利特開2010-40972號公報 Patent Document 2: Japanese Patent Laid-Open No. 2010-40972
專利文獻3：日本專利特開2013-227198號公報 Patent Document 3: Japanese Patent Laid-Open No. 2013-227198
本發明係鑒於此種問題而完成者，目的在於提供一種藉由將自然氧化膜控制於特定厚度以下且於其上形成帶隙較寬之金屬氧化物，從而發揮優異之電流-電壓特性的積層體。 The present invention has been completed in view of such problems, and its object is to provide a build-up layer that exhibits excellent current-voltage characteristics by controlling a natural oxide film below a specific thickness and forming a metal oxide with a wide band gap thereon. body.
根據本發明，提供以下之積層體等。 According to the present invention, the following laminate and the like are provided.
1.一種積層體，其包含Si層及金屬氧化物層，且上述Si層之上述金屬氧化物層側之面上之SiO2層的膜厚為0.0nm~15.0nm。 1. A layered body comprising a Si layer and a metal oxide layer, and the thickness of the SiO 2 layer on the side of the metal oxide layer of the Si layer is 0.0 nm to 15.0 nm.
2.如1所記載之積層體，其中於上述Si層與上述金屬氧化物層之間包含金屬含有層。 2. The laminate according to 1, wherein a metal-containing layer is included between the Si layer and the metal oxide layer.
3.如1或2所記載之積層體，其中上述金屬氧化物層為非晶質或微晶結構。 3. The laminate according to 1 or 2, wherein the metal oxide layer has an amorphous or microcrystalline structure.
4.如1至3中任一項所記載之積層體，其中上述金屬氧化物層之組成比(原子比)滿足下述式(1)~(3)，0≦x/(x+y+z)≦0.5 (1) 4. The laminate as described in any one of 1 to 3, wherein the composition ratio (atomic ratio) of the metal oxide layer satisfies the following formulas (1) to (3), 0≦x/(x+y+ z)≦0.5 (1)
0≦y/(x+y+z)≦0.8 (2) 0≦y/(x+y+z)≦0.8 (2)
0.2≦z/(x+y+z)≦1.0 (3) 0.2≦z/(x+y+z)≦1.0 (3)
(式中，x、y及z分別表示選自下述元素中之1種以上之原子數，x=In、Sn、Ge、Ti (In the formula, x, y and z respectively represent the number of atoms of one or more selected from the following elements, x=In, Sn, Ge, Ti
y=Zn、Y、Sm、Ce、Nd y=Zn, Y, Sm, Ce, Nd
z=Ga、Al)。 z=Ga, Al).
5.如1至4中任一項所記載之積層體，其中上述金屬氧化物層之載子濃度為1×1014cm-3~1×1017cm-3。 5. The laminate according to any one of 1 to 4, wherein the carrier concentration of the metal oxide layer is 1×10 14 cm -3 to 1×10 17 cm -3 .
6.如1至5中任一項所記載之積層體，其中上述Si層之功函數為3.9eV~5.0eV。 6. The laminate according to any one of 1 to 5, wherein the work function of the Si layer is 3.9 eV to 5.0 eV.
7.如2至6中任一項所記載之積層體，其中上述金屬含有層之功函 數為3.5eV~5.8eV。 7. The laminate as described in any one of 2 to 6, wherein the work function of the metal-containing layer The number is 3.5eV~5.8eV.
8.一種積層體，其包含金屬層及金屬氧化物層，上述金屬層包含與構成上述金屬氧化物層之金屬氧化物之金屬不同的金屬M，並且上述金屬層之上述金屬氧化物層側之面上之MxOy層(x及y分別為整數)的膜厚為0.0nm~15.0nm。 8. A laminated body comprising a metal layer and a metal oxide layer, the metal layer comprising a metal M different from the metal of the metal oxide constituting the metal oxide layer, and the metal layer is on the metal oxide layer side The film thickness of the M x O y layer (x and y are integers) on the surface is 0.0 nm to 15.0 nm.
9.如8所記載之積層體，其中上述金屬氧化物層之組成比(原子比)滿足下述式(1)~(3)，0≦x/(x+y+z)≦0.5 (1) 9. The laminate as described in 8, wherein the composition ratio (atomic ratio) of the metal oxide layer satisfies the following formulas (1)~(3), 0≦x/(x+y+z)≦0.5 (1 )
0≦y/(x+y+z)≦0.8 (2) 0≦y/(x+y+z)≦0.8 (2)
0.2≦z/(x+y+z)≦1.0 (3) 0.2≦z/(x+y+z)≦1.0 (3)
(式中，x、y及z分別表示選自下述元素中之1種以上之原子數，x=In、Sn、Ge、Ti (In the formula, x, y and z respectively represent the number of atoms of one or more selected from the following elements, x=In, Sn, Ge, Ti
y=Zn、Y、Sm、Ce、Nd y=Zn, Y, Sm, Ce, Nd
z=Ga、Al)。 z=Ga, Al).
10.一種元件，其包含如1至9中任一項所記載之積層體。 10. An element comprising the laminate as described in any one of 1 to 9.
11.如10所記載之元件，其具有非線性導電。 11. The device as described in 10, which has non-linear conductivity.
12.一種電路或感測器，其包含如10或11所記載之元件。 12. A circuit or sensor comprising the element described in 10 or 11.
13.一種電器機器或車輛，其包含如10或11所記載之元件。 13. An electrical machine or vehicle, which contains the element as described in 10 or 11.
根據本發明，可提供一種可發揮優異之電流-電壓特性之積層體。藉由將自然氧化膜控制於特定厚度以下且於其上形成帶隙較寬之金屬氧化物，可發揮優異之電流-電壓特性。進而，金屬氧化物由於可以廉價且量產性優異之方法形成，故而相較於先前可明顯提高生產性。 According to the present invention, it is possible to provide a laminate that can exhibit excellent current-voltage characteristics. By controlling the natural oxide film below a specific thickness and forming a metal oxide with a wide band gap thereon, excellent current-voltage characteristics can be exhibited. Furthermore, since the metal oxide can be formed by a method that is inexpensive and excellent in mass productivity, the productivity can be significantly improved compared to the prior art.
1:積層體 1: Layered body
2:積層體 2: Layered body
3:積層體 3: Layered body
4:積層體 4: Layered body
5:積層體 5: Laminated body
6:積層體 6: Laminated body
7:積層體 7: Laminated body
8:積層體 8: Laminated body
9:積層體 9: Laminated body
10:Si層 10: Si layer
101:積層體 101: layered body
10:支持基板 10: Support substrate
10:高摻雜n型矽晶圓 10: Highly doped n-type silicon wafer
11:積層體 11: Laminated body
12:金屬層 12: Metal layer
14:金屬層 14: Metal layer
20:SiO2層 20: SiO 2 layer
22:Mo之氧化物之層 22: Mo oxide layer
24:金屬之氧化物層 24: Metal oxide layer
25:金屬含有層 25: Metal containing layer
26:背面電極 26: back electrode
30:金屬氧化物層 30: metal oxide layer
30:n型金屬氧化物半導體 30: n-type metal oxide semiconductor
40:表面金屬層 40: Surface metal layer
50:保護膜 50: Protective film
60:保護環 60: Protective ring
70:p型半導體 70: p-type semiconductor
75:p型半導體或低載子濃度之n型半導體 75: p-type semiconductor or n-type semiconductor with low carrier concentration
80:閘極電極 80: gate electrode
90:源極電極 90: source electrode
100:汲極電極 100: Drain electrode
110:閘極絕緣膜 110: Gate insulating film
115:SiO2膜 115: SiO 2 film
120:p型Si(p區域) 120: p-type Si (p area)
130:n+區域 130: n+ area
131:電極端子 131: Electrode terminal
132:鋁線 132: Aluminum wire
133:金線 133: Gold thread
134:二極體 134: Diode
135:MOSFET 135: MOSFET
136:驅動器IC 136: Driver IC
137:模製樹脂 137: Molded resin
138:銅板 138: Copper Plate
139:絕緣散熱薄片 139: Insulation and heat dissipation sheet
140:散熱片 140: heat sink
141:FWD晶片 141: FWD chip
142:MOS FET晶片 142: MOS FET chip
143:氧化物半導體 143: oxide semiconductor
144:Si晶圓 144: Si wafer
145:背面金屬 145: back metal
146:焊料 146: Solder
圖1係表示本發明之積層體之一實施形態(Si層/SiO2層/金屬氧化 物層)的圖。 Fig. 1 is a diagram showing an embodiment (Si layer/SiO 2 layer/metal oxide layer) of the laminate of the present invention.
圖2係表示本發明之積層體之一實施形態(Si層/金屬氧化物層)的圖。 Fig. 2 is a diagram showing an embodiment (Si layer/metal oxide layer) of the laminate of the present invention.
圖3係表示本發明之積層體之一實施形態(Si層/SiO2層/中間金屬層(金屬含有層)/金屬氧化物層)的圖。 Fig. 3 is a diagram showing an embodiment (Si layer/SiO 2 layer/intermediate metal layer (metal containing layer)/metal oxide layer) of the laminate of the present invention.
圖4係表示本發明之積層體之一實施形態(Si層/中間金屬層/金屬氧化物層)的圖。 Fig. 4 is a diagram showing an embodiment (Si layer/intermediate metal layer/metal oxide layer) of the laminate of the present invention.
圖5係表示本發明之積層體之一實施形態(Si層/SiO2層/金屬氧化物層/上部金屬(表面金屬層))的圖。 Fig. 5 is a diagram showing an embodiment (Si layer/SiO 2 layer/metal oxide layer/upper metal (surface metal layer)) of the laminate of the present invention.
圖6係表示本發明之積層體之一實施形態(Si層/SiO2層/金屬氧化物層/上部金屬/保護膜)的圖。 Fig. 6 is a diagram showing an embodiment (Si layer/SiO 2 layer/metal oxide layer/upper metal/protective film) of the laminated body of the present invention.
圖7係表示本發明之積層體之一實施形態(Si層/SiO2層/金屬氧化物層(於上部電極側埋入保護環)/上部金屬/保護膜)的圖。 Fig. 7 is a diagram showing an embodiment of the laminate of the present invention (Si layer/SiO 2 layer/metal oxide layer (protection ring embedded on the upper electrode side)/upper metal/protective film).
圖8係表示本發明之積層體之一實施形態(Si層/SiO2層/金屬氧化物層(於下部電極側埋入保護環)/上部金屬/保護膜)的圖。 Fig. 8 is a diagram showing an embodiment of the laminate of the present invention (Si layer/SiO 2 layer/metal oxide layer (protection ring embedded on the lower electrode side)/upper metal/protective film).
圖9係表示本發明之積層體之一實施形態(MPS二極體)的圖。 Fig. 9 is a diagram showing an embodiment (MPS diode) of the laminate of the present invention.
圖10係表示本發明之積層體之一實施形態(金屬M層/MxOy層/金屬氧化物層(於上部電極側埋入保護環)/上部金屬/保護膜)的圖。 Fig. 10 is a diagram showing an embodiment of the laminate of the present invention (metal M layer/M x O y layer/metal oxide layer (protection ring embedded on the upper electrode side)/upper metal/protective film).
圖11係表示本發明之積層體之一實施形態(Si層/SiO2層/金屬M層/MxOy層/金屬氧化物層(於上部電極側埋入保護環)/上部金屬/保護膜)的圖。 Fig. 11 shows an embodiment of the laminate of the present invention (Si layer/SiO 2 layer/metal M layer/M x O y layer/metal oxide layer (protection ring is embedded on the upper electrode side)/upper metal/protection Film).
圖12係表示本發明之積層體之製造方法之一實施形態的圖。 Fig. 12 is a diagram showing an embodiment of a method for manufacturing a laminate of the present invention.
圖13係表示本發明之積層體之製造方法之一實施形態的圖。 Fig. 13 is a diagram showing an embodiment of a method for manufacturing a laminate of the present invention.
圖14係表示將本發明之積層體用於平面式閘極型功率MOSFET之情形時之一實施形態的圖。 FIG. 14 is a diagram showing an embodiment when the laminate of the present invention is used in a planar gate type power MOSFET.
圖15係表示將本發明之積層體用於溝槽式閘極型功率MOSFET之 情形時之一實施形態的圖。 Fig. 15 shows the application of the laminated body of the present invention to trench gate type power MOSFET A diagram of an embodiment of the situation.
圖16係表示於使用本發明之積層體之平面式閘極型功率MOSFET中漂移區域使用金屬氧化物、且通道區域使用多晶矽之情形時之一實施形態的圖。 16 is a diagram showing an embodiment in a case where metal oxide is used in the drift region and polysilicon is used in the channel region in the planar gate type power MOSFET using the laminate of the present invention.
圖17係表示將本發明之元件組合而構成之模組之一實施形態的圖。 Fig. 17 is a diagram showing an embodiment of a module constructed by combining the elements of the present invention.
圖18係表示於圖17之模組中二極體與MOSFET介隔背面金屬與焊料而連接於銅板且二極體之Si晶圓側與MOSFET之集電極連接之情形時之實施形態的圖。 18 is a diagram showing an embodiment when the diode and the MOSFET are connected to a copper plate via the back metal and solder in the module of FIG. 17 and the Si wafer side of the diode is connected to the collector of the MOSFET.
圖19係表示於圖17之模組中二極體與MOSFET介隔背面金屬與焊料而連接於銅板且二極體之氧化物半導體側與MOSFET之集電極連接之情形時之實施形態的圖。 19 is a diagram showing an embodiment when the diode and the MOSFET are connected to a copper plate via the back metal and solder in the module of FIG. 17 and the oxide semiconductor side of the diode is connected to the collector of the MOSFET.
圖20係於實施例1中獲得之9700nm之Ga2O3膜與實施例2中獲得之3700nm之Ga2O3膜的XRD樣式。 FIG 20 based on the Ga 9700nm obtained in Example 1 of Embodiment 2 O 3 film and 3700nm XRD pattern of the obtained in Example 2 Ga 2 O 3 film of the embodiment.
圖21係於實施例1中獲得之膜厚9700nm之Ga2O3膜之電子束繞射圖像。 FIG. 21 is an electron beam diffraction image of a Ga 2 O 3 film with a film thickness of 9700 nm obtained in Example 1. FIG.
圖22係於實施例1、7、8中獲得之積層體之Si層界面之SiO2部分的TEM像。 22 is a TEM image of the SiO 2 part of the Si layer interface of the laminate obtained in Examples 1, 7, and 8.
圖23係表示製造實施例15中製造之肖特基勢壘二極體之製程的圖。 FIG. 23 is a diagram showing the manufacturing process of the Schottky barrier diode manufactured in Example 15. FIG.
本發明之第1積層體包含Si層及氧化物金屬層。又，Si層之金屬氧化物層側之面上之SiO2層的膜厚為0.0nm~15.0nm。即，SiO2層可存在亦可不存在。 The first laminate of the present invention includes a Si layer and an oxide metal layer. In addition, the film thickness of the SiO 2 layer on the side of the metal oxide layer of the Si layer is 0.0 nm to 15.0 nm. That is, the SiO 2 layer may or may not exist.
本發明之第1積層體即便於廉價之Si基板上存在特定厚度之自然 氧化膜，亦可藉由於其上形成帶隙較寬之化合物半導體，而實現優異之電流-電壓特性。 The first laminate of the present invention has a certain thickness even on a cheap Si substrate. The oxide film can also achieve excellent current-voltage characteristics by forming a compound semiconductor with a wide band gap thereon.
本發明之第2積層體包含金屬層及金屬氧化物層。此處，金屬層包含與構成金屬氧化物層之金屬氧化物之金屬不同的金屬M。又，金屬層之金屬氧化物層側之面上之MxOy層(x及y分別為整數)的膜厚為0.0nm~15.0nm。MxOy層係包含金屬M之氧化物之層，該MxOy層可存在亦可不存在。 The second laminate of the present invention includes a metal layer and a metal oxide layer. Here, the metal layer includes a metal M different from the metal of the metal oxide constituting the metal oxide layer. In addition, the thickness of the M x O y layer (x and y are integers) on the surface of the metal oxide layer side of the metal layer is 0.0 nm to 15.0 nm. The M x O y layer is a layer containing metal M oxide, and the M x O y layer may or may not exist.
除了第1積層體之Si層為金屬M層以外，本發明之第2積層體與第1積層體相同，即便於金屬M層上存在特定厚度之自然氧化膜，亦可藉由於其上形成帶隙較寬之化合物半導體，而實現優異之電流-電壓特性。 Except that the Si layer of the first laminate is a metal M layer, the second laminate of the present invention is the same as the first laminate. Even if a natural oxide film of a specific thickness is present on the metal M layer, it can be formed by forming a band on it. Compound semiconductors with wider gaps can achieve excellent current-voltage characteristics.
以下，存在將本發明之第1積層體及本發明之第2積層體一併稱為本發明之積層體之情形。 Hereinafter, there are cases where the first laminate of the present invention and the second laminate of the present invention are collectively referred to as the laminate of the present invention.
將本發明之積層體之一實施形態示於圖1、2。 One embodiment of the laminate of the present invention is shown in Figs. 1 and 2.
積層體1表示本發明之積層體包含SiO2層之情形時之實施形態，於Si層10(基板)上存在SiO2層20，於其上形成有金屬氧化物層30。
The laminated body 1 represents an embodiment when the laminated body of the present invention includes an SiO 2 layer. The SiO 2 layer 20 is present on the Si layer 10 (substrate), and the
積層體2表示不包含SiO2層之情形時之實施形態，於Si層10(基板)上形成有金屬氧化物層30。
The
再者，圖1及圖2係對應於本發明之第1積層體之圖式，但亦可對應於本發明之第2積層體。具體而言，於圖1及2中，設為金屬M層代替Si層10，且設為MxOy層代替SiO2層20。下述圖3~9亦相同。
1 and 2 are diagrams corresponding to the first laminate of the present invention, but they may also correspond to the second laminate of the present invention. Specifically, in FIGS. 1 and 2, the
以下，對用於積層體之各層進行說明。 Hereinafter, each layer used in the laminate will be described.
(1-1)Si層 (1-1) Si layer
Si層並無特別限制，可使用矽晶圓，亦可使用藉由濺鍍法或CVD(chemical vapor deposition，化學氣相沈積)法於玻璃等適當之基材上將Si成膜而成者。又，亦可被摻雜。 The Si layer is not particularly limited. A silicon wafer may be used, or a film formed by forming Si on a suitable substrate such as glass by a sputtering method or a CVD (chemical vapor deposition) method may be used. Also, it can be doped.
矽晶圓可為單晶及多晶中之任一結構。關於製法，可使用丘克拉斯基法或浮動帶域法等，亦可直接使用先前公知之矽晶圓基板。 The silicon wafer can be of either single crystal or polycrystalline structure. Regarding the manufacturing method, the Chukraski method or the floating zone method can be used, or the previously known silicon wafer substrate can be used directly.
又，矽晶圓根據有無摻雜、及種類，存在n型、i型、p型，於使電流縱向流動方面，較佳為電阻較小之n型或p型。作為摻雜劑，可使用先前公知之B、P、Sb等。於欲特別降低電阻之情形時，亦可將As或紅磷作為摻雜劑。 In addition, silicon wafers may be n-type, i-type, and p-type depending on the presence or absence of doping and the type. In terms of allowing the current to flow vertically, the n-type or p-type with lower resistance is preferred. As the dopant, previously known B, P, Sb, etc. can be used. When it is desired to particularly reduce the resistance, As or red phosphorus can also be used as a dopant.
又，Si層之厚度並無限制，通常為200~1000μm，於欲降低縱向之電阻之情形時，亦可藉由CMP(chemical mechanical polishing，化學機械研磨)法等進行研磨。於基板之翹曲成為問題之情形時，可使用殘留有外周部之太鼓(TAIKO)型之構造。研磨可於積層金屬氧化物前進行亦可於其後進行。 In addition, the thickness of the Si layer is not limited, and is usually 200-1000 μm. When it is desired to reduce the resistance in the vertical direction, it can also be polished by a CMP (chemical mechanical polishing) method or the like. When the warpage of the substrate becomes a problem, a TAIKO type structure with a peripheral part remaining can be used. The polishing may be performed before or after the metal oxide is deposited.
Si層之功函數較佳為3.9eV~5.0eV，更佳為4.0eV~4.5eV。Si層之功函數係藉由大氣中光電子分光裝置(例如，Rikenkeiki AC-3)進行測定。 The work function of the Si layer is preferably 3.9 eV to 5.0 eV, more preferably 4.0 eV to 4.5 eV. The work function of the Si layer is measured by an atmospheric photoelectron spectrometer (for example, Rikenkeiki AC-3).
(1-2)金屬M層 (1-2) Metal M layer
構成金屬M層之金屬M只要為與構成金屬氧化物層之金屬氧化物之金屬不同的金屬，則無特別限定。金屬M例如只要為表面平滑性較高者即可，於積層於其上之金屬氧化物之膜厚超過1μm之情形時，較佳為接近金屬氧化物之線膨脹係數之材料。具體而言，金屬M較佳為線膨脹係數為4~10×10-6K-1之範圍之金屬，作為該金屬，可列舉選自Ti、Cr、Nb、Mo及Ta中之1種以上之金屬。本發明之基板所使用之氧化物之線膨脹係數例如為5×10-6~8×10-6K-1之範圍。因此，於藉由後續步驟之製程加熱之情形時，若線膨脹係數存在較大差異，則有產生翹曲之虞。具體而言，金屬氧化物層於金屬M之線膨脹係數小於4×10-6K-1時受到壓縮應力，於金屬M之線膨脹係數大於10×10-6K-1時受到拉伸應力。 The metal M constituting the metal M layer is not particularly limited as long as it is a metal different from the metal of the metal oxide constituting the metal oxide layer. For example, the metal M may have a relatively high surface smoothness. When the thickness of the metal oxide layered thereon exceeds 1 μm, it is preferably a material close to the linear expansion coefficient of the metal oxide. Specifically, the metal M is preferably a metal having a linear expansion coefficient in the range of 4 to 10×10 -6 K -1 . As the metal, one or more selected from Ti, Cr, Nb, Mo, and Ta Of metal. The linear expansion coefficient of the oxide used in the substrate of the present invention is, for example, in the range of 5×10 -6 to 8×10 -6 K -1 . Therefore, in the case of heating by a subsequent process, if there is a large difference in the coefficient of linear expansion, there is a risk of warping. Specifically, the metal oxide layer is subjected to compressive stress when the linear expansion coefficient of metal M is less than 4×10 -6 K -1 , and is subjected to tensile stress when the linear expansion coefficient of metal M is greater than 10×10 -6 K -1 .
但，於金屬M為低熔點之金屬、或反應性較高之金屬之情形時，有因積層體之製造步驟等而被污染之虞。作為此種金屬，可列舉Ga、Hg、Cs、K、Na等。 However, when the metal M is a metal with a low melting point or a metal with high reactivity, there is a risk of contamination due to the manufacturing steps of the laminate. Examples of such metals include Ga, Hg, Cs, K, Na, and the like.
金屬M與構成金屬氧化物層之金屬氧化物之金屬不同，此處，所謂「不同」意指金屬M與金屬氧化物層之金屬完全不同，例如於金屬氧化物層之金屬為包含2種以上之金屬之合金的情形時，金屬M與合金亦可部分一致。 The metal M is different from the metal of the metal oxide constituting the metal oxide layer. Here, the so-called "different" means that the metal of the metal M and the metal of the metal oxide layer are completely different. For example, the metal of the metal oxide layer contains two or more kinds of metals In the case of the alloy of the metal, the metal M and the alloy may be partially consistent.
(2-1)SiO2層 (2-1) SiO 2 layer
SiO2層之膜厚為0.0nm以上、15.0nm以下，較佳為0.0nm以上、8.0nm以下，更佳為0.0nm以上、4.0nm以下，進而較佳為0.0nm以上、2.5nm以下，尤佳為0.0nm以上、1.5nm以下。SiO2層之膜厚越薄越佳。 The thickness of the SiO 2 layer is 0.0 nm or more and 15.0 nm or less, preferably 0.0 nm or more and 8.0 nm or less, more preferably 0.0 nm or more and 4.0 nm or less, and still more preferably 0.0 nm or more and 2.5 nm or less, especially Preferably it is 0.0 nm or more and 1.5 nm or less. The film thickness of the SiO 2 layer is as thin as possible.
SiO2層之膜厚係藉由TEM(Transmission Electron Microscopy，穿透式電子顯微鏡)對其剖面進行測定。關於測定部位，於SiO2層為例如四邊形之情形時，觀察對角線之交點、及交點與各頂點之中間點共計5點之視野，於將該視野等間隔地10等分之部位進行測定，將該共計55個部位之平均值設為SiO2層之膜厚。 The film thickness of the SiO 2 layer was measured by TEM (Transmission Electron Microscopy, transmission electron microscope) for its cross-section. Regarding the measurement location, when the SiO 2 layer is a quadrilateral, for example, observe the intersection of the diagonals, and the midpoint between the intersection and each vertex, a total of 5 visual fields, and measure the visual field at 10 equal intervals. , The average value of the total of 55 locations is taken as the film thickness of the SiO 2 layer.
一般而言，於矽晶圓之表面存在自然氧化膜(SiO2)。因此，若於Si基板上積層金屬氧化物，則通常於Si層與金屬氧化物層之界面存在SiO2膜，但若SiO2膜之厚度超過15.0nm，則於使電流縱向流動之情形時該SiO2膜會作為明確之電阻成分起作用。為了將SiO2膜之厚度設為15.0nm以下，通常必須於積層金屬氧化物層前預先去除特定量之自然氧化膜。 Generally speaking, there is a natural oxide film (SiO 2 ) on the surface of the silicon wafer. Therefore, if a metal oxide is laminated on a Si substrate, there is usually a SiO 2 film at the interface between the Si layer and the metal oxide layer. However, if the thickness of the SiO 2 film exceeds 15.0 nm, this will be the case when the current flows vertically. The SiO 2 film will act as a clear resistance component. In order to set the thickness of the SiO 2 film to 15.0 nm or less, it is usually necessary to remove a certain amount of the natural oxide film in advance before laminating the metal oxide layer.
作為去除自然氧化膜(SiO2)之方法，可列舉逆向濺鍍、乾式蝕刻、減壓下或還原氣氛下之退火、浸漬於氫氟酸系溶劑之方法等。 As a method of removing the natural oxide film (SiO 2 ), a method of reverse sputtering, dry etching, annealing under reduced pressure or a reducing atmosphere, and immersion in a hydrofluoric acid solvent can be cited.
又，於使金屬氧化物層積層於Si層後，為了使電性接合變得確實 而進行退火處理之情形時，退火溫度較佳為設為300℃以下。若超過300℃進行退火，則存在金屬氧化物層之氧與Si發生反應而形成超過15.0nm之SiO2膜之情形。 Moreover, when an annealing treatment is performed to ensure the electrical bonding after the metal oxide layer is laminated on the Si layer, the annealing temperature is preferably set to 300° C. or less. If the annealing is performed at a temperature exceeding 300°C, oxygen in the metal oxide layer may react with Si to form a SiO 2 film exceeding 15.0 nm.
(2-2)MxOy層 (2-2) M x O y layer
與矽晶圓之情形相同，於金屬M層之表面存在自然氧化膜(MxOy)，而必須於積層金屬氧化物層前，預先去除特定量之自然氧化膜。 As in the case of silicon wafers, there is a natural oxide film (M x O y ) on the surface of the metal M layer, and a certain amount of the natural oxide film must be removed in advance before the metal oxide layer is laminated.
自然氧化膜之厚度、去除方法、積層金屬氧化物層後之退火處理等係與SiO2層之情形相同。 The thickness of the natural oxide film, the removal method, and the annealing treatment after laminating the metal oxide layer are the same as those of the SiO 2 layer.
(3)金屬含有層 (3) Metal containing layer
於本發明之積層體中，亦可於Si層與金屬氧化物層之間設置金屬含有層。若如此，則更容易將SiO2層之厚度控制於0.0nm以上、15.0nm以下。與Si層及金屬氧化物層之情形相同，亦可於金屬M層與金屬氧化物層之間設置金屬含有層。更容易將MxOy層之厚度控制於0.0nm以上、15.0nm以下。 In the laminate of the present invention, a metal-containing layer may be provided between the Si layer and the metal oxide layer. If so, it is easier to control the thickness of the SiO 2 layer to 0.0 nm or more and 15.0 nm or less. As in the case of the Si layer and the metal oxide layer, a metal containing layer may also be provided between the metal M layer and the metal oxide layer. It is easier to control the thickness of the M x O y layer above 0.0 nm and below 15.0 nm.
金屬含有層之厚度通常為5~100nm。 The thickness of the metal-containing layer is usually 5-100 nm.
將設置有金屬含有層之積層體之實施形態示於圖3、4。 The embodiment of the laminate provided with the metal-containing layer is shown in FIGS. 3 and 4.
於積層體3中，於Si層10上存在SiO2層20，於SiO2層20上形成有金屬含有層25，於金屬含有層25上形成有金屬氧化物層30。
In the
於積層體4中，於Si層10上形成有金屬含有層25，於金屬含有層25上形成有金屬氧化物層30。
In the
用於金屬含有層之材料只要有導電性則無特別限制。此處，根據與金屬氧化物層進行肖特基連接、亦或歐姆連接，適合之材料有所不同，故而以下進行說明。 The material used for the metal-containing layer is not particularly limited as long as it has conductivity. Here, depending on the Schottky connection or the ohmic connection with the metal oxide layer, suitable materials are different, so the following description will be given.
(3-1)使金屬含有層與金屬氧化物層進行肖特基連接之情形 (3-1) The case of Schottky connection between the metal-containing layer and the metal oxide layer
於與金屬氧化物層進行肖特基連接時，較佳為功函數為4.2eV~ 5.8eV左右之金屬材料，更佳為4.4eV~5.6eV之金屬材料。具體可列舉Pt、Au、Ag、Cr、Cu、Mo、Ti、W、Ni、Pd、Ru等。於因單質而於密接性或耐久性存在問題之情形時，亦可視需要使用先前公知之合金。例如，AgPdCu、AgNd、AgCe、MoW、MoTa、MoNi等為高功函數且耐久性優異之合金材料。又，並不限於金屬，ITO、ZnO、SnO、IZO(註冊商標)等氧化物導電體薄膜作為高功函數電極亦優異。進而，若以5nm以下且與金屬氧化物接觸而形成PbO、PtO、MoO3、TiO2等氧化物介電體薄膜，則可不提高順向之接通電阻而實現良好之肖特基能障。 When performing Schottky connection with the metal oxide layer, it is preferably a metal material with a work function of about 4.2 eV to 5.8 eV, and more preferably a metal material with a work function of 4.4 eV to 5.6 eV. Specific examples include Pt, Au, Ag, Cr, Cu, Mo, Ti, W, Ni, Pd, Ru, and the like. When there is a problem in adhesion or durability due to simple substance, a previously known alloy can also be used as needed. For example, AgPdCu, AgNd, AgCe, MoW, MoTa, MoNi, etc. are alloy materials with high work function and excellent durability. Moreover, it is not limited to metals, and oxide conductor films such as ITO, ZnO, SnO, and IZO (registered trademark) are also excellent as high work function electrodes. Furthermore, if oxide dielectric films such as PbO, PtO, MoO 3 , and TiO 2 are formed in contact with metal oxides with a thickness of 5 nm or less, a good Schottky barrier can be achieved without increasing the on-resistance in the forward direction.
(3-2)使金屬含有層與金屬氧化物層進行歐姆連接之情形 (3-2) The case of ohmic connection between the metal-containing layer and the metal oxide layer
另一方面，為了對金屬氧化物獲得歐姆特性，功函數通常為3.5~4.3eV，較佳為3.5~4.2eV左右之金屬材料，更佳為3.6eV~4.1eV之金屬材料。例如，可列舉Hf、In、Mg、Zn、Ti、Al等金屬、TiN、MgAg、AlLi等合金材料。於功函數低於3.5eV之情形時，存在多數情況下缺少穩定性而必須注意之情形。若功函數超過4.2eV，則有阻礙對金屬氧化物層之電子注入而容易發生肖特基接合之虞。又，Ti由於密接性較佳，故而同樣作為電子注入金屬較佳。若除上述以外，使用In或Zn作為金屬含有層，則即便因加熱而與金屬氧化物中之氧發生反應亦保持導電性，故而作為歐姆電極較佳。因同樣之理由，ITO、ZnO、SnO、IZO(註冊商標)等氧化物導電體薄膜亦可保持導電性，故而作為歐姆電極較佳。但，氧化物導電體薄膜之功函數多數情形時為4.4eV以上，故而較佳為電性積層之氧化物半導體之費米能階亦與其接近之材料。具體而言，構成氧化物半導體之材料組成較佳為以In2O3、ZnO、SnO2為主成分。若將帶隙較寬之Ga2O3或Al2O3等氧化物材料相對於構成氧化物半導體之金屬比抑制於20~50%，則容易與上述氧化物導電體薄膜歐姆接合。 On the other hand, in order to obtain ohmic characteristics for metal oxides, the work function is usually 3.5 to 4.3 eV, preferably about 3.5 to 4.2 eV, and more preferably 3.6 eV to 4.1 eV. For example, metals such as Hf, In, Mg, Zn, Ti, and Al, and alloy materials such as TiN, MgAg, and AlLi can be cited. When the work function is lower than 3.5 eV, there are situations where stability is lacking in most cases and attention must be paid. If the work function exceeds 4.2 eV, electron injection into the metal oxide layer may be hindered, and Schottky bonding may easily occur. In addition, Ti is also suitable as an electron injection metal because of its good adhesion. In addition to the above, if In or Zn is used as the metal-containing layer, conductivity is maintained even if it reacts with oxygen in the metal oxide due to heating, so it is preferable as an ohmic electrode. For the same reason, oxide conductor films such as ITO, ZnO, SnO, IZO (registered trademark), etc. can also maintain conductivity, so they are preferable as ohmic electrodes. However, the work function of the oxide conductive thin film is 4.4 eV or more in most cases, so it is preferable that the fermi level of the oxide semiconductor of the electrical build-up layer is also close to it. Specifically, the composition of the material constituting the oxide semiconductor is preferably In 2 O 3 , ZnO, and SnO 2 as main components. If the ratio of oxide materials such as Ga 2 O 3 or Al 2 O 3 with a wide band gap to the metal constituting the oxide semiconductor is suppressed to 20 to 50%, it is easy to ohmically bond with the above-mentioned oxide conductor thin film.
若於金屬氧化物層之上積層歐姆電極，則可獲得具有良好之整流特性之二極體。 If an ohmic electrode is laminated on the metal oxide layer, a diode with good rectification characteristics can be obtained.
再者，電極之功函數係表示電子注入之容易程度之重要之指標，但與金屬氧化物層之密接性亦較重要。上述金屬若單獨使用則存在引起遷移或氧化之情形。例如，若使用Al，則容易產生小凸起等不良情況，故而可藉由Nd或Ce等先前公知之添加金屬而防止上述不良情況。又，若對Al混入微量之Li則可大幅度降低功函數，而作為本發明之寬能隙金屬氧化物之電子注入金屬較佳。 Furthermore, the work function of the electrode is an important indicator of the ease of electron injection, but the adhesion to the metal oxide layer is also more important. If the above-mentioned metals are used alone, they may cause migration or oxidation. For example, if Al is used, defects such as small bumps are likely to occur. Therefore, the aforementioned defects can be prevented by previously known added metals such as Nd or Ce. In addition, if a small amount of Li is mixed into Al, the work function can be greatly reduced, and it is preferable as the electron injection metal of the wide band gap metal oxide of the present invention.
功函數係使用大氣中光電子分光裝置(例如，Rikenkeiki製之AC-3)進行測定。 The work function is measured using an atmospheric photoelectron spectrometer (for example, AC-3 manufactured by Rikenkeiki).
於使金屬含有層與金屬氧化物層進行歐姆接合之情形時，金屬氧化物不與矽或金屬M直接接觸，故而退火溫度亦可超過300℃。但，根據金屬含有層之金屬種類之不同，會因加熱而產生凹凸從而導致絕緣破壞電場降低，故而退火溫度根據材料而適當選擇。 In the case of ohmic bonding between the metal-containing layer and the metal oxide layer, the metal oxide does not directly contact silicon or metal M, so the annealing temperature can also exceed 300°C. However, depending on the type of metal of the metal-containing layer, unevenness will be generated due to heating, resulting in a decrease in the insulation breakdown electric field, so the annealing temperature is appropriately selected according to the material.
(4)金屬氧化物層 (4) Metal oxide layer
金屬氧化物層係包含1種或2種以上之金屬氧化物之層。作為金屬氧化物，可列舉In、Sn、Ge、Ti、Zn、Y、Sm、Ce、Nd、Ga或Al之氧化物等。 The metal oxide layer is a layer containing one or more metal oxides. Examples of metal oxides include In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, or Al oxides.
(4-1)原子組成 (4-1) Atomic composition
構成金屬氧化物層之金屬氧化物若滿足下述式(1)~(3)之原子比則較佳。若為此種組成，則可成為高耐壓、低接通(On)電阻。 It is preferable that the metal oxide constituting the metal oxide layer satisfies the atomic ratio of the following formulas (1) to (3). With such a composition, it can become a high withstand voltage and low on-resistance.
0≦x/(x+y+z)≦0.5 (1) 0≦x/(x+y+z)≦0.5 (1)
0≦y/(x+y+z)≦0.8 (2) 0≦y/(x+y+z)≦0.8 (2)
0.2≦z/(x+y+z)≦1.0 (3) 0.2≦z/(x+y+z)≦1.0 (3)
(式中，x、y及z分別表示選自下述元素中之1種以上之原子數。 (In the formula, x, y, and z each represent the number of atoms of one or more selected from the following elements.
x=In、Sn、Ge、Ti x=In, Sn, Ge, Ti
y=Zn、Y、Sm、Ce、Nd y=Zn, Y, Sm, Ce, Nd
z=Ga、Al) z=Ga, Al)
若z低於0.2，則金屬氧化物中之氧容易脫離，而成為電氣特性變動之原因。若x之濃度超過0.5，則於x為In或Sn之情形時，有金屬氧化物之絕緣性變低而難以獲得肖特基接合之虞。於x為Ge或Ti之情形時，有金屬氧化物之絕緣性變高而成為因歐姆損耗導致發熱之原因之虞。 If z is less than 0.2, oxygen in the metal oxide is easily desorbed, which causes changes in electrical characteristics. If the concentration of x exceeds 0.5, when x is In or Sn, the insulating properties of the metal oxide may become low and it may be difficult to obtain Schottky bonding. When x is Ge or Ti, the insulation of the metal oxide may increase, which may cause heat generation due to ohmic loss.
金屬氧化物之組成係藉由ICP(Inductively Coupled Plasma，感應耦合電漿)發光分析裝置或XRF(X-ray Fluorescence Analysis，X射線螢光分析儀)或SIMS(Secondary Ion Mass Spectrometry，二次離子質譜儀)進行測定。 The composition of the metal oxide is achieved by ICP (Inductively Coupled Plasma) luminescence analysis device or XRF (X-ray Fluorescence Analysis) or SIMS (Secondary Ion Mass Spectrometry) Instrument) for measurement.
上述組成範圍(1)及(3)更佳為分別由下述式(1')及(3')表示。 The above composition ranges (1) and (3) are more preferably represented by the following formulas (1') and (3'), respectively.
0≦x/(x+y+z)≦0.25 (1') 0≦x/(x+y+z)≦0.25 (1')
0.3≦z/(x+y+z)≦1.0 (3') 0.3≦z/(x+y+z)≦1.0 (3')
(式中，x、y及z與上述相同)。 (In the formula, x, y and z are the same as above).
(4-2)結晶結構等 (4-2) Crystal structure, etc.
構成金屬氧化物層之金屬氧化物可為非晶質亦可為結晶質，結晶可為微晶亦可為單晶，但金屬氧化物較佳為非晶質或微晶結構。雖亦可為單晶，但若要使金屬氧化物成為單晶，則必須將晶種作為起點使結晶成長，或者使用MBE(分子束磊晶)或PLD(脈衝雷射沈積)等方法。若於SiO2表面或金屬表面上使結晶成長，則容易產生結晶缺陷，於用作使電流縱向流動之裝置時，有該結晶缺陷成為不良情況之原因之虞。於在SiO2表面或金屬表面上使結晶成長之情形時，必須適當調整加熱溫度、時間等，以免粒徑變得過大。 The metal oxide constituting the metal oxide layer may be amorphous or crystalline, and the crystal may be microcrystalline or single crystal, but the metal oxide preferably has an amorphous or microcrystalline structure. Although it may be a single crystal, if the metal oxide is to be a single crystal, a seed crystal must be used as a starting point to grow the crystal, or methods such as MBE (Molecular Beam Epitaxy) or PLD (Pulse Laser Deposition) must be used. If crystals are grown on the surface of SiO 2 or on the metal surface, crystal defects are likely to occur. When used as a device for making electric current flow in the longitudinal direction, the crystal defects may become a cause of failure. In the case of growing crystals on the surface of SiO 2 or metal, the heating temperature and time must be appropriately adjusted to prevent the particle size from becoming too large.
另一方面，若為非晶質，則即便存在懸鍵亦不會作為結晶缺陷而存在，故而可緩和電氣特性之變動或大幅度之特性劣化。進而，金 屬氧化物不同於Si半導體等之共價鍵結而離子鍵結性較強，故而由懸鍵產生之能階與導電帶或占滿帶接近。因此，與Si或SiC等相比，金屬氧化物因結構產生之遷移率等電氣特性之差異較小。若積極地利用金屬氧化物之此種性質，則即便單晶，亦可以較高之良率提供高耐壓且可靠性較高之大電流二極體或開關元件。 On the other hand, if it is amorphous, even if there are dangling bonds, it does not exist as a crystal defect, and therefore it is possible to alleviate changes in electrical characteristics or significant deterioration in characteristics. Furthermore, gold The genus oxide is different from the covalent bonding of Si semiconductors and the like and has stronger ionic bonding, so the energy level generated by the dangling bond is close to the conductive band or the full band. Therefore, compared with Si or SiC, the difference in electrical properties such as mobility due to the structure of metal oxides is relatively small. If such properties of metal oxides are actively used, even single crystals can provide high-withstand voltage and high-reliability high-current diodes or switching elements with high yield.
此處，所謂「非晶質」，於金屬氧化物層為例如四邊形之情形時，意指如下者：於藉由電子束繞射評價對角線之交點、及交點與各頂點之中間點共計5點之情形時，於將電子束繞射之光點大小設為膜厚之80%而獲得之繞射圖像無法確認明確之光點。又，「非晶質」亦包括存在局部經結晶化或微晶化之部分之情形。存在於對局部結晶化之部分照射電子束時確認出繞射圖像之情況。 Here, the term "amorphous" refers to the following when the metal oxide layer is a quadrilateral, for example, when evaluating the intersection of diagonal lines by electron beam diffraction, and the total of the intermediate points between the intersection and each vertex In the case of 5 o'clock, the diffraction image obtained by setting the size of the light spot diffracted by the electron beam to 80% of the film thickness cannot confirm the clear light spot. In addition, "amorphous" also includes the case where there is a part that is partially crystallized or microcrystallized. There are cases where a diffraction image is confirmed when an electron beam is irradiated to a partially crystallized part.
所謂「微晶結構」，意指結晶粒徑之尺寸為次微米以下而不存在明確之晶界者。 The so-called "microcrystalline structure" means that the size of the crystal grain size is sub-micron or less without clear grain boundaries.
所謂「多晶」，意指結晶粒徑之尺寸超過微米尺寸而存在明確之晶界者。 The so-called "polycrystalline" refers to those whose crystal grain size exceeds the micron size and there are clear grain boundaries.
例如，二極體所尋求之性質為高速切換或高耐壓、低接通電阻，若使用本發明之積層體則可兼具該等特性。其原因在於，本發明中所使用之金屬氧化物最初帶隙較寬且高耐壓。又，藉由氧缺陷容易成為n型而不易產生p型之情況亦適於高速切換。 For example, the properties sought by diodes are high-speed switching, high withstand voltage, and low on-resistance. If the laminate of the present invention is used, these properties can be combined. The reason is that the metal oxide used in the present invention has a wide initial band gap and high withstand voltage. In addition, it is also suitable for high-speed switching when the oxygen defect tends to become n-type but not p-type.
若要降低接通電阻則必須提高遷移率，故而只要使之結晶化即可，但較佳為止於不產生晶粒界之程度。於晶粒界經常存在空孔，於被施加電場時產生極化，而有該極化使耐壓性能降低之虞。於耐壓之降低較明顯之情形時，較佳為直接以非晶質狀態使用。於作為非晶質使用之情形時，雖亦取決於形成金屬氧化物層之元素之種類，但只要將加熱處理條件設定為例如200℃以下、1小時以內即可。藉由以200℃以下之低溫加熱，可獲得穩定之非晶質狀態。 If the on-resistance is to be lowered, the mobility must be increased, so it is only necessary to crystallize it, but it is preferably to the extent that no grain boundaries are formed. There are often pores in the crystal grain boundaries, and polarization occurs when an electric field is applied, and this polarization may reduce the withstand voltage performance. When the reduction in withstand voltage is obvious, it is better to use it directly in an amorphous state. When it is used as an amorphous substance, although it also depends on the type of element forming the metal oxide layer, it is only necessary to set the heat treatment conditions to, for example, 200° C. or less and within 1 hour. By heating at a low temperature below 200°C, a stable amorphous state can be obtained.
金屬氧化物層之室溫下之載子濃度較佳為1×1014cm-3~1×1017cm-3，更佳為2×1014cm-3~5×1016cm-3。若為該範圍，則可顯示良好之二極體特性。於載子濃度未達1×1014cm-3之情形時，接通電阻變得過高，從而於動作時導致發熱，故而欠佳。於載子濃度超過1×1017cm-3之情形時，有電阻變得過低，而逆向偏壓時之漏電流上升之虞。 The carrier concentration of the metal oxide layer at room temperature is preferably 1×10 14 cm -3 to 1×10 17 cm -3 , more preferably 2×10 14 cm -3 to 5×10 16 cm -3 . If it is in this range, good diode characteristics can be shown. When the carrier concentration is less than 1×10 14 cm -3 , the on-resistance becomes too high, which causes heat during operation, which is not good. When the carrier concentration exceeds 1×10 17 cm -3 , the resistance may become too low, and the leakage current at the time of reverse bias may increase.
載子濃度係藉由C-V評價而測定。 The carrier concentration is determined by C-V evaluation.
C-V評價係使用下述式，根據C-2τsV之斜率而求出N(載子濃度)。 The CV evaluation system uses the following formula to obtain N (carrier concentration) from the slope of C -2 τsV.
各符號意指下述情況。 Each symbol means the following.
C：金屬與金屬氧化物之接面電容 C: Junction capacitance of metal and metal oxide
q：基本電荷 q: basic charge
ε：金屬氧化物之介電常數 ε: Dielectric constant of metal oxide
V：施加電壓 V: Applied voltage
再者，與Si層、SiO2層、中間金屬層中之任一者接觸之側之金屬氧化物界面藉由局部地使載子濃度升高而容易獲得歐姆特性。具體之載子濃度較佳為1×1017cm-3~1×1022cm-3以下。使載子濃度升高之方法可列舉使氧缺陷增加之方法或使摻雜濃度增加之方法。與金屬M層、MxOy層、中間金屬層中之任一者接觸之側之金屬氧化物界面亦相同。 Furthermore, the metal oxide interface on the side in contact with any of the Si layer, the SiO 2 layer, and the intermediate metal layer can easily obtain ohmic characteristics by locally increasing the carrier concentration. The specific carrier concentration is preferably 1×10 17 cm -3 to 1×10 22 cm -3 or less. The method of increasing the carrier concentration can be a method of increasing the oxygen defect or a method of increasing the doping concentration. The metal oxide interface on the side contacting any one of the metal M layer, the M x O y layer, and the intermediate metal layer is also the same.
作為使氧缺陷增加之方法，可列舉於氧化物半導體之成膜時於氧不足之狀態下成膜之方法、於還原氣氛下加熱之方法等。 As a method of increasing oxygen defects, a method of forming a film in an oxygen-deficient state during film formation of an oxide semiconductor, a method of heating in a reducing atmosphere, and the like can be cited.
使摻雜濃度增加之方法係主要使用多晶之氧化物半導體而使摻雜劑活化之方法。例如，可最初使Ti、Si、Ge、Sn等四價之元素於0.1~10%之範圍內混入至靶材料，或藉由離子摻雜而混入並進行退火。 The method of increasing the doping concentration is mainly a method of activating the dopant by using a polycrystalline oxide semiconductor. For example, Ti, Si, Ge, Sn and other tetravalent elements can be mixed into the target material in the range of 0.1-10% at first, or mixed and annealed by ion doping.
金屬氧化物層之成膜方法並無特別限制，可使用公知之方法。尤其是，於欲將膜厚設為1μm以上之情形時，除了濺鍍法以外，亦可利用刮刀法、射出法、擠出法、熱加壓法等陶瓷之製法、或離子鍍覆法、氣溶膠沈積法等適於厚膜之先前公知之製法。 The method of forming the metal oxide layer is not particularly limited, and a known method can be used. In particular, when the film thickness is to be 1 μm or more, in addition to the sputtering method, ceramic manufacturing methods such as the doctor blade method, the injection method, the extrusion method, and the hot press method, or the ion plating method, can also be used. The aerosol deposition method is a previously known method suitable for thick film.
用於本發明之金屬氧化物之絕緣破壞電場通常為0.5~3.0MV/cm，與先前之矽系二極體相比具有非常優異之性能。 The dielectric breakdown electric field of the metal oxide used in the present invention is usually 0.5-3.0 MV/cm, which has very excellent performance compared with the previous silicon-based diodes.
例如，已知單晶之β-Ga2O3之理論之絕緣破壞電場為8.0MV/cm以上(APEX5-2012-035502)，但若存在微小之缺陷或孔隙等則其會大幅度降低。其原因在於，若存在塊體中之微小之缺陷或孔隙，則於施加電場時產生極化，容易以此處為起點產生絕緣破壞。於本發明中使用之氧化物半導體為非晶質或微晶結構之情形時，原理上不存在微小之缺陷或孔隙，故而雖未達到單晶之理論值，但可良率較佳地獲得以此為基準之較大之絕緣破壞電場。 For example, the theoretical insulation breakdown electric field of known single crystal β-Ga 2 O 3 is 8.0 MV/cm or more (APEX5-2012-035502), but if there are tiny defects or pores, it will be greatly reduced. The reason is that if there are tiny defects or pores in the block, polarization occurs when an electric field is applied, and it is easy to cause insulation failure from this point as a starting point. When the oxide semiconductor used in the present invention has an amorphous or microcrystalline structure, there are no tiny defects or pores in principle, so although it does not reach the theoretical value of a single crystal, the yield can be better obtained This is the benchmark for the larger insulation destruction electric field.
金屬氧化物層之膜厚根據耐壓、用途或目的而不同，若為60V耐受電壓則較佳為0.2μm~1.2μm，若為600V耐受電壓則較佳為2μm~12μm。 The film thickness of the metal oxide layer varies according to the withstand voltage, use, or purpose. If it is a 60V withstand voltage, it is preferably 0.2μm~1.2μm, and if it is a 600V withstand voltage, it is preferably 2μm~12μm.
(5)表面金屬層 (5) Surface metal layer
於與Si層、SiO2層、中間金屬層中之任一者接觸之金屬氧化物層之界面為肖特基連接的情形時，若於金屬氧化物層之上積層歐姆電極則可獲得具有良好之整流特性之二極體。設為歐姆連接之情形時之材料等條件係與上述(3-2)相同。又，於設為肖特基連接之情形時，材料等條件係與上述(3-1)相同。 When the interface of the metal oxide layer in contact with any of the Si layer, the SiO 2 layer, and the intermediate metal layer is Schottky connection, if an ohmic electrode is stacked on the metal oxide layer, a good performance can be obtained. The rectification characteristic of the diode. The material and other conditions for the case of ohmic connection are the same as the above (3-2). In the case of Schottky connection, conditions such as materials are the same as in (3-1) above.
與金屬M層、MxOy層、中間金屬層中之任一者接觸之金屬氧化物層之情形亦與上述相同。 The situation of the metal oxide layer in contact with any one of the metal M layer, the M x O y layer, and the intermediate metal layer is also the same as described above.
將設置有表面金屬層之情形時之實施形態示於圖5。 The embodiment in the case where the surface metal layer is provided is shown in FIG. 5.
於積層體5中，於Si層10、SiO2層20及金屬氧化物層30之上設置
有表面金屬層40。再者，對於表面金屬層40以外之積層體之構成，可如上述所說明般設為各種構成。例如，可不設置SiO2層20，亦可設置金屬含有層。
In the
包含本發明之積層體之元件可應用於多種電路或電器機器、車輛等。尤其是，作為用以獲得二極體或縱型MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金屬氧化物半導體場效應電晶體)之基板最佳。使用本發明之積層體之二極體可實現高耐壓且高速切換。以下，對該等情況進行說明。 The component including the laminated body of the present invention can be applied to various circuits, electrical appliances, vehicles, and the like. In particular, it is best as a substrate for obtaining a diode or a vertical MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide-Semiconductor Field-Effect Transistor). The use of the diode of the laminated body of the present invention can realize high withstand voltage and high-speed switching. Hereinafter, these situations will be explained.
(1)肖特基勢壘二極體 (1) Schottky barrier diode
於二極體中，根據其用途，可分為肖特基勢壘二極體、及PN二極體兩種。一般而言，使用矽之肖特基勢壘二極體為單極，可高速切換，但耐壓較差。相反，使用矽之PN二極體為雙極，高速切換較差，但耐壓性優異。 Among the diodes, according to their use, they can be divided into two types: Schottky barrier diodes and PN diodes. Generally speaking, Schottky barrier diodes using silicon are unipolar, which can be switched at high speed, but their withstand voltage is poor. On the contrary, the PN diode using silicon is bipolar, which is poor in high-speed switching, but has excellent voltage resistance.
使用本發明之積層體製作之二極體由於使用氧化物半導體故而為單極，帶隙較寬。因此，可兼具矽所難以實現之高速切換與高耐壓。 The diode produced by using the laminated body of the present invention is unipolar due to the use of an oxide semiconductor, and has a wide band gap. Therefore, it can have both high-speed switching and high withstand voltage that silicon can hardly achieve.
於SiC或GaN之情形時，均難以高效率地獲得缺陷較少之單晶，於良率方面亦存在問題。於此方面，使用本發明之積層體之二極體之製造良率亦較高，於產業上較有效。 In the case of SiC or GaN, it is difficult to efficiently obtain single crystals with fewer defects, and there are also problems in yield. In this regard, the manufacturing yield of the diode using the laminated body of the present invention is also higher, which is more industrially effective.
為了進一步提高作為二極體之性能或穩定性，可使用先前公知之保護膜或保護環構造、台面構造、場板構造、及場光闌構造。具體而言，藉由利用SiO2等使金屬氧化物層之露出部分鈍化，可抑制表面能階之形成，而減少被稱為電流崩潰之順向電流之降低現象。又，藉由將保護環層埋入至金屬氧化物層，於超過防護逆向突波電壓之電壓範圍之情形時，可抑制有使二極體破損之虞之突崩潰(Avalanche breakdown)。 In order to further improve the performance or stability as a diode, the previously known protective film or protective ring structure, mesa structure, field plate structure, and field stop structure can be used. Specifically, by using SiO 2 etc. to passivate the exposed part of the metal oxide layer, the formation of surface energy levels can be suppressed, and the reduction of forward current called current collapse can be reduced. In addition, by embedding the guard ring layer in the metal oxide layer, when the voltage range of the protection against reverse surge voltage is exceeded, Avalanche breakdown that may damage the diode can be suppressed.
於本發明中積層體所使用之金屬氧化物層為n型之情形時，保護環層較佳為使用p型、或i型半導體。藉由保護環層，可於逆向偏壓時緩和接合界面端部之電場集中，而可提高耐壓。 When the metal oxide layer used in the laminate in the present invention is an n-type, the guard ring layer is preferably a p-type or i-type semiconductor. With the guard ring layer, the concentration of the electric field at the end of the bonding interface can be alleviated during reverse bias, and the withstand voltage can be improved.
p型層可使用作為先前公知之p型半導體之摻雜有B、Al、Ga、In之Si，亦可使用NiO或CuO、或者以CuTMO2(TM：3d過渡金屬)為代表之p型氧化物半導體。 The p-type layer can use Si doped with B, Al, Ga, In, which is a previously known p-type semiconductor, or use NiO, CuO, or p-type oxidation represented by CuTMO 2 (TM: 3d transition metal)物 Semiconductors.
又，保護環為了提高其效果，亦可設計為雙重、3重。此處，p型半導體並非使電洞流動者，而無需高遷移率。 In addition, the guard ring can be designed as double or triple in order to improve its effect. Here, p-type semiconductors are not the ones that make holes flow, and do not need high mobility.
於與Si層、SiO2層、中間金屬層中之任一者接觸之金屬氧化物之界面為肖特基連接的情形時，只要首先形成保護環層，繼而積層金屬氧化物層即可。又，於與Si層、SiO2層、中間金屬層中之任一者接觸之金屬氧化物之界面為歐姆連接的情形時，首先成膜金屬氧化物層，將其蝕刻成保護環狀，其後將p型或i型半導體成膜。繼而，只要於藉由CMP等對表面進行研磨後，將成為歐姆連接之表面金屬層成膜即可。 When the interface of the metal oxide in contact with any of the Si layer, the SiO 2 layer, and the intermediate metal layer is Schottky connection, it is only necessary to form the guard ring layer first, and then laminate the metal oxide layer. In addition, when the interface of the metal oxide in contact with any of the Si layer, the SiO 2 layer, and the intermediate metal layer is ohmic, the metal oxide layer is first formed and etched into a protective ring. Then the p-type or i-type semiconductor is formed into a film. Then, as long as the surface is polished by CMP or the like, the surface metal layer that becomes the ohmic connection is formed into a film.
與金屬M層、MxOy層、中間金屬層中之任一者接觸之金屬氧化物之情形亦與上述相同。 The situation of the metal oxide in contact with any one of the metal M layer, the M x O y layer, and the intermediate metal layer is also the same as described above.
該等保護膜及保護環層可藉由濺鍍、離子鍍覆、PECVD(Plasma Enhanced Chemical Vapor Deposition，電漿加強化學氣相沈積)等真空製程、印刷、塗佈熱解、霧化CVD、溶膠凝膠等濕式製程等先前公知之成膜法而形成。又，關於保護環，亦可對所需區域以離子形式注入成為p型之Cu或Ni等元素。於形成時，可使用區域遮罩，亦可使用先前公知之光微影法。對於圖案化技術，可使用先前公知之濕式蝕刻、乾式蝕刻。於形成保護膜及保護環層時，只要根據加工精度及材質適當組合並實施最佳之製程即可。 The protective film and protective ring layer can be made by sputtering, ion plating, PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) and other vacuum processes, printing, coating pyrolysis, atomized CVD, sol It is formed by a conventionally known film forming method such as a wet process such as a gel. In addition, regarding the guard ring, elements such as Cu or Ni, which are p-type, may be implanted in the form of ions into the desired area. When forming, area masks can be used, or the previously known photolithography method can also be used. For the patterning technique, previously known wet etching and dry etching can be used. When forming the protective film and the protective ring layer, it is only necessary to appropriately combine them according to the processing precision and materials and implement the best process.
將設置有保護膜及/或保護環之情形時之實施形態示於圖6~8。 The embodiment when the protective film and/or the protective ring are provided is shown in Figs. 6-8.
於積層體6中，於金屬氧化物層30及表面金屬層40之上，以覆蓋該等之方式設置有保護膜50。於積層體7中，於金屬氧化物層30之上表面側埋入有保護環60。又，於積層體8中，於金屬氧化物層30之下表面側埋入有保護環60。
In the
再者，於積層體6~8中，對於保護膜50或保護環60以外之積層體之構成，可如上述所說明般設為各種構成。
In addition, in the
關於使用本發明之積層體之肖特基勢壘二極體，為了降低Si層之接觸電阻，只要於藉由逆向濺鍍或氫氟酸去除Si之自然氧化膜後積層背面電極即可。作為電性接觸良好之組合，可使用Ti-Ni-Au、Ti-Ni-Ag等積層體、或摻雜有Si之Al電極等。以此方式獲得之肖特基勢壘二極體係於矽晶圓上積層而成，故而並非如SiC般高硬度、高脆性。因此，可藉由通常之切割技術，良率較佳地進行加工。 Regarding the Schottky barrier diode using the laminate of the present invention, in order to reduce the contact resistance of the Si layer, it is only necessary to laminate the back electrode after removing the natural oxide film of Si by reverse sputtering or hydrofluoric acid. As a combination with good electrical contact, laminates such as Ti-Ni-Au, Ti-Ni-Ag, or Al electrodes doped with Si can be used. The Schottky barrier diode system obtained in this way is laminated on a silicon wafer, so it is not as hard and brittle as SiC. Therefore, it can be processed with the usual cutting technology with better yield.
(2)MPS(Merged Pin and Shottky，合併pin與肖特基)二極體 (2) MPS (Merged Pin and Shottky, merge pin and Schottky) diode
本發明之積層體可用於MPS二極體。MPS二極體係兼具Pin二極體之通電能力與肖特基二極體之高速切換特性之優點的二極體。 The laminated body of the present invention can be used for MPS diodes. MPS diode system is a diode that has both the energizing ability of Pin diode and the high-speed switching characteristics of Schottky diode.
於與Si層、SiO2層、中間金屬層中之任一者接觸之金屬氧化物之界面為肖特基連接的情形時，只要首先使p層或i層積層、圖案化，繼而積層金屬氧化物即可。與金屬M層、MxOy層、中間金屬層中之任一者接觸之金屬氧化物亦相同。 When the interface of the metal oxide in contact with any of the Si layer, the SiO 2 layer, and the intermediate metal layer is Schottky connection, only the p-layer or i-layer is layered and patterned first, and then the layered metal is oxidized Things can be. The metal oxide in contact with any of the metal M layer, the M x O y layer, and the intermediate metal layer is also the same.
於圖9表示將本發明之積層體設為MPS之情形時之實施形態。 Fig. 9 shows an embodiment when the laminate of the present invention is set to MPS.
於積層體9中，於SiO2層20之上形成有複數個p型半導體70。再者，對於p型半導體70以外之積層體之構成，可如上述所說明般設為各種構成。
In the layered body 9, a plurality of p-
又，於與Si層、SiO2層、中間金屬層中之任一者接觸之金屬氧化物之界面為歐姆連接的情形時，首先成膜金屬氧化物層，並挖掘溝 槽，其後將p型或i型半導體成膜。繼而，只要於藉由CMP等對表面進行研磨後，將成為歐姆連接之表面金屬層成膜即可。 Also, when the interface of the metal oxide in contact with any of the Si layer, the SiO 2 layer, and the intermediate metal layer is ohmically connected, the metal oxide layer is first formed, and the trench is excavated, and then the p Type or i-type semiconductor film formation. Then, as long as the surface is polished by CMP or the like, the surface metal layer that becomes the ohmic connection is formed into a film.
而且，藉由設為此種構成，可獲得接通電阻較小、先前之絕緣破壞電場較大之積層體。該性質具有改善先前難以高壓化之Si肖特基勢壘二極體之耐壓區域(200~600V)之效果。 Moreover, by adopting such a configuration, a laminate having a low on-resistance and a large electric field for the previous insulation breakdown can be obtained. This property has the effect of improving the withstand voltage region (200~600V) of the Si Schottky barrier diode, which was difficult to be high-voltage previously.
圖10係表示支持基板包含金屬M之情形時之積層體之一實施形態的圖。 FIG. 10 is a diagram showing an embodiment of a laminate when the supporting substrate contains metal M. FIG.
積層體101之Si層10為包含Mo之金屬層12且SiO2層20為Mo之氧化物之層22，除此以外，與積層體7相同。Mo與金屬氧化物之線膨脹係數接近，故而於金屬氧化物積層後之加熱製程中可抑制內部應力之產生。例如，於使用IGZO(33：33：33)作為金屬氧化物層30之情形時，相對於IGZO之線膨脹係數為6.5×10-6/K，Mo之線膨脹係數為5.1×10-6/K而較為接近。因此，即便使用CVD步驟以300℃以上之溫度形成SiO2作為保護膜，亦可防止產生膜剝離或龜裂。另一方面，於將Si晶圓用作支持基板之情形時，Si之線膨脹係數為2.8×10-6/K，與IGZO相比為一半以下，而容易產生金屬氧化物層之膜剝離或龜裂。
The
圖11之積層體11於SiO2層20與金屬氧化物層30之間積層有金屬層14及構成該金屬層14之金屬之氧化物層24，除此以外，與積層體7相同。
The laminated body 11 of FIG. 11 is the same as the
如圖11所示，於在Si晶圓10上積層金屬氧化物層30之情形時，較佳為於其間夾著成為緩衝之金屬層14。該金屬層係用以緩和因支持基板與金屬氧化物之線膨脹係數之差而產生之應力的層，其厚度根據金屬氧化物層之厚度或組成而適當選擇。金屬層之厚度較佳為大於金屬氧化物層之厚度。
As shown in FIG. 11, when a
又，Si以外之支持基板、或緩衝層所使用之金屬較佳為線膨脹係數大於Si且小於金屬氧化物之材料。具體而言，除Mo以外，可列舉 Ti、Cr、Nb、Ta等。 In addition, the metal used for the support substrate or the buffer layer other than Si is preferably a material with a coefficient of linear expansion greater than that of Si and less than that of a metal oxide. Specifically, in addition to Mo, one can cite Ti, Cr, Nb, Ta, etc.
於積層體11中，SiO2層20及構成金屬層14之金屬之氧化物層24(均為自然氧化物層)的膜厚只要分別設為0.0nm~15.0nm即可。
In the layered body 11, the film thickness of the SiO 2
圖12及13分別為表示圖11之積層體11之製造方法之一實施形態的圖。 12 and 13 are diagrams each showing an embodiment of the method of manufacturing the layered body 11 of FIG. 11.
圖12係藉由使形成於金屬層14上之積層體與Si晶圓接合而製造積層體。藉由以此方式製造，可於後續步驟應用Si製程，從而於製造上較為有利。圖13係於首先將金屬層14與金屬氧化物層30之積層體與Si層10接合後積層表面金屬層40、保護膜50及保護環60等之情形。
In FIG. 12, a laminated body formed on the
接合技術有先前公知之SOI(Silicon On Insulator，絕緣層上覆矽)或電漿等。再者，於將異種金屬彼此貼合時，容易因熱膨脹係數之差產生破裂或龜裂，故而必須確保升溫降溫時之溫度均一性。 The bonding technology includes previously known SOI (Silicon On Insulator) or plasma. Furthermore, when bonding dissimilar metals to each other, cracks or cracks are likely to occur due to the difference in the coefficient of thermal expansion. Therefore, it is necessary to ensure temperature uniformity during heating and cooling.
本發明之元件較佳為具有非線性導電。所謂非線性導電意指不依據歐姆法則之導電。 The device of the present invention preferably has nonlinear conductivity. The so-called nonlinear conduction means conduction that does not follow Ohm's law.
(3)功率MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金屬氧化物半導體場效應電晶體) (3) Power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)
本發明之積層體可用於功率MOSFET。功率MOSFET係經由氧化膜藉由電場控制載子之流動之絕緣閘極型場效電晶體。藉由使用本發明之積層體，可製成將電子作為載子之單極裝置。 The laminate of the present invention can be used for power MOSFETs. The power MOSFET is an insulated gate type field effect transistor that controls the flow of carriers by an electric field through an oxide film. By using the laminate of the present invention, a unipolar device using electrons as carriers can be made.
於圖14表示將本發明之積層體用於平面式閘極型功率MOSFET之情形時之一實施形態。 FIG. 14 shows an embodiment when the laminate of the present invention is used in a planar gate type power MOSFET.
圖14係表示使用金屬氧化物半導體之縱型MOSFET之剖面圖。使用n型Si(對應於Si層10)作為支持基板，介隔Ti、Ni、In(對應於金屬含有層25)積層有n型之金屬氧化物半導體(對應於金屬氧化物層30)。Si晶圓與Ti之界面可存在亦可不存在SiO2層20，但於存在之情形時必須為15nm以下。 Fig. 14 is a cross-sectional view showing a vertical MOSFET using a metal oxide semiconductor. An n-type Si (corresponding to the Si layer 10) is used as a support substrate, and an n-type metal oxide semiconductor (corresponding to the metal oxide layer 30) is laminated with Ti, Ni, and In (corresponding to the metal containing layer 25). The interface between the Si wafer and Ti may or may not exist the SiO 2 layer 20, but if it exists, it must be 15 nm or less.
n型Si於另一面積層有Ti、Ni、Au(背面電極26)，該層與汲極電極100(未圖示)接觸。 The n-type Si has Ti, Ni, and Au in another area layer (back electrode 26), and this layer is in contact with the drain electrode 100 (not shown).
於圖14中，n型之金屬氧化物半導體之上部於藉由乾式蝕刻形成凹槽(槽)後，積層p型半導體或低載子濃度之n型半導體75。通常於該區域(以下為凹槽區域)使用p型半導體，但若使用寬能隙之氧化物半導體，則即便於閘極80斷開(Off)之狀態下漏電流亦較小，故而並非必須為p型。
In FIG. 14, a p-type semiconductor or an n-
形成於凹槽區域之p型半導體或低載子濃度之n型半導體75的費米能階較佳為低於本發明之積層體中所使用之氧化物半導體。
The Fermi level of the p-type semiconductor or the low-carrier-concentration n-
作為用於凹槽區域之p型半導體，可使用NiO、PdO、CuO、摻硼矽等先前公知之p型半導體材料。 As the p-type semiconductor used in the recessed region, previously known p-type semiconductor materials such as NiO, PdO, CuO, and boron-doped silicon can be used.
又，低載子濃度之n型半導體可使用氧化物半導體。該區域係於閘極接通之狀態下形成通道之區域，故而有可能成為散射源之過渡金屬之濃度較佳為儘可能小。 In addition, an oxide semiconductor can be used as an n-type semiconductor with a low carrier concentration. This region is the region where the channel is formed when the gate is turned on. Therefore, the concentration of the transition metal that may become the scattering source is preferably as small as possible.
介隔閘極絕緣膜110而存在之源極電極區域90可使用W、Ti、Mo、Al、Cr等先前公知之低電阻配線材料。又，為了抑制接觸電阻，亦可進行於成膜前藉由Ar電漿等還原而僅使接觸部分提高載子濃度之處理。
The
p型區域、源極電極區域均藉由光微影技術將金屬氧化物層圖案化並藉由磁控濺鍍或電漿CVD等方法形成而獲得。表面係進行CMP處理而適當使之平滑。於包含以此方式獲得之源極電極、及p型或低載子濃度n型區域之積層體上積層絕緣膜，並進行圖案化而製成閘極絕緣膜。 The p-type region and the source electrode region are all obtained by patterning the metal oxide layer by photolithography technology and forming by methods such as magnetron sputtering or plasma CVD. The surface is properly smoothed by CMP treatment. An insulating film is laminated on a laminate including the source electrode obtained in this way and a p-type or low-carrier-concentration n-type region, and patterned to form a gate insulating film.
構成絕緣膜之材料並無特別限制，可於不損及本發明之效果之範圍內任意選擇一般所使用之材料。例如，可使用SiO2、SiNx、Al2O3、Ta2O5、TiO2、MgO、ZrO2、CeO2、K2O、Li2O、Na2O、 Rb2O、Sc2O3、Y2O3、HfO2、CaHfO3、PbTi3、BaTa2O6、SrTiO3或AlN等氧化物或氮化物。 The material constituting the insulating film is not particularly limited, and generally used materials can be arbitrarily selected within a range that does not impair the effects of the present invention. For example, SiO 2 , SiN x , Al 2 O 3 , Ta 2 O 5 , TiO 2 , MgO, ZrO 2 , CeO 2 , K 2 O, Li 2 O, Na 2 O, Rb 2 O, Sc 2 O can be used 3. Oxides or nitrides such as Y 2 O 3 , HfO 2 , CaHfO 3 , PbTi 3 , BaTa 2 O 6 , SrTiO 3 or AlN.
再者，作為對絕緣膜要求之項目，重要的是膜厚不均較小、及不存在成為漏電之原因之針孔。作為一般之閘極絕緣膜，可使用SiO2、SiNx、Al2O3等。 Furthermore, as an item required for an insulating film, it is important that the unevenness of the film thickness is small and that there is no pinhole that causes electric leakage. As a general gate insulating film, SiO 2 , SiN x , Al 2 O 3, etc. can be used.
最後，濺鍍金屬而圖案化為所需形狀，藉此可獲得附源極、閘極之積層體。 Finally, the metal is sputtered and patterned into a desired shape, thereby obtaining a laminate with source and gate.
又，於在成為汲極電極之積層體之背面側產生SiO2等自然氧化膜之情形時，於藉由氫氟酸或逆向濺鍍等去除該自然氧化膜後，以Ti/Ni/Au之順序積層金屬。此處，Ti具有作為密接層之作用，Ni具有作為防擴散層之作用，Au具有低電阻層之作用。 In addition, when a natural oxide film such as SiO 2 is formed on the back side of the laminate that becomes the drain electrode, after removing the natural oxide film by hydrofluoric acid or reverse sputtering, a Ti/Ni/Au Laminate metals sequentially. Here, Ti has a role as an adhesion layer, Ni has a role as an anti-diffusion layer, and Au has a role as a low-resistance layer.
以此方式獲得之縱型MOSFET由於耐壓層使用寬能隙氧化物半導體，故而耐壓優異，從而可兼具Si所難以實現之600V以上之耐壓與高速切換。又，由於通道電阻部分使用藉由閘極偏壓之n通道傳導，故而載子為高遷移率之電子，而可實現低接通電阻。 The vertical MOSFET obtained in this way has an excellent withstand voltage due to the use of a wide band gap oxide semiconductor for the withstand voltage layer, so that it can have both a withstand voltage above 600V and high-speed switching that Si is difficult to achieve. In addition, since the channel resistance part uses n-channel conduction by gate bias, the carriers are electrons with high mobility, and low on-resistance can be achieved.
於圖15表示將本發明之積層體用於溝槽式閘極型功率MOSFET之情形時之一實施形態。 FIG. 15 shows an embodiment when the laminate of the present invention is used in a trench gate type power MOSFET.
圖15係表示使用氧化物半導體之溝槽式閘極型功率MOSFET之剖面圖者。相較於平面構造，本構造可進行微細化，而可降低通道之電阻。亦可提高溝槽之密度而製成超級接面構造。 FIG. 15 shows a cross-sectional view of a trench gate type power MOSFET using an oxide semiconductor. Compared with the planar structure, this structure can be miniaturized, and the resistance of the channel can be reduced. It can also increase the density of the grooves to make a super junction structure.
於圖15中，p型半導體或低載子濃度之n型半導體75形成於n型金屬氧化物半導體30上而並非形成於凹槽內。又，於p型半導體或低載子濃度之n型半導體75上形成有源極電極90，貫通該源極電極90及p型半導體或低載子濃度之n型半導體75而設置有凹槽，於該凹槽內介隔閘極絕緣膜110而形成有閘極80。除該等構成以外，與圖14相同。
In FIG. 15, a p-type semiconductor or a low-carrier concentration n-
將於使用本發明之積層體之平面式閘極型功率MOSFET中漂移區 域使用金屬氧化物、且通道區域使用多晶矽之情形時的一實施形態示於圖16。 The drift region in the planar gate type power MOSFET using the laminated body of the present invention An embodiment in the case where metal oxide is used for the domain and polysilicon is used for the channel area is shown in FIG. 16.
圖16表示藉由於漂移區域使用金屬氧化物、且通道區域使用多晶矽而兼具高耐壓與高速切換之功率MOSFET。 Fig. 16 shows a power MOSFET with high withstand voltage and high-speed switching due to the use of metal oxide in the drift region and the use of polysilicon in the channel region.
於圖16中，將高摻雜n型矽晶圓用作基板(對應於Si層10)，並藉由稀氫氟酸等對表面進行處理而去除自然氧化膜。繼而，將n型氧化物半導體(對應於金屬氧化物層30)成膜。於將n型氧化物半導體結晶化而使用之情形時，只要於150~1400℃之範圍內進行退火即可。退火之恰當範圍依存於氧化物半導體之構成元素而適當被決定。若退火溫度超過1400℃，則有使矽熔解之虞。若退火溫度低於150℃，則有未進行結晶化之虞。 In FIG. 16, a highly doped n-type silicon wafer is used as a substrate (corresponding to the Si layer 10), and the surface is treated with dilute hydrofluoric acid to remove the natural oxide film. Then, an n-type oxide semiconductor (corresponding to the metal oxide layer 30) is formed into a film. In the case of crystallizing an n-type oxide semiconductor for use, it is only necessary to perform annealing in the range of 150 to 1400°C. The proper range of annealing is appropriately determined depending on the constituent elements of the oxide semiconductor. If the annealing temperature exceeds 1400°C, silicon may be melted. If the annealing temperature is lower than 150°C, crystallization may not proceed.
於退火結束後，藉由PECVD等方法將非晶矽成膜於n型氧化物半導體上，並進行圖案化。圖案化係於塗佈抗蝕劑後，進行曝光、顯影，並使用鹵素系氣體進行乾式蝕刻。於抗蝕劑剝離後，使用雷射退火等方法進行多晶化。繼而，藉由PECVD等方法，成膜SiO2膜115。進而，於其上使用濺鍍或蒸鍍法將金屬電極成膜，圖案化為閘極電極80之形狀。圖案化無論乾式、濕式均可利用先前公知之方法，但為了進行下述活化退火，較佳為W、Cr、Mo、Ta等高熔點金屬。
After the annealing, the amorphous silicon film is formed on the n-type oxide semiconductor by PECVD and other methods, and then patterned. Patterning is performed after the resist is applied, exposure, development, and dry etching using halogen-based gas. After the resist is stripped, it is polycrystallized using methods such as laser annealing. Then, the SiO 2
繼而，隔著該閘極電極80，對p型Si進行離子摻雜。離子摻雜由於成為經由作為絕緣膜之SiO2膜之覆蓋方式，故而摻雜量及其深度之控制只要藉由模擬等確認即可，例如以50~500keV之加速電壓且於摻雜量為1013~1014cm-2等條件下進行P、Sb、As等之摻雜。該離子摻雜由於使用以閘極電極80為遮罩之自對準技術，故而可使製程簡化，並且可減少閘極電容而進行高速切換動作。
Then, the p-type Si is ion-doped with the
於離子摻雜後，進行活化退火。於防止電極之劣化方面，活化退火較佳為閃光燈退火等高速退火、或雷射退火法。 After ion doping, activation annealing is performed. In terms of preventing the deterioration of the electrode, the activation annealing is preferably high-speed annealing such as flash lamp annealing, or a laser annealing method.
退火溫度係溫度越高則活化率越上升，但於不產生電極之劣化之範圍內進行適當選擇。退火溫度較佳為600℃~1100℃，更佳為700~1000℃。如此般，可將p型Si(p區域)120之一部分設為經n型化之n+區域130。
The annealing temperature is the higher the temperature, the more the activation rate increases, but it is appropriately selected within a range that does not cause deterioration of the electrode. The annealing temperature is preferably 600°C to 1100°C, more preferably 700 to 1000°C. In this way, a part of the p-type Si (p region) 120 can be used as the
繼而，於相當於SiO2之源極電極之部分使用光微影而形成接觸孔，最後形成源極電極90。 Then, photolithography is used to form a contact hole on the part corresponding to the source electrode of SiO 2, and finally the source electrode 90 is formed.
再者，於高摻雜n型矽晶圓10，與圖14及15同樣地積層有Ti、Ni、Au(背面電極26)，該層與汲極電極100(未圖示)接觸。
Furthermore, on the highly doped n-
(3)模組 (3) Module
使用本發明之積層體之MOSFET與先前之Si系MOSFET同樣地內置體二極體，亦可與回流二極體組合而使用。 The MOSFET using the laminated body of the present invention has a built-in body diode like the conventional Si-based MOSFET, and can also be used in combination with a reflow diode.
圖17係表示組合本發明之元件而構成之模組之一實施形態的圖。功率MOSFET、回流二極體均由包含本發明之積層體之元件構成。該模組由於MOSFET、回流二極體均包括包含Si層及金屬氧化物層且上述Si層之上述金屬氧化物層側之面上之SiO2層的膜厚為0.0nm~15.0nm之積層體，故而可兼具優異之電流-電壓特性、即較低之接通電阻與高速切換。 Fig. 17 is a diagram showing an embodiment of a module constructed by combining the elements of the present invention. Both the power MOSFET and the reflux diode are composed of elements including the laminated body of the present invention. This module includes a MOSFET and a reflow diode including a Si layer and a metal oxide layer, and the SiO 2 layer on the side of the metal oxide layer of the Si layer has a film thickness of 0.0nm~15.0nm. , So it can have excellent current-voltage characteristics, that is, low on-resistance and high-speed switching.
此處，圖17之回流二極體之連接之朝向於Si層側為歐姆連接(陰極)之情形與肖特基連接(陽極)之情形有所不同。圖18係表示於圖17之模組中二極體與MOSFET介隔背面金屬與焊料而連接於銅板且二極體之Si晶圓側與MOSFET之集電極連接之情形時之實施形態的圖。於Si側為歐姆連接之情形時，Si側與模組之銅板連接。又，圖19係表示於圖17之模組中二極體與MOSFET介隔背面金屬與焊料而連接於銅板且二極體之氧化物半導體側與MOSFET之集電極連接之情形時之實施形態的圖。於Si側為肖特基連接之情形時，表面金屬層側與模組之銅板連接。 Here, the connection of the reflux diode in FIG. 17 is different from the case of Schottky connection (anode) when it is ohmic connection (cathode) toward the side of the Si layer. 18 is a diagram showing an embodiment when the diode and the MOSFET are connected to a copper plate via the back metal and solder in the module of FIG. 17 and the Si wafer side of the diode is connected to the collector of the MOSFET. In the case of ohmic connection on the Si side, the Si side is connected to the copper plate of the module. In addition, FIG. 19 shows an embodiment when the diode and the MOSFET are connected to a copper plate via the back metal and solder in the module of FIG. 17, and the oxide semiconductor side of the diode is connected to the collector of the MOSFET. Figure. When the Si side is Schottky connection, the surface metal layer side is connected to the copper plate of the module.
再者，關於模組之構成，為了去除先前公知之Si-IGBT(Insulated Gate Bipolar Transistor，絕緣柵雙極電晶體)、SiC-MOSFET、GaN-MOSFET之過剩載子，亦可與本發明之二極體組合。又，為了去除本發明之MOSFET之過剩載子，亦可使用先前公知之回流二極體。 Furthermore, regarding the structure of the module, in order to remove the excess carriers of the previously known Si-IGBT (Insulated Gate Bipolar Transistor), SiC-MOSFET, and GaN-MOSFET, it can also be the same as the second of the present invention. Polar body combination. In addition, in order to remove the excess carriers of the MOSFET of the present invention, a previously known reflux diode can also be used.
除上述以外，作為使用本發明之元件之電路，可列舉升壓、降壓斬波電路、反相器、轉換器電路、電源電路、開關調節器等，作為電器機器，可列舉行動電話、電腦、空調、冰箱、顯像機、照明器具、電磁蒸煮器等，作為車輛，可列舉腳踏車、汽車、軌道車輛等。進而，本發明之元件亦可使用於氧氣感測器、光觸媒、紫外感測器、紫外太陽電池、人體感測器、紫外二極體、紫外雷射等。 In addition to the above, as the circuit using the element of the present invention, there can be a step-up, step-down chopper circuit, an inverter, a converter circuit, a power supply circuit, a switching regulator, etc., as an electrical device, a mobile phone, a computer can be mentioned , Air conditioners, refrigerators, video cameras, lighting equipment, electromagnetic cookers, etc. Examples of vehicles include bicycles, automobiles, and rail vehicles. Furthermore, the device of the present invention can also be used in oxygen sensors, photocatalysts, ultraviolet sensors, ultraviolet solar cells, human sensors, ultraviolet diodes, ultraviolet lasers, and the like.
以下，一面適當參照圖式一面對本發明之實施例進行說明。本發明不受該等實施例任何限定。 Hereinafter, the embodiments of the present invention will be described with appropriate reference to the drawings. The present invention is not limited in any way by these embodiments.
準備電阻率0.02Ω‧cm之n型Si基板(直徑4英吋)及載玻片。將該等安裝於濺鍍裝置(ULVAC製：CS-200)，最初以逆向濺鍍模式處理15秒，對自然氧化膜之一部分進行蝕刻。繼而，作為金屬氧化物，以RF(Radio Frequency，射頻)300W、19小時之條件，將Ga2O3成膜9700nm。又，將該基板自腔室取出，並藉由電爐以空氣中、150℃之條件退火1小時。 Prepare an n-type Si substrate (4 inches in diameter) with a resistivity of 0.02Ω‧cm and a glass slide. These were installed in a sputtering device (ULVAC: CS-200), and initially treated in a reverse sputtering mode for 15 seconds to etch a part of the natural oxide film. Then, as a metal oxide, Ga 2 O 3 was formed into a film of 9700 nm under RF (Radio Frequency) conditions of 300 W for 19 hours. Furthermore, the substrate was taken out from the chamber, and annealed in the air at 150° C. for 1 hour in an electric furnace.
於載玻片上成膜之元件係由XRD(X-ray diffraction，X射線繞射測定)裝置確認結構，結果為非晶質(圖20)。又，確認電子束繞射，結果觀測到暈樣式，同樣確認為非晶質(圖21)。藉由TEM確認自然氧化膜之膜厚，結果為2.4nm(圖22)。 The structure of the element formed into a film on the glass slide was confirmed by an XRD (X-ray diffraction, X-ray diffraction measurement) device, and the result was amorphous (Figure 20). In addition, the diffraction of the electron beam was confirmed, and as a result, a halo pattern was observed, which was also confirmed to be amorphous (Figure 21). The thickness of the natural oxide film was confirmed by TEM, and the result was 2.4 nm (Figure 22).
其次，再次將上述基板與區域遮罩一併設置於濺鍍裝置，其後，以Ti、Au之順序，以濺鍍成膜形成電極。 Next, the above-mentioned substrate and the area mask are set in the sputtering device together again, and then the electrodes are formed by sputtering in the order of Ti and Au.
對於以此方式獲得之元件(Si/SiO2(自然氧化膜)/Ga2O3/Ti/Au)，使用東陽技術公司製造之SCS-4200進行評價。評價項目設為順向上升電壓(Vf)、接通電流、絕緣破壞電場(Vbd)及n值。再者，順向上升電壓(Vf)設為電流密度超過10mA/cm2時之施加電壓，接通電流設為施加電壓超過3V時之電流密度，絕緣破壞電場(Vbd)設為漏電流超過10-5A/cm2時之電壓。將結果示於表1。 For the device obtained in this way (Si/SiO 2 (natural oxide film)/Ga 2 O 3 /Ti/Au), SCS-4200 manufactured by Toyo Technology Co., Ltd. was used for evaluation. The evaluation items were set as the forward rising voltage (Vf), the on-current, the insulation breakdown electric field (Vbd), and the n value. Further, to set forward rising voltage (Vf) exceeds a current density of 10mA / cm 2, the voltage is applied, current was turned on when the current density of the applied voltage exceeds 3V, the dielectric breakdown field (Vbd in) to the leakage current exceeds 10 Voltage at -5 A/cm 2. The results are shown in Table 1.
準備電阻率0.02Ω‧cm之n型Si基板(直徑4英吋)及載玻片。將該等安裝於濺鍍裝置(ULVAC製：CS-200)，最初以逆向濺鍍模式處理5分鐘，對自然氧化膜之一部分進行蝕刻。繼而，作為金屬氧化物，以RF 300W、6小時之條件，將Ga2O3成膜3700nm。又，將該基板自腔室取出，並藉由電爐以空氣中、150℃之條件退火1小時。 Prepare an n-type Si substrate (4 inches in diameter) with a resistivity of 0.02Ω‧cm and a glass slide. These were installed in a sputtering device (ULVAC: CS-200), and initially treated in a reverse sputtering mode for 5 minutes to etch a part of the natural oxide film. Next, as a metal oxide, Ga 2 O 3 was formed into a film of 3700 nm under the conditions of RF 300 W for 6 hours. Furthermore, the substrate was taken out from the chamber, and annealed in the air at 150° C. for 1 hour in an electric furnace.
於載玻片上成膜之元件係由XRD裝置確認結構，結果為非晶質(圖20)。 The structure of the element formed into a film on a glass slide was confirmed by an XRD device, and the result was amorphous (Figure 20).
再次將上述基板與區域遮罩一併設置於濺鍍裝置，其後，以MgAg、Au之順序，以濺鍍成膜形成電極。 The above-mentioned substrate and the area mask are set again in the sputtering device together, and then, the electrodes are formed by sputtering in the order of MgAg and Au.
對於以此方式獲得之元件(Si/SiO2(自然氧化膜)/Ga2O3/MgAg/Au)，使用東陽技術公司製造之SCS-4200，與實施例1同樣地進行評價。將結果示於表1。 For the element (Si/SiO 2 (natural oxide film)/Ga 2 O 3 /MgAg/Au) obtained in this way, SCS-4200 manufactured by Toyo Technology Co., Ltd. was used, and evaluation was performed in the same manner as in Example 1. The results are shown in Table 1.
準備電阻率0.02Ω‧cm之n型多晶Si基板(直徑4英吋)及載玻片。將該等安裝於濺鍍裝置(ULVAC製：CS-200)，最初以逆向濺鍍模式進行處理，對自然氧化膜之一部分進行蝕刻。繼而，作為金屬氧化物，以RF 300W、18分鐘之條件，將Ga2O3成膜200nm。又，將該基板自腔室取出，並藉由電爐以空氣中、150℃之條件退火1小時。 Prepare an n-type polycrystalline Si substrate (4 inches in diameter) and a glass slide with a resistivity of 0.02Ω‧cm. These were installed in a sputtering device (ULVAC: CS-200), and initially processed in a reverse sputtering mode to etch a part of the natural oxide film. Next, as a metal oxide, Ga 2 O 3 was formed into a film of 200 nm under the conditions of RF 300 W for 18 minutes. Furthermore, the substrate was taken out from the chamber, and annealed in the air at 150° C. for 1 hour in an electric furnace.
於載玻片上成膜之元件係由XRD裝置確認結構，結果為非晶 質。 The structure of the element formed on the glass slide was confirmed by the XRD device, and the result was amorphous quality.
再次將上述基板與區域遮罩一併設置於濺鍍裝置，其後，以Ti、Au之順序，以濺鍍成膜形成電極。 The above-mentioned substrate and the area mask are set in the sputtering device together again, and then the electrodes are formed by sputtering in the order of Ti and Au.
對於以此方式獲得之元件(Si/SiO2(自然氧化膜)/Ga2O3/Ti/Au)，使用東陽技術公司製造之SCS-4200，與實施例1同樣地進行評價。將結果示於表1。 For the element (Si/SiO 2 (natural oxide film)/Ga 2 O 3 /Ti/Au) obtained in this way, SCS-4200 manufactured by Toyo Technology Co., Ltd. was used, and evaluation was performed in the same manner as in Example 1. The results are shown in Table 1.
準備電阻率0.02Ω‧cm之n型多晶Si基板(直徑4英吋)及載玻片。將該等安裝於濺鍍裝置(ULVAC製：CS-200)，最初以逆向濺鍍模式進行處理，對自然氧化膜進行蝕刻。繼而，作為金屬氧化物，以RF 300W、90分鐘之條件，將IGO(In：Ga=30：70)成膜1000nm。 Prepare an n-type polycrystalline Si substrate (4 inches in diameter) and a glass slide with a resistivity of 0.02Ω‧cm. These were installed in a sputtering device (ULVAC: CS-200), and initially processed in a reverse sputtering mode to etch the natural oxide film. Then, as a metal oxide, IGO (In:Ga=30:70) was formed into a film of 1000 nm under the conditions of RF 300W for 90 minutes.
於載玻片上成膜之元件係由XRD裝置確認結構，結果為非晶質。 The structure of the element formed on the glass slide was confirmed by an XRD device, and the result was amorphous.
再次將上述基板與區域遮罩一併設置於濺鍍裝置，其後，以AlNd、Au之順序，以濺鍍成膜形成電極。將該基板自腔室取出，並藉由電爐以空氣中、200℃、1小時之條件進行退火。 The above-mentioned substrate and the area mask are set again in the sputtering device together, and then, in the order of AlNd and Au, the electrodes are formed by sputtering. The substrate was taken out from the chamber, and annealed in the air at 200° C. for 1 hour in an electric furnace.
對於以此方式獲得之元件(Si/SiO2(自然氧化膜)/IGO/AlNd/Au)，使用東陽技術公司製造之SCS-4200，與實施例1同樣地進行評價。將結果示於表1。 For the element (Si/SiO 2 (natural oxide film)/IGO/AlNd/Au) obtained in this way, SCS-4200 manufactured by Toyo Technology Co., Ltd. was used, and the evaluation was performed in the same manner as in Example 1. The results are shown in Table 1.
準備電阻率0.004Ω‧cm之n型高摻雜單晶Si基板(直徑4英吋)及載玻片。將該等安裝於濺鍍裝置(ULVAC製：CS-200)，最初以逆向濺鍍模式進行處理，對自然氧化膜之一部分進行蝕刻。其次，作為金屬氧化物，以RF 100W、20小時之條件將GZO(Ga：Zn=70：30)成膜9700nm。又，將該基板自腔室取出，並藉由電爐以空氣中、150℃之條件退火2小時。於玻璃上成膜之元件係由XRD裝置確認結構，結果
為非晶質。
Prepare an n-type highly doped single crystal Si substrate (4 inches in diameter) and a glass slide with a resistivity of 0.004Ω‧cm. These were installed in a sputtering device (ULVAC: CS-200), and initially processed in a reverse sputtering mode to etch a part of the natural oxide film. Next, as a metal oxide, GZO (Ga:Zn=70:30) was formed into a film of 9700 nm under the conditions of
再次將上述基板與區域遮罩一併設置於濺鍍裝置，其後，以In、Au之順序，以濺鍍成膜形成電極。將該基板自腔室取出，並藉由電爐以空氣中、200℃、1小時之條件進行退火。 The above-mentioned substrate and the area mask are set together in the sputtering device again, and then the electrodes are formed by sputtering in the order of In and Au. The substrate was taken out from the chamber, and annealed in the air at 200° C. for 1 hour in an electric furnace.
對於以此方式獲得之元件(Si/SiO2(自然氧化膜)/GZO/In/Au)，使用東陽技術公司製造之SCS-4200，與實施例1同樣地進行評價。將結果示於表1。 For the element (Si/SiO 2 (natural oxide film)/GZO/In/Au) obtained in this way, SCS-4200 manufactured by Toyo Technology Co., Ltd. was used, and the evaluation was performed in the same manner as in Example 1. The results are shown in Table 1.
準備電阻率0.02Ω‧cm之n型Si基板(直徑4英吋)。將該Si晶圓安裝於濺鍍裝置(ULVAC製：CS-200)，最初以逆向濺鍍模式，對自然氧化膜進行蝕刻。其次，將Mo成膜15nm，進而將Ga2O3成膜1000nm。將該基板自腔室取出，並藉由電爐以空氣中、150℃之條件退火1小時。 Prepare an n-type Si substrate (4 inches in diameter) with a resistivity of 0.02Ω‧cm. This Si wafer was mounted on a sputtering device (ULVAC: CS-200), and the natural oxide film was etched in a reverse sputtering mode at first. Next, Mo was formed into a film of 15 nm, and Ga 2 O 3 was further formed into a film of 1000 nm. The substrate was taken out from the chamber, and annealed in the air at 150° C. for 1 hour in an electric furnace.
繼而，再次使殘餘之基板返回至腔室，並設置具有所需圖案之區域遮罩，其後以Ti、Au之順序，以濺鍍成膜形成電極。 Then, the remaining substrate is returned to the chamber again, and the area mask with the desired pattern is set, and then the electrode is formed by sputtering in the order of Ti and Au.
對於以此方式獲得之元件(Si/Mo/Ga2O3/Ti/Au)，使用東陽技術公司製造之SCS-4200，與實施例1同樣地進行評價。將結果示於表1。 For the element (Si/Mo/Ga 2 O 3 /Ti/Au) obtained in this way, SCS-4200 manufactured by Toyo Technology Co., Ltd. was used, and the evaluation was performed in the same manner as in Example 1. The results are shown in Table 1.
以下，一面如表1般變更Si基板、逆向濺鍍條件、金屬含有層材料、金屬氧化物層材料，一面與實施例6同樣地製作積層體，並評價各種特性。將結果示於表1。又，實施例7、8之基板係經過TEM測定。將基板之剖面圖示於圖22。 Hereinafter, while changing the Si substrate, reverse sputtering conditions, metal-containing layer material, and metal oxide layer material as shown in Table 1, a laminate was produced in the same manner as in Example 6, and various characteristics were evaluated. The results are shown in Table 1. In addition, the substrates of Examples 7 and 8 were measured by TEM. The cross-sectional view of the substrate is shown in FIG. 22.
再者，於比較例2中，設置SiC層(Si：C(原子比)=50：50)代替金屬氧化物層。 Furthermore, in Comparative Example 2, a SiC layer (Si:C (atomic ratio)=50:50) was provided instead of the metal oxide layer.
一面如表1般變更基板、逆向濺鍍條件、金屬氧化物層材料等，
一面與實施例1同樣地製作積層體，並評價各種特性。將結果示於表1。再者，關於作為實施例15及比較例3之金屬氧化物層之成膜方法之「離子鍍覆」，具體以如下方式實施。設置10個In：Ga：Zn=33：33：33之IGZO平板(
又，於實施例15及比較例3中，使用Mo基板作為基板。因此，於實施例15及比較例3中，經逆向蝕刻之自然氧化膜為MoOx層而並非SiO2層。 In addition, in Example 15 and Comparative Example 3, a Mo substrate was used as the substrate. Therefore, in Example 15 and Comparative Example 3, the reverse-etched natural oxide film is a MoO x layer instead of an SiO 2 layer.
藉由圖23所示之製程製造肖特基勢壘二極體。具體而言，準備電阻率0.02Ω‧cm之n型Si基板(直徑4英吋)。將該Si晶圓放入熱氧化爐中，而形成100nm之熱氧化膜。繼而，於進行抗蝕劑塗佈後，使用光罩進行曝光、顯影、蝕刻，而形成接觸孔。進而，於其上，使用Pd靶並藉由濺鍍法，以Pd及PdO之順序，分別各成膜10nm。繼而，以使SiO2上之Pd/PdO積層部分呈同心圓狀地殘留之方式，使用王水進行蝕刻，而形成保護環。進而，於其上，將作為氧化物半導體之IGZO成膜200nm而形成耐壓層，並且將Mo成膜，最後以空氣中、300℃、1小時之條件進行退火。存在於Si晶圓之背面之熱氧化膜係由保護膜覆蓋表面後，藉由稀氫氟酸進行蝕刻而去除。其後，以Ti、Ni、Au之順序進行成膜。 The Schottky barrier diode is manufactured by the process shown in FIG. 23. Specifically, an n-type Si substrate (4 inches in diameter) with a resistivity of 0.02Ω·cm was prepared. The Si wafer was placed in a thermal oxidation furnace to form a 100nm thermal oxide film. Then, after the resist is applied, exposure, development, and etching are performed using a photomask to form contact holes. Furthermore, on it, a Pd target was used and a sputtering method was used to form a film of 10 nm each in the order of Pd and PdO. Then, aqua regia was used to etch to form a guard ring so that the Pd/PdO layered part on the SiO 2 remained concentrically. Furthermore, IGZO, which is an oxide semiconductor, was formed into a film of 200 nm to form a pressure-resistant layer, and Mo was formed into a film, and finally annealed in air at 300° C. for 1 hour. The thermal oxide film on the back of the Si wafer is covered with a protective film and then removed by etching with dilute hydrofluoric acid. Thereafter, film formation is performed in the order of Ti, Ni, and Au.
將所獲得之積層體之Si晶圓側設為肖特基接合，而獲得附保護環及背面電極之肖特基勢壘二極體。 The Si wafer side of the obtained laminate was used as a Schottky junction to obtain a Schottky barrier diode with a guard ring and a back electrode.
對以此方式獲得之肖特基勢壘二極體之Si與Pd之界面的SiO2之膜厚進行評價，結果為0.2nm。再者，接觸孔為圓形，觀察圓之中心及與圓內接之正方形之各頂點之中間點共計5點，於將該視野等間隔地10等分之部位進行測定，從而將該共計55個部位之平均值設為SiO2層之膜厚。 The film thickness of SiO 2 at the interface between Si and Pd of the Schottky barrier diode obtained in this manner was evaluated, and the result was 0.2 nm. Furthermore, the contact hole is circular, and the center of the observation circle and the midpoints of the vertices of the square inscribed with the circle are 5 points in total. The field of view is measured at 10 equal intervals to obtain a total of 55 points. The average value of each part is taken as the film thickness of the SiO 2 layer.
準備膜厚500μm、直徑4英吋
繼而，作為肖特基電極，將Pd積層100nm，並藉由CMP對周邊之Pd層進行研磨直至出現SiO2面。將以此方式獲得之二極體之Ti基板側之背面與n型Si基板(直徑4英吋)設置於常溫晶圓接合裝置並進行接合。 Then, as a Schottky electrode, 100 nm of Pd was deposited, and the surrounding Pd layer was polished by CMP until the SiO 2 surface appeared. The back surface of the Ti substrate side of the diode obtained in this way and the n-type Si substrate (4 inches in diameter) were set in a normal temperature wafer bonding device and bonded.
所獲得之肖特基二極體雖於中途經由藉由電漿CVD進行之超過300℃之步驟，但使用線膨脹係數接近銦鎵鋅氧化物(IGZO)之Ti作為支持體，而未確認出翹曲或龜裂之產生。藉由與實施例17相同之評價法對存在於Ti與IGZO之界面之TiO2之膜厚進行測定，結果為0.5nm。 Although the obtained Schottky diode went through a step over 300°C by plasma CVD in the middle, it used Ti with a linear expansion coefficient close to that of indium gallium zinc oxide (IGZO) as a support, and no warpage was confirmed. The occurrence of kinks or cracks. The film thickness of TiO 2 existing at the interface between Ti and IGZO was measured by the same evaluation method as in Example 17, and the result was 0.5 nm.
又，藉由將Ti與Si貼合，切割、焊接、鋁線接合等後續步驟可直接使用先前之Si系肖特基二極體之步驟，從而於生產上有利。 In addition, by bonding Ti and Si, subsequent steps such as cutting, welding, and aluminum wire bonding can directly use the previous steps of Si-based Schottky diodes, which is advantageous in production.
包含本發明之積層體之元件可用作肖特基勢壘二極體或MOSFET等功率裝置或將其等組合而成之模組。具體而言，可用於反相器或轉換器等電力轉換電路、電源電路、以及使用其等之電路功率轉換器、IPM(Intelligent Power Module，智慧功率模組)、電器機器或車輛。又，進而亦可用於氧氣感測器、光觸媒、紫外感測器、紫外太陽電池、人體感測器、紫外二極體、紫外雷射等。 The device including the laminated body of the present invention can be used as a power device such as a Schottky barrier diode or a MOSFET, or a module formed by combining them. Specifically, it can be used in power conversion circuits such as inverters or converters, power supply circuits, and circuit power converters using them, IPM (Intelligent Power Module), electrical appliances, or vehicles. Furthermore, it can also be used for oxygen sensors, photocatalysts, ultraviolet sensors, ultraviolet solar cells, human body sensors, ultraviolet diodes, ultraviolet lasers, etc.
上述對若干本發明之實施形態及/或實施例進行了詳細說明，但業者容易於不實質上自本發明之新穎之教示及效果脫離之情況下，對該等作為例示之實施形態及/或實施例施加較多變更。因此，該等較多之變更係包含於本發明之範圍內。 A number of embodiments and/or embodiments of the present invention have been described in detail above, but it is easy for the industry to exemplify these embodiments and/or embodiments without substantially departing from the novel teachings and effects of the present invention. The embodiment imposes many changes. Therefore, these many changes are included in the scope of the present invention.
將成為本申請案之巴黎優先之基礎之日本申請案說明書的內容全部援引於此。 The contents of the Japanese application specification that will form the basis of the Paris priority of this application are all quoted here.
1:積層體 1: Layered body
10:Si層 10: Si layer
20:SiO2層 20: SiO 2 layer
30:金屬氧化物層 30: metal oxide layer
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| JP7165322B2 (en) * | 2018-03-30 | 2022-11-04 | Tdk株式会社 | schottky barrier diode |
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