TWI730869B - Line end structure and forming method thereof - Google Patents

Line end structure and forming method thereof Download PDF

Info

Publication number
TWI730869B
TWI730869B TW109126776A TW109126776A TWI730869B TW I730869 B TWI730869 B TW I730869B TW 109126776 A TW109126776 A TW 109126776A TW 109126776 A TW109126776 A TW 109126776A TW I730869 B TWI730869 B TW I730869B
Authority
TW
Taiwan
Prior art keywords
insulating
layer
substrate
wires
end structure
Prior art date
Application number
TW109126776A
Other languages
Chinese (zh)
Other versions
TW202207402A (en
Inventor
羅文彰
Original Assignee
力晶積成電子製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 力晶積成電子製造股份有限公司 filed Critical 力晶積成電子製造股份有限公司
Priority to TW109126776A priority Critical patent/TWI730869B/en
Priority to CN202010816535.1A priority patent/CN114068324A/en
Application granted granted Critical
Publication of TWI730869B publication Critical patent/TWI730869B/en
Publication of TW202207402A publication Critical patent/TW202207402A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A line end structure including a substrate, a plurality of circuits, and a first insulating pattern layer is provided. The circuits are disposed on the substrate. The first insulating pattern layer is disposed on the substrate. The first insulating pattern layer includes a plurality of first insulating parts and a second insulating part. The plurality of first insulating parts are disposed on the plurality of wires. The second insulating part connects the plurality of first insulating parts. A forming method of a line end structure is also provided.

Description

線路末端結構及其形成方法Line terminal structure and its forming method

本發明是有關於一種線路結構及其形成方法，且特別是有關於一種線路末端結構及其形成方法。 The present invention relates to a line structure and its forming method, and more particularly to a line terminal structure and its forming method.

在半導體的製程中，導線末端斷切(line end cut)的缺陷常會造成線路佈局失效(layout failed)。舉例而言，若相鄰的導線在其末端的附近有不預期的相連，則會因此造成不預期的短路而影響元件的品質。 In the semiconductor manufacturing process, the defect of the wire end cut (line end cut) often causes a layout failure (layout failed). For example, if adjacent wires are unexpectedly connected near their ends, it will cause unexpected short circuits and affect the quality of the device.

本發明提供一種線路末端結構及其形成方法，其具有較佳的品質。 The present invention provides a line terminal structure and a forming method thereof, which has better quality.

本發明的線路末端結構包括基板、多個導線以及第一絕緣圖案層。多個導線位於基板上。第一絕緣圖案層位於基板上。第一絕緣圖案層包括多個第一絕緣部分以及第二絕緣部分。多個第一絕緣部分分別位於多個導線上。第二絕緣部分係連接兩相鄰 的多個第一絕緣部分。第二絕緣部分與基板間未形成多個導線。 The line terminal structure of the present invention includes a substrate, a plurality of wires, and a first insulating pattern layer. Multiple wires are located on the substrate. The first insulating pattern layer is located on the substrate. The first insulating pattern layer includes a plurality of first insulating parts and second insulating parts. The plurality of first insulating parts are respectively located on the plurality of wires. The second insulating part connects two adjacent The multiple first insulating parts. Multiple wires are not formed between the second insulating part and the substrate.

在本發明的一實施例中，多個第一絕緣部分的厚度小於第二絕緣部分的厚度。 In an embodiment of the present invention, the thickness of the plurality of first insulating parts is smaller than the thickness of the second insulating part.

在本發明的一實施例中，多個第一絕緣部分的厚度與多個導線的厚度的總合相同於第二絕緣部分的厚度。 In an embodiment of the present invention, the sum of the thickness of the plurality of first insulating parts and the thickness of the plurality of wires is the same as the thickness of the second insulating part.

在本發明的一實施例中，多個第一絕緣部分的頂面與第二絕緣部分的頂面共面。 In an embodiment of the present invention, the top surfaces of the plurality of first insulating parts are coplanar with the top surfaces of the second insulating parts.

在本發明的一實施例中，多個第一絕緣部分覆蓋多個導線的頂面，且第二絕緣部分覆蓋多個導線的末端的側表面。 In an embodiment of the present invention, the plurality of first insulating parts cover the top surfaces of the plurality of wires, and the second insulating parts cover the side surfaces of the ends of the plurality of wires.

在本發明的一實施例中，第二絕緣部分包括向遠離多個導線的方向凸出的弧狀圖案。 In an embodiment of the present invention, the second insulating portion includes an arc-shaped pattern protruding in a direction away from the plurality of wires.

在本發明的一實施例中，第二絕緣部分的寬度大於或等於多個第一絕緣部分的寬度。 In an embodiment of the present invention, the width of the second insulating portion is greater than or equal to the width of the plurality of first insulating portions.

在本發明的一實施例中，線路末端結構更包括第二絕緣層。第二絕緣層至少位於多個導線之間。第二絕緣層覆蓋導線的相對二側面。 In an embodiment of the present invention, the line end structure further includes a second insulating layer. The second insulating layer is located at least between the plurality of wires. The second insulating layer covers two opposite sides of the wire.

在本發明的一實施例中，第二絕緣層更覆蓋第一絕緣圖案層的相對二側面。 In an embodiment of the present invention, the second insulating layer further covers two opposite sides of the first insulating pattern layer.

本發明的線路末端結構的形成方法包括以下步驟：提供基板；形成導電層於基板上；形成第一絕緣層於基板上，且第一絕緣層至少覆蓋導電層；移除部分的第一絕緣層，以形成第一絕緣圖案層，其中第一絕緣圖案層包括多個第一絕緣部分以及第二 絕緣部分，第二絕緣部分係連接兩相鄰的多個第一絕緣部分；以及移除部分的導電層，以形成多個導線，其中多個導線分別位於多個第一絕緣部分與基板之間，並且第二絕緣部分與基板間未形成多個導線。 The method for forming a line terminal structure of the present invention includes the following steps: providing a substrate; forming a conductive layer on the substrate; forming a first insulating layer on the substrate, and the first insulating layer covers at least the conductive layer; removing part of the first insulating layer , To form a first insulating pattern layer, wherein the first insulating pattern layer includes a plurality of first insulating parts and a second The insulating part, the second insulating part connects two adjacent first insulating parts; and removing part of the conductive layer to form a plurality of wires, wherein the plurality of wires are respectively located between the plurality of first insulating parts and the substrate And there are no multiple wires formed between the second insulating part and the substrate.

基於上述，線路末端結構的導線可以具有較佳的品質。 Based on the above, the wires of the line end structure can have better quality.

100、200:線路末端結構 100, 200: Line end structure

110:基板 110: substrate

111:第一區 111: District 1

112:第二區 112: District 2

113:第三區 113: District Three

120:絕緣層 120: Insulation layer

121、122:膜層 121, 122: Membrane

139:導電層 139: conductive layer

130、131、132:導線 130, 131, 132: wire

130h:厚度 130h: thickness

130a:第一側面 130a: first side

130b:第二側面 130b: second side

130c:第三側面 130c: third side

130d:頂面 130d: top surface

140:第一絕緣層 140: first insulating layer

140d:頂面 140d: top surface

141:部分第一絕緣層 141: Part of the first insulating layer

141h:厚度 141h: thickness

142:部分第一絕緣層 142: Part of the first insulating layer

142h:厚度 142h: thickness

151、152、153:膜層 151, 152, 153: film layer

155:罩幕層 155: mask layer

160:第一絕緣圖案層 160: first insulating pattern layer

160b、160c:側面 160b, 160c: side

160d:頂面 160d: top surface

161:第一絕緣部分 161: The first insulating part

161d:頂面 161d: top surface

161h:厚度 161h: thickness

162:第二絕緣部分 162: The second insulating part

162d:頂面 162d: top surface

162h:厚度 162h: thickness

270:第二絕緣層 270: second insulating layer

S:間距 S: Spacing

L1、L2、L3、L4:寬度 L1, L2, L3, L4: width

圖1A、圖2A、圖3A及圖4A是依照本發明的第一實施例的一種線路末端結構的部分形成方法的部分上視示意圖。 1A, 2A, 3A, and 4A are schematic partial top views of a method for partially forming a line end structure according to a first embodiment of the present invention.

圖1B、圖2B、圖3B及圖4B是依照本發明的第一實施例的一種線路末端結構的部分形成方法的部分剖視示意圖。 FIG. 1B, FIG. 2B, FIG. 3B, and FIG. 4B are schematic partial cross-sectional views of a method for partially forming a line terminal structure according to the first embodiment of the present invention.

圖1C、圖2C、圖3C、圖3D、圖4C及圖4D是依照本發明的第一實施例的一種線路末端結構的部分形成方法的部分剖視示意圖。 FIG. 1C, FIG. 2C, FIG. 3C, FIG. 3D, FIG. 4C, and FIG. 4D are schematic partial cross-sectional views of a method for partially forming a line terminal structure according to the first embodiment of the present invention.

圖5A是依照本發明的第二實施例的一種線路末端結構的部分上視示意圖。 FIG. 5A is a schematic partial top view of a line end structure according to the second embodiment of the present invention.

圖5B及圖5C是依照本發明的第二實施例的一種線路末端結構的部分剖視示意圖。 5B and 5C are schematic partial cross-sectional views of a line terminal structure according to the second embodiment of the present invention.

下文列舉一些實施例並配合所附圖式來進行詳細地說 明，但所提供的實施例並非用以限制本發明所涵蓋的範圍。此外，圖式僅以說明為目的，並未依照原尺寸作圖。為了方便理解，下述說明中相同的元件將以相同之符號標示來說明。另外，關於文中所使用「包括」或「具有」等等用語，均為開放性的用語；也就是指「包括」或「具有」但不限於。 Here are some embodiments and will be described in detail with the accompanying drawings. However, the provided embodiments are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only, and are not drawn in accordance with the original dimensions. To facilitate understanding, the same elements in the following description will be described with the same symbols. In addition, the terms "including" or "having" used in the text are all open terms; that is, "including" or "having" but not limited to them.

關於文中所使用「基本上」或「大致上」等等用語，可以是包含可接受的公差範圍(tolerance range)。而且，文中所提到的方向性用語，例如：「上」、「下」、「頂」、「底」等，僅是用以參考圖式的方向。因此，使用的方向性用語是用來說明，而並非用來限制本發明。 Regarding terms such as "basically" or "approximately" used in the text, it may include an acceptable tolerance range. Moreover, the directional terms mentioned in the text, such as "upper", "lower", "top", "bottom", etc., are only used to refer to the direction of the schema. Therefore, the directional terms used are used to illustrate, but not to limit the present invention.

當一元件(如：一膜層、一區域或一其他類似的用語)被稱為在「另一元件上」或「連接到另一元件」時，其可以直接在另一元件上或與另一元件連接，或其之間也可存在其他的元件。類似地，當一步驟(如：一製程或一其他類似的用語)被稱為在「另一步驟之後」時，其可以直接在另一步驟之後執行，或其之間也可存在其他的步驟。 When an element (such as a film, a region, or a similar term) is referred to as being "on" or "connected to another element," it can be directly on or with another element. One element is connected, or there may be other elements between them. Similarly, when a step (such as a process or a similar term) is called "after another step", it can be performed directly after another step, or there may be other steps in between. .

圖1A、圖2A、圖3A及圖4A是依照本發明的第一實施例的一種線路末端結構的部分形成方法的部分上視示意圖。圖1B可以是對應於圖1A中A-A’剖線上的剖視示意圖。圖1C可以是對應於圖1A中B-B’剖線或C-C’剖線上的剖視示意圖。圖2B可以是對應於圖2A中D-D’剖線上的剖視示意圖。圖2C可以是對應於圖2A中E-E’剖線或F-F’剖線上的剖視示意圖。圖3B可以是對應於 圖3A中G-G’剖線上的剖視示意圖。圖3C可以是對應於圖3A中H-H’剖線上的剖視示意圖。圖3D可以是對應於圖3A中J-J’剖線上的剖視示意圖。圖4B可以是對應於圖4A中K-K’剖線上的剖視示意圖。圖4C可以是對應於圖4A中L-L’剖線上的剖視示意圖。圖4D可以是對應於圖4A中M-M’剖線上的剖視示意圖。另外，剖線A-A’、剖線D-D’、剖線G-G’及/或剖線K-K’對應於基板110的位置可以相同或相似，剖線B-B’、剖線E-E’、剖線H-H’及/或剖線L-L’對應於基板110的位置可以相同或相似，剖線C-C’、剖線F-F’、剖線J-J’及/或剖線M-M’對應於基板110的位置可以相同或相似。 1A, 2A, 3A, and 4A are schematic partial top views of a method for partially forming a line end structure according to a first embodiment of the present invention. Fig. 1B may be a schematic cross-sectional view corresponding to the A-A' section line in Fig. 1A. Fig. 1C may be a schematic cross-sectional view corresponding to the section line B-B' or the section line C-C' in Fig. 1A. Fig. 2B may be a schematic cross-sectional view corresponding to the line D-D' in Fig. 2A. FIG. 2C may be a schematic cross-sectional view corresponding to the E-E' section line or the F-F' section line in FIG. 2A. Figure 3B may correspond to A schematic cross-sectional view on the G-G' section line in Fig. 3A. Fig. 3C may be a schematic cross-sectional view corresponding to the section line H-H' in Fig. 3A. Fig. 3D may be a schematic cross-sectional view corresponding to the J-J' section line in Fig. 3A. Fig. 4B may be a schematic cross-sectional view corresponding to the K-K' section line in Fig. 4A. Fig. 4C may be a schematic cross-sectional view corresponding to the line L-L' in Fig. 4A. Fig. 4D may be a schematic cross-sectional view corresponding to the M-M' section line in Fig. 4A. In addition, the position of the section line A-A', the section line D-D', the section line G-G' and/or the section line K-K' corresponding to the substrate 110 may be the same or similar, and the section line B-B', the section line The position of the line E-E', the section line H-H' and/or the section line L-L' corresponding to the substrate 110 may be the same or similar, the section line C-C', the section line F-F', and the section line J- The positions of J'and/or section line M-M' corresponding to the substrate 110 may be the same or similar.

請參照圖1A、圖1B及圖1C，提供基板110。基板110可以具有第一區111、第二區112以及第三區113。第二區112位於第一區111與第三區113之間。第一區111與第三區113可以分別連接於第二區112的兩不同側。 Please refer to FIG. 1A, FIG. 1B and FIG. 1C, a substrate 110 is provided. The substrate 110 may have a first area 111, a second area 112 and a third area 113. The second area 112 is located between the first area 111 and the third area 113. The first area 111 and the third area 113 may be connected to two different sides of the second area 112 respectively.

在本實施例中，基板110可以包括矽質基板或其他類似的半導體基板，但本發明不限於此。舉例而言，基板110可以包括矽晶圓。 In this embodiment, the substrate 110 may include a silicon substrate or other similar semiconductor substrates, but the invention is not limited thereto. For example, the substrate 110 may include a silicon wafer.

請參照圖1A、圖1B及圖1C，於基板110的第一區111上形成導電層139。導電層139可以藉由濺鍍(sputtering)、沉積(deposition)、電鍍(plating)及/或其他適宜的製程所形成，但本發明不限於此。在本實施例中，導電層139基本上不覆蓋於基板110的第二區112或第三區113上。基於導電性的考量，導電 層139的材質可以包括金屬、金屬合金、金屬矽化物、金屬氮化物或上述之堆疊，然本發明不限於此。 1A, 1B, and 1C, a conductive layer 139 is formed on the first region 111 of the substrate 110. The conductive layer 139 may be formed by sputtering, deposition, plating and/or other suitable processes, but the invention is not limited thereto. In this embodiment, the conductive layer 139 basically does not cover the second region 112 or the third region 113 of the substrate 110. Based on the consideration of conductivity, conductive The material of the layer 139 may include metal, metal alloy, metal silicide, metal nitride, or a stack of the above, but the present invention is not limited thereto.

在本實施例中，可以於基板110上形成絕緣層120，且導電層139可以形成於絕緣層120上。也就是說，部分的絕緣層120可以位於導電層139與基板110之間。 In this embodiment, the insulating layer 120 may be formed on the substrate 110, and the conductive layer 139 may be formed on the insulating layer 120. That is, part of the insulating layer 120 may be located between the conductive layer 139 and the substrate 110.

在一實施例中，絕緣層120可以藉由沉積製程或其他適宜的製程而形成，但本發明不限於此。在一實施例中，絕緣層120的材質可以包括矽的氧化物、矽的氮化物或上述之組合，但本發明不限於此。 In an embodiment, the insulating layer 120 may be formed by a deposition process or other suitable processes, but the invention is not limited thereto. In an embodiment, the material of the insulating layer 120 may include silicon oxide, silicon nitride, or a combination of the above, but the invention is not limited thereto.

在本實施例中，絕緣層120可以包括多個膜層121、122，但本發明不限於此。在一實施例中，絕緣層120可以為單層結構。 In this embodiment, the insulating layer 120 may include a plurality of film layers 121 and 122, but the present invention is not limited to this. In an embodiment, the insulating layer 120 may have a single-layer structure.

在一未繪示的實施例中，膜層121或膜層122在基板110上其他未繪示的區域中，可能具有其他相同或不同的用途。舉例而言，膜層121可以包括用於將基板110與其上的元件相分離的氧化矽(Silicon dioxide；SiOx)層，但本發明不限於此。又舉例而言，膜層122可以包括作為硬遮罩(hard mask；HM)層。 In an unshown embodiment, the film layer 121 or the film layer 122 may have other same or different uses in other unshown areas on the substrate 110. For example, the film layer 121 may include a silicon dioxide (SiO x ) layer for separating the substrate 110 from the components thereon, but the present invention is not limited thereto. For another example, the film layer 122 may be included as a hard mask (HM) layer.

在一實施例中，絕緣層120可以包括被稱為緩衝層(buffer layer)的膜層，但本發明不限於此。 In an embodiment, the insulating layer 120 may include a film layer called a buffer layer, but the present invention is not limited thereto.

請參照圖2A、圖2B及圖2C，至少於基板110的第一區111及第二區112上形成第一絕緣層140。第一絕緣層140覆蓋導電層139。 2A, 2B, and 2C, a first insulating layer 140 is formed on at least the first region 111 and the second region 112 of the substrate 110. The first insulating layer 140 covers the conductive layer 139.

在本實施例中，第一絕緣層140可以更位於基板110的 第三區113上，但本發明不限於此。 In this embodiment, the first insulating layer 140 may be more located on the substrate 110 On the third area 113, but the present invention is not limited to this.

在本實施例中，第一絕緣層140的頂面140d可以為一平坦表面，但本發明不限於此。舉例而言，可以藉由相同或相似於絕緣層120的形成方式，於基板110上形成第一絕緣材料層(未繪示)。然後，可以對前述的第一絕緣材料層實施化學機械平坦化製程(Chemical-mechanical polishing process；CMP process)或其他適宜的平坦化製程(planarization process)，而形成具有平坦的頂面140d的第一絕緣層140。 In this embodiment, the top surface 140d of the first insulating layer 140 may be a flat surface, but the invention is not limited to this. For example, the first insulating material layer (not shown) can be formed on the substrate 110 by the same or similar formation method of the insulating layer 120. Then, a chemical-mechanical polishing process (CMP process) or other suitable planarization process (planarization process) may be performed on the aforementioned first insulating material layer to form a first flat top surface 140d. Insulation layer 140.

在本實施例中，覆蓋於導電層139上的部分第一絕緣層141的厚度141h可能不同於其他某處(如：未覆蓋導電層139之處)的其他部分第一絕緣層142的厚度142h。舉例而言，厚度141h可能小於厚度142h。 In this embodiment, the thickness 141h of the part of the first insulating layer 141 covering the conductive layer 139 may be different from the thickness 142h of the other part of the first insulating layer 142 somewhere else (for example, where the conductive layer 139 is not covered) . For example, the thickness 141h may be less than the thickness 142h.

在一實施例中，第一絕緣層140可以包括被稱為平坦層(planarizing layer)的膜層，但本發明不限於此。 In an embodiment, the first insulating layer 140 may include a film layer called a planarizing layer, but the present invention is not limited thereto.

請參照圖3A、圖3B、圖3C及圖3D，可以於基板110上形成罩幕層155。罩幕層155可以重疊於部分的導電層139及部分的第一絕緣層140，且罩幕層155的材質基本上不同於導電層139及第一絕緣層140。舉例而言，罩幕層155可以包括藉由沉積及微影蝕刻的方式所形成的圖案化非晶矽層，但本發明不限於此。 Referring to FIGS. 3A, 3B, 3C, and 3D, a mask layer 155 may be formed on the substrate 110. The mask layer 155 may overlap a part of the conductive layer 139 and a part of the first insulating layer 140, and the material of the mask layer 155 is basically different from that of the conductive layer 139 and the first insulating layer 140. For example, the mask layer 155 may include a patterned amorphous silicon layer formed by deposition and photolithography, but the invention is not limited thereto.

請參照圖3A至圖4A、圖3B至圖4B、圖3C至圖4C及圖3D至圖4D，在一實施例中，可以藉由蝕刻或其他適宜的方式，以移除位於第一絕緣層140上且未被罩幕層155覆蓋的部分膜層 151、152、153。 Please refer to FIGS. 3A to 4A, 3B to 4B, 3C to 4C, and 3D to 4D. In one embodiment, the first insulating layer can be removed by etching or other suitable methods. Part of the film on 140 that is not covered by the mask layer 155 151, 152, 153.

在一未繪示的實施例中，膜層151、膜層152或膜層153在基板110上其他未繪示的區域中，可能具有其他相同或不同的用途。 In an unillustrated embodiment, the film layer 151, the film layer 152, or the film layer 153 may have other same or different uses in other unillustrated areas on the substrate 110.

請參照圖3A至圖4A、圖3B至圖4B、圖3C至圖4C及圖3D至圖4D，移除部分的第一絕緣層140，以形成第一絕緣圖案層160。第一絕緣圖案層160包括多個第一絕緣部分161以及第二絕緣部分162。多個第一絕緣部分161位於第一區111。第二絕緣部分162位於第二區112。第二絕緣部分162連接多個第一絕緣部分161。 Referring to FIGS. 3A to 4A, 3B to 4B, 3C to 4C, and 3D to 4D, a portion of the first insulating layer 140 is removed to form the first insulating pattern layer 160. The first insulating pattern layer 160 includes a plurality of first insulating parts 161 and second insulating parts 162. The plurality of first insulating portions 161 are located in the first region 111. The second insulating portion 162 is located in the second region 112. The second insulating part 162 connects the plurality of first insulating parts 161.

在本實施例中，可以藉由蝕刻(如：乾蝕刻(dry etching)，但不限)或其他適宜的方式移除未被罩幕層155覆蓋的部分第一絕緣層140，但本發明不限於此。 In this embodiment, the part of the first insulating layer 140 that is not covered by the mask layer 155 can be removed by etching (such as dry etching, but not limited) or other suitable methods, but the invention is not limited to this.

在本實施例中，第一絕緣圖案層160的圖案可以相同或相似於罩幕層155的圖案。也就是說，第一絕緣圖案層160的圖案至少可以依據罩幕層155的圖案設計而進行調整，於本發明並不加以限制。 In this embodiment, the pattern of the first insulating pattern layer 160 may be the same or similar to the pattern of the mask layer 155. In other words, the pattern of the first insulating pattern layer 160 can be adjusted at least according to the pattern design of the mask layer 155, which is not limited in the present invention.

請參照圖3A至圖4A、圖3B至圖4B、圖3C至圖4C及圖3D至圖4D，移除部分的導電層139，以形成多個導線130。多個導線130位於多個第一絕緣部分161與基板110之間。舉例而言，各個導線130位於各個第一絕緣部分161與基板110之間。 Please refer to FIGS. 3A to 4A, 3B to 4B, 3C to 4C, and 3D to 4D to remove part of the conductive layer 139 to form a plurality of wires 130. The plurality of wires 130 are located between the plurality of first insulating portions 161 and the substrate 110. For example, each wire 130 is located between each first insulating portion 161 and the substrate 110.

在本實施例中，可以藉由蝕刻(如：乾蝕刻(dry etching)， 但不限)或其他適宜的方式移除未被罩幕層155覆蓋的部分導電層139，但本發明不限於此。 In this embodiment, etching (such as dry etching) can be used to But not limited to) or other suitable methods to remove part of the conductive layer 139 that is not covered by the mask layer 155, but the present invention is not limited to this.

在本實施例中，導線130的圖案可以相同或相似於罩幕層155的部分圖案。也就是說，導線130的圖案至少可以依據罩幕層155的圖案設計而進行調整，於本發明並不加以限制。 In this embodiment, the pattern of the wire 130 may be the same or similar to a part of the pattern of the mask layer 155. In other words, the pattern of the wire 130 can be adjusted at least according to the pattern design of the mask layer 155, which is not limited in the present invention.

在一實施例中，於形成第一絕緣圖案層160及多個導線130之後，可以移除罩幕層155。舉例而言，可以藉由移除第一絕緣圖案層160與罩幕層155之間的膜層(如：將膜層151圖案化後的膜層)，以移除罩幕層155。 In one embodiment, after the first insulating pattern layer 160 and the plurality of wires 130 are formed, the mask layer 155 may be removed. For example, the mask layer 155 can be removed by removing the film layer between the first insulating pattern layer 160 and the mask layer 155 (eg, the film layer after patterning the film layer 151).

在一實施例中，於移除部分的導電層139或移除罩幕層155的過程(如：將第一絕緣圖案層160與罩幕層155之間的膜層移除的過程)中，部分的絕緣層120可能被些微地移除，但本發明不限於此。 In one embodiment, in the process of removing part of the conductive layer 139 or removing the mask layer 155 (for example, the process of removing the film layer between the first insulating pattern layer 160 and the mask layer 155), Part of the insulating layer 120 may be slightly removed, but the invention is not limited to this.

經過上述形成方法後即可大致上完成本實施例之線路末端結構100的製作。 After the above-mentioned forming method, the fabrication of the line terminal structure 100 of this embodiment can be substantially completed.

請參照圖4A、圖4B、圖4C及圖4D，線路末端結構100包括基板110、多個導線130以及第一絕緣圖案層160。基板110具有第一區111及第二區112。第二區112相連於第一區111。多個導線130位於基板110的第一區111上。第一絕緣圖案層160包括多個第一絕緣部分161以及第二絕緣部分162。第一絕緣部分161位於基板110的第一區111上。多個導線130位於多個第一絕緣部分161與基板110之間。第二絕緣部分162位於基板110的 第二區112上。第二絕緣部分162連接多個第一絕緣部分161。 Referring to FIGS. 4A, 4B, 4C, and 4D, the line end structure 100 includes a substrate 110, a plurality of wires 130, and a first insulating pattern layer 160. The substrate 110 has a first area 111 and a second area 112. The second area 112 is connected to the first area 111. The plurality of wires 130 are located on the first area 111 of the substrate 110. The first insulating pattern layer 160 includes a plurality of first insulating parts 161 and second insulating parts 162. The first insulating portion 161 is located on the first region 111 of the substrate 110. The plurality of wires 130 are located between the plurality of first insulating portions 161 and the substrate 110. The second insulating portion 162 is located on the substrate 110 On the second area 112. The second insulating part 162 connects the plurality of first insulating parts 161.

在本實施例中，藉由上述形成方法所形成的線路末端結構100，可以降低相鄰的導線130產生不預期地相接觸的可能，因此導線130具有較佳的品質。舉例而言，多個導線130可以包括相鄰的導線131及導線132，且導線131及導線132可以彼此分離。 In this embodiment, the line end structure 100 formed by the above-mentioned forming method can reduce the possibility of unintended contact between adjacent wires 130, so the wires 130 have better quality. For example, the plurality of wires 130 may include adjacent wires 131 and 132, and the wires 131 and the wires 132 may be separated from each other.

在本實施例中，藉由上述形成方法所形成的線路末端結構100可以用於具有高密度線路的電子元件。舉例而言，導線130可以為位元線(bit line；BL)，且相鄰的導線130之間的間距S可以小於或等於70奈米(nanometer；nm)，但本發明不限於此。在一實施例中，相鄰的導線130之間的間距S可以小於或等於60奈米。 In this embodiment, the circuit end structure 100 formed by the above-mentioned forming method can be used for electronic components with high-density circuits. For example, the wire 130 may be a bit line (BL), and the distance S between adjacent wires 130 may be less than or equal to 70 nanometers (nm), but the present invention is not limited thereto. In an embodiment, the spacing S between adjacent conductive lines 130 may be less than or equal to 60 nanometers.

在本實施例中，第一絕緣圖案層160可以提供導線130良好的保護，或是，可以降低導線130與其他導體產生不預期地相接觸的可能。 In this embodiment, the first insulating pattern layer 160 can provide good protection for the wire 130, or it can reduce the possibility of the wire 130 being in unexpected contact with other conductors.

在本實施例中，藉由第二絕緣部分162將多個第一絕緣部分161連接，可以降低第一絕緣部分161傾倒或剝離(peeling)的可能。 In this embodiment, the plurality of first insulating parts 161 are connected by the second insulating part 162 to reduce the possibility of the first insulating part 161 toppling or peeling.

在本實施例中，第二絕緣部分162的寬度可以大於或等於第一絕緣部分161的寬度L1。舉例而言，第二絕緣部分162與第一絕緣部分161相接之處的寬度可以大致上等於第一絕緣部分161的寬度L1，而第二絕緣部分162遠離第一絕緣部分161處的寬度(如：寬度L2、寬度L3或寬度L4)可以大於第一絕緣部分 161的寬度L1。在本實施例中，第一絕緣部分161的寬度L1大致上等於導線130的寬度。 In this embodiment, the width of the second insulating part 162 may be greater than or equal to the width L1 of the first insulating part 161. For example, the width where the second insulating part 162 meets the first insulating part 161 may be substantially equal to the width L1 of the first insulating part 161, and the width of the second insulating part 162 away from the first insulating part 161 ( For example: the width L2, the width L3 or the width L4) can be larger than the first insulating part 161 width L1. In this embodiment, the width L1 of the first insulating portion 161 is substantially equal to the width of the wire 130.

在本實施例中，第二絕緣部分162的寬度可以自與第一絕緣部分161相接之處向遠離第一絕緣部分161的延伸方向逐漸增加。舉例而言，寬度L4可以大於寬度L3，且寬度L3可以大於寬度L2。如此一來，可以降低第二絕緣部分162傾倒或剝離的可能。 In this embodiment, the width of the second insulating portion 162 may gradually increase from the point where it is in contact with the first insulating portion 161 to the extending direction away from the first insulating portion 161. For example, the width L4 may be greater than the width L3, and the width L3 may be greater than the width L2. In this way, it is possible to reduce the possibility of the second insulating portion 162 toppling or peeling off.

在本實施例中，第二絕緣部分162包括向遠離所述多個導線的方向凸出的弧狀圖案。如此一來，更可以降低第二絕緣部分162傾倒或剝離的可能。 In this embodiment, the second insulating portion 162 includes an arc-shaped pattern protruding in a direction away from the plurality of wires. In this way, the possibility of the second insulating portion 162 toppling or peeling can be reduced.

在本實施例中，基板110可以更具有第三區113。多個導線130及第一絕緣圖案層160可以位於第三區113以外的區域上。 In this embodiment, the substrate 110 may further have a third region 113. The plurality of conductive lines 130 and the first insulating pattern layer 160 may be located on a region other than the third region 113.

在本實施例中，第一絕緣部分161的厚度161h小於第二絕緣部分162的厚度162h。 In this embodiment, the thickness 161h of the first insulating portion 161 is smaller than the thickness 162h of the second insulating portion 162.

在本實施例中，第一絕緣部分161的厚度161h與導線130的厚度130h的總合基本上相同於第二絕緣部分162的厚度162h。舉例而言，一導線130的厚度130h以及前述導線130上方的第一絕緣部分161的厚度161h的總合，可以相同於第二絕緣部分162的厚度162h。 In this embodiment, the sum of the thickness 161h of the first insulating portion 161 and the thickness 130h of the wire 130 is substantially the same as the thickness 162h of the second insulating portion 162. For example, the sum of the thickness 130h of the wire 130 and the thickness 161h of the first insulating portion 161 above the wire 130 may be the same as the thickness 162h of the second insulating portion 162.

在本實施例中，第一絕緣部分161的頂面161d基本上與第二絕緣部分162的頂面162d共面。 In this embodiment, the top surface 161d of the first insulating portion 161 is substantially coplanar with the top surface 162d of the second insulating portion 162.

在本實施例中，導線130可以具有頂面130d、第一側面 130a、第二側面130b以及第三側面130c。頂面130d可以是在導線130中遠離基板110的表面。第一側面130a可以是導線130末端的側表面。頂面130d連接第一側面130a、第二側面130b以及第三側面130c。第一側面130a連接頂面130d、第二側面130b以及第三側面130c。第二側面130b相對於第三側面130c。第一絕緣部分161可以覆蓋對應的導線130的頂面130d。第二絕緣部分162可以覆蓋對應的導線130的第一側面130a。在一實施例中，導線130的第二側面130b以及第三側面130c可以不被第一絕緣圖案層160所覆蓋。 In this embodiment, the wire 130 may have a top surface 130d and a first side surface. 130a, the second side 130b, and the third side 130c. The top surface 130 d may be a surface away from the substrate 110 in the wire 130. The first side 130a may be a side surface of the end of the wire 130. The top surface 130d connects the first side surface 130a, the second side surface 130b, and the third side surface 130c. The first side surface 130a is connected to the top surface 130d, the second side surface 130b, and the third side surface 130c. The second side 130b is opposite to the third side 130c. The first insulating portion 161 may cover the top surface 130 d of the corresponding wire 130. The second insulating portion 162 may cover the first side surface 130 a of the corresponding wire 130. In an embodiment, the second side 130b and the third side 130c of the wire 130 may not be covered by the first insulating pattern layer 160.

圖5A是依照本發明的第二實施例的一種線路末端結構的部分上視示意圖。圖5B可以是對應於圖5A中N-N’剖線上的剖視示意圖。圖5B可以是對應於圖5A中P-P’剖線上的剖視示意圖。第二實施例的線路末端結構200的形成方法與第一實施例的線路末端結構100的形成方法相似，其類似的構件以相同的標號表示，且具有類似的功能、材質或形成步驟，並省略描述。 FIG. 5A is a schematic partial top view of a line end structure according to the second embodiment of the present invention. Fig. 5B may be a schematic cross-sectional view corresponding to the line N-N' in Fig. 5A. Fig. 5B may be a schematic cross-sectional view corresponding to the line P-P' in Fig. 5A. The formation method of the line end structure 200 of the second embodiment is similar to the formation method of the line end structure 100 of the first embodiment, and similar components are denoted by the same reference numerals, and have similar functions, materials or forming steps, and are omitted description.

請參照圖5A、圖5B及圖5C，線路末端結構200包括基板110、多個導線130、第一絕緣圖案層160以及第二絕緣層270。第二絕緣層270至少位於多個導線130之間。第二絕緣層270可以覆蓋導線130的第二側面130b及/或第三側面130c。 Referring to FIGS. 5A, 5B, and 5C, the line end structure 200 includes a substrate 110, a plurality of wires 130, a first insulating pattern layer 160, and a second insulating layer 270. The second insulating layer 270 is located at least between the plurality of wires 130. The second insulating layer 270 may cover the second side 130b and/or the third side 130c of the wire 130.

在本實施例中，可以藉由沉積製程或其他適宜的製程，以於基板110上形成第二絕緣層270。 In this embodiment, the second insulating layer 270 can be formed on the substrate 110 by a deposition process or other suitable processes.

在本實施例中，第二絕緣層270可以更位於基板110的 第三區113上。 In this embodiment, the second insulating layer 270 may be more located on the substrate 110 On the third area 113.

在本實施例中，第二絕緣層270可以覆蓋第一絕緣圖案層160的相對兩側面160b、160c。 In this embodiment, the second insulating layer 270 may cover the opposite side surfaces 160 b and 160 c of the first insulating pattern layer 160.

在本實施例中，第二絕緣層270可以降低第一絕緣圖案層160傾倒或剝離(peeling)的可能。 In this embodiment, the second insulating layer 270 can reduce the possibility of the first insulating pattern layer 160 toppling or peeling.

在本實施例中，第二絕緣層270與第一絕緣圖案層160可以是在不同的步驟中所形成。因此，第二絕緣層270與第一絕緣圖案層160之間可以具有對應的界面(interface)。 In this embodiment, the second insulating layer 270 and the first insulating pattern layer 160 may be formed in different steps. Therefore, there may be a corresponding interface between the second insulating layer 270 and the first insulating pattern layer 160.

在本實施例中，第二絕緣層270可以更覆蓋第一絕緣圖案層160的頂面160d。在一實施例中，可以在第二絕緣層270上形成其他的元件或膜層。 In this embodiment, the second insulating layer 270 may further cover the top surface 160d of the first insulating pattern layer 160. In an embodiment, other elements or film layers may be formed on the second insulating layer 270.

在一未繪的實施例中，於前述圖式中的膜層於基板110的其他未繪示區域上，可以具有相同、相似或不同的圖案；或是，不會出現於基板110的其他未繪示區域上。舉例而言，導線130在其他未繪示的區域上，可能包括曲線的條紋。 In an unillustrated embodiment, the film in the foregoing figures may have the same, similar or different patterns on other unillustrated areas of the substrate 110; or, it may not appear on other unillustrated areas of the substrate 110. Draw on the area. For example, the wire 130 may include curved stripes on other areas not shown.

在一未繪的實施例中，在兩步驟之間可能會有其他未繪示或說明的步驟。舉例而言，在完成圖2A、圖2B及圖2C所繪示的結構之後，以及在形成圖3A、圖3B、圖3C及圖3D所繪示的結構之前，可能會在基板110上形成、圖案化及/或移除其他的膜層。 In an unillustrated embodiment, there may be other unillustrated or illustrated steps between the two steps. For example, after the structures shown in FIGS. 2A, 2B, and 2C are completed, and before the structures shown in FIGS. 3A, 3B, 3C, and 3D are formed, the substrate 110 may be formed, Pattern and/or remove other layers.

在一未繪的實施例中，於基板110的其他未繪示區域上，可以具有其他的膜層或構件。舉例而言，在圖4A、圖4B、圖4C 及圖4D的基板110的其他未繪示區域上，可以包括由一個或多個的導電層、半導電層及/或絕緣層所構成主動元件(如：薄膜電晶體)、被動元件(如：電容)或其他適宜的元件。 In an unillustrated embodiment, other films or components may be provided on other unillustrated regions of the substrate 110. For example, in Figure 4A, Figure 4B, and Figure 4C And other areas not shown on the substrate 110 in FIG. 4D may include active components (such as thin film transistors) and passive components (such as: Capacitor) or other suitable components.

在前述實施例(包括所繪示的實施例、所描述的實施例或未繪示的實施例)中，導電層可為單層或多層結構。而若為多層結構的導電層，則前述的多層結構之間可以不具有絕緣材質。 In the foregoing embodiments (including the illustrated embodiment, the described embodiment, or the unillustrated embodiment), the conductive layer may be a single-layer or multi-layer structure. If it is a conductive layer with a multi-layer structure, the aforementioned multi-layer structure may not have an insulating material between them.

在前述實施例(包括所繪示的實施例、所描述的實施例或未繪示的實施例)中，絕緣層可為單層或多層結構。而若為多層結構的絕緣層，則前述的多層結構之間可以不具有導電材質。 In the foregoing embodiments (including the illustrated embodiment, the described embodiment, or the unillustrated embodiment), the insulating layer may be a single-layer or multi-layer structure. If it is an insulating layer with a multi-layer structure, the aforementioned multi-layer structure may not have conductive materials between them.

綜上所述，本發明的線路末端結構及其形成方法，可以使其導線具有較佳的品質。 In summary, the circuit terminal structure and the method for forming the circuit terminal of the present invention can make the wires have better quality.

100:線路末端結構 100: Line end structure

111:第一區 111: District 1

112:第二區 112: Second District

113:第三區 113: District Three

122:膜層 122: Membrane

130、131、132:導線 130, 131, 132: wire

130a:第一側面 130a: first side

130b:第二側面 130b: second side

130c:第三側面 130c: third side

130d:頂面 130d: top surface

160:第一絕緣圖案層 160: first insulating pattern layer

161:第一絕緣部分 161: The first insulating part

162:第二絕緣部分 162: The second insulating part

L4:寬度 L4: width

Claims (10)

一種線路末端結構，包括：基板；多個導線，位於所述基板上；以及第一絕緣圖案層，位於所述基板上，且所述第一絕緣圖案層包括：多個第一絕緣部分，分別位於所述多個導線上；以及第二絕緣部分，係連接兩相鄰的所述多個第一絕緣部分，其中所述第二絕緣部分與所述基板間未形成所述多個導線。 A line terminal structure includes: a substrate; a plurality of wires located on the substrate; and a first insulating pattern layer located on the substrate, and the first insulating pattern layer includes: a plurality of first insulating parts, respectively Located on the plurality of conductive lines; and a second insulating part connecting two adjacent first insulating parts, wherein the plurality of conductive lines are not formed between the second insulating part and the substrate. 如請求項1所述的線路末端結構，其中所述多個第一絕緣部分的厚度小於所述第二絕緣部分的厚度。 The line end structure according to claim 1, wherein the thickness of the plurality of first insulating parts is smaller than the thickness of the second insulating part. 如請求項2所述的線路末端結構，其中所述多個第一絕緣部分的厚度與所述多個導線的厚度的總合相同於所述第二絕緣部分的厚度。 The line end structure according to claim 2, wherein the sum of the thickness of the plurality of first insulating parts and the thickness of the plurality of wires is the same as the thickness of the second insulating part. 如請求項1所述的線路末端結構，其中所述多個第一絕緣部分的頂面與所述第二絕緣部分的頂面共面。 The line end structure according to claim 1, wherein the top surfaces of the plurality of first insulating parts are coplanar with the top surfaces of the second insulating parts. 如請求項1所述的線路末端結構，其中所述多個第一絕緣部分覆蓋所述多個導線的頂面，且所述第二絕緣部分覆蓋所述多個導線的末端的側表面。 The line end structure according to claim 1, wherein the plurality of first insulating portions cover the top surfaces of the plurality of wires, and the second insulating portions cover the side surfaces of the ends of the plurality of wires. 如請求項1所述的線路末端結構，其中所述第二絕緣部分包括向遠離所述多個導線的方向凸出的弧狀圖案。 The line end structure according to claim 1, wherein the second insulating portion includes an arc-shaped pattern protruding in a direction away from the plurality of wires. 如請求項1所述的線路末端結構，其中所述第二絕緣部分的寬度大於或等於所述多個第一絕緣部分的寬度。 The line end structure according to claim 1, wherein the width of the second insulating portion is greater than or equal to the width of the plurality of first insulating portions. 如請求項1所述的線路末端結構，更包括：第二絕緣層，至少位於所述多個導線之間，且所述第二絕緣層覆蓋所述多個導線的相對二側面。 The line end structure according to claim 1, further comprising: a second insulating layer at least located between the plurality of wires, and the second insulating layer covers two opposite sides of the plurality of wires. 如請求項8所述的線路末端結構，其中所述第二絕緣層更覆蓋所述第一絕緣圖案層的相對二側面。 The line end structure according to claim 8, wherein the second insulating layer further covers two opposite sides of the first insulating pattern layer. 一種線路末端結構的形成方法，包括：提供基板；形成導電層於所述基板上；形成第一絕緣層於所述基板上，且所述第一絕緣層至少覆蓋所述導電層；以及移除部分的所述第一絕緣層，以形成第一絕緣圖案層，其中第一絕緣圖案層包括多個第一絕緣部分以及第二絕緣部分，並且所述第二絕緣部分係連接兩相鄰的所述多個第一絕緣部分；以及移除部分的所述導電層，以形成多個導線，其中所述多個導線分別位於所述多個第一絕緣部分與所述基板之間，並且所述第二絕緣部分與所述基板間未形成所述多個導線。 A method for forming a line terminal structure includes: providing a substrate; forming a conductive layer on the substrate; forming a first insulating layer on the substrate, and the first insulating layer at least covers the conductive layer; and removing Part of the first insulating layer to form a first insulating pattern layer, wherein the first insulating pattern layer includes a plurality of first insulating parts and a second insulating part, and the second insulating part is connected to two adjacent The plurality of first insulating portions; and removing part of the conductive layer to form a plurality of wires, wherein the plurality of wires are respectively located between the plurality of first insulating portions and the substrate, and the The plurality of wires are not formed between the second insulating part and the substrate.
TW109126776A 2020-08-07 2020-08-07 Line end structure and forming method thereof TWI730869B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW109126776A TWI730869B (en) 2020-08-07 2020-08-07 Line end structure and forming method thereof
CN202010816535.1A CN114068324A (en) 2020-08-07 2020-08-14 Line end structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW109126776A TWI730869B (en) 2020-08-07 2020-08-07 Line end structure and forming method thereof

Publications (2)

Publication Number Publication Date
TWI730869B true TWI730869B (en) 2021-06-11
TW202207402A TW202207402A (en) 2022-02-16

Family

ID=77517221

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109126776A TWI730869B (en) 2020-08-07 2020-08-07 Line end structure and forming method thereof

Country Status (2)

Country Link
CN (1) CN114068324A (en)
TW (1) TWI730869B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201724183A (en) * 2015-06-26 2017-07-01 英特爾股份有限公司 Textile patterning for subtractively-patterned self-aligned interconnects, plugs, and vias
US20200105662A1 (en) * 2018-09-27 2020-04-02 Intel Corporation Single mask lithography line end enhancement
TW202025319A (en) * 2018-12-27 2020-07-01 南亞科技股份有限公司 Semiconductor structure and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201724183A (en) * 2015-06-26 2017-07-01 英特爾股份有限公司 Textile patterning for subtractively-patterned self-aligned interconnects, plugs, and vias
US20200105662A1 (en) * 2018-09-27 2020-04-02 Intel Corporation Single mask lithography line end enhancement
TW202025319A (en) * 2018-12-27 2020-07-01 南亞科技股份有限公司 Semiconductor structure and manufacturing method thereof

Also Published As

Publication number Publication date
TW202207402A (en) 2022-02-16
CN114068324A (en) 2022-02-18

Similar Documents

Publication Publication Date Title
KR101129919B1 (en) Semiconductor device and method for forming the same
JP7142607B2 (en) How to protect the low-k layer
JP2000286263A (en) Semiconductor device and its manufacture
KR100833201B1 (en) Semiconductor device having fine patterns of wiring line integrated with contact plug and method of manufacturing the same
JP6625200B2 (en) Method for manufacturing semiconductor device
JP2930025B2 (en) Semiconductor device and manufacturing method thereof
TW202001998A (en) Self-aligned multiple patterning processes with layered mandrels
JP4785623B2 (en) Semiconductor device and manufacturing method thereof
JPH07122638A (en) Fabrication of semiconductor device
TWI730869B (en) Line end structure and forming method thereof
US11804381B2 (en) Conductive wire structure
JP2006294942A (en) Semiconductor device and its manufacturing method
TWI744933B (en) Conductive wire structrue and manufacturing method thereof
JP5881569B2 (en) Pattern formation method
KR100886642B1 (en) Method for fabricating capacitor
TWI840608B (en) Semiconductor device manufacturing method
KR20050073890A (en) Interconnection structure for semiconductor device and method of forming the same
WO2023279545A1 (en) Method for manufacturing semiconductor structure, and semiconductor structure
TWI641100B (en) Method for manufacturing semiconductor device
JP4379245B2 (en) Manufacturing method of semiconductor device
TWI697032B (en) Method of fabricating semiconductor device
KR100574645B1 (en) Method for forming tungsten plug
KR100508534B1 (en) Method for forming an air gap in a semiconductor metal line manufacturing process
CN118098936A (en) Manufacturing method of semiconductor structure, mask structure and semiconductor structure
KR19990060819A (en) Metal wiring formation method of semiconductor device