TWI726247B

TWI726247B - Semiconductor device and method for forming the same

Info

Publication number: TWI726247B
Application number: TW107136581A
Authority: TW
Inventors: 甘鎧銓; 許書維; 宋建憲; 陳姿亘
Original assignee: 世界先進積體電路股份有限公司
Priority date: 2018-10-17
Filing date: 2018-10-17
Publication date: 2021-05-01
Also published as: TW202017017A

Abstract

A semiconductor device includes a semiconductor substrate, a buried layer disposed in the semiconductor substrate, and a first well region, a second well region, a third well region and a fourth well region disposed in the semiconductor substrate on the buried layer. The semiconductor device also includes a source region disposed in the second well region, a drain region disposed in the first well region, a gate structure disposed on the first well region and the second well region, and a deep trench isolation structure disposed in the semiconductor substrate and surrounding the source region and the drain region. The second well region surrounds the first well region. The third well region and the fourth well region are located on opposite sides of the second well region. The deep trench isolation structure penetrates through the buried layer.

Description

半導體裝置及其形成方法Semiconductor device and its forming method

本發明實施例關於一種半導體裝置，且特別有關於一種具有深溝槽隔離結構之半導體裝置及其形成方法。The embodiment of the present invention relates to a semiconductor device, and more particularly to a semiconductor device with a deep trench isolation structure and a method of forming the same.

半導體裝置已廣泛地使用於各種電子產品中，舉例而言，諸如個人電腦、手機、以及數位相機…等。半導體裝置的製造通常是藉由在半導體基板上形成絕緣層或介電層、導電層以及半導體層，接著使用微影製程圖案化所形成的各種材料層，藉以在此半導體基板之上形成電路零件及組件。Semiconductor devices have been widely used in various electronic products, such as personal computers, mobile phones, and digital cameras, etc., for example. The manufacturing of semiconductor devices usually involves forming an insulating layer or a dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and then patterning the formed layers of various materials using a lithography process to form circuit components on the semiconductor substrate. And components.

現有的半導體裝置及其製造方法大抵上可滿足一般需求，然而隨著裝置的微型化，其並非在各方面皆令人滿意。Existing semiconductor devices and their manufacturing methods can generally meet general requirements. However, with the miniaturization of devices, they are not satisfactory in all aspects.

本發明實施例包括一種半導體裝置。上述半導體裝置包括半導體基板、設置於上述半導體基板中的埋藏層、設置於上述埋藏層上及上述半導體基板中的第一井區、設置於上述埋藏層上及上述半導體基板中的第二井區。上述第二井區圍繞上述第一井區。上述半導體裝置亦包括設置於上述埋藏層上及上述半導體基板中的第三井區與第四井區。上述第三井區與上述第四井區位於上述第二井區的相對兩側。上述半導體裝置亦包括設置於上述第二井區中的源極區、設置於上述第一井區中的汲極區、設置於上述第一井區與上述第二井區之上的閘極結構、以及設置於上述半導體基板中且圍繞上述源極區與上述汲極區的深溝槽隔離結構。上述深溝槽隔離結構穿過上述埋藏層。The embodiment of the present invention includes a semiconductor device. The semiconductor device includes a semiconductor substrate, a buried layer provided in the semiconductor substrate, a first well region provided on the buried layer and in the semiconductor substrate, and a second well region provided on the buried layer and in the semiconductor substrate . The second well area surrounds the first well area. The semiconductor device also includes a third well region and a fourth well region disposed on the buried layer and in the semiconductor substrate. The third well area and the fourth well area are located on opposite sides of the second well area. The semiconductor device also includes a source region disposed in the second well region, a drain region disposed in the first well region, and a gate structure disposed on the first well region and the second well region And a deep trench isolation structure disposed in the semiconductor substrate and surrounding the source region and the drain region. The deep trench isolation structure passes through the buried layer.

本發明實施例亦包括一種半導體裝置。上述半導體裝置包括半導體基板、設置於上述半導體基板中的埋藏層、設置於上述埋藏層上及上述半導體基板中的第一井區、設置於上述埋藏層上及上述半導體基板中的第二井區。上述第二井區環繞上述第一井區。上述半導體裝置亦包括設置於上述埋藏層上及上述半導體基板中的第三井區與第四井區。上述第三井區與上述第四井區相鄰於上述第二井區且上述第三井區與上述第四井區彼此分離。上述埋藏層、上述第一井區、上述第三井區以及上述第四井區具有第一導電型態，上述第二井區具有相反於上述第一導電型態的第二導電型態。上述半導體裝置亦包括設置於上述第二井區中的源極區、設置於上述第一井區中的汲極區、設置於上述第一井區與上述第二井區之上的閘極結構、以及設置於上述半導體基板中且環繞上述第二井區的深溝槽隔離結構。上述深溝槽隔離結構的底表面低於上述埋藏層的底表面。The embodiment of the present invention also includes a semiconductor device. The semiconductor device includes a semiconductor substrate, a buried layer provided in the semiconductor substrate, a first well region provided on the buried layer and in the semiconductor substrate, and a second well region provided on the buried layer and in the semiconductor substrate . The second well area surrounds the first well area. The semiconductor device also includes a third well region and a fourth well region disposed on the buried layer and in the semiconductor substrate. The third well area and the fourth well area are adjacent to the second well area, and the third well area and the fourth well area are separated from each other. The buried layer, the first well region, the third well region, and the fourth well region have a first conductivity type, and the second well region has a second conductivity type opposite to the first conductivity type. The semiconductor device also includes a source region disposed in the second well region, a drain region disposed in the first well region, and a gate structure disposed on the first well region and the second well region And a deep trench isolation structure arranged in the semiconductor substrate and surrounding the second well region. The bottom surface of the deep trench isolation structure is lower than the bottom surface of the buried layer.

本發明實施例亦包括一種半導體裝置之形成方法。上述方法包括提供半導體基板。上述半導體基板中設置有埋藏層。上述方法亦包括於上述半導體基板中及上述埋藏層之上形成第一井區、第二井區、第三井區以及第四井區。上述第二井區環繞上述第一井區。上述第三井區與上述第四井區部分地環繞上述第二井區，上述第三井區與上述第四井區彼此分離。上述埋藏層、上述第一井區、上述第三井區以及上述第四井區具有第一導電型態，上述第二井區具有相反於上述第一導電型態的第二導電型態。上述方法亦包括於上述第二井區中形成源極區、於上述第一井區中形成汲極區、於上述第一井區與上述第二井區之上形成閘極結構、以及於上述半導體基板中形成深溝槽隔離結構。The embodiment of the present invention also includes a method of forming a semiconductor device. The above method includes providing a semiconductor substrate. A buried layer is provided in the above-mentioned semiconductor substrate. The above method also includes forming a first well region, a second well region, a third well region, and a fourth well region in the semiconductor substrate and on the buried layer. The second well area surrounds the first well area. The third well area and the fourth well area partially surround the second well area, and the third well area and the fourth well area are separated from each other. The buried layer, the first well region, the third well region, and the fourth well region have a first conductivity type, and the second well region has a second conductivity type opposite to the first conductivity type. The above method also includes forming a source region in the second well region, forming a drain region in the first well region, forming a gate structure on the first well region and the second well region, and forming a gate structure on the first well region and the second well region. A deep trench isolation structure is formed in the semiconductor substrate.

以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下的揭露內容敘述各個構件及其排列方式的特定範例，以簡化說明。當然，這些特定的範例並非用以限定。例如，若是本發明實施例敘述了一第一特徵部件形成於一第二特徵部件之上或上方，即表示其可能包含上述第一特徵部件與上述第二特徵部件是直接接觸的實施例，亦可能包含了有附加特徵部件形成於上述第一特徵部件與上述第二特徵部件之間，而使上述第一特徵部件與第二特徵部件可能未直接接觸的實施例。The following disclosure provides many different embodiments or examples to implement different features of this case. The following disclosure describes specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not meant to be limiting. For example, if the embodiment of the present invention describes that a first characteristic component is formed on or above a second characteristic component, it means that it may include an embodiment in which the above-mentioned first characteristic component is in direct contact with the above-mentioned second characteristic component. It may include an embodiment in which an additional characteristic part is formed between the first characteristic part and the second characteristic part, and the first characteristic part and the second characteristic part may not be in direct contact.

應理解的是，額外的操作步驟可實施於所述方法之前、之間或之後，且在所述方法的其他實施例中，部分的操作步驟可被取代或省略。It should be understood that additional operation steps may be implemented before, during, or after the method, and in other embodiments of the method, part of the operation steps may be replaced or omitted.

此外，其中可能用到與空間相關用詞，例如「在…下方」、「下方」、「較低的」、「上方」、「較高的」及類似的用詞，這些空間相關用詞係為了便於描述圖示中一個(些)元件或特徵部件與另一個(些)元件或特徵部件之間的關係，這些空間相關用詞包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位)，則其中所使用的空間相關形容詞也將依轉向後的方位來解釋。In addition, terms related to space may be used, such as "below", "below", "lower", "above", "higher" and similar terms. These space-related terms are In order to facilitate the description of the relationship between one element(s) or characteristic part and another element(s) or characteristic part in the figure, these spatially related terms include the different orientations of the device in use or operation, as well as in the drawings. The orientation described. When the device is turned in different directions (rotated by 90 degrees or other directions), the space-related adjectives used therein will also be interpreted according to the turned position.

除非另外定義，在此使用的全部用語(包括技術及科學用語)具有與此篇揭露所屬之一般技藝者所通常理解的相同涵義。能理解的是，這些用語，例如在通常使用的字典中定義的用語，應被解讀成具有與相關技術及本發明的背景或上下文一致的意思，而不應以一理想化或過度正式的方式解讀，除非在本發明實施例有特別定義。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by the general artisans to whom the disclosure belongs. It is understandable that these terms, such as those defined in commonly used dictionaries, should be interpreted as having meanings consistent with the relevant technology and the background or context of the present invention, rather than in an idealized or overly formal way. Interpretation, unless there is a special definition in the embodiment of the present invention.

本發明實施例之半導體裝置包括部分圍繞源極區的多個井區(例如:後文所述之第三井區106與第四井區108)、以及圍繞源極區與汲極區的深溝槽隔離結構，藉此可降低半導體裝置之尺寸、減少或避免基板漏電流的發生並避免或減輕閂鎖效應(latch-up)。The semiconductor device of the embodiment of the present invention includes a plurality of well regions partially surrounding the source region (e.g., the third well region 106 and the fourth well region 108 described later), and deep trenches surrounding the source region and the drain region The trench isolation structure can reduce the size of the semiconductor device, reduce or avoid the occurrence of substrate leakage current, and avoid or reduce the latch-up effect.

首先，請參照第1、2及3圖。第1圖係為根據本發明一些實施例之半導體裝置10的部分上視圖，第2圖係為沿著第1圖之剖面線A-A所繪示之部分剖面圖，第3圖係為沿著第1圖之剖面線B-B所繪示之部分剖面圖。詳細而言，剖面線A-A大抵上平行於方向X，剖面線B-B大抵上平行於方向Y，且方向X大抵上垂直於方向Y。應理解的是，為了簡明起見，未將半導體裝置10的所有元件繪示於第1-3圖中。First, please refer to Figures 1, 2 and 3. FIG. 1 is a partial top view of a semiconductor device 10 according to some embodiments of the present invention, FIG. 2 is a partial cross-sectional view along the section line AA of FIG. 1, and FIG. 3 is a partial cross-sectional view along the line AA of FIG. Part of the cross-sectional view shown by the section line BB in Figure 1. In detail, the section line A-A is approximately parallel to the direction X, the section line B-B is approximately parallel to the direction Y, and the direction X is approximately perpendicular to the direction Y. It should be understood that, for the sake of brevity, not all the components of the semiconductor device 10 are shown in FIGS. 1-3.

如第1-3圖所示，根據本發明一些實施例，半導體裝置10包括半導體基板100的至少一部分。半導體基板100可為矽基板，但本發明實施例並非以此為限。舉例而言，半導體基板100可包括一些其他的元素半導體基板(例如:鍺)。半導體基板100亦可包括化合物半導體基板(例如:碳化矽、砷化鎵、砷化銦或磷化銦)。半導體基板100亦可包括合金半導體基板(例如:矽化鍺、碳化矽鍺(silicon germanium carbide)、磷砷化鎵(gallium arsenic phosphide)或磷化銦鎵(gallium indium phosphide))。在一些實施例中，半導體基板100可包括絕緣層上半導體(semiconductor on insulator ，SOI)基板(例如:絕緣層上矽基板或絕緣層上鍺基板)，上述絕緣層上半導體基板可包括底板、設置於上述底板上之埋藏氧化層以及設置於上述埋藏氧化層上之半導體層。在一些實施例中，半導體基板100可包括單晶基板、多層基板(multi-layer substrate)、梯度基板(gradient substrate)、其他適當之基板或上述之組合。As shown in FIGS. 1-3, according to some embodiments of the present invention, the semiconductor device 10 includes at least a part of the semiconductor substrate 100. The semiconductor substrate 100 may be a silicon substrate, but the embodiment of the present invention is not limited to this. For example, the semiconductor substrate 100 may include some other elemental semiconductor substrate (for example, germanium). The semiconductor substrate 100 may also include a compound semiconductor substrate (for example, silicon carbide, gallium arsenide, indium arsenide, or indium phosphide). The semiconductor substrate 100 may also include an alloy semiconductor substrate (for example, germanium silicide, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide). In some embodiments, the semiconductor substrate 100 may include a semiconductor on insulator (SOI) substrate (for example, a silicon-on-insulator substrate or a germanium-on-insulator substrate). The semiconductor substrate on an insulation layer may include a bottom plate, A buried oxide layer on the bottom plate and a semiconductor layer arranged on the buried oxide layer. In some embodiments, the semiconductor substrate 100 may include a single crystal substrate, a multi-layer substrate, a gradient substrate, other suitable substrates, or a combination thereof.

如第2、3圖所示，半導體基板100可具有頂表面100T以及相對於頂表面100T的底表面100B。可於頂表面100T與底表面100B之間形成適當之摻雜區與元件以形成本發明實施例之半導體裝置10，於後文將對此進行詳細說明。As shown in FIGS. 2 and 3, the semiconductor substrate 100 may have a top surface 100T and a bottom surface 100B opposite to the top surface 100T. Suitable doped regions and elements can be formed between the top surface 100T and the bottom surface 100B to form the semiconductor device 10 of the embodiment of the present invention, which will be described in detail later.

半導體基板100可具有第二導電型態，為了簡明起見，後文將以半導體基板100之第二導電型態為P型(亦即，半導體基板100為P型半導體基板)的實施例進行說明。然而，在一些其他的實施例中，半導體基板100之第二導電型態亦可為N型。The semiconductor substrate 100 may have a second conductivity type. For the sake of brevity, the following will describe an embodiment in which the second conductivity type of the semiconductor substrate 100 is P-type (that is, the semiconductor substrate 100 is a P-type semiconductor substrate). . However, in some other embodiments, the second conductivity type of the semiconductor substrate 100 can also be N-type.

如第2、3圖所示，半導體基板100中可設置有埋藏層(buried layer)202。在一些實施例中，可經由設置於埋藏層202上的井區以及摻雜區對埋藏層202施加適當的電壓而避免或減輕閂鎖效應，於後文將對此進行詳細說明。As shown in FIGS. 2 and 3, a buried layer 202 may be provided in the semiconductor substrate 100. In some embodiments, an appropriate voltage can be applied to the buried layer 202 through the well region and the doped region provided on the buried layer 202 to avoid or reduce the latch-up effect, which will be described in detail later.

埋藏層202可具有相反於第二導電型態的第一導電型態。在一些實施例中，半導體基板100為P型基板，因此埋藏層202為N型埋藏層。在一些實施例中，N型埋藏層202可包括如氮、磷、砷、銻、鉍之摻質，且其摻雜濃度可為10¹⁷ 至10¹⁸ cm^-3 。舉例而言，可使用離子佈植製程將適當的摻質佈植至半導體基板100之一部分中以形成埋藏層202。The buried layer 202 may have a first conductivity type opposite to the second conductivity type. In some embodiments, the semiconductor substrate 100 is a P-type substrate, so the buried layer 202 is an N-type buried layer. In some embodiments, the N-type buried layer 202 may include dopants such as nitrogen, phosphorus, arsenic, antimony, and bismuth, and the doping concentration thereof may be 10 ¹⁷ to 10 ¹⁸ cm ⁻³ . For example, an ion implantation process can be used to implant appropriate dopants into a portion of the semiconductor substrate 100 to form the buried layer 202.

請繼續參照第1-3圖，根據一些實施例，半導體裝置10之第一井區102與第二井區104可形成於半導體基板100中。在一些實施例中，如第1圖所示，第二井區104圍繞第一井區102。在一些實施例中，如第2、3圖所示，第一井區102與第二井區104位於埋藏層202之上。Please continue to refer to FIGS. 1-3. According to some embodiments, the first well region 102 and the second well region 104 of the semiconductor device 10 may be formed in the semiconductor substrate 100. In some embodiments, as shown in FIG. 1, the second well area 104 surrounds the first well area 102. In some embodiments, as shown in FIGS. 2 and 3, the first well area 102 and the second well area 104 are located above the buried layer 202.

第一井區102可具有第一導電型態，第二井區104可具有第二導電型態。換句話說，第一井區102的導電型態相反於第二井區104的導電型態。在一些實施例中，第一井區102為N型井區，第二井區104為P型井區。在一些實施例中，N型第一井區102包括如氮、磷、砷、銻、鉍之摻質，且其摻雜濃度可為10¹⁶ 至10¹⁷ cm^-3 。在一些實施例中，P型第二井區104包括如硼、鋁、鎵、銦、鉈之摻質，且其摻雜濃度可為10¹⁶ 至10¹⁷ cm^-3 。舉例而言，可使用離子佈植製程將適當的摻質佈植至半導體基板100之一部分中以形成第一井區102與第二井區104。The first well region 102 may have a first conductivity type, and the second well region 104 may have a second conductivity type. In other words, the conductivity type of the first well region 102 is opposite to the conductivity type of the second well region 104. In some embodiments, the first well area 102 is an N-type well area, and the second well area 104 is a P-type well area. In some embodiments, the N-type first well region 102 includes dopants such as nitrogen, phosphorus, arsenic, antimony, and bismuth, and the doping concentration thereof can be 10 ¹⁶ to 10 ¹⁷ cm ⁻³ . In some embodiments, the P-type second well region 104 includes dopants such as boron, aluminum, gallium, indium, and thallium, and the doping concentration thereof can be 10 ¹⁶ to 10 ¹⁷ cm ⁻³ . For example, an ion implantation process can be used to implant appropriate dopants into a portion of the semiconductor substrate 100 to form the first well region 102 and the second well region 104.

在一些實施例中，如第2、3圖所示，第一井區102與埋藏層202相互分離，而可隔絕源極和汲極達到元件完全隔離的效果。在一些實施例中，如第2、3圖所示，第二井區104直接接觸埋藏層202。In some embodiments, as shown in FIGS. 2 and 3, the first well region 102 and the buried layer 202 are separated from each other, and the source and drain can be isolated to achieve the effect of complete isolation of the device. In some embodiments, as shown in FIGS. 2 and 3, the second well region 104 directly contacts the buried layer 202.

請繼續參照第1、3圖，根據一些實施例，半導體裝置10之第三井區106與第四井區108形成於半導體基板100中。在一些實施例中，如第3圖所示，第三井區106與第四井區108位於埋藏層202之上。在一些實施例中，如第1、3圖所示，第三井區106與第四井區108相鄰於第二井區104，第三井區106與第四井區108被第二井區104隔開而彼此分離。Please continue to refer to FIGS. 1 and 3. According to some embodiments, the third well region 106 and the fourth well region 108 of the semiconductor device 10 are formed in the semiconductor substrate 100. In some embodiments, as shown in FIG. 3, the third well area 106 and the fourth well area 108 are located above the buried layer 202. In some embodiments, as shown in Figures 1 and 3, the third well area 106 and the fourth well area 108 are adjacent to the second well area 104, and the third well area 106 and the fourth well area 108 are separated by the second well area. The regions 104 are separated from each other.

在一些實施例中，如第1圖所示，第三井區106與第四井區108僅部分地圍繞第二井區104而非完全地圍繞第二井區104，因此可降低半導體裝置10的尺寸。在一些實施例中，如第1、3圖所示，第三井區106位於第二井區104的第一側104a，第四井區108位於第二井區104相對於第一側104a的第二側104b。在一些實施例中，第二井區104的第一側104a直接接觸第三井區106，第二井區104的第二側104b直接接觸第四井區108。In some embodiments, as shown in Figure 1, the third well region 106 and the fourth well region 108 only partially surround the second well region 104 instead of completely surrounding the second well region 104, so the semiconductor device 10 can be reduced. size of. In some embodiments, as shown in Figures 1 and 3, the third well region 106 is located on the first side 104a of the second well region 104, and the fourth well region 108 is located on the second well region 104 relative to the first side 104a. The second side 104b. In some embodiments, the first side 104 a of the second well region 104 directly contacts the third well region 106, and the second side 104 b of the second well region 104 directly contacts the fourth well region 108.

第三井區106與第四井區108可具有第一導電型態。換句話說，第三井區106與第四井區108的導電型態可相同於埋藏層202的導電型態。在一些實施例中，埋藏層202為N型埋藏層，因此第三井區106與第四井區108為N型井區。在一些實施例中，N型第三井區106包括如氮、磷、砷、銻、鉍之摻質，且其摻雜濃度可為10¹⁶ 至10¹⁷ cm^-3 。在一些實施例中，N型第四井區108包括如氮、磷、砷、銻、鉍之摻質，且其摻雜濃度可為10¹⁶ 至10¹⁷ cm^-3 。第三井區106的摻雜濃度可大抵上等於第四井區108的摻雜濃度，但本發明實施例並非以此為限。舉例而言，可使用離子佈植製程將適當的摻質佈植至半導體基板100之一部分中以形成第三井區106與第四井區108。The third well region 106 and the fourth well region 108 may have the first conductivity type. In other words, the conductivity type of the third well region 106 and the fourth well region 108 may be the same as the conductivity type of the buried layer 202. In some embodiments, the buried layer 202 is an N-type buried layer, so the third well region 106 and the fourth well region 108 are N-type well regions. In some embodiments, the N-type third well region 106 includes dopants such as nitrogen, phosphorus, arsenic, antimony, and bismuth, and the doping concentration thereof can be 10 ¹⁶ to 10 ¹⁷ cm ⁻³ . In some embodiments, the N-type fourth well region 108 includes dopants such as nitrogen, phosphorus, arsenic, antimony, and bismuth, and the doping concentration thereof can be 10 ¹⁶ to 10 ¹⁷ cm ⁻³ . The doping concentration of the third well region 106 may be substantially equal to the doping concentration of the fourth well region 108, but the embodiment of the present invention is not limited to this. For example, an ion implantation process can be used to implant appropriate dopants into a portion of the semiconductor substrate 100 to form the third well region 106 and the fourth well region 108.

請繼續參照第2、3圖，根據一些實施例，半導體裝置10可包括形成於第二井區104中的摻雜區204。在一些實施例中，摻雜區204可環繞第一井區102。在一些實施例中，如第2、3圖所示，摻雜區204與第一井區102被第二井區104隔開而彼此分離。Please continue to refer to FIGS. 2 and 3. According to some embodiments, the semiconductor device 10 may include a doped region 204 formed in the second well region 104. In some embodiments, the doped region 204 may surround the first well region 102. In some embodiments, as shown in FIGS. 2 and 3, the doped region 204 and the first well region 102 are separated by the second well region 104 to be separated from each other.

摻雜區204可具有第二導電型態。換句話說，摻雜區204與第二井區104可具有相同的導電型態。在一些實施例中，第二井區104為P型井區，因此摻雜區204為P型摻雜區。在一些實施例中，P型摻雜區204包括如硼、鋁、鎵、銦、鉈之摻質，且其摻雜濃度可為10¹⁷ 至10¹⁸ cm^-3 。在一些實施例中，摻雜區204的摻雜濃度大於第二井區104的摻雜濃度。舉例而言，可使用離子佈植製程將適當的摻質佈植至半導體基板100之一部分中以於第二井區104中形成摻雜區204。The doped region 204 may have the second conductivity type. In other words, the doped region 204 and the second well region 104 may have the same conductivity type. In some embodiments, the second well region 104 is a P-type well region, so the doped region 204 is a P-type doped region. In some embodiments, the P-type doped region 204 includes dopants such as boron, aluminum, gallium, indium, and thallium, and the doping concentration thereof may be 10 ¹⁷ to 10 ¹⁸ cm ⁻³ . In some embodiments, the doping concentration of the doping region 204 is greater than the doping concentration of the second well region 104. For example, an ion implantation process may be used to implant appropriate dopants into a portion of the semiconductor substrate 100 to form the doped region 204 in the second well region 104.

請繼續參照第1-3圖，根據一些實施例，半導體裝置10之源極區110形成於第二井區104中，半導體裝置10之汲極區112形成於第一井區102中。在一些實施例中，半導體裝置10之源極區110形成於第二井區104中之摻雜區204中。在一些實施例中，如第1圖所示，源極區110環繞汲極區112。Please continue to refer to FIGS. 1-3. According to some embodiments, the source region 110 of the semiconductor device 10 is formed in the second well region 104, and the drain region 112 of the semiconductor device 10 is formed in the first well region 102. In some embodiments, the source region 110 of the semiconductor device 10 is formed in the doped region 204 in the second well region 104. In some embodiments, as shown in FIG. 1, the source region 110 surrounds the drain region 112.

源極區110與汲極區112可具有第一導電型態。換句話說，源極區110與汲極區112的導電型態可相反於第二井區104的導電型態。在一些實施例中，第二井區104為P型井區，因此源極區110與汲極區112為N型源極區與N型汲極區。在一些實施例中，N型源極區110包括如氮、磷、砷、銻、鉍之摻質，且其摻雜濃度可為10¹⁸ 至10¹⁹ cm^-3 。在一些實施例中，N型汲極區112包括如氮、磷、砷、銻、鉍之摻質，且其摻雜濃度可為10¹⁸ 至10¹⁹ cm^-3 。舉例而言，可使用離子佈植製程將適當的摻質佈植至半導體基板100之一部分中以形成源極區110與汲極區112。The source region 110 and the drain region 112 may have a first conductivity type. In other words, the conductivity type of the source region 110 and the drain region 112 may be opposite to the conductivity type of the second well region 104. In some embodiments, the second well region 104 is a P-type well region, so the source region 110 and the drain region 112 are an N-type source region and an N-type drain region. In some embodiments, the N-type source region 110 includes dopants such as nitrogen, phosphorus, arsenic, antimony, and bismuth, and the doping concentration thereof may be 10 ¹⁸ to 10 ¹⁹ cm ⁻³ . In some embodiments, the N-type drain region 112 includes dopants such as nitrogen, phosphorus, arsenic, antimony, and bismuth, and the doping concentration thereof can be 10 ¹⁸ to 10 ¹⁹ cm ⁻³ . For example, an ion implantation process can be used to implant appropriate dopants into a portion of the semiconductor substrate 100 to form the source region 110 and the drain region 112.

請繼續參照第2、3圖，根據一些實施例，半導體裝置10可包括形成於摻雜區204中的摻雜區206。在一些實施例中，摻雜區206環繞源極區110。在一些實施例中，摻雜區206之導電型態相反於源極區110的導電型態且摻雜區206直接接觸源極區110，而可降低元件特徵電阻值。Please continue to refer to FIGS. 2 and 3. According to some embodiments, the semiconductor device 10 may include a doped region 206 formed in the doped region 204. In some embodiments, the doped region 206 surrounds the source region 110. In some embodiments, the conductivity type of the doped region 206 is opposite to the conductivity type of the source region 110 and the doped region 206 directly contacts the source region 110, which can reduce the characteristic resistance of the device.

在一些實施例中，源極區110為N型源極區，因此摻雜區206為P型摻雜區。在一些實施例中，P型摻雜區206包括如硼、鋁、鎵、銦、鉈之摻質，且其摻雜濃度可為10¹⁸ 至10¹⁹ cm^-3 。在一些實施例中，摻雜區206的摻雜濃度大於摻雜區204的摻雜濃度。舉例而言，可使用離子佈植製程將適當的摻質佈植至半導體基板100之一部分中以於摻雜區204中形成摻雜區206。In some embodiments, the source region 110 is an N-type source region, so the doped region 206 is a P-type doped region. In some embodiments, the P-type doped region 206 includes dopants such as boron, aluminum, gallium, indium, and thallium, and the doping concentration thereof may be 10 ¹⁸ to 10 ¹⁹ cm ⁻³ . In some embodiments, the doping concentration of the doping region 206 is greater than the doping concentration of the doping region 204. For example, an ion implantation process may be used to implant appropriate dopants into a portion of the semiconductor substrate 100 to form the doped region 206 in the doped region 204.

請繼續參照第3圖，根據一些實施例，半導體裝置10可包括形成於第二井區104中的摻雜區302與摻雜區304。在一些實施例中，摻雜區302與摻雜區304係與摻雜區204分離。在一些實施例中，摻雜區302與摻雜區304圍繞摻雜區204。摻雜區302與摻雜區304的導電型態可相同於第二井區104的導電型態。在一些實施例中，第二井區104為P型井區，因此摻雜區302與摻雜區304為P型摻雜區。在一些實施例中，P型摻雜區302包括如硼、鋁、鎵、銦、鉈之摻質，且其摻雜濃度可為10¹⁸ 至10¹⁹ cm^-3 。在一些實施例中，P型摻雜區304包括如硼、鋁、鎵、銦、鉈之摻質，且其摻雜濃度可為10¹⁸ 至10¹⁹ cm^-3 。舉例而言，可使用離子佈植製程將適當的摻質佈植至半導體基板100之一部分中以於第二井區104中形成摻雜區302與摻雜區304。Please continue to refer to FIG. 3, according to some embodiments, the semiconductor device 10 may include a doped region 302 and a doped region 304 formed in the second well region 104. In some embodiments, the doped region 302 and the doped region 304 are separated from the doped region 204. In some embodiments, the doped region 302 and the doped region 304 surround the doped region 204. The conductivity type of the doped region 302 and the doped region 304 may be the same as the conductivity type of the second well region 104. In some embodiments, the second well region 104 is a P-type well region, so the doped region 302 and the doped region 304 are P-type doped regions. In some embodiments, the P-type doped region 302 includes dopants such as boron, aluminum, gallium, indium, and thallium, and the doping concentration thereof may be 10 ¹⁸ to 10 ¹⁹ cm ⁻³ . In some embodiments, the P-type doped region 304 includes dopants such as boron, aluminum, gallium, indium, and thallium, and the doping concentration thereof may be 10 ¹⁸ to 10 ¹⁹ cm ⁻³ . For example, an ion implantation process can be used to implant appropriate dopants into a portion of the semiconductor substrate 100 to form the doped regions 302 and the doped regions 304 in the second well region 104.

請繼續參照第2、3圖，根據一些實施例，半導體裝置10可包括形成於第一井區102中的摻雜區207。在一些實施例中，摻雜區207直接接觸汲極區112的側壁與底表面。在一些實施例中，摻雜區207可優化元件靜電保護(ESD)的能力。Please continue to refer to FIGS. 2 and 3. According to some embodiments, the semiconductor device 10 may include a doped region 207 formed in the first well region 102. In some embodiments, the doped region 207 directly contacts the sidewall and bottom surface of the drain region 112. In some embodiments, the doped region 207 can optimize the electrostatic protection (ESD) capability of the device.

摻雜區207的導電型態可相同於汲極區112的導電型態。在一些實施例中，汲極區112為N型汲極區，因此摻雜區207為N型摻雜區。在一些實施例中，N型摻雜區207包括如氮、磷、砷、銻、鉍之摻質，且其摻雜濃度可為10¹⁶ 至10¹⁷ cm^-3 。在一些實施例中，摻雜區207的摻雜濃度小於汲極區112的摻雜濃度。舉例而言，可使用離子佈植製程將適當的摻質佈植至半導體基板100之一部分中以於第一井區102中形成摻雜區207。The conductivity type of the doped region 207 may be the same as the conductivity type of the drain region 112. In some embodiments, the drain region 112 is an N-type drain region, so the doped region 207 is an N-type doped region. In some embodiments, the N-type doped region 207 includes dopants such as nitrogen, phosphorus, arsenic, antimony, and bismuth, and the doping concentration thereof may be 10 ¹⁶ to 10 ¹⁷ cm ⁻³ . In some embodiments, the doping concentration of the doped region 207 is less than the doping concentration of the drain region 112. For example, an ion implantation process may be used to implant appropriate dopants into a portion of the semiconductor substrate 100 to form the doped region 207 in the first well region 102.

請繼續參照第1、3圖，根據一些實施例，半導體裝置10可包括形成於第三井區106中的摻雜區114與形成於第四井區108中的摻雜區116。在一些實施例中，可經由摻雜區114、第三井區106、摻雜區116、第四井區108對埋藏層202施加適當的電壓而避免或減輕閂鎖效應。Please continue to refer to FIGS. 1 and 3. According to some embodiments, the semiconductor device 10 may include a doped region 114 formed in the third well region 106 and a doped region 116 formed in the fourth well region 108. In some embodiments, an appropriate voltage can be applied to the buried layer 202 through the doped region 114, the third well region 106, the doped region 116, and the fourth well region 108 to avoid or reduce the latch-up effect.

在一些實施例中，摻雜區114與摻雜區116的導電型態相同於第三井區106與第四井區108的導電型態(亦即，摻雜區114、摻雜區116、第三井區106與第四井區108皆具有第一導電型態)。在一些實施例中，第三井區106與第四井區108為N型井區，因此摻雜區114與摻雜區116為N型摻雜區。在一些實施例中，N型摻雜區114包括如氮、磷、砷、銻、鉍之摻質，且其摻雜濃度可為10¹⁸ 至10¹⁹ cm^-3 。在一些實施例中，N型摻雜區116包括如氮、磷、砷、銻、鉍之摻質，且其摻雜濃度可為10¹⁸ 至10¹⁹ cm^-3 。在一些實施例中，摻雜區114與摻雜區116的摻雜濃度大於第三井區106與第四井區108的摻雜濃度。舉例而言，可使用離子佈植製程將適當的摻質佈植至半導體基板100之一部分中以形成摻雜區114與摻雜區116。In some embodiments, the conductivity type of the doped region 114 and the doped region 116 is the same as the conductivity type of the third well region 106 and the fourth well region 108 (that is, the doped region 114, the doped region 116, Both the third well region 106 and the fourth well region 108 have the first conductivity type). In some embodiments, the third well region 106 and the fourth well region 108 are N-type well regions, so the doped region 114 and the doped region 116 are N-type doped regions. In some embodiments, the N-type doped region 114 includes dopants such as nitrogen, phosphorus, arsenic, antimony, and bismuth, and the doping concentration thereof can be 10 ¹⁸ to 10 ¹⁹ cm ⁻³ . In some embodiments, the N-type doped region 116 includes dopants such as nitrogen, phosphorus, arsenic, antimony, and bismuth, and the doping concentration thereof can be 10 ¹⁸ to 10 ¹⁹ cm ⁻³ . In some embodiments, the doping concentration of the doping region 114 and the doping region 116 is greater than the doping concentration of the third well region 106 and the fourth well region 108. For example, an ion implantation process may be used to implant appropriate dopants into a portion of the semiconductor substrate 100 to form the doped regions 114 and 116.

請繼續參照第1-3圖，根據一些實施例，半導體裝置10包括形成於半導體基板100中的深溝槽隔離結構118。在一些實施例中，深溝槽隔離結構118從半導體基板100的頂表面100T延伸進入半導體基板100中。在一些實施例中，深溝槽隔離結構118延伸穿過埋藏層202。在一些實施例中，深溝槽隔離結構118的底表面低於埋藏層202的底表面且高於半導體基板100的底表面100B。在一些實施例中，深溝槽隔離結構118延伸穿過埋藏層202並進入埋藏層202下方的半導體基板100中，而可避免或減少基板漏電流的發生。Please continue to refer to FIGS. 1-3. According to some embodiments, the semiconductor device 10 includes a deep trench isolation structure 118 formed in the semiconductor substrate 100. In some embodiments, the deep trench isolation structure 118 extends from the top surface 100T of the semiconductor substrate 100 into the semiconductor substrate 100. In some embodiments, the deep trench isolation structure 118 extends through the buried layer 202. In some embodiments, the bottom surface of the deep trench isolation structure 118 is lower than the bottom surface of the buried layer 202 and higher than the bottom surface 100B of the semiconductor substrate 100. In some embodiments, the deep trench isolation structure 118 extends through the buried layer 202 and enters the semiconductor substrate 100 under the buried layer 202, so as to avoid or reduce the occurrence of substrate leakage current.

在一些實施例中，如第1圖所示，深溝槽隔離結構118環繞第二井區104。在一些實施例中，如第1圖所示，深溝槽隔離結構118環繞第三井區106與第四井區108。在一些實施例中，由於深溝槽隔離結構118環繞第一井區102、第二井區104、第三井區106、第四井區108以及形成於此些井區中的摻雜區(例如:源極區110、汲極區112)，因此可進一步避免或減少基板漏電流的發生。In some embodiments, as shown in FIG. 1, the deep trench isolation structure 118 surrounds the second well region 104. In some embodiments, as shown in FIG. 1, the deep trench isolation structure 118 surrounds the third well region 106 and the fourth well region 108. In some embodiments, since the deep trench isolation structure 118 surrounds the first well region 102, the second well region 104, the third well region 106, the fourth well region 108, and the doped regions formed in these well regions (for example, : Source region 110, drain region 112), so that the occurrence of substrate leakage current can be further avoided or reduced.

在一些實施例中，深溝槽隔離結構118直接接觸第二井區104、第三井區106與第四井區108。在一些實施例中，如第1圖所示，深溝槽隔離結構118直接接觸第二井區104的第三側104c以及相對於第三側104c的第四側104d。在一些實施例中，深溝槽隔離結構118直接接觸第二井區104的第三側104c以及第四側104d但與第二井區104的第一側104a以及第二側104b相互分離。在一些實施例中，深溝槽隔離結構118與第二井區104的第一側104a被第三井區106分隔而彼此分離，深溝槽隔離結構118與第二井區104的第二側104b被第四井區108分隔而彼此分離。In some embodiments, the deep trench isolation structure 118 directly contacts the second well region 104, the third well region 106 and the fourth well region 108. In some embodiments, as shown in FIG. 1, the deep trench isolation structure 118 directly contacts the third side 104c of the second well region 104 and the fourth side 104d opposite to the third side 104c. In some embodiments, the deep trench isolation structure 118 directly contacts the third side 104c and the fourth side 104d of the second well region 104 but is separated from the first side 104a and the second side 104b of the second well region 104. In some embodiments, the deep trench isolation structure 118 and the first side 104a of the second well region 104 are separated from each other by the third well region 106, and the deep trench isolation structure 118 and the second side 104b of the second well region 104 are separated by The fourth well regions 108 are separated and separated from each other.

在一些實施例中，可進行適當的蝕刻製程於半導體基板100中蝕刻出溝槽118a，接著於溝槽118a中填入適當的絕緣材料(例如:氧化矽、氮化矽或氮氧化矽)以形成深溝槽隔離結構108。在一些實施例中，上述蝕刻製程為非等向性蝕刻製程(例如:電漿蝕刻製程)，而可使溝槽118a具有較大的深寬比(亦即，H/W)。舉例而言，溝槽118a的深寬比可為10至20。在一些實施例中，可進行適當的平坦化製程(例如:化學機械研磨製程)移除溝槽118a外的絕緣材料，使得深溝槽隔離結構108的頂表面大抵上與半導體基板100之頂表面100T共平面。In some embodiments, a suitable etching process may be performed to etch the trench 118a in the semiconductor substrate 100, and then a suitable insulating material (such as silicon oxide, silicon nitride, or silicon oxynitride) may be filled in the trench 118a. A deep trench isolation structure 108 is formed. In some embodiments, the above-mentioned etching process is an anisotropic etching process (for example, a plasma etching process), so that the trench 118a can have a larger aspect ratio (ie, H/W). For example, the aspect ratio of the trench 118a may be 10-20. In some embodiments, a suitable planarization process (such as a chemical mechanical polishing process) may be performed to remove the insulating material outside the trench 118a, so that the top surface of the deep trench isolation structure 108 is substantially equal to the top surface 100T of the semiconductor substrate 100. Coplanar.

請繼續參照第2、3圖，根據一些實施例，半導體裝置10包括形成於第一井區102與第二井區104之上的閘極結構208。在一些實施例中，閘極結構208可圍繞汲極區112。閘極結構208可包括閘極介電層208a以及位於閘極介電層208a上的閘極電極層208b。Please continue to refer to FIGS. 2 and 3. According to some embodiments, the semiconductor device 10 includes a gate structure 208 formed on the first well region 102 and the second well region 104. In some embodiments, the gate structure 208 may surround the drain region 112. The gate structure 208 may include a gate dielectric layer 208a and a gate electrode layer 208b on the gate dielectric layer 208a.

舉例而言，閘極介電層208a可由氧化矽、氮化矽、氮氧化矽、高介電常數(high-k)介電材料、其他任何適合之介電材料或上述之組合所形成。舉例而言，上述高介電常數介電材料可為LaO、AlO、ZrO、TiO、Ta₂ O₅ 、Y₂ O₃ 、SrTiO₃ （STO）、BaTiO₃ （BTO）、BaZrO、HfO₂ 、HfO₃ 、HfZrO、HfLaO、HfSiO、HfSiON、LaSiO、AlSiO、HfTaO、HfTiO、HfTaTiO、HfAlON、（Ba,Sr）TiO₃ （BST）、Al₂ O₃ 、其他合適之高介電常數介電材料或上述組合。在一些實施例中，可藉由化學氣相沉積法、原子層沉積法或其他適當之方法形成閘極介電層208a。舉例而言，上述化學氣相沉積法可為低壓化學氣相沉積法、低溫化學氣相沉積法、快速升溫化學氣相沉積法或電漿輔助化學氣相沉積法。For example, the gate dielectric layer 208a may be formed of silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, any other suitable dielectric material, or a combination of the foregoing. For example, the above-mentioned high-k dielectric material can be LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfO ₂ , HfO _3. HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba, Sr)TiO ₃ (BST), Al ₂ O ₃ , other suitable high-k dielectric materials or the above combination. In some embodiments, the gate dielectric layer 208a can be formed by chemical vapor deposition, atomic layer deposition, or other suitable methods. For example, the above-mentioned chemical vapor deposition method may be a low pressure chemical vapor deposition method, a low temperature chemical vapor deposition method, a rapid temperature rise chemical vapor deposition method, or a plasma assisted chemical vapor deposition method.

舉例而言，閘極電極層208b可由多晶矽、金屬、金屬合金、金屬氮化物、金屬矽化物、金屬氧化物、其他適當的導電材料或上述之組合所形成。舉例而言，可使用化學氣相沉積製程、物理氣相沉積製程(例如:真空蒸鍍製程或濺鍍製程)、其他適當的製程或上述之組合形成閘極電極層208b。For example, the gate electrode layer 208b may be formed of polysilicon, metal, metal alloy, metal nitride, metal silicide, metal oxide, other suitable conductive materials, or a combination of the foregoing. For example, a chemical vapor deposition process, a physical vapor deposition process (for example, a vacuum vapor deposition process or a sputtering process), other appropriate processes, or a combination of the foregoing can be used to form the gate electrode layer 208b.

在一些實施例中，半導體裝置10可包括形成閘極結構208之側壁上的閘極側壁間隔物210。舉例而言，閘極側壁間隔物210可由絕緣材料(例如:SiO₂ 、SiN、SiON、SiOCN或SiCN)形成。舉例而言，可以化學氣相沉積製程或其他合適的製程形成絕緣材料之毯覆層(blanket layer)，接著對上述絕緣材料之毯覆層進行非等向性的(anisotropic)蝕刻而於閘極結構208之側壁上形成閘極側壁間隔物210。In some embodiments, the semiconductor device 10 may include gate sidewall spacers 210 formed on the sidewalls of the gate structure 208. For example, the gate sidewall spacer 210 may be formed of an insulating material (eg, SiO ₂ , SiN, SiON, SiOCN, or SiCN). For example, a blanket layer of insulating material can be formed by a chemical vapor deposition process or other suitable processes, and then the blanket layer of insulating material can be anisotropically etched on the gate electrode Gate sidewall spacers 210 are formed on the sidewalls of the structure 208.

綜合上述，本發明實施例之半導體裝置10包括位於第二井區104第一側104a的第三井區106、位於第二井區104第二側104b的第四井區108、以及環繞第一井區102、第二井區104、第三井區106與第四井區108的深溝槽隔離結構118，因此可降低半導體裝置10之尺寸、減少或避免基板漏電流的發生並避免或減輕閂鎖效應。In summary, the semiconductor device 10 of the embodiment of the present invention includes a third well region 106 located on the first side 104a of the second well region 104, a fourth well region 108 located on the second side 104b of the second well region 104, and surrounding the first The deep trench isolation structure 118 of the well region 102, the second well region 104, the third well region 106, and the fourth well region 108 can reduce the size of the semiconductor device 10, reduce or avoid the occurrence of substrate leakage current, and avoid or reduce latching. Locking effect.

在一些實施例中，如第4圖所示，複數個半導體裝置10可設置於半導體基板100中及/或上，由於此些半導體裝置10之第二井區104僅部分地被第三井區106與第四井區108圍繞，因此此些半導體裝置10在方向X上具有較小的尺寸而可以增加集積密度。在一些實施例中，如第4圖所示，相鄰兩半導體裝置10之間的距離D1可為3至4微米。In some embodiments, as shown in FIG. 4, a plurality of semiconductor devices 10 may be disposed in and/or on the semiconductor substrate 100, since the second well region 104 of these semiconductor devices 10 is only partially covered by the third well region 106 is surrounded by the fourth well region 108, so these semiconductor devices 10 have a smaller size in the direction X, which can increase the accumulation density. In some embodiments, as shown in FIG. 4, the distance D1 between two adjacent semiconductor devices 10 may be 3 to 4 microns.

綜合上述，本發明實施例之半導體裝置包括圍繞源極區與汲極區的深溝槽隔離結構，因此可減少或避免基板漏電流的發生。此外，在本發明實施例之半導體裝置中，汲極區形成於第一井區中，源極區形成於第二井區中，與埋藏層電性連接的第三井區與第四井區僅部分地圍繞第二井區，因此可降低半導體裝置的尺寸並可避免或減輕閂鎖效應。In summary, the semiconductor device of the embodiment of the present invention includes a deep trench isolation structure surrounding the source region and the drain region, so that the occurrence of substrate leakage current can be reduced or avoided. In addition, in the semiconductor device of the embodiment of the present invention, the drain region is formed in the first well region, the source region is formed in the second well region, and the third and fourth well regions are electrically connected to the buried layer. The second well region is only partially surrounded, so the size of the semiconductor device can be reduced and the latch-up effect can be avoided or reduced.

前述內文概述了許多實施例的特徵部件，使本技術領域中具有通常知識者可以從各個方面更佳地了解本發明實施例。本技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明實施例的發明精神與範圍。在不背離本發明實施例的發明精神與範圍之前提下，可對本發明實施例進行各種改變、置換或修改，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。另外，雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，且並非所有優點都已於此詳加說明。The foregoing text summarizes the characteristic components of many embodiments, so that those skilled in the art can better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand, and can easily design or modify other processes and structures based on the embodiments of the present invention, so as to achieve the same purpose and/or achieve the same purpose as the embodiments described herein. The same advantages. Those skilled in the art should also understand that these equivalent structures do not depart from the inventive spirit and scope of the embodiments of the present invention. Without departing from the spirit and scope of the embodiments of the present invention, various changes, substitutions or modifications can be made to the embodiments of the present invention. Therefore, the scope of protection of the present invention shall be subject to those defined by the appended patent scope. In addition, although the present invention has been disclosed as above in several preferred embodiments, it is not intended to limit the present invention, and not all the advantages have been described in detail here.

10:半導體裝置；100:半導體基板；100T:半導體基板的頂表面；100B:半導體基板的底表面；102:第一井區；104:第二井區；104a:第二井區之第一側；104b:第二井區之第二側；104c:第二井區之第三側；104d:第二井區之第四側；106:第三井區；108:第四井區；110:源極區；112:汲極區；114:摻雜區；116:摻雜區；118:深溝槽隔離結構；118a:溝槽；A-A:剖面線；B-B:剖面線；X、Y:方向；202:埋藏層；204:摻雜區；206:摻雜區；207:摻雜區；208:閘極結構；208a:閘極介電層；208b:閘極電極層；210:閘極側壁間隔物；302:摻雜區；304:摻雜區；W:寬度；H:深度。10: semiconductor device; 100: semiconductor substrate; 100T: the top surface of the semiconductor substrate; 100B: the bottom surface of the semiconductor substrate; 102: the first well region; 104: the second well region; 104a: the first side of the second well region 104b: the second side of the second well area; 104c: the third side of the second well area; 104d: the fourth side of the second well area; 106: the third well area; 108: the fourth well area; 110: Source region; 112: drain region; 114: doped region; 116: doped region; 118: deep trench isolation structure; 118a: trench; AA: profile line; BB: profile line; X, Y: direction; 202: buried layer; 204: doped region; 206: doped region; 207: doped region; 208: gate structure; 208a: gate dielectric layer; 208b: gate electrode layer; 210: gate sidewall spacing Object; 302: doped area; 304: doped area; W: width; H: depth.

以下將配合所附圖式詳述本發明實施例。應注意的是，各種特徵部件並未按照比例繪製且僅用以說明例示。事實上，元件的尺寸可能經放大或縮小，以清楚地表現出本發明實施例的技術特徵。第1圖繪示出本發明實施例之半導體裝置10的部分上視圖。第2圖係沿著第1圖的剖面線A-A繪示出本發明實施例之半導體裝置10的部分剖面圖。第3圖係沿著第1圖的剖面線B-B繪示出本發明實施例之半導體裝置10的部分剖面圖。第4圖繪示出本發明實施例之複數個半導體裝置10的部分上視圖。The embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that the various characteristic components are not drawn to scale and are only used for illustration and illustration. In fact, the size of the element may be enlarged or reduced to clearly show the technical features of the embodiment of the present invention. FIG. 1 shows a partial top view of a semiconductor device 10 according to an embodiment of the present invention. FIG. 2 is a partial cross-sectional view of the semiconductor device 10 according to the embodiment of the present invention along the section line A-A of FIG. 1. FIG. FIG. 3 is a partial cross-sectional view of the semiconductor device 10 according to the embodiment of the present invention along the section line B-B of FIG. 1. FIG. FIG. 4 shows a partial top view of a plurality of semiconductor devices 10 according to an embodiment of the present invention.

10:半導體裝置 10: Semiconductor device

100:半導體基板 100: Semiconductor substrate

102:第一井區 102: The first well area

104:第二井區 104: The second well area

104a:第二井區之第一側 104a: The first side of the second well area

104b:第二井區之第二側 104b: The second side of the second well area

104c:第二井區之第三側 104c: The third side of the second well area

104d:第二井區之第四側 104d: The fourth side of the second well area

106:第三井區 106: The third well area

108:第四井區 108: The fourth well area

110:源極區 110: source region

112:汲極區 112: Drain Region

114:摻雜區 114: doped area

116:摻雜區 116: doped area

118:深溝槽隔離結構 118: Deep trench isolation structure

A-A:剖面線 A-A: Section line

B-B:剖面線 B-B: Section line

X:方向 X: direction

Y:方向 Y: direction

Claims

一種半導體裝置，包括：一半導體基板；一埋藏層，設置於該半導體基板中；一第一井區，設置於該埋藏層上及該半導體基板中；一第二井區，設置於該埋藏層上及該半導體基板中，其中該第二井區圍繞該第一井區；一第三井區與一第四井區，設置於該埋藏層上及該半導體基板中，其中該第三井區與該第四井區位於該第二井區的相對兩側；一源極區，設置於該第二井區中；一汲極區，設置於該第一井區中；一閘極結構，設置於該第一井區與該第二井區之上；以及一深溝槽隔離結構，設置於該半導體基板中且圍繞該第一井區、該第二井區、該第三井區與該第四井區，其中該深溝槽隔離結構穿過該埋藏層；其中該埋藏層、該第一井區、該第三井區以及該第四井區具有一第一導電型態，該第二井區具有相反於該第一導電型態的一第二導電型態。 A semiconductor device includes: a semiconductor substrate; a buried layer arranged in the semiconductor substrate; a first well area arranged on the buried layer and in the semiconductor substrate; and a second well area arranged in the buried layer And in the semiconductor substrate, wherein the second well region surrounds the first well region; a third well region and a fourth well region are arranged on the buried layer and in the semiconductor substrate, wherein the third well region Located on opposite sides of the second well area with the fourth well area; a source area arranged in the second well area; a drain area arranged in the first well area; a gate structure, Is disposed on the first well region and the second well region; and a deep trench isolation structure is disposed in the semiconductor substrate and surrounds the first well region, the second well region, the third well region and the The fourth well region, wherein the deep trench isolation structure passes through the buried layer; wherein the buried layer, the first well region, the third well region, and the fourth well region have a first conductivity type, and the second The well region has a second conductivity type opposite to the first conductivity type.

如申請專利範圍第1項所述之半導體裝置，其中該第三井區與該第四井區直接接觸該埋藏層。 According to the semiconductor device described in claim 1, wherein the third well area and the fourth well area directly contact the buried layer.

如申請專利範圍第1項所述之半導體裝置，其中該第一導電型態為N型，該第二導電型態為P型。 The semiconductor device described in claim 1, wherein the first conductivity type is N-type, and the second conductivity type is P-type.

如申請專利範圍第1項所述之半導體裝置，更包括：一摻雜區，設置於該第三井區中，其中該摻雜區具有該第一導電型態。 The semiconductor device described in item 1 of the scope of patent application includes: A doped region is arranged in the third well region, wherein the doped region has the first conductivity type.

如申請專利範圍第1項所述之半導體裝置，其中該深溝槽隔離結構直接接觸該第二井區、該第三井區以及該第四井區。 According to the semiconductor device described in claim 1, wherein the deep trench isolation structure directly contacts the second well region, the third well region, and the fourth well region.

一種半導體裝置，包括：一半導體基板；一埋藏層，設置於該半導體基板中；一第一井區，設置於該埋藏層上及該半導體基板中；一第二井區，設置於該埋藏層上及該半導體基板中，其中該第二井區環繞該第一井區；一第三井區與一第四井區，設置於該埋藏層上及該半導體基板中，其中該第三井區與該第四井區相鄰於該第二井區且該第三井區與該第四井區彼此分離，其中該埋藏層、該第一井區、該第三井區以及該第四井區具有一第一導電型態，該第二井區具有相反於該第一導電型態的一第二導電型態；一源極區，設置於該第二井區中；一汲極區，設置於該第一井區中；一閘極結構，設置於該第一井區與該第二井區之上；以及一深溝槽隔離結構，設置於該半導體基板中且環繞該第一井區、該第二井區、該第三井區與該第四井區，其中該深溝槽隔離結構穿過該埋藏層且該深溝槽隔離結構的一底表面低於該埋藏層的一底表面。 A semiconductor device includes: a semiconductor substrate; a buried layer arranged in the semiconductor substrate; a first well area arranged on the buried layer and in the semiconductor substrate; and a second well area arranged in the buried layer And in the semiconductor substrate, wherein the second well region surrounds the first well region; a third well region and a fourth well region are arranged on the buried layer and in the semiconductor substrate, wherein the third well region The fourth well area is adjacent to the second well area and the third well area and the fourth well area are separated from each other, wherein the buried layer, the first well area, the third well area and the fourth well area The region has a first conductivity type, the second well region has a second conductivity type opposite to the first conductivity type; a source region is disposed in the second well region; and a drain region, Disposed in the first well region; a gate structure disposed on the first well region and the second well region; and a deep trench isolation structure disposed in the semiconductor substrate and surrounding the first well region , The second well area, the third well area and the fourth well area, wherein the deep trench isolation structure passes through the buried layer and a bottom surface of the deep trench isolation structure is lower than a bottom surface of the buried layer.

如申請專利範圍第6項所述之半導體裝置，更包括：一第一摻雜區，設置於該第二井區中且具有該第二導電型態，其中該源極區設置於該第一摻雜區中；以及一第二摻雜區，設置於該第一摻雜區中且具有該第二導電型態。 The semiconductor device described in item 6 of the scope of the patent application further includes: a first doped region disposed in the second well region and having the second conductivity type, wherein The source region is disposed in the first doped region; and a second doped region is disposed in the first doped region and has the second conductivity type.

如申請專利範圍第7項所述之半導體裝置，其中該源極區直接接觸該第二摻雜區。 According to the semiconductor device described in claim 7, wherein the source region directly contacts the second doped region.

如申請專利範圍第6項所述之半導體裝置，其中該第一導電型態為N型，該第二導電型態為P型。 The semiconductor device described in item 6 of the scope of patent application, wherein the first conductivity type is N-type, and the second conductivity type is P-type.

如申請專利範圍第6項所述之半導體裝置，其中該深溝槽隔離結構直接接觸該第二井區、第三井區以及該第四井區。 According to the semiconductor device described in claim 6, wherein the deep trench isolation structure directly contacts the second well region, the third well region, and the fourth well region.

如申請專利範圍第6項所述之半導體裝置，其中該第三井區與該第四井區直接接觸該埋藏層。 The semiconductor device described in item 6 of the scope of patent application, wherein the third well region and the fourth well region directly contact the buried layer.

一種半導體裝置之形成方法，包括：提供一半導體基板，其中該半導體基板中設置有一埋藏層；於該半導體基板中及該埋藏層之上形成一第一井區、一第二井區、一第三井區以及一第四井區，其中該第二井區環繞該第一井區，該第三井區與該第四井區部分地環繞該第二井區，該第三井區與該第四井區彼此分離，其中該埋藏層、該第一井區、該第三井區以及該第四井區具有一第一導電型態，該第二井區具有相反於該第一導電型態的一第二導電型態；於該第二井區中形成一源極區；於該第一井區中形成一汲極區；於該第一井區與該第二井區之上形成一閘極結構；以及於該半導體基板中形成一深溝槽隔離結構，其中該深溝槽隔離結構圍繞該第一井區、該第二井區、該第三井區與該第四井區，且該深溝槽隔離結構穿過該埋藏層。 A method for forming a semiconductor device includes: providing a semiconductor substrate, wherein a buried layer is provided in the semiconductor substrate; forming a first well region, a second well region, and a second well region in the semiconductor substrate and on the buried layer A three well area and a fourth well area, wherein the second well area surrounds the first well area, the third well area and the fourth well area partially surround the second well area, the third well area and the The fourth well area is separated from each other, wherein the buried layer, the first well area, the third well area and the fourth well area have a first conductivity type, and the second well area has a conductivity type opposite to the first conductivity type Form a second conductivity type in the second well region; form a source region in the second well region; form a drain region in the first well region; form on the first well region and the second well region A gate structure; and forming a deep trench isolation structure in the semiconductor substrate, wherein the deep trench isolation structure surrounds the first well region, the second well region, the third well region and the fourth well region, and The deep trench isolation structure passes through the buried layer.

如申請專利範圍第12項所述之半導體裝置之形成方法，其中於該半導體基板中形成該深溝槽隔離結構的步驟包括：蝕刻該半導體基板以於該半導體基板中形成一溝槽；以及於該溝槽中填入一絕緣材料。 According to the method for forming a semiconductor device according to claim 12, wherein the step of forming the deep trench isolation structure in the semiconductor substrate includes: etching the semiconductor substrate to form a trench in the semiconductor substrate; and An insulating material is filled in the trench.

如申請專利範圍第13項所述之半導體裝置之形成方法，其中該溝槽穿過該埋藏層且環繞該該第一井區、第二井區、該第三井區與該第四井區。 The method for forming a semiconductor device according to claim 13, wherein the trench penetrates the buried layer and surrounds the first well area, the second well area, the third well area, and the fourth well area .

如申請專利範圍第12項所述之半導體裝置之形成方法，其中該第一導電型態為N型，該第二導電型態為P型。 According to the method for forming a semiconductor device described in claim 12, the first conductivity type is N-type, and the second conductivity type is P-type.

如申請專利範圍第12項所述之半導體裝置之形成方法，更包括：於該第二井區中形成一第一摻雜區，其中該第一摻雜區具有該第二導電型態；以及於該第一摻雜區中形成一第二摻雜區，其中該第二摻雜區具有該第二導電型態且直接接觸該源極區。 The method for forming a semiconductor device as described in claim 12, further comprising: forming a first doped region in the second well region, wherein the first doped region has the second conductivity type; and A second doped region is formed in the first doped region, wherein the second doped region has the second conductivity type and directly contacts the source region.

如申請專利範圍第12項所述之半導體裝置之形成方法，更包括：於該第三井區中形成一摻雜區，其中該摻雜區具有該第一導電型態。 According to the method for forming a semiconductor device described in claim 12, further comprising: forming a doped region in the third well region, wherein the doped region has the first conductivity type.

如申請專利範圍第12項所述之半導體裝置之形成方法，其中該深溝槽隔離結構直接接觸該第二井區、第三井區以及該第四井區。 According to the method for forming a semiconductor device described in claim 12, wherein the deep trench isolation structure directly contacts the second well region, the third well region and the fourth well region.

如申請專利範圍第12項所述之半導體裝置之形成方法，其中該第三井區與該第四井區直接接觸該埋藏層。 According to the method for forming a semiconductor device described in claim 12, wherein the third well region and the fourth well region directly contact the buried layer.