TWI723822B - Test method for memory device - Google Patents

Test method for memory device Download PDF

Info

Publication number
TWI723822B
TWI723822B TW109110421A TW109110421A TWI723822B TW I723822 B TWI723822 B TW I723822B TW 109110421 A TW109110421 A TW 109110421A TW 109110421 A TW109110421 A TW 109110421A TW I723822 B TWI723822 B TW I723822B
Authority
TW
Taiwan
Prior art keywords
data
read
cell array
memory cell
backup information
Prior art date
Application number
TW109110421A
Other languages
Chinese (zh)
Other versions
TW202137229A (en
Inventor
潘嗣文
Original Assignee
華邦電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 華邦電子股份有限公司 filed Critical 華邦電子股份有限公司
Priority to TW109110421A priority Critical patent/TWI723822B/en
Application granted granted Critical
Publication of TWI723822B publication Critical patent/TWI723822B/en
Publication of TW202137229A publication Critical patent/TW202137229A/en

Links

Images

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

A test method for a memory device includes: disabling a redundancy function of the memory device, and writing a first data to a first memory array; enabling the redundancy function of the memory device, and writing a second data to a second memory array, where the first data and the second data are complementary; reading a redundancy information from a non-volatile memory block according to a margin condition, and obtaining a first readout data from the second memory array based on the redundancy information; and generating a first test result by comparing the second data and the first readout data. The second memory array includes part memory cells of the first memory array and at least one redundancy memory cell.

Description

記憶體裝置的測試方法Test method of memory device

本發明是有關於一種記憶體裝置的測試方法,且特別是有關於一種動態隨機存取記憶體的記憶體裝置的測試方法。The present invention relates to a testing method of a memory device, and more particularly to a testing method of a memory device with dynamic random access memory.

在動態隨機存取記憶體裝置中,為了提升製作上的良率,常設置多個備援記憶胞以置代在製造過程中損壞的主記憶胞。相關於上述置代狀態的備援資訊,常透過一次性可編程記憶體來儲存,這個一次性可編程記憶體可內嵌於記憶體裝置中。In a dynamic random access memory device, in order to improve the manufacturing yield, multiple spare memory cells are often set to replace the main memory cells damaged during the manufacturing process. The backup information related to the above-mentioned substitution state is often stored through a one-time programmable memory, which can be embedded in a memory device.

一次性可編程記憶體的測試動作通常由供應廠商執行。供應廠商會針對一次性可編程記憶體進行正常條件以及邊界條件等多種測試動作。然而,當一次性可編程記憶體被內嵌入動態隨機存取記憶體的記憶體裝置中時,可能因為加工過程產生變異。而在習知的技術中,當執行記憶體裝置的測試動作時,並不會針對一次性可編程記憶體再次執行多種條件的測試動作,而僅會通過正常條件來讀取一次性可編程記憶體中的備援資訊。如此一來,記憶體裝置的測試動作中的錯誤覆蓋率將會被降低。The test action of the one-time programmable memory is usually performed by the supplier. Suppliers will carry out various test actions such as normal conditions and boundary conditions for the one-time programmable memory. However, when the one-time programmable memory is embedded in a memory device with a dynamic random access memory, variation may occur due to the processing process. In the conventional technology, when the test action of the memory device is executed, the test action of multiple conditions is not executed again for the one-time programmable memory, but the one-time programmable memory is only read under normal conditions. The backup information in the body. As a result, the error coverage rate in the test action of the memory device will be reduced.

本發明提供一種記憶體裝置的測試方法,可有效提升測試的錯誤覆蓋率(fault coverage)。The present invention provides a testing method of a memory device, which can effectively improve the fault coverage of the test.

本發明的記憶體裝置的測試方法包括:關閉記憶體裝置的備援功能,並對第一記憶胞陣列寫入第一資料;啟動記憶體裝置的備援功能,並對第二記憶胞陣列寫入第二資料,其中第一資料與第二資料互補;依據邊界條件,對非揮發記憶區塊讀取備援資訊,基於備援資訊,讀取第二記憶胞陣列以獲得第一讀取資料;以及依據比較第二資料與第一讀取資料以產生第一測試結果。其中,第二記憶胞陣列包括第一記憶胞陣列的部分記憶胞以及至少一備援記憶胞。The test method of the memory device of the present invention includes: turning off the backup function of the memory device and writing first data to the first memory cell array; activating the backup function of the memory device and writing to the second memory cell array Enter the second data, where the first data and the second data are complementary; according to the boundary conditions, read the backup information for the non-volatile memory block, and based on the backup information, read the second memory cell array to obtain the first read data ; And based on comparing the second data with the first read data to generate the first test result. Wherein, the second memory cell array includes part of the memory cells of the first memory cell array and at least one backup memory cell.

基於上述,本發明透過在正常條件以及邊界條件中,使記憶體裝置中的非揮發記憶區塊分別提供不同的備援資訊,基於不同的備援資訊來執行記憶胞陣列的讀寫動作,藉以檢測出非揮發記憶區塊在邊界條件中是否可維持正常用運作。基於不大幅增加記憶體裝置的測試時間的前提下,提升記憶體裝置測試的錯誤覆蓋率,提升記憶體裝置的可靠度。Based on the above, the present invention allows the non-volatile memory blocks in the memory device to provide different backup information under normal conditions and boundary conditions, and executes the read and write operations of the memory cell array based on the different backup information. Detect whether the non-volatile memory block can maintain normal operation under the boundary conditions. On the premise of not greatly increasing the test time of the memory device, the error coverage rate of the memory device test is improved, and the reliability of the memory device is improved.

請參照圖1,圖1為本發明一實施例的記憶體裝置及測試設備的示意圖。記憶體裝置100包括記憶體110、非揮發記憶區塊120以及暫存器鏈LC。記憶體裝置100與測試設備TE相耦接,測試設備TE並發送命令以執行對記憶體110及/或非揮發記憶區塊120的測試動作。在本實施例中,記憶體110、非揮發記憶區塊120以及暫存器鏈LC可以設置在相同的積體電路中。亦即,非揮發記憶區塊120可內嵌在積體電路中。非揮發記憶區塊120可以是電子熔絲電路或其他的一次性可編程記憶體。此外,記憶體110可以為動態隨機存取記憶體。測試設備TE可以為積體電路外的測試機台,或是設置在積體電路中用以執行內建自我測試(Built-In Self-Test, BIST)的電路。Please refer to FIG. 1. FIG. 1 is a schematic diagram of a memory device and testing equipment according to an embodiment of the present invention. The memory device 100 includes a memory 110, a non-volatile memory block 120, and a register chain LC. The memory device 100 is coupled to the test equipment TE, and the test equipment TE sends commands to perform a test action on the memory 110 and/or the non-volatile memory block 120. In this embodiment, the memory 110, the non-volatile memory block 120, and the register chain LC can be arranged in the same integrated circuit. That is, the non-volatile memory block 120 can be embedded in the integrated circuit. The non-volatile memory block 120 may be an electronic fuse circuit or other one-time programmable memory. In addition, the memory 110 may be a dynamic random access memory. The test equipment TE can be a test machine outside the integrated circuit, or a circuit set in the integrated circuit to perform a built-in self-test (BIST).

在本實施例中,非揮發記憶區塊120可記錄備援資訊FI。當記憶體110中部分主要記憶胞發生損壞時,可透過記憶體110中的備援記憶胞來置代,並維持記憶體裝置100的正常運作。備援資訊FI用以記錄上述的備援狀態。In this embodiment, the non-volatile memory block 120 can record the backup information FI. When some of the main memory cells in the memory 110 are damaged, the spare memory cells in the memory 110 can be used to replace them, and the normal operation of the memory device 100 can be maintained. The backup information FI is used to record the above-mentioned backup status.

在執行測試動作時,測試設備TE可使非揮發記憶區塊120中的備援資訊FI被讀出,並使備援資訊FI被載入至暫存器鏈LC。暫存器鏈LC由多個暫存器所構成。並且,在執行記憶體110的讀寫測試動作的過程中,當備援功能被啟動時,記憶體110可依據備援資訊FI來提供可正常工作的記憶胞以執行測試動作。When performing a test operation, the test equipment TE can read the backup information FI in the non-volatile memory block 120 and load the backup information FI into the register chain LC. The register chain LC is composed of multiple registers. In addition, in the process of executing the read/write test action of the memory 110, when the backup function is activated, the memory 110 can provide a working memory cell according to the backup information FI to perform the test action.

關於測試動作的流程,請參照圖2的本發明實施例的記憶體測試動作的流程圖。其中,在步驟S210中,關閉記憶體裝置的備援功能,並對第一記憶胞陣列寫入第一資料。在此,基於備援功能為被關閉的狀態,第一記憶胞陣列所包括的記憶胞皆為主記憶胞,並不包括備援記憶胞。For the flow of the test action, please refer to the flowchart of the memory test action in the embodiment of the present invention in FIG. 2. Wherein, in step S210, the backup function of the memory device is turned off, and the first data is written to the first memory cell array. Here, based on the state where the backup function is turned off, the memory cells included in the first memory cell array are all the main memory cells, and the backup memory cells are not included.

接著,步驟S220中,啟動記憶體裝置的備援功能,並對第二記憶胞陣列寫入第二資料。在此,第一記憶胞陣列與第二記憶胞陣列的邏輯位址是相同的。基於備援功能被啟動的前提下,第二記憶胞陣列包括第一記憶胞陣列的部分記憶胞以及一個或多個備援記憶胞。並且,上述的第一資料與第二資料為互補的狀態。以八個位元的資料為範例,第一資料可以為11111111,第二資料則可以為00000000。或者,也可以設定第一資料可以為00000000,第二資料則可以為11111111。Next, in step S220, the backup function of the memory device is activated, and the second data is written to the second memory cell array. Here, the logical addresses of the first memory cell array and the second memory cell array are the same. Based on the premise that the backup function is activated, the second memory cell array includes part of the memory cells of the first memory cell array and one or more backup memory cells. In addition, the above-mentioned first data and second data are in a complementary state. Taking eight-bit data as an example, the first data can be 11111111, and the second data can be 00000000. Alternatively, the first data can be set to 00000000, and the second data can be 11111111.

值得一提的,在步驟S220中,記憶體裝置的備援功能,是依據在正常條件下,對非揮發記憶區塊進行讀取的備援資訊來進行的。亦即,第二記憶胞陣列中的記憶胞的組成,是對應正常條件的備援資訊。It is worth mentioning that in step S220, the backup function of the memory device is performed based on the backup information read from the non-volatile memory block under normal conditions. That is, the composition of the memory cells in the second memory cell array is backup information corresponding to normal conditions.

在步驟S230中,則依據一邊界(margin)條件,來進行記憶體裝置中的非揮發記憶區塊的讀取動作,並讀出非揮發記憶區塊的備援資訊。再基於備援資訊,讀取第二記憶胞陣列以獲得讀取資料。In step S230, a read operation of the non-volatile memory block in the memory device is performed according to a margin condition, and the backup information of the non-volatile memory block is read. Based on the backup information, the second memory cell array is read to obtain the read data.

在步驟S240中,則進行第二資料與讀取資料的比較動作,並藉以產生測試結果。在此請注意,由於讀取資料是基於邊界條件的備援資訊來讀出的,若邊界條件的備援資訊是正確的,那邊界條件的備援資訊與正常條件的備援資訊將會相同,而第二資料與讀取資料則應該是相同的。相對的,若邊界條件的備援資訊是錯誤的,那邊界條件的備援資訊與正常條件的備援資訊將會不同,而第二資料與讀取資料則應該是不同的。所以,依據第二資料與讀取資料的比較動作,可得知非揮發記憶區塊在邊界條件下使否仍可正常運作,並藉以判定記憶體裝置是否可正常出貨。In step S240, a comparison operation between the second data and the read data is performed, thereby generating a test result. Please note here that since the read data is read based on the backup information of the boundary conditions, if the backup information of the boundary conditions is correct, the backup information of the boundary conditions and the backup information of the normal conditions will be the same , And the second data and the read data should be the same. In contrast, if the backup information of the boundary condition is wrong, the backup information of the boundary condition and the backup information of the normal condition will be different, and the second data and the read data should be different. Therefore, based on the comparison between the second data and the read data, it can be known whether the non-volatile memory block can still operate normally under the boundary conditions, and it can be used to determine whether the memory device can be shipped normally.

請參照圖3,圖3為本發明第一實施例的記憶體裝置的測試動作的流程圖。其中,步驟S310中,關閉記憶體裝置的備援功能,並針對第一記憶胞陣列的每個位元進行資料1(第一資料)的寫入動作。接著,基於正常狀態下的備援資訊,在步驟S320中,開啟備援功能,並針對第二記憶胞陣列的每個位元進行資料0(第二資料)的寫入動作。在此,第一記憶胞陣列與第二記憶胞陣列對應相同的邏輯位址。且第二記憶胞陣列包括第一記憶胞陣列中部分的記憶胞,並包括一個或多個備援記憶胞。Please refer to FIG. 3, which is a flowchart of the test operation of the memory device according to the first embodiment of the present invention. Wherein, in step S310, the backup function of the memory device is turned off, and a data 1 (first data) write operation is performed for each bit of the first memory cell array. Then, based on the backup information in the normal state, in step S320, the backup function is turned on, and data 0 (second data) is written for each bit of the second memory cell array. Here, the first memory cell array and the second memory cell array correspond to the same logical address. And the second memory cell array includes part of the memory cells in the first memory cell array, and includes one or more backup memory cells.

在步驟S330中,依據邊界條件來讀取記憶體裝置中的非揮發記憶區塊中的備援資訊。在第一實施例中,相對的邊界條件的正常條件,為依據正常讀取電壓來對非揮發記憶區塊進行讀取,並藉以獲得備援資訊。而在邊界條件下,則是透過提高或降低正常讀取電壓以產生邊界讀取電壓,並依據邊界讀取電壓對非揮發記憶區塊進行讀取,來獲得備援資訊。亦即,對應正常讀取電壓的備援資訊,與對應邊界讀取電壓的備援資訊,可能相同的或是不相同的。In step S330, the backup information in the non-volatile memory block in the memory device is read according to the boundary conditions. In the first embodiment, the normal condition of the relative boundary condition is to read the non-volatile memory block according to the normal read voltage to obtain backup information. Under boundary conditions, the normal read voltage is increased or decreased to generate the boundary read voltage, and the non-volatile memory block is read according to the boundary read voltage to obtain backup information. That is, the backup information corresponding to the normal read voltage and the backup information corresponding to the boundary read voltage may be the same or different.

步驟S340中,則基於對應邊界讀取電壓的備援資訊,來讀取第二記憶胞陣列,並藉以獲得讀取資料。透過針對讀取資料進行判斷,可以產生測試結果。其中,若讀取資料與第二資料相同,表示非揮發記憶區塊在邊界條件下仍可提供正確的備援資訊,測試結果為測試通過。相對的,若對讀取資料與第二資料不同,表示非揮發記憶區塊在邊界條件下無法提供正確的備援資訊,測試結果為測試不通過。其中,測試通過的記憶體裝置可正常出貨,而測試不通過的記憶體裝置則須被檢出(步驟S350)。In step S340, the second memory cell array is read based on the backup information corresponding to the boundary read voltage to obtain read data. By judging the read data, test results can be generated. Among them, if the read data is the same as the second data, it means that the non-volatile memory block can still provide correct backup information under the boundary conditions, and the test result is the test passed. In contrast, if the read data is different from the second data, it means that the non-volatile memory block cannot provide correct backup information under the boundary conditions, and the test result is that the test fails. Among them, the memory device that passes the test can be shipped normally, and the memory device that fails the test must be detected (step S350).

請參照圖4A至圖4C,圖4A至圖4C為本發明一實施例的實施方式的示意圖。對應圖3的流程,圖4A對應步驟S310,在備援功能被關閉的情況下,對第一記憶胞陣列MA進行資料1的寫入動作。並且,圖4B對應步驟S320,在備援功能被開啟的情況下,對第二記憶胞陣列進行資料0的寫入動作。此時第一記憶胞陣列MA中具有兩個位元的記憶胞MC2、MC4經判斷是損壞的記憶胞,並依據備援資訊以分別由備援記憶胞RC1、RC2所置換。因此,基於正常條件的備援資訊,第二記憶胞陣列包括第一記憶胞陣列MA的部分記憶胞MC1、MC3以及MC5以及備援記憶胞RC1以及RC2。而透過步驟S320的寫入動作,記憶胞MC1、MC3以及MC5以及備援記憶胞RC1以及RC2中的資料,皆被寫為等於資料0。Please refer to FIGS. 4A to 4C. FIGS. 4A to 4C are schematic diagrams of an implementation of an embodiment of the present invention. Corresponding to the flow of FIG. 3, FIG. 4A corresponds to step S310. When the backup function is turned off, data 1 is written to the first memory cell array MA. In addition, FIG. 4B corresponds to step S320. When the backup function is turned on, data 0 is written to the second memory cell array. At this time, the memory cells MC2 and MC4 with two bits in the first memory cell array MA are judged to be damaged memory cells, and are replaced by the backup memory cells RC1 and RC2 respectively according to the backup information. Therefore, based on the backup information under normal conditions, the second memory cell array includes some of the memory cells MC1, MC3, and MC5 of the first memory cell array MA and the backup memory cells RC1 and RC2. Through the write operation in step S320, the data in the memory cells MC1, MC3, and MC5 and the backup memory cells RC1 and RC2 are all written as equal to data 0.

圖4C則對應步驟S330以及S340,依據邊界條件以讀取備援資訊,並在對應邊界條件下的備援資訊有錯誤時,第二記憶胞陣列中所包括的記憶胞可能產生改變,其中,原本用以置換記憶胞MC2的備援記憶胞RC1未被選中,而變更選中備援記憶胞RC3。且備援記憶胞RC3並非用以置換記憶胞MC2。如此一來,由第二記憶胞陣列中讀取的讀取資料中,會變更為0100000000000,與步驟S320寫入的0000000000000不相同。由此可以得知,在邊界條件下所獲得的備援資訊是不正確的。Figure 4C corresponds to steps S330 and S340. The backup information is read according to the boundary conditions, and when the backup information under the corresponding boundary conditions is wrong, the memory cells included in the second memory cell array may be changed. Among them, The backup memory cell RC1 originally used to replace the memory cell MC2 is not selected, and the backup memory cell RC3 is changed. And the backup memory cell RC3 is not used to replace the memory cell MC2. As a result, the read data read from the second memory cell array will be changed to 0100000000000, which is different from the 00000000000000 written in step S320. It can be seen that the backup information obtained under the boundary conditions is incorrect.

請參照圖5,圖5為本發明第二實施例的記憶體裝置的測試動作的流程圖。請注意,在本實施例中,非揮發記憶區塊可提供多個資料位元對以分別對應備援資訊中的多個備援資訊位元。亦即,對應備援資訊中的一個位元,非揮發記憶區塊可提供兩個資料位元來表示。舉例來說,對應備援資訊的一第一位元為非揮發記憶區塊的一第一資料位元及一第二資料位元。其中,當第一資料位元及第二資料位元中的至少其中之一發生被程式化動作時,對應產生的備援資訊的所述第一位元等同是被程式化的狀態。Please refer to FIG. 5. FIG. 5 is a flowchart of a test operation of the memory device according to the second embodiment of the present invention. Please note that in this embodiment, the non-volatile memory block can provide multiple data bit pairs to respectively correspond to multiple backup information bits in the backup information. That is, corresponding to one bit in the backup information, the non-volatile memory block can provide two data bits to represent it. For example, a first bit corresponding to the backup information is a first data bit and a second data bit of the non-volatile memory block. Wherein, when at least one of the first data bit and the second data bit undergoes a programmed action, the first bit corresponding to the generated backup information is equivalent to a programmed state.

在本發明第二實施例中,步驟S510中,關閉備援功能,並針對第一記憶胞陣列進行資料1(第一資料)的寫入動作。步驟S520中,開啟備援功能,並針對第二記憶胞陣列進行資料0(第二資料)的寫入動作。接著,在步驟S530中,則讀取非揮發記憶區塊中,資料位元對中的第一資料位元,並依據第一資料位元來產生備援資訊。在此請注意,有別於一般狀況,在本實施例中,備援資訊的一個位元僅依據資料位元對中的單一個位元來產生,並藉以作為邊界條件。In the second embodiment of the present invention, in step S510, the backup function is turned off, and data 1 (first data) is written to the first memory cell array. In step S520, the backup function is turned on, and data 0 (second data) is written to the second memory cell array. Then, in step S530, the first data bit in the data bit pair in the non-volatile memory block is read, and the backup information is generated according to the first data bit. Please note here that, different from the general situation, in this embodiment, one bit of the backup information is generated only based on a single bit in the data bit pair and is used as a boundary condition.

接著,步驟S540中,讀取第二記憶胞陣列以獲得第一讀取資料針對第一讀取資料進行判斷,並藉以獲得測試結果。在此,可透過比較第一讀取資料與第二資料來得知測試結果。在當測試不通過時,執行步驟S550並檢出此記憶體裝置。在當測試通過後,則執行步驟S560。Next, in step S540, the second memory cell array is read to obtain the first read data to determine the first read data, and to obtain the test result. Here, the test result can be obtained by comparing the first read data with the second data. When the test fails, step S550 is executed and the memory device is detected. After the test is passed, step S560 is executed.

步驟S560中,依據正常條件以讀取非揮發記憶區塊來更新備援資訊(以非揮發記憶區塊中的一資料位元對來表示備援資訊的單一位元)。步驟S570中則重新關閉備援功能對第一記憶胞陣列寫入1,步驟S580則開啟備援功能對第二記憶胞陣列寫入0。In step S560, read the non-volatile memory block according to normal conditions to update the backup information (a data bit pair in the non-volatile memory block is used to represent a single bit of the backup information). In step S570, the backup function is turned off again to write 1 to the first memory cell array, and in step S580, the backup function is turned on to write 0 to the second memory cell array.

接著,步驟S590中讀取非揮發記憶區塊的資料位元對中的第二資料位元,並藉以重新產生備援資訊。基於更新後的備援資訊,步驟S5100中讀取第二記憶胞陣列以獲得第二讀取資料,並針對第二讀取資料進行判斷,以產生測試結果。在此,可透過比較第二讀取資料與第二資料來得知測試結果。在當測試不通過時,執行步驟S5110並檢出此記憶體裝置。在當測試通過後,則表示受測的記憶體裝置是可出貨的。Then, in step S590, the second data bit in the data bit pair of the non-volatile memory block is read, and the backup information is regenerated accordingly. Based on the updated backup information, in step S5100, the second memory cell array is read to obtain the second read data, and a judgment is made on the second read data to generate a test result. Here, the test result can be obtained by comparing the second read data with the second data. When the test fails, step S5110 is executed and the memory device is detected. After the test passes, it means that the tested memory device is shippable.

請參照圖6,圖6為本發明第三實施例的記憶體裝置的測試動作的流程圖。步驟S610中,關閉備援功能,並針對第一記憶胞陣列進行資料1(第一資料)的寫入動作。步驟S620中,讀取記憶體區塊中的非揮發記憶區塊的資料位元對中的第一資料位元以產生備援資訊。步驟S630中,開啟備援功能,並對第二記憶胞陣列寫入0(第二資料)。步驟S640中,則讀取非揮發記憶區塊的資料位元對中的第二資料位元以產生備援資訊。步驟S650中,則讀取第二記憶胞陣列以獲得讀取資料針對讀取資料進行判斷,並據以產生測試結果。其中,若讀取資料與第二資料相同,表示第一資料位元與第二資料位元對應的備援資訊相同,則測試結果為測試通過,記憶體裝置可以正常出貨。相對的,若對讀取資料與第二資料不相同,表示第一資料位元與第二資料位元對應的備援資訊並不相同,故測試結果為測試不通過,記憶體裝置須被檢出(步驟S660)。Please refer to FIG. 6. FIG. 6 is a flowchart of a test operation of the memory device according to the third embodiment of the present invention. In step S610, the backup function is turned off, and data 1 (first data) is written to the first memory cell array. In step S620, the first data bit in the data bit pair of the non-volatile memory block in the memory block is read to generate backup information. In step S630, the backup function is turned on, and 0 (second data) is written into the second memory cell array. In step S640, the second data bit in the data bit pair of the non-volatile memory block is read to generate backup information. In step S650, the second memory cell array is read to obtain the read data to determine the read data, and the test result is generated accordingly. Wherein, if the read data is the same as the second data, it means that the backup information corresponding to the first data bit and the second data bit are the same, and the test result is that the test passed, and the memory device can be shipped normally. On the other hand, if the read data is different from the second data, it means that the backup information corresponding to the first data bit and the second data bit are not the same, so the test result is that the test fails, and the memory device must be checked Out (step S660).

參照圖7,圖7為本發明實施例的記憶體裝置的完整測試動作的流程圖。在本實施例中,為強化記憶體裝置測試的可靠度,步驟S710至步驟S730可依序執行如上所述的第一實施例、第二實施例以及第三實施例的測試流程。並在當步驟S710至步驟S730的其中之一發生測試失敗(不通過)的情況,執行記憶體裝置的檢出步驟(步驟S711、S721、S731)。Referring to FIG. 7, FIG. 7 is a flowchart of a complete test operation of the memory device according to an embodiment of the present invention. In this embodiment, in order to enhance the reliability of the memory device test, steps S710 to S730 may sequentially execute the test procedures of the first embodiment, the second embodiment, and the third embodiment as described above. And when a test failure (failure) occurs in one of the steps S710 to S730, the detection step of the memory device (steps S711, S721, S731) is executed.

在當步驟S710、步驟S720以及步驟S730的測試皆通過時,則可執行步驟S740,並依據正常條件以讀取備援資訊,並依據備援資訊來執行記憶體的讀寫測試。若步驟S740的讀寫測試失敗,可以執行步驟S750的第二次的記憶體的讀寫測試。其中,步驟S740、S750的記憶體的讀寫測試中,若其中之一的測試通過時,受測的記憶體裝置可以進行出貨的動作,而若步驟S740、S750的記憶體的讀寫測試皆失敗,則可判定受測的記憶體裝置為不良品,並執行檢出的步驟(步驟S760)。When the tests of step S710, step S720, and step S730 are all passed, step S740 can be executed, and the backup information is read according to normal conditions, and the read and write test of the memory is executed according to the backup information. If the read and write test in step S740 fails, the second memory read and write test in step S750 can be performed. Among them, in the memory read and write tests in steps S740 and S750, if one of the tests passes, the tested memory device can be shipped, and if the memory read and write tests in steps S740 and S750 pass If all fail, the memory device under test can be determined to be defective, and the detection step can be executed (step S760).

綜上所述,本發明依據正常條件的備援資訊以針對記憶胞陣列進行寫入動作,再依據邊界條件的備援資訊以針對記憶胞陣列進行讀出動作。藉由比較寫入的資料與讀取資料相比較,可以判斷出非揮發記憶區塊在邊界條件中是否可提供正確的備援資訊,並藉以測試出記憶體裝置是否可正常動作。在不大幅增加測試時間的條件下,有效提升記憶體裝置測試的錯誤覆蓋率。In summary, the present invention performs write operations on the memory cell array based on the backup information of the normal conditions, and then performs read operations on the memory cell array based on the backup information of the boundary conditions. By comparing the written data with the read data, it can be judged whether the non-volatile memory block can provide correct backup information under the boundary conditions, and can test whether the memory device can operate normally. Without significantly increasing the test time, the error coverage rate of the memory device test is effectively improved.

100:記憶體裝置100: Memory device

110:記憶體110: memory

120:非揮發記憶區塊120: Non-volatile memory block

LC:暫存器鏈LC: register chain

TE:測試設備TE: test equipment

FI:備援資訊FI: Backup Information

MA:記憶胞陣列MA: Memory cell array

MC1~MC5:記憶胞MC1~MC5: memory cell

RC1~RC3:備援記憶胞RC1~RC3: Spare memory cells

S210~S240、S310~S350、S510~S5110、S610~S660、S710~S760:測試方法的步驟S210~S240, S310~S350, S510~S5110, S610~S660, S710~S760: steps of the test method

圖1為本發明一實施例的記憶體裝置及測試設備的示意圖。 圖2的本發明實施例的記憶體測試動作的流程圖。 圖3為本發明第一實施例的記憶體裝置的測試動作的流程圖。 圖4A至圖4C為本發明一實施例的實施方式的示意圖。 圖5為本發明第二實施例的記憶體裝置的測試動作的流程圖。 圖6為本發明第三實施例的記憶體裝置的測試動作的流程圖。 圖7為本發明實施例的記憶體裝置的完整測試動作的流程圖。 FIG. 1 is a schematic diagram of a memory device and testing equipment according to an embodiment of the invention. FIG. 2 is a flowchart of a memory test action according to an embodiment of the present invention. FIG. 3 is a flowchart of a test operation of the memory device according to the first embodiment of the present invention. 4A to 4C are schematic diagrams of implementation of an embodiment of the present invention. FIG. 5 is a flowchart of a test operation of the memory device according to the second embodiment of the present invention. FIG. 6 is a flowchart of a test operation of the memory device according to the third embodiment of the present invention. FIG. 7 is a flowchart of a complete test operation of the memory device according to an embodiment of the present invention.

S210~S240:測試方法的步驟 S210~S240: Steps of the test method

Claims (10)

一種記憶體裝置的測試方法,包括:關閉該記憶體裝置的一備援功能,並對一第一記憶胞陣列寫入一第一資料;啟動該記憶體裝置的該備援功能,並對一第二記憶胞陣列寫入一第二資料,其中該第一資料與該第二資料互補;依據一邊界條件以調整一正常讀取電壓以產生一邊界讀取電壓,依據該邊界讀取電壓對一非揮發記憶區塊讀取一備援資訊,基於該備援資訊,讀取該第二記憶胞陣列以獲得一第一讀取資料;以及依據比較該第二資料與該第一讀取資料以產生一第一測試結果,其中,該第二記憶胞陣列包括該第一記憶胞陣列的部分記憶胞以及至少一備援記憶胞。 A test method for a memory device includes: turning off a backup function of the memory device, and writing a first data to a first memory cell array; activating the backup function of the memory device, and checking The second memory cell array writes a second data, where the first data is complementary to the second data; a normal read voltage is adjusted according to a boundary condition to generate a boundary read voltage, and the boundary read voltage pair is A non-volatile memory block reads backup information, based on the backup information, reads the second memory cell array to obtain a first read data; and compares the second data with the first read data based on To generate a first test result, wherein the second memory cell array includes a part of the memory cells of the first memory cell array and at least one backup memory cell. 如請求項1所述的測試方法,其中在啟動記憶體裝置的該備援功能,並對該第二記憶胞陣列寫入該第二資料的步驟之前更包括:依據一正常條件,對該非揮發記憶區塊讀取該備援資訊。 The test method according to claim 1, wherein before the step of activating the backup function of the memory device and writing the second data to the second memory cell array, it further comprises: according to a normal condition, the non-volatile The memory block reads the backup information. 如請求項2所述的測試方法,其中依據該正常條件,對該非揮發記憶區塊讀取該備援資訊的步驟包括:依據該正常讀取電壓對該非揮發記憶區塊進行讀取以獲得該備援資訊。 The test method according to claim 2, wherein the step of reading the backup information for the non-volatile memory block according to the normal condition includes: reading the non-volatile memory block according to the normal read voltage to obtain the Backup information. 如請求項3所述的測試方法,其中依據該邊界條件以調整該正常讀取電壓以產生該邊界讀取電壓,依據該邊界讀取電壓對該非揮發記憶區塊讀取該備援資訊的步驟包括:提高或降低該正常讀取電壓以產生該邊界讀取電壓,依據該邊界讀取電壓對該非揮發記憶區塊進行讀取以獲得該備援資訊。 The test method according to claim 3, wherein the normal read voltage is adjusted according to the boundary condition to generate the boundary read voltage, and the step of reading the backup information for the non-volatile memory block according to the boundary read voltage It includes: increasing or decreasing the normal reading voltage to generate the boundary reading voltage, and reading the non-volatile memory block according to the boundary reading voltage to obtain the backup information. 如請求項1所述的測試方法,其中該非揮發記憶區塊提供多個資料位元對以分別對應備援資訊中的多個備援資訊位元。 The test method according to claim 1, wherein the non-volatile memory block provides a plurality of data bit pairs to respectively correspond to a plurality of redundant information bits in the redundant information. 如請求項5所述的測試方法,其中依據該邊界條件以調整該正常讀取電壓以產生該邊界讀取電壓,依據該邊界讀取電壓對該非揮發記憶區塊讀取該備援資訊,基於該備援資訊,讀取該第二記憶胞陣列以獲得該第一讀取資料的步驟包括:讀取該非揮發記憶區塊的該些資料位元對中的多個第一資料位元,並依據該些第一資料位元分別產生該些備援資訊位元。 The test method according to claim 5, wherein the normal read voltage is adjusted according to the boundary condition to generate the boundary read voltage, and the backup information is read for the non-volatile memory block according to the boundary read voltage, based on The step of reading the backup information and reading the second memory cell array to obtain the first read data includes: reading a plurality of first data bits in the data bit pairs of the non-volatile memory block, and The redundant information bits are respectively generated according to the first data bits. 如請求項6所述的測試方法,其中在依據比較該第二資料與該第一讀取資料以產生該第一測試結果的步驟之後更包括:依據一正常條件,讀取該非揮發記憶區塊以更新該備援資訊。 The test method according to claim 6, wherein after the step of generating the first test result by comparing the second data with the first read data, it further comprises: reading the non-volatile memory block according to a normal condition To update the backup information. 如請求項7所述的測試方法,更包括:再次關閉該記憶體裝置的該備援功能,並對該第一記憶胞陣列寫入該第一資料; 再次啟動記憶體裝置的該備援功能,並對該第二記憶胞陣列寫入該第二資料;讀取該非揮發記憶區塊的該些資料位元對中的多個第二資料位元,並依據該些第二資料位元分別更新該些備援資訊位元;基於更新後的該些備援資訊位元,讀取該第二記憶胞陣列以獲得一第二讀取資料;以及依據比較該第二資料與該第二讀取資料以產生一第二測試結果。 The test method according to claim 7, further comprising: turning off the backup function of the memory device again, and writing the first data to the first memory cell array; The backup function of the memory device is activated again, and the second data is written to the second memory cell array; the second data bits in the data bit pairs of the non-volatile memory block are read, And update the backup information bits respectively according to the second data bits; read the second memory cell array based on the updated backup information bits to obtain a second read data; and according to The second data is compared with the second read data to generate a second test result. 如請求項5所述的測試方法,其中在並對該第二記憶胞陣列寫入該第二資料的步驟之前包括:讀取該非揮發記憶區塊的該些資料位元對中的多個第一資料位元,並依據該些第一資料位元分別產生該些備援資訊位元。 The test method according to claim 5, wherein before the step of writing the second data to the second memory cell array, the method includes: reading a plurality of second data bit pairs of the non-volatile memory block One data bit, and the redundant information bits are generated respectively according to the first data bits. 如請求項9所述的測試方法,其中在對該第二記憶胞陣列寫入該第二資料的步驟之後包括:讀取該非揮發記憶區塊的該些資料位元對中的多個第二資料位元,並依據該些第二資料位元分別調整該些備援資訊位元。 The test method according to claim 9, wherein after the step of writing the second data to the second memory cell array, it comprises: reading a plurality of second data bit pairs of the non-volatile memory block Data bits, and adjust the backup information bits respectively according to the second data bits.
TW109110421A 2020-03-27 2020-03-27 Test method for memory device TWI723822B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW109110421A TWI723822B (en) 2020-03-27 2020-03-27 Test method for memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW109110421A TWI723822B (en) 2020-03-27 2020-03-27 Test method for memory device

Publications (2)

Publication Number Publication Date
TWI723822B true TWI723822B (en) 2021-04-01
TW202137229A TW202137229A (en) 2021-10-01

Family

ID=76605134

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109110421A TWI723822B (en) 2020-03-27 2020-03-27 Test method for memory device

Country Status (1)

Country Link
TW (1) TWI723822B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030009615A1 (en) * 2001-07-03 2003-01-09 International Business Machines Corporation Integrated redundancy architecture system for an embedded dram
US20120182776A1 (en) * 2006-12-14 2012-07-19 Best Scott C Dram device with built-in self-test circuitry
US20130095580A1 (en) * 2011-10-18 2013-04-18 Zvi Or-Bach Semiconductor device and structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030009615A1 (en) * 2001-07-03 2003-01-09 International Business Machines Corporation Integrated redundancy architecture system for an embedded dram
US20120182776A1 (en) * 2006-12-14 2012-07-19 Best Scott C Dram device with built-in self-test circuitry
US20130095580A1 (en) * 2011-10-18 2013-04-18 Zvi Or-Bach Semiconductor device and structure

Also Published As

Publication number Publication date
TW202137229A (en) 2021-10-01

Similar Documents

Publication Publication Date Title
US8615688B2 (en) Method and system for iteratively testing and repairing an array of memory cells
US8015438B2 (en) Memory circuit
KR100314362B1 (en) Semiconductor memory
US8315116B2 (en) Repair circuit and repair method of semiconductor memory apparatus
CN111312321A (en) Memory device and fault repairing method thereof
JP3842238B2 (en) Memory system and test method thereof
KR100745403B1 (en) Semiconductor memory apparatus and method for self-testing thereof
JP2010225239A (en) Semiconductor integrated circuit and method for verifying function of memory
JPH08255500A (en) Method and apparatus regarding constructible built-in self- repair of asic memory design
US20060242492A1 (en) Method and apparatus for masking known fails during memory tests readouts
JP2003059292A (en) Method and apparatus for storing memory test information
JP4777417B2 (en) Semiconductor memory and test system
TW202123232A (en) Repair circuit and method for memory, and memory module using the same
US20050066226A1 (en) Redundant memory self-test
US7464309B2 (en) Method and apparatus for testing semiconductor memory device and related testing methods
JP4257342B2 (en) Semiconductor memory device, memory module, and memory module inspection method
TWI723822B (en) Test method for memory device
US11901031B2 (en) Memory device performing repair operation
US11929136B2 (en) Reference bits test and repair using memory built-in self-test
CN113517018B (en) Method for testing memory device
JP4738405B2 (en) Storage device test method and storage device
Ghale et al. Design and implementation of memory BIST for hybrid cache architecture
CN110827878B (en) Memory device
US11164649B1 (en) Test method for memory device
US11574699B2 (en) Semiconductor device equipped with global column redundancy