TWI721748B - Surge current suppression circuit and power circuit having the same - Google Patents
Surge current suppression circuit and power circuit having the same Download PDFInfo
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Description
本發明係有關一種突波電流抑制電路與具有該突波電流抑制電路之電源電路，尤指一種在維持時間期間輸入電源回電時所造成的突波電流電能夠被大幅度地抑制的突波電流抑制電路與具有該突波電流抑制電路之電源電路。 The present invention relates to a surge current suppression circuit and a power supply circuit with the surge current suppression circuit, in particular to a surge current that can be greatly suppressed when the input power is recycled during the maintenance period A current suppression circuit and a power supply circuit with the surge current suppression circuit.
在實際使用各種用電設備時，尤其是在電源插頭插拔瞬間，經常會出現插頭打火花甚至是爆響等現象。這是由於出現的大浪湧電流(inrush current)沒有被有效抑制而導致兩個導體瞬間接觸時產生電弧效應。顯然，對於消費者而言，出現插頭打火花甚至是爆響等現象，不僅大大地影響了消費者的使用感受，時間久了也會導致插頭五金的鍍金層被破壞，出現接觸不良而發熱嚴重，從而增加安全隱患。此外，還將可能引起對電網雜訊瞬間波動，嚴重干擾附近的用電設施等。 In the actual use of various electrical equipment, especially when the power plug is plugged in or unplugged, the plug sparks or even bursts. This is because the large inrush current (inrush current) that appears is not effectively suppressed, which causes an arc effect to occur when two conductors are in instantaneous contact. Obviously, for consumers, the occurrence of plug sparks or even explosions will not only greatly affect the consumer's experience, but also cause the gold-plated layer of the plug hardware to be damaged over time, resulting in poor contact and serious heat generation. , Thereby increasing security risks. In addition, it may also cause instantaneous fluctuations of noise to the power grid and severely interfere with nearby electrical facilities.
習知做法是在輸入端電流迴路上串接一個電阻，該電阻可為負溫度係數電阻、正溫度係數電阻、或一般電阻來限制開機瞬間輸入之突波電流，並且為了降低損失，會在其兩端並接一個開關，該開關可為繼電器、電晶體等元件，在突波電流結束之後，導通該開關來降低損耗。 The conventional method is to connect a resistor in series with the current loop of the input end. The resistor can be a negative temperature coefficient resistor, a positive temperature coefficient resistor, or a general resistor to limit the inrush current input at the moment of startup. A switch is connected in parallel at both ends. The switch can be a relay, transistor, etc. After the inrush current ends, the switch is turned on to reduce loss.
然而在輸入瞬間掉電又回電的不穩定區間，系統需要維持運作穩定，於是會需要電源供應器在交流電源掉電時在某一段時間內維持輸出電壓，此 稱為維持時間(hold-up time)。隨著功率密度要求越來越高，對於維持時間的要求越來越大。是故在掉電期間，內部儲能電容的電壓會盡可能用到最低，於是當交流電源回電時，輸入電網與內部儲能電容電壓的壓差仍會導致高突波電流。該習知作法雖有效解決開機瞬間之突波電流，卻無法控制在維持時間後回電時的電流大小，導致電網更加不穩定，嚴重干擾周遭用電設施，損壞上游斷路器(breaker)，可能導致整個系統停止運作。 However, the system needs to maintain stable operation during the unstable interval of the input momentary power-down and then the power-back. Therefore, the power supply is required to maintain the output voltage for a certain period of time when the AC power is lost. It is called hold-up time. As the power density requirements become higher and higher, the maintenance time requirements become greater. Therefore, during a power failure, the voltage of the internal energy storage capacitor will be used as low as possible, so when the AC power is recycled, the voltage difference between the input grid and the internal energy storage capacitor voltage will still cause high inrush current. Although this conventional method effectively solves the inrush current at the moment of power-on, it cannot control the magnitude of the current when the power is returned after the maintenance time. This causes the grid to be more unstable, seriously disturbs the surrounding electrical facilities, and damages the upstream breaker. Cause the entire system to stop functioning.
請參見圖1與圖2，圖1係為現有技術之供電系統的電路圖，圖2係為圖1之供電系統發生掉電又回電狀況的電壓、電流波形圖。如圖1所示，在開關SW，例如斷路器(breaker)為導通，當輸入電源Vdc發生瞬間地掉電然後又回電的狀況時，其中時間點t1為發生掉電的時間點(即時間點t1之前為供電穩定的狀態)，時間點t2為發生回電的時間點，因此，時間點t1至時間點t2為系統供電的不穩定時段，此時負載RL所需的供電係由電容C1供應，即電容C1上的儲能會被負載RL所抽載。因此，在時間點t1開始，由於電容C1持續地供應負載RL所需的電源，因此系統的輸出電壓Vb逐漸減小。附帶一提，圖1所示的輸入電源Vdc係為省略交流電源經整流電路後所得到的直流電源，因此，以直流的輸入電源Vdc表現掉電又回電的狀況，等效於交流的輸入電源發生掉電又回電的狀況，合先敘明。 Please refer to FIG. 1 and FIG. 2. FIG. 1 is a circuit diagram of a power supply system in the prior art, and FIG. 2 is a voltage and current waveform diagram of the power supply system of FIG. As shown in Figure 1, when the switch SW, such as a breaker, is turned on, when the input power source Vdc is momentarily powered off and then recharged, the time point t1 is the time point when the power failure occurs (ie, time Before point t1 is the stable state of power supply), time point t2 is the time point when recycling occurs. Therefore, time point t1 to time point t2 is the unstable period of system power supply. At this time, the power supply required by the load R L is provided by the capacitor C1 supply, i.e., the storage capacitor C1 on a load R L can be pumped contained. Thus, it starts at time point t1, since the power supply capacitor C1 is continuously required load R L, the output voltage Vb gradually decreases system. Incidentally, the input power supply Vdc shown in Figure 1 is a DC power supply obtained by omitting the AC power supply through the rectifier circuit. Therefore, the DC input power supply Vdc is used to show the power failure and recycle condition, which is equivalent to the AC input The situation of power failure and recycle is first stated.
當輸入電源Vdc於時間點t2時回電，使得輸出電壓Vb在時間點t2時瞬間增加，導致產生大的浪湧電流(inrush current)流經電容C1(即電容電流IC1)。如圖2所示，輸入電源Vdc正常供電時，電容電流IC1大小約為7~10安培，而當掉電後又瞬間回電的狀況發生時，電容電流IC1大小約為400安培，這樣大的突波電流，輕者將造成開關SW(即斷路器)損壞，重者將造成系統電路的失效。 When the input power source Vdc is energized at the time point t2, the output voltage Vb increases instantaneously at the time point t2, resulting in a large inrush current flowing through the capacitor C1 (ie, the capacitor current I C1 ). As shown in Figure 2, when the input power supply Vdc is normally supplied, the capacitance current I C1 is about 7~10 amperes, and when the power cycle occurs after a power failure, the capacitance current I C1 is about 400 amperes. Large surge currents will cause damage to the switch SW (namely circuit breaker) in the lighter ones, and will cause the failure of the system circuit in the severe ones.
為此，如何設計出一種在維持時間期間輸入電源回電時所造成的突波電流電能夠被大幅度地抑制的突波電流抑制電路與具有該突波電流抑制電路之電源電路，來解決前述的技術問題，乃為本案發明人所研究的重要課題。 For this reason, how to design a surge current suppression circuit and a power supply circuit with the surge current suppression circuit that can greatly suppress the surge current caused by the input power supply during the maintenance time period to solve the aforementioned problem The technical problem of is an important subject studied by the inventor of this case.
本發明之目的在於提供一種突波電流抑制電路，解決現有技術之問題。 The purpose of the present invention is to provide a surge current suppression circuit to solve the problems of the prior art.
為達成前揭目的，本發明所提出的突波電流抑制電路包含一主開關、一旁路電阻、一檢測電阻以及一比較器。該主開關串聯耦接於一儲能電容的一第一端，該儲能電容的一第二端耦接一負載並接收一輸入電源，其中該儲能電容用以穩定提供給該負載的該輸入電源。該旁路電阻並聯耦接該主開關。該檢測電阻串聯耦接該主開關，且根據流經該儲能電容的一電容電流產生一檢測電壓。該比較器用以比較該檢測電壓與參考電壓以產生一控制訊號。當該檢測電壓大於該參考電壓時，該控制訊號控制該主開關截止；當該檢測電壓小於該參考電壓時，該控制訊號控制該主開關導通。 In order to achieve the aforementioned objective, the surge current suppression circuit proposed by the present invention includes a main switch, a bypass resistor, a detection resistor, and a comparator. The main switch is coupled in series to a first end of an energy storage capacitor, a second end of the energy storage capacitor is coupled to a load and receives an input power, wherein the energy storage capacitor is used to stably provide the load to the load Input power. The bypass resistor is coupled to the main switch in parallel. The detection resistor is coupled to the main switch in series, and generates a detection voltage according to a capacitance current flowing through the energy storage capacitor. The comparator is used to compare the detection voltage with the reference voltage to generate a control signal. When the detection voltage is greater than the reference voltage, the control signal controls the main switch to turn off; when the detection voltage is less than the reference voltage, the control signal controls the main switch to turn on.
在一實施例中，當該主開關截止時，該電容電流經由該旁路電阻流經該檢測電阻，藉以減小該電容電流。 In one embodiment, when the main switch is turned off, the capacitor current flows through the detection resistor through the shunt resistor, so as to reduce the capacitor current.
在一實施例中，當該電容電流大於或等於一上臨界電流時，該檢測電壓係大於該參考電壓；當該電容電流小於或等於一下臨界電流時，該檢測電壓係小於該參考電壓。 In one embodiment, when the capacitor current is greater than or equal to an upper threshold current, the detection voltage is greater than the reference voltage; when the capacitance current is less than or equal to a lower threshold current, the detection voltage is less than the reference voltage.
在一實施例中，該突波電流抑制電路更包含一電壓放大器。該電壓放大器用以放大該檢測電壓，且將放大之該檢測電壓輸出給該比較器。 In one embodiment, the surge current suppression circuit further includes a voltage amplifier. The voltage amplifier is used to amplify the detection voltage, and output the amplified detection voltage to the comparator.
在一實施例中，響應於該輸入電源的一暫態電壓變化，當該電容電流大於或等於該上臨界電流，該比較器控制該主開關截止，該電容電流流經該旁路電阻，使該電容電流減小；當該電容電流小於或等於該下臨界電流，該比較器控制該主開關導通，該電容電流流經該主開關，使該電容電流增大。 In one embodiment, in response to a transient voltage change of the input power source, when the capacitor current is greater than or equal to the upper critical current, the comparator controls the main switch to turn off, and the capacitor current flows through the bypass resistor to make The capacitor current decreases; when the capacitor current is less than or equal to the lower critical current, the comparator controls the main switch to turn on, and the capacitor current flows through the main switch to increase the capacitor current.
在一實施例中，該主開關的一第一端耦接該儲能電容的該第二端及該旁路電阻的一第一端，該主開關的一第二端耦接該旁路電阻的一第二端及該檢測電阻的一第一端。 In one embodiment, a first end of the main switch is coupled to the second end of the energy storage capacitor and a first end of the bypass resistor, and a second end of the main switch is coupled to the bypass resistor A second end of the detection resistor and a first end of the detection resistor.
在一實施例中，該檢測電阻的該第一端和一第二端分別耦接於該電壓放大器的一第一輸入端和一第二輸入端，該電壓放大器的一輸出端耦接於該比較器的一第一輸入端，該比較器的一第二輸入端接收該參考電壓，且該比較器的一輸出端耦接該主開關的一控制端。 In an embodiment, the first terminal and the second terminal of the detection resistor are respectively coupled to a first input terminal and a second input terminal of the voltage amplifier, and an output terminal of the voltage amplifier is coupled to the A first input terminal of the comparator, a second input terminal of the comparator receive the reference voltage, and an output terminal of the comparator is coupled to a control terminal of the main switch.
藉由所提出的突波電流抑制電路，透過直接控制主開關的導通與關斷，使得電容電流流經不同電阻值的電流路徑，而達到有效地調節電容電流的大小，使得當掉電後的瞬間回電的電容電流能夠被有效地抑制與控制。 With the proposed inrush current suppression circuit, by directly controlling the turn-on and turn-off of the main switch, the capacitor current flows through the current paths of different resistance values to effectively adjust the size of the capacitor current, so that the The capacitive current of instantaneous recycling can be effectively suppressed and controlled.
本發明之另一目的在於提供一種電源電路，解決現有技術之問題。 Another object of the present invention is to provide a power supply circuit to solve the problems of the prior art.
為達成前揭目的，本發明所提出的電源電路用以提供一輸入電源給一負載。該電源電路包含一儲能電容與一突波電流抑制電路。該儲能電容耦接該輸入電源與該負載，用以穩定提供給該負載的該輸入電源，且一電容電流流經該儲能電容。該突波電流抑制電路串聯耦接該儲能電容。響應於該輸入電源的一暫態電壓變化，當該電容電流大於或等於一上臨界電流，該突波電流抑制電路控制該電容電流減小；當該電容電流小於或等於一下臨界電流，該突波電流抑制電路控制該電容電流增大。 In order to achieve the aforementioned purpose, the power circuit proposed in the present invention is used to provide an input power to a load. The power circuit includes an energy storage capacitor and a surge current suppression circuit. The energy storage capacitor is coupled to the input power source and the load for stably providing the input power to the load, and a capacitor current flows through the energy storage capacitor. The surge current suppression circuit is coupled to the energy storage capacitor in series. In response to a transient voltage change of the input power source, when the capacitor current is greater than or equal to an upper critical current, the inrush current suppression circuit controls the capacitor current to decrease; when the capacitor current is less than or equal to the lower critical current, the inrush current The wave current suppression circuit controls the capacitance current to increase.
在一實施例中，該突波電流抑制電路包含一主開關、一旁路電阻、一檢測電阻以及一比較器。該主開關串聯耦接於該儲能電容的一第一端，該儲能電容的一第二端耦接該負載並接收一輸入電源。該旁路電阻並聯耦接該主開關。該檢測電阻串聯耦接該主開關，且根據流經該儲能電容的該電容電流產生一檢測電壓。該比較器用以比較該檢測電壓與該參考電壓以產生一控制訊號。當該檢測電壓大於該參考電壓時，該控制訊號控制該主開關截止；當該檢測電壓小於該參考電壓時，該控制訊號控制該主開關導通。 In one embodiment, the inrush current suppression circuit includes a main switch, a bypass resistor, a detection resistor, and a comparator. The main switch is coupled to a first end of the energy storage capacitor in series, and a second end of the energy storage capacitor is coupled to the load and receives an input power. The bypass resistor is coupled to the main switch in parallel. The detection resistor is coupled to the main switch in series, and generates a detection voltage according to the capacitance current flowing through the energy storage capacitor. The comparator is used to compare the detection voltage with the reference voltage to generate a control signal. When the detection voltage is greater than the reference voltage, the control signal controls the main switch to turn off; when the detection voltage is less than the reference voltage, the control signal controls the main switch to turn on.
在一實施例中，當該主開關截止時，該電容電流經由該旁路電阻流經該檢測電阻，藉以減小該電容電流。 In one embodiment, when the main switch is turned off, the capacitor current flows through the detection resistor through the shunt resistor, so as to reduce the capacitor current.
在一實施例中，當該電容電流大於或等於該上臨界電流時，該檢測電壓係大於該參考電壓；當該電容電流小於或等於該下臨界電流時，該檢測電壓係小於該參考電壓。 In one embodiment, when the capacitor current is greater than or equal to the upper threshold current, the detection voltage is greater than the reference voltage; when the capacitance current is less than or equal to the lower threshold current, the detection voltage is less than the reference voltage.
在一實施例中，該突波電流抑制電路更包含一電壓放大器。該電壓放大器用以放大該檢測電壓，且將放大之該檢測電壓輸出給該比較器。 In one embodiment, the surge current suppression circuit further includes a voltage amplifier. The voltage amplifier is used to amplify the detection voltage, and output the amplified detection voltage to the comparator.
在一實施例中，響應於該輸入電源的暫態電壓變化，當該電容電流大於或等於該上臨界電流，該比較器控制該主開關截止，該電容電流流經該旁路電阻，使該電容電流減小；當該電容電流小於或等於該下臨界電流，該比較器控制該主開關導通，該電容電流流經該主開關，使該電容電流增大。 In one embodiment, in response to the transient voltage change of the input power source, when the capacitor current is greater than or equal to the upper critical current, the comparator controls the main switch to turn off, and the capacitor current flows through the bypass resistor, causing the The capacitor current decreases; when the capacitor current is less than or equal to the lower critical current, the comparator controls the main switch to turn on, and the capacitor current flows through the main switch to increase the capacitor current.
藉由所提出的電源電路，透過直接控制主開關的導通與關斷，使得電容電流流經不同電阻值的電流路徑，而達到有效地調節電容電流的大小，使得當掉電後的瞬間回電的電容電流能夠被有效地抑制與控制。 With the proposed power supply circuit, by directly controlling the turn-on and turn-off of the main switch, the capacitor current flows through the current paths of different resistance values, and the size of the capacitor current is effectively adjusted, so that the capacitor current will be recycled immediately after power failure. The capacitive current can be effectively suppressed and controlled.
為了能更進一步瞭解本發明為達成預定目的所採取之技術、手段及功效，請參閱以下有關本發明之詳細說明與附圖，相信本發明之目的、特徵與特點，當可由此得一深入且具體之瞭解，然而所附圖式僅提供參考與說明用，並非用來對本發明加以限制者。 In order to have a better understanding of the technology, means and effects adopted by the present invention to achieve the intended purpose, please refer to the following detailed description and drawings of the present invention. I believe that the purpose, features and characteristics of the present invention can be obtained from this in depth and For specific understanding, however, the accompanying drawings are only provided for reference and illustration, and are not intended to limit the present invention.
Vdc:輸入電源 Vdc: input power
Sw:開關 Sw: switch
C1:儲能電容 C1: Energy storage capacitor
RL:負載 R L : load
10:突波電流抑制電路 10: Surge current suppression circuit
Q1:主開關 Q1: Main switch
Rb:旁路電阻 Rb: Bypass resistance
Rinrush:檢測電阻 R inrush : detection resistance
Cv:比較器 Cv: Comparator
Av:電壓放大器 Av: voltage amplifier
Dh:二極體 Dh: Diode
Rh:電阻 Rh: resistance
Ri:輸入電阻 Ri: Input resistance
Vinrush:檢測電壓 V inrush : detection voltage
IC1:電容電流 I C1 : Capacitance current
Vb:輸出電壓 Vb: output voltage
Vx:增益電壓 Vx: gain voltage
Vref:參考電壓 Vref: reference voltage
Vg1:閘極控制電壓 Vg1: Gate control voltage
VCP:電源電壓 VCP: Power supply voltage
t1:時間點 t1: point in time
t2:時間點 t2: point in time
圖1：為現有技術之供電系統的電路圖。 Figure 1: Circuit diagram of a prior art power supply system.
圖2：為圖1之供電系統發生掉電又回電狀況的電壓、電流波形圖。 Figure 2: The voltage and current waveforms of the power supply system shown in Figure 1 when the power is off and the power is recycled.
圖3：為本發明具有突波電流抑制電路之供電系統的電路圖。 Figure 3 is a circuit diagram of a power supply system with a surge current suppression circuit according to the present invention.
圖4：為本發明突波電流抑制電路之實施例的電路圖。 Figure 4: is a circuit diagram of an embodiment of the inrush current suppression circuit of the present invention.
圖5：為本發明具有突波電流抑制電路之供電系統發生掉電又回電狀況的電壓、電流波形圖。 Figure 5: is a voltage and current waveform diagram of a power supply system with a surge current suppression circuit of the present invention when a power failure occurs and a power cycle occurs.
茲有關本發明之技術內容及詳細說明，配合圖式說明如下。 The technical content and detailed description of the present invention are described below in conjunction with the drawings.
請參見圖3所示，其係為本發明具有突波電流抑制電路之供電系統的電路圖。該突波電流抑制電路10應用於圖1所示的供電系統，即該突波電流抑制電路10應用於具有一輸入電源Vdc耦接一儲能電容C1與一負載RL的電路架構。該突波電流抑制電路10的兩端，耦接於儲能電容C1的一端(A點)與接地端(B點)之間，即該突波電流抑制電路10與該儲能電容C1耦接於同一路徑上。
Please refer to FIG. 3, which is a circuit diagram of a power supply system with a surge current suppression circuit of the present invention. The inrush
請參見圖4所示，其係為本發明突波電流抑制電路之實施例的電路圖。該突波電流抑制電路10主要包含一主開關Q1、一旁路電阻Rb、一檢測電阻Rinrush以及一比較器Cv。該旁路電阻Rb並聯耦接該主開關Q1，形成一並聯結構。以一金屬氧化物半導體場效電晶體(MOSFET)作為該主開關Q1為例，該旁路電阻Rb並聯耦接於該MOSFET的汲極(drain)與源極(source)之間。該檢測電阻Rinrush串聯耦接該並聯結構，且該檢測電阻Rinrush根據流經該儲能電容C1的一電容電流IC1產生一檢測電壓Vinrush，即在檢測電阻Rinrush兩端所產生電壓降的該檢測電壓Vinrush大小等於該電容電流IC1與該檢測電阻Rinrush的乘積(Vinrush=IC1×Rinrush)。因此，若該電容電流IC1較大，獲得的該檢測電壓Vinrush也較大，反之亦然。
Please refer to FIG. 4, which is a circuit diagram of an embodiment of the surge current suppression circuit of the present invention. The inrush
該比較器Cv接收該檢測電壓Vinrush與一參考電壓Vref，且比較該檢測電壓Vinrush與該參考電壓Vref。其中，該參考電壓Vref係為可調整的參考電壓，其係可透過使用一分壓電路對一電源電壓VCP進行分壓所得到，然不以此為限制本發明。 The comparator Cv receives the detection voltage V inrush and a reference voltage Vref, and compares the detection voltage V inrush with the reference voltage Vref. Wherein, the reference voltage Vref is an adjustable reference voltage, which can be obtained by dividing a power supply voltage VCP using a voltage divider circuit, but the present invention is not limited by this.
此外，該突波電流抑制電路10更包含一遲滯單元，該遲滯單元係由一二極體Dh與一電阻Rh所組成。具體地，該二極體Dh的陰極端耦接該電阻Rh的一端，形成串聯結構的該遲滯單元。該串聯結構的一端(即該二極體Dh的陽極端耦接該比較器Cv的輸出端，且該串聯結構的另一端(即該電阻Rh的另一端)耦接該比較器Cv的非反相輸入端。
In addition, the surge
當該比較器Cv的反相輸入端所接收的電壓大於非反相輸入端所接收的電壓時，該比較器Cv輸出低準位的電壓(即接地電壓)。該低準位的電壓使得二極體Dh逆偏而截止，因此該遲滯單元相當於開路的狀態。在此狀態下，該比較器Cv的非反相輸入端的電壓不受影響。反之，當該比較器Cv的反相輸入端所接收的電壓小於非反相輸入端所接收的電壓時，該比較器Cv輸出高準位的電壓(即該電源電壓VCP)。該高準位的電壓使得二極體Dh順偏而導通，因此， 相當於該電阻Rh加入該比較器Cv的非反相輸入端，如此，該電源電壓VCP透過該電阻Rh與一輸入電阻Ri分壓，而增加非反相輸入端的電壓值。 When the voltage received by the inverting input terminal of the comparator Cv is greater than the voltage received by the non-inverting input terminal, the comparator Cv outputs a low-level voltage (ie, the ground voltage). The low-level voltage causes the diode Dh to reversely bias and cut off, so the hysteresis unit is equivalent to an open circuit state. In this state, the voltage of the non-inverting input terminal of the comparator Cv is not affected. Conversely, when the voltage received by the inverting input terminal of the comparator Cv is less than the voltage received by the non-inverting input terminal, the comparator Cv outputs a high-level voltage (ie, the power supply voltage VCP). The high-level voltage makes the diode Dh turn on in a forward bias, therefore, It is equivalent to adding the resistor Rh to the non-inverting input terminal of the comparator Cv, so that the power supply voltage VCP is divided by the resistor Rh and an input resistor Ri to increase the voltage value of the non-inverting input terminal.
因此，透過該遲滯單元，可使得該比較器Cv的反相輸入端在前述所增加的電壓範圍(遲滯範圍)內，可提供穩定的輸出，因此該比較器Cv的兩輸入端可從“電壓點”的比較變為“電壓段”(遲滯範圍)的比較，而可允許該比較器Cv的反相輸入端所接收的電壓在遲滯範圍內的波動，仍能得到穩定的輸出。 Therefore, through the hysteresis unit, the inverting input terminal of the comparator Cv can be made within the aforementioned increased voltage range (hysteresis range), and a stable output can be provided. Therefore, the two input terminals of the comparator Cv can be adjusted from the voltage The comparison of “point” becomes the comparison of “voltage segment” (hysteresis range), and the voltage received by the inverting input terminal of the comparator Cv can be allowed to fluctuate within the hysteresis range, and a stable output can still be obtained.
當流經該儲能電容C1的該電容電流IC1大於或等於一上臨界電流時，該檢測電壓Vinrush大於該參考電壓Vref，該比較器Cv則控制該主開關Q1截止(關斷)，該電容電流IC1係流經與該主開關Q1並聯的該旁路電阻Rb，使該電容電流IC1減小，達到對該電容電流IC1大於或等於該上臨界電流的抑制。反之，當該電容電流IC1小於或等於一下臨界電流時，該檢測電壓Vinrush小於該參考電壓Vref，該比較器Cv則控制該主開關Q1導通，該電容電流IC1係流經該主開關Q1，使該電容電流IC1增大。其中，該上臨界電流大於該下臨界電流。藉此，透過直接控制該主開關Q1的導通與截止，使得該電容電流IC1流經不同電流路徑，由於不同電流路徑的電阻值不同，而達到有效地調節該電容電流IC1的大小，使得當掉電後的瞬間回電的電容電流IC1能夠被有效地抑制與控制。 When the capacitor current I C1 flowing through the energy storage capacitor C1 is greater than or equal to an upper critical current, the detection voltage V inrush is greater than the reference voltage Vref, and the comparator Cv controls the main switch Q1 to turn off (turn off), The capacitor current I C1 flows through the bypass resistor Rb connected in parallel with the main switch Q1, so that the capacitor current I C1 is reduced, so as to suppress the capacitor current I C1 being greater than or equal to the upper critical current. Conversely, when the capacitor current I C1 is less than or equal to the next critical current, the detection voltage V inrush is less than the reference voltage Vref, the comparator Cv controls the main switch Q1 to turn on, and the capacitor current I C1 flows through the main switch Q1 increases the capacitor current I C1 . Wherein, the upper critical current is greater than the lower critical current. Therefore, by directly controlling the on and off of the main switch Q1, the capacitor current I C1 flows through different current paths. Due to the different resistance values of the different current paths, the magnitude of the capacitor current I C1 can be effectively adjusted, so that The capacitive current I C1 that is recycled at the moment of power failure can be effectively suppressed and controlled.
在一實施例中，該突波電流抑制電路10更包含一電壓放大器Av。該電壓放大器Av的輸入端係耦接該檢測電阻Rinrush，該電壓放大器Av的輸出端係耦接該比較器Cv。其中，該電壓放大器Av的兩輸入端係分別耦接該檢測電阻Rinrush的兩端，以差動放大的方式放大該檢測電壓Vinrush。
In one embodiment, the inrush
以下，將說明響應於該輸入電源的暫態電壓變化的情況下該突波電流抑制電路10的作用。在本實施例中，該輸入電源的暫態電壓變化係指該輸入電源Vdc瞬間掉電再回電的狀況。具體來說，該輸入電源Vdc瞬間掉電再回電，意指著該輸入電源Vdc在一時間內從正常工作電壓掉到異常工作電壓，接
著再回到正常工作電壓的情況。舉例來說，該輸入電源Vdc在10至20毫秒的時間內從正常工作電壓(例如，127伏特~370伏特)掉到異常電壓(例如，0~100伏特)，接著再回到正常工作電壓(即127伏特~370伏特)的狀況，但本發明並不以此為限。在其他例子中，該輸入電源Vdc可透過一個交流電源經由一整流器轉換而得到，而該輸入電源Vdc瞬間掉電再回電的狀況，可例如為，該交流電源從正常工作電壓(例如，90伏特~264伏特)在10至20毫秒的時間內掉到異常電壓(例如，0~70伏特)，接著再回到正常工作電壓(即90伏特~264伏特)，連帶著使得該輸入電源Vdc相應於該交流電源之變化的情況，但本發明並不以此為限。
Hereinafter, the function of the surge
請配合參見圖4與圖5，其中圖5係為本發明具有突波電流抑制電路之供電系統發生掉電又回電狀況的電壓、電流波形圖。 Please refer to FIG. 4 and FIG. 5 in cooperation, where FIG. 5 is a voltage and current waveform diagram of the power supply system with a surge current suppression circuit of the present invention in a power-down and power-back condition.
假設供電系統在時間點t1時發生輸入電源Vdc掉電，因此，負載RL所需的電源則由儲能電容C1提供，因此，當負載RL對儲能電容C1，輸出電壓Vb則逐漸減小。在時間點t2時發生輸入電源Vdc回電，此時輸出電壓Vb瞬間增加，但由於流經該儲能電容C1的該電容電流IC1受到抑制，因此輸出電壓Vb增加的程度(斜率)較圖2所示的輸出電壓Vb來得小。因為該電容電流IC1受到抑制，所以從圖5可看出該電容電流IC1並不像圖2所示的電容電流IC1瞬間突波增加。其中，該電容電流IC1受到抑制與調節的說明如下。 Suppose that the power supply system has a power failure of the input power Vdc at time t1. Therefore, the power required by the load RL is provided by the energy storage capacitor C1. Therefore, when the load RL faces the energy storage capacitor C1, the output voltage Vb gradually decreases. small. At time t2, the input power supply Vdc is recharged. At this time, the output voltage Vb increases instantaneously. However, since the capacitor current I C1 flowing through the energy storage capacitor C1 is suppressed, the degree of increase (slope) of the output voltage Vb is as shown in the figure. The output voltage Vb shown in 2 is small. Because the capacitor current I C1 is suppressed, it can be seen from FIG. 5 that the capacitor current I C1 does not increase in sudden surge like the capacitor current I C1 shown in FIG. 2. The description of the suppression and adjustment of the capacitor current I C1 is as follows.
當該輸出電壓Vb瞬間增加，因此該電容電流IC1瞬間增大，但由於該電容電流IC1大於或等於該上臨界電流時，例如但不限制為15安培，該檢測電壓Vinrush大於該參考電壓Vref，假設該參考電壓Vref為1伏特。在一實施例中，該檢測電阻Rinrush的大小約為0.01歐姆，因此該檢測電壓Vinrush約為0.15伏特，再者，該檢測電壓Vinsush經由該電壓放大器Av放大後，假設該電壓放大器Av的一增益電壓Vx約為1.5伏特。由於該增益電壓Vx大於該參考電壓Vref，因此該 比較器Cv輸出低準位的一閘極控制電壓Vg1。該閘極控制電壓Vg1無法驅動該主開關Q1導通，所以該電容電流IC1流經該旁路電阻Rb，使得該電容電流IC1減小，因此達到對該電容電流IC1的抑制，避免該電容電流IC1以突波的方式瞬間增加。 When the output voltage Vb increases instantaneously, the capacitor current I C1 increases instantaneously, but because the capacitor current I C1 is greater than or equal to the upper critical current, for example, but not limited to 15 amperes, the detection voltage V inrush is greater than the reference The voltage Vref, assuming that the reference voltage Vref is 1 volt. In one embodiment, the size of the detection resistor R inrush is about 0.01 ohm, so the detection voltage V inrush is about 0.15 volts. Furthermore, after the detection voltage Vinsush is amplified by the voltage amplifier Av, it is assumed that the voltage amplifier Av A gain voltage Vx of about 1.5 volts. Since the gain voltage Vx is greater than the reference voltage Vref, the comparator Cv outputs a low-level gate control voltage Vg1. The gate control voltage Vg1 cannot drive the main switch Q1 to turn on, so the capacitor current I C1 flows through the bypass resistor Rb, so that the capacitor current I C1 is reduced, thus achieving the suppression of the capacitor current I C1 and avoiding the The capacitive current I C1 increases instantaneously in a sudden wave.
在該電容電流IC1減小的過程中，若當該電容電流IC1小於或等於該下臨界電流時，例如但不限制為8安培，該檢測電壓Vinrush經由該電壓放大器Av放大後所得到的該增益電壓Vx為0.8伏特。由於該增益電壓Vx小於該參考電壓Vref，因此該比較器Cv輸出高準位的該閘極控制電壓Vg1。該閘極控制電壓Vg1驅動該主開關Q1導通，所以該電容電流IC1流經該主開關Q1，由於該主開關Q1的導通電阻(RDS(on))相對於該旁路電阻Rb(例如但不限制約為25歐姆)而言相當的小，因此，流經該主開關Q1的該電容電流IC1將增大。然而，一旦該電容電流IC1增大至大於或等於該上臨界電流時，該比較器Cv則再次輸出低準位的該閘極控制電壓Vg1，以關斷該主開關Q1，使得該電容電流IC1再次流經該旁路電阻Rb而受到抑制。據此，該電容電流IC1則在增大、減小的過程中呈現穩態振盪的狀態，如圖5所示，直到突波能量釋放完成後，該電容電流IC1則恢復穩態時的電流大小。故此，該突波電流抑制電路10可達到在維持時間期間輸入電源回電時所造成的突波電流電能夠被大幅度地抑制的功效。
In the process of reducing the capacitor current I C1 , if the capacitor current I C1 is less than or equal to the lower critical current, for example but not limited to 8 amperes, the detection voltage V inrush is amplified by the voltage amplifier Av The gain voltage Vx is 0.8 volts. Since the gain voltage Vx is less than the reference voltage Vref, the comparator Cv outputs the gate control voltage Vg1 at a high level. The gate control voltage Vg1 drives the main switch Q1 to turn on, so the capacitance current I C1 flows through the main switch Q1, because the on-resistance (RDS(on)) of the main switch Q1 is relative to the bypass resistor Rb (for example, but It is not limited to about 25 ohms). Therefore, the capacitor current I C1 flowing through the main switch Q1 will increase. However, once the capacitor current I C1 increases to be greater than or equal to the upper critical current, the comparator Cv again outputs the low-level gate control voltage Vg1 to turn off the main switch Q1, so that the capacitor current IC1 flows through the shunt resistor Rb again and is suppressed. According to this, the capacitor current I C1 presents a steady-state oscillation state during the process of increasing and decreasing, as shown in Figure 5, until the surge energy is released, the capacitor current I C1 returns to the steady-state state. The magnitude of the current. Therefore, the surge
綜上所述，本發明係具有以下之特徵與優點： In summary, the present invention has the following features and advantages:
1、透過簡易的主開關、偵測電阻與比較電路可實現對突波電流的抑制與調節。 1. The suppression and adjustment of inrush current can be achieved through a simple main switch, detection resistance and comparison circuit.
2、透過直接控制主開關的導通與關斷，使得電容電流流經不同電阻值的電流路徑，而達到有效地調節電容電流的大小，使得當掉電後的瞬間回電的電容電流能夠被有效地抑制與控制。 2. By directly controlling the turn-on and turn-off of the main switch, the capacitor current flows through the current paths of different resistance values, so as to effectively adjust the size of the capacitor current, so that the capacitor current that is recycled at the moment of power failure can be effectively Local restraint and control.
以上所述，僅為本發明較佳具體實施例之詳細說明與圖式，惟本發明之特徵並不侷限於此，並非用以限制本發明，本發明之所有範圍應以下述之申請專利範圍為準，凡合於本發明申請專利範圍之精神與其類似變化之實施例，皆應包含於本發明之範疇中，任何熟悉該項技藝者在本發明之領域內，可輕易思及之變化或修飾皆可涵蓋在以下本案之專利範圍。 The above are only detailed descriptions and drawings of the preferred embodiments of the present invention. However, the features of the present invention are not limited to these, and are not intended to limit the present invention. The full scope of the present invention shall be within the scope of the following patent applications. As the standard, all embodiments that conform to the spirit of the patent application of the present invention and similar changes should be included in the scope of the present invention. Anyone familiar with the art in the field of the present invention can easily think of changes or Modifications can be covered in the following patent scope of this case.
10:突波電流抑制電路 10: Surge current suppression circuit
Q1:主開關 Q1: Main switch
Rb:旁路電阻 Rb: Bypass resistance
Rinrush:檢測電阻 R inrush : detection resistance
Cv:比較器 Cv: Comparator
Av:電壓放大器 Av: voltage amplifier
Dh:二極體 Dh: Diode
Rh:電阻 Rh: resistance
Ri:輸入電阻 Ri: Input resistance
Vinrush:檢測電壓 V inrush : detection voltage
Vx:增益電壓 Vx: gain voltage
Vref:參考電壓 Vref: reference voltage
Vg1:閘極控制電壓 Vg1: Gate control voltage
VCP:電源電壓 VCP: Power supply voltage
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| Publication number | Publication date |
|---|---|
| TW202127766A (en) | 2021-07-16 |
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