TWI717897B

TWI717897B - Semiconductor device and manufacturing method of the same

Info

Publication number: TWI717897B
Application number: TW108141088A
Authority: TW
Inventors: 李書銘; 劉嘉鴻; 歐陽自明
Original assignee: 華邦電子股份有限公司
Priority date: 2019-11-13
Filing date: 2019-11-13
Publication date: 2021-02-01
Also published as: TW202119543A

Abstract

A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate having a plurality of active regions, at least one dielectric layer formed on the substrate, and a plurality of contacts disposed in the dielectric layer and contacting with the active regions. The contact is a barrel-shaped structure with a middle portion, a head portion having a perimeter small than that of the middle portion, and an end portion having a perimeter small than that of the middle portion.

Description

半導體元件及其製造方法Semiconductor element and its manufacturing method

本發明是有關於一種半導體技術，且特別是有關於一種能具有特定構造接觸窗的半導體元件及其製造方法。The present invention relates to a semiconductor technology, and particularly relates to a semiconductor element capable of having a contact window of a specific structure and a manufacturing method thereof.

在新一代半導體製程的微縮下，將使得半導體元件的各個構件相對縮小，譬如半導體元件的接觸窗不但縮小，且接觸窗之間的距離也會縮小。因此，為了突破微影製程中光源解析度的限制，目前有使用自對準雙重圖案（Self Alignment Double Patterning，SADP）製程來實現接觸窗的縮小。Under the shrinking of the new generation of semiconductor manufacturing process, the various components of the semiconductor device will be relatively reduced. For example, the contact windows of the semiconductor device will not only shrink, but also the distance between the contact windows. Therefore, in order to break through the limitation of the light source resolution in the lithography process, a self-alignment double patterning (SADP) process is currently used to reduce the contact window.

然而，無論是傳統微影蝕刻製程或者上述自對準雙重圖案製程，都有可能因為最初的微影製程所導致的對準誤差，而使接觸窗與基底或其他構件的接觸面積變小，從而影響元件性能。However, whether it is the traditional lithographic etching process or the above-mentioned self-aligned double patterning process, the alignment error caused by the initial lithography process may reduce the contact area between the contact window and the substrate or other components. Affect component performance.

本發明提供一種半導體元件及其製造方法，具有特定構造的接觸窗，能增加接觸窗與主動區域的接觸面積並藉此增進元件的電性。The present invention provides a semiconductor device and a manufacturing method thereof. A contact window with a specific structure can increase the contact area between the contact window and an active area and thereby improve the electrical properties of the device.

本發明的半導體元件，包括具有多個主動區域的基底、至少一介電層以及多個接觸窗。所述介電層形成於基底上，接觸窗則是位於介電層中並連接至所述主動區域。每個接觸窗是桶狀結構（barrel-shaped structure），具有一中段部（middle portion）、周長比中段部的周長小的頂部（head portion）和周長比中段部的所述周長小的底部（end portion）。The semiconductor device of the present invention includes a substrate with multiple active regions, at least one dielectric layer, and multiple contact windows. The dielectric layer is formed on the substrate, and the contact window is located in the dielectric layer and connected to the active area. Each contact window is a barrel-shaped structure, having a middle portion, a head portion with a circumference smaller than the circumference of the middle portion, and a head portion with a circumference longer than the circumference of the middle portion A small end portion.

本發明的另一種半導體元件的製造方法包括在基底中定義多個主動區域，在所述基底上形成至少一介電層，並在介電層內形成多個開口並露出主動區域。通入第一氧電漿與第一氟電漿，以去除開口內的副產物並氧化開口的內面。通入第二氧電漿與第二氟電漿，以去除經氧化的內面而擴大開口並同時修補主動區域。通入第三氧電漿，以氧化經擴大的開口內面而形成一氧化層。然後去除氧化層，以形成多個接觸窗洞，其中兩相鄰接觸窗洞之剖面結構包括柱頭（Capital）、柱座（Base）以及介於柱頭與柱座之間的柱身（shaft），且所述柱身的寬度小於柱座的寬度、所述柱身的寬度也小於柱頭的寬度。於基底上沉積導體材料並填滿接觸窗洞，再平坦化所述導體材料，以於接觸窗洞內形成多個接觸窗。Another method of manufacturing a semiconductor device of the present invention includes defining a plurality of active regions in a substrate, forming at least one dielectric layer on the substrate, and forming a plurality of openings in the dielectric layer to expose the active regions. The first oxygen plasma and the first fluorine plasma are introduced to remove the by-products in the opening and oxidize the inner surface of the opening. Pass in the second oxygen plasma and the second fluorine plasma to remove the oxidized inner surface to expand the opening and repair the active area at the same time. A third oxygen plasma is introduced to oxidize the inner surface of the enlarged opening to form an oxide layer. The oxide layer is then removed to form a plurality of contact window holes, wherein the cross-sectional structure of two adjacent contact window holes includes a capital, a base, and a shaft between the capital and the base. The width of the column body is smaller than the width of the column base, and the width of the column body is also smaller than the width of the column head. A conductive material is deposited on the substrate and the contact hole is filled, and then the conductive material is planarized to form a plurality of contact windows in the contact hole.

基於上述，本發明的方法能形成具有特定結構的多個接觸窗，每個接觸窗略成桶狀，且兩相鄰接觸窗之間的距離比一般微影蝕刻製程或自對準雙重圖案製程所形成的接觸窗的距離更近，意味著每個接觸窗與基底的接觸面積更大，因此能改善元件的電性。而且，即使接觸窗與主動區域有些微對準差異，也不影響電性連接。Based on the above, the method of the present invention can form a plurality of contact windows with a specific structure, each contact window is slightly barrel-shaped, and the distance between two adjacent contact windows is shorter than that of a general photolithography process or a self-aligned double pattern process. The formed contact windows are closer in distance, which means that each contact window has a larger contact area with the substrate, thus improving the electrical properties of the device. Moreover, even if there is a slight alignment difference between the contact window and the active area, the electrical connection is not affected.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

以下實施例中所附的圖式是為了能更完整地描述發明概念的示範性實施例，然而本發明仍可使用許多不同的形式來實施，且其不應該被視為受限於所記載的實施例。此外，本文使用「第一」、「第二」、「第三」等來描述不同階段的製程或者結構中不同的區域、膜層及/或區塊，其中在製程方面有先後順序的意思，但是在結構中這樣的用語僅用於區別一個區域、膜層或區塊與另一個區域、膜層或區塊。為了清楚起見，膜層、區域及/或結構元件的相對尺寸及位置可能縮小或放大。此外，相同或相似之標號表示相同或相似之元件，以下段落將不再贅述。The drawings attached to the following embodiments are intended to more fully describe the exemplary embodiments of the inventive concept. However, the present invention can still be implemented in many different forms, and it should not be considered as being limited to what is described. Examples. In addition, this article uses "first", "second", "third", etc. to describe different regions, layers, and/or blocks in different stages of the process or structure, where the order of the process means the order. However, in the structure, such terms are only used to distinguish one area, film layer or section from another area, film layer or section. For clarity, the relative sizes and positions of the film layers, regions, and/or structural elements may be reduced or enlarged. In addition, the same or similar reference numerals indicate the same or similar elements, and the details will not be repeated in the following paragraphs.

圖1是依照本發明的一實施例的一種半導體元件的上視示意圖，且為了清楚起見省略部分構件，如介電層。圖2A是圖1的I-I線段的剖面示意圖。圖2B是圖1的II-II線段的剖面示意圖。FIG. 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention, and some components, such as a dielectric layer, are omitted for clarity. Fig. 2A is a schematic cross-sectional view of the line I-I in Fig. 1. FIG. 2B is a schematic cross-sectional view of line II-II in FIG. 1.

請參照圖1與圖2A，本實施例的半導體元件10包括具有多個主動區域102的基底100、至少一介電層104以及多個接觸窗106。所述介電層104形成於基底100上，接觸窗106則是位於介電層104中並連接至主動區域102，且後續會在接觸窗106上方形成電容結構（未繪示）與其連接。每個接觸窗106是桶狀結構，具有中段部108、頂部110和底部112，且所述底部112可與主動區域102直接接觸，其中頂部110的周長比中段部108的周長小，底部112的周長也比中段部108的周長小，而頂部110的周長可大於或等於底部112的周長。文中的「周長」一般是指最寬部位的周長。另外，中段部108接近頂部110的部位108a可具有往頂部110漸縮的寬度。舉例而言，中段部108接近頂部110的部位108a的寬度縮減比例（即，中段部108寬度w1與部位108a的寬度w2的差值除以中段部108寬度w1）約在10%~25%之間，較佳是在12%~16%之間。而且，本實施例的中段部108在接近底部112的部位可具有階梯狀剖面114，其中階梯狀剖面114包括階底114a與側壁114b，且側壁114b連接階底114a與桶狀結構108的底部112。在一些實施方式中，階梯狀剖面114的最大寬度w3是頂部110的寬度w2的2.5倍以下，較佳是在1.66倍以下。在一些實施方式中，接觸窗106的材料例如是經摻雜或未經摻雜的多晶矽、氮化鈦、鎢、其類似者或其組合。1 and 2A, the semiconductor device 10 of this embodiment includes a substrate 100 having a plurality of active regions 102, at least one dielectric layer 104, and a plurality of contact windows 106. The dielectric layer 104 is formed on the substrate 100, and the contact window 106 is located in the dielectric layer 104 and connected to the active region 102, and subsequently a capacitor structure (not shown) will be formed above the contact window 106 to be connected to it. Each contact window 106 is a barrel-shaped structure with a middle section 108, a top 110 and a bottom 112, and the bottom 112 can directly contact the active area 102. The circumference of the top 110 is smaller than the circumference of the middle 108, and the bottom The circumference of 112 is also smaller than the circumference of the middle section 108, and the circumference of the top 110 may be greater than or equal to the circumference of the bottom 112. "Circumference" in the text generally refers to the circumference of the widest part. In addition, the portion 108 a of the middle section 108 close to the top 110 may have a width tapering toward the top 110. For example, the width reduction ratio of the portion 108a of the middle section 108 close to the top 110 (that is, the difference between the width w1 of the middle section 108 and the width w2 of the section 108a divided by the width w1 of the middle section 108) is approximately 10% to 25% It is preferably between 12% and 16%. Moreover, the middle section 108 of this embodiment may have a stepped cross section 114 near the bottom 112. The stepped cross section 114 includes a stepped bottom 114a and a side wall 114b, and the side wall 114b connects the stepped bottom 114a and the bottom 112 of the barrel structure 108. . In some embodiments, the maximum width w3 of the stepped profile 114 is less than 2.5 times the width w2 of the top portion 110, preferably less than 1.66 times. In some embodiments, the material of the contact window 106 is, for example, doped or undoped polysilicon, titanium nitride, tungsten, the like or a combination thereof.

接著，請參照圖1、圖2A和圖2B，在以記憶體元件為例的一實施方式中，半導體元件10還可包括在基底100內定義主動區域102的隔離結構116、沿第一方向D1延伸並沿第三方向D3排列的多條埋入式字元線118以及沿第三方向D3延伸並沿第一方向D1排列的多條位元線120。隔離結構116可為淺溝渠隔離結構（shallow trench isolation，STI）或深溝渠隔離結構（deep trench isolation，DTI）。而第一方向D1與第三方向D3交錯。舉例而言，第一方向D1可實質上正交於第三方向D3。另一方面，主動區域102沿第二方向D2延伸。第二方向D2交錯於第一方向D1與第三方向D3。在一實施方式中，第二方向D2與第三方向D3的夾角為30°至45°。Next, referring to FIGS. 1, 2A and 2B, in an embodiment taking a memory device as an example, the semiconductor device 10 may further include an isolation structure 116 defining an active region 102 in the substrate 100 along the first direction D1 A plurality of buried word lines 118 extending and arranged along the third direction D3 and a plurality of bit lines 120 extending along the third direction D3 and arranged along the first direction D1. The isolation structure 116 may be a shallow trench isolation (STI) structure or a deep trench isolation (DTI) structure. The first direction D1 and the third direction D3 are staggered. For example, the first direction D1 may be substantially orthogonal to the third direction D3. On the other hand, the active area 102 extends in the second direction D2. The second direction D2 is staggered with the first direction D1 and the third direction D3. In one embodiment, the angle between the second direction D2 and the third direction D3 is 30° to 45°.

在圖2A中，埋入式字元線118貫穿部分隔離結構116並於埋入式字元線118頂部設置有蓋層（cover layer）122，用以阻隔埋入式字元線118與其上方的結構。此外，在埋入式字元線118與隔離結構116之間可設有閘介電層（未繪示）。埋入式字元線118的材料例如是經摻雜或未經摻雜的多晶矽、鎢、其類似者或其組合。In FIG. 2A, the buried character line 118 penetrates a part of the isolation structure 116 and a cover layer 122 is provided on top of the buried character line 118 to block the buried character line 118 from the structure above it. . In addition, a gate dielectric layer (not shown) may be provided between the buried word line 118 and the isolation structure 116. The material of the buried word line 118 is, for example, doped or undoped polysilicon, tungsten, the like or a combination thereof.

在圖2B中，接觸窗106是位在兩條位元線120之間，且位元線120的側壁形成有間隙壁124、位元線120的頂部形成有蓋層126，這些結構都可用來保護位元線120並與接觸窗106隔離，且圖中因為相鄰的位元線120的間距小，所以接觸窗106的側面並不像圖2A所示；然而，若是相鄰的位元線120的間距夠大，則接觸窗106的側面也會如圖2A所示，具有往頂部漸縮的寬度。另外，基底100與位元線120之間還可設置絕緣層128和介電層130等膜層，但本發明並不限於此。位元線120的材料例如是經摻雜或未經摻雜的多晶矽、鎢、其類似者或其組合。In FIG. 2B, the contact window 106 is located between the two bit lines 120, and the sidewalls of the bit lines 120 are formed with spacers 124, and the top of the bit lines 120 is formed with a cap layer 126. These structures can be used for protection The bit line 120 is separated from the contact window 106, and because the distance between adjacent bit lines 120 is small in the figure, the side surface of the contact window 106 is not as shown in FIG. 2A; however, if it is an adjacent bit line 120 If the distance between φ is large enough, the side surface of the contact window 106 will also have a width tapering toward the top as shown in FIG. 2A. In addition, film layers such as an insulating layer 128 and a dielectric layer 130 may also be provided between the substrate 100 and the bit line 120, but the present invention is not limited thereto. The material of the bit line 120 is, for example, doped or undoped polysilicon, tungsten, the like or a combination thereof.

在一些實施方式中，基底100可為半導體基底或半導體上覆絕緣體（semiconductor on insulator，SOI）基底。半導體基底或SOI基底中的半導體材料可包括元素半導體、合金半導體或化合物半導體。舉例而言，元素半導體可包括Si或Ge。合金半導體可包括SiGe、SiC、SiGeC等。化合物半導體可包括III-V族半導體材料或II-VI族半導體材料。在一些實施方式中，基底100可經摻雜為第一導電型或與第一導電型互補的第二導電型。舉例而言，第一導電型可為N型，而第二導電型則可為P型。在一些實施方式中，位於基底100中的隔離結構116的材料為絕緣材料，如氧化矽、氮化矽、氮氧化矽、其類似者或其組合。In some embodiments, the substrate 100 may be a semiconductor substrate or a semiconductor on insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or the SOI substrate may include elemental semiconductors, alloy semiconductors, or compound semiconductors. For example, the elemental semiconductor may include Si or Ge. The alloy semiconductor may include SiGe, SiC, SiGeC, and the like. The compound semiconductor may include group III-V semiconductor materials or group II-VI semiconductor materials. In some embodiments, the substrate 100 may be doped into a first conductivity type or a second conductivity type complementary to the first conductivity type. For example, the first conductivity type can be N type, and the second conductivity type can be P type. In some embodiments, the material of the isolation structure 116 in the substrate 100 is an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, the like or a combination thereof.

此外，位於基底100上的介電層104則是由絕緣材料構成，例如是氧化矽、氮化矽、氮氧化矽、其類似者或其組合。在一些實施方式中，介電層104可為單層結構，且此單層結構的材料可包括氧化矽或其他低介電常數介電材料（例如是介電常數低於4的介電材料）。在替代實施方式中，介電層104可為多層結構，例如是由氧化矽、氮化矽或其他介電材料構成的多層結構。此外，在其他實施方式中，介電層104中可具有空氣間隙（air gap）。In addition, the dielectric layer 104 on the substrate 100 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, the like or a combination thereof. In some embodiments, the dielectric layer 104 may be a single-layer structure, and the material of the single-layer structure may include silicon oxide or other low-k dielectric materials (for example, dielectric materials with a dielectric constant lower than 4) . In alternative embodiments, the dielectric layer 104 may be a multilayer structure, for example, a multilayer structure made of silicon oxide, silicon nitride, or other dielectric materials. In addition, in other embodiments, the dielectric layer 104 may have an air gap.

圖3A至圖3G是依照本發明的一實施例的一種半導體元件的製造流程剖面示意圖，其中使用與上一實施例相同的元件符號來代表相同或相似的構件，且所省略的部分技術說明，如各層或區域的位置、尺寸、材料等均可參照上一實施例的內容，因此於下文不再贅述。3A to 3G are schematic cross-sectional views of a manufacturing process of a semiconductor device according to an embodiment of the present invention, in which the same component symbols as in the previous embodiment are used to represent the same or similar components, and some technical descriptions are omitted. For example, the position, size, material, etc. of each layer or region can be referred to the content of the previous embodiment, and therefore will not be described in detail below.

請參照圖3A，在基底100中先定義多個主動區域102，譬如在基底100內形成隔離結構116，而定義出主動區域102。而，若是以記憶體元件為例，還可接續埋入式字元線118的形成，且於基底100上會有保護層300，用以保護基底100的表面不受先前製作隔離結構116過程中所施行的蝕刻製程的影響，並作為後續蝕刻製程的中止層。接著，在基底100上形成至少一介電層104，並在介電層104內形成多個開口302。在一實施例中，各開口302具有實質上相同的孔徑。而形成開口302的方式例如微影蝕刻製程或自對準雙重圖案（SADP）製程。Referring to FIG. 3A, a plurality of active regions 102 are first defined in the substrate 100. For example, an isolation structure 116 is formed in the substrate 100 to define the active regions 102. However, if the memory device is taken as an example, the formation of embedded character lines 118 can also be continued, and there will be a protective layer 300 on the substrate 100 to protect the surface of the substrate 100 from the previous process of manufacturing the isolation structure 116 The effect of the etching process performed is used as a stop layer for the subsequent etching process. Next, at least one dielectric layer 104 is formed on the substrate 100, and a plurality of openings 302 are formed in the dielectric layer 104. In one embodiment, each opening 302 has substantially the same aperture. The method of forming the opening 302 is, for example, a photolithography process or a self-aligned double pattern (SADP) process.

之後，請參照圖3B，去除基底100表面的保護層300，以露出主動區域102，而去除保護層300的方式例如濕式蝕刻或乾式蝕刻。若是沒有設置保護層300或者保護層300已於先前步驟去除，則不需此步驟。Afterwards, referring to FIG. 3B, the protective layer 300 on the surface of the substrate 100 is removed to expose the active region 102, and the protective layer 300 is removed by wet etching or dry etching. If the protective layer 300 is not provided or the protective layer 300 has been removed in the previous step, this step is not required.

然後，請參照圖3C，介電層104若為氮化矽，則先通入第一氧電漿與第一氟電漿，以去除開口302內的副產物並氧化開口302的內面302a。在一些實施方式中，產生第一氧電漿的氣體包括流量為1000 sccm~3000 sccm的氧氣，產生第一氟電漿的氣體包括流量為10 sccm~50 sccm的CF ₄氣體，且製程壓力為10mT~1000mT以及功率為500W ~ 2000W。 Then, referring to FIG. 3C, if the dielectric layer 104 is silicon nitride, the first oxygen plasma and the first fluorine plasma are introduced to remove the by-products in the opening 302 and oxidize the inner surface 302a of the opening 302. In some embodiments, the gas for generating the first oxygen plasma includes oxygen with a flow rate of 1000 sccm to 3000 sccm, and the gas for generating the first fluorine plasma includes CF ₄ gas with a flow rate of 10 sccm to 50 sccm, and the process pressure is 10mT~1000mT and power of 500W~2000W.

隨後，請參照圖3D，通入第二氧電漿與第二氟電漿，以去除經氧化的內面（圖3C的302a）而擴大開口302並同時修補主動區域102，其中產生第二氟電漿的氣體流量可大於產生上述第一氟電漿的氣體流量。在一些實施方式中，產生第二氧電漿的氣體包括流量為1000 sccm~3000 sccm的氧氣，產生第二氟電漿的氣體包括流量為50 sccm~200 sccm的CF ₄氣體，且製程壓力為10mT~1000mT以及功率為500W ~ 2000W。 Subsequently, referring to FIG. 3D, a second oxygen plasma and a second fluorine plasma are introduced to remove the oxidized inner surface (302a of FIG. 3C) to enlarge the opening 302 and repair the active area 102 at the same time, which generates second fluorine. The gas flow rate of the plasma may be greater than the gas flow rate for generating the first fluorine plasma. In some embodiments, the gas for generating the second oxygen plasma includes oxygen with a flow rate of 1000 sccm to 3000 sccm, and the gas for generating the second fluorine plasma includes CF ₄ gas with a flow rate of 50 sccm to 200 sccm, and the process pressure is 10mT~1000mT and power of 500W~2000W.

接著，請參照圖3E，通入第三氧電漿，以氧化經擴大的開口302內面而形成一氧化層304。在一些實施方式中，產生第三氧電漿的氣體包括流量為50sccm~3000 sccm的氧氣，且製程壓力為10mT~1000mT以及功率為500W ~ 2000W。Next, referring to FIG. 3E, a third oxygen plasma is introduced to oxidize the inner surface of the enlarged opening 302 to form an oxide layer 304. In some embodiments, the gas for generating the third oxygen plasma includes oxygen at a flow rate of 50 sccm to 3000 sccm, and the process pressure is 10 mT to 1000 mT and the power is 500W to 2000W.

以上有關第一氧電漿與第一氟電漿、第二氧電漿與第二氟電漿以及第三氧電漿的產生條件並不用以限制本發明的實施方式，舉例來說，產生第二氟電漿的氣體也可選擇其他氣體，如NF ₃、CH ₂F ₂等。原則上，若是使用相同的氣體，則產生第一氧電漿的氣體流量接近或實質上等於產生第二氧電漿的氣體流量，產生第二氟電漿的氣體流量大於產生第一氟電漿的氣體流量。 The above production conditions of the first oxygen plasma and the first fluorine plasma, the second oxygen plasma and the second fluorine plasma, and the third oxygen plasma are not intended to limit the embodiments of the present invention. For example, the The gas of difluoride plasma can also choose other gases, such as NF ₃ , CH ₂ F ₂ and so on. In principle, if the same gas is used, the gas flow rate for generating the first oxygen plasma is close to or substantially equal to the gas flow rate for generating the second oxygen plasma, and the gas flow rate for generating the second fluorine plasma is greater than that for generating the first fluorine plasma. The gas flow rate.

然後，請參照圖3F，去除氧化層（圖3E的304），以形成多個接觸窗洞306，去除氧化層的方法例如濕式蝕刻。兩相鄰接觸窗洞306的剖面結構包括柱頭（Capital）308、柱座（Base）310以及介於柱頭308與柱座310之間的柱身（shaft）312，且柱身312的寬度w4小於柱座310的寬度w5、柱身312的寬度w4也小於柱頭308的寬度w6。在一些實施方式中，每個接觸窗洞306的孔徑d2例如是每個開口的孔徑（圖3B的d1）的1.05倍~2倍（即，1+[(d2-d1)/d1]）。文中的「孔徑」一般是指最寬部位的孔徑。而且，每個接觸窗洞306在柱座310與柱身312之間有階梯狀剖面114，其中因為上述濕式製程的影響，階梯狀剖面114的側壁114b可能是錐形側壁。由於接觸窗洞306比先前經微影蝕刻製程或自對準雙重圖案製程所形成的開口要大，所以即使在前述製程有些微對準誤差，也不致影響後續形成的接觸窗與主動區域102的接觸面積。Then, referring to FIG. 3F, the oxide layer (304 in FIG. 3E) is removed to form a plurality of contact holes 306. The oxide layer is removed by a method such as wet etching. The cross-sectional structure of two adjacent contact window holes 306 includes a column head (Capital) 308, a column base (Base) 310, and a shaft (shaft) 312 between the column head 308 and the column base 310, and the width w4 of the column body 312 is smaller than the column The width w5 of the seat 310 and the width w4 of the column 312 are also smaller than the width w6 of the column head 308. In some embodiments, the aperture d2 of each contact hole 306 is, for example, 1.05 to 2 times (ie, 1+[(d2-d1)/d1]) of the aperture of each opening (d1 in FIG. 3B). "Aperture" in the text generally refers to the aperture of the widest part. Moreover, each contact hole 306 has a stepped cross section 114 between the column base 310 and the column body 312. Due to the influence of the wet process, the side wall 114b of the stepped cross section 114 may be a tapered side wall. Since the contact hole 306 is larger than the opening formed by the previous lithographic etching process or the self-aligned double patterning process, even if there is a slight alignment error in the foregoing process, it will not affect the contact between the subsequently formed contact window and the active region 102 area.

接著，請參照圖3G，於基底100上先沉積導體材料並填滿接觸窗洞306，再平坦化所述導體材料，以於接觸窗洞306內形成多個接觸窗106。在一些實施方式中，導體材料包括經摻雜或未經摻雜的多晶矽、氮化鈦、鎢、其類似者或其組合。而平坦化所述導體材料的方式例如化學機械研磨（CMP）。Next, referring to FIG. 3G, a conductive material is deposited on the substrate 100 and the contact hole 306 is filled first, and then the conductive material is planarized to form a plurality of contact holes 106 in the contact hole 306. In some embodiments, the conductive material includes doped or undoped polysilicon, titanium nitride, tungsten, the like, or a combination thereof. The method of planarizing the conductive material is, for example, chemical mechanical polishing (CMP).

綜上所述，本發明通過一連串特定製程可突破目前製程限制而形成桶狀結構的接觸窗，並因此增加接觸窗與主動區域的接觸面積，進而改善元件有關電的特性。To sum up, the present invention can break through the current process limitations through a series of specific manufacturing processes to form a barrel-shaped contact window, thereby increasing the contact area between the contact window and the active area, thereby improving the electrical characteristics of the device.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100:基底 102:主動區域 104、130:介電層 106:接觸窗 108:中段部 108a:部位 110:頂部 112:底部 114:階梯狀剖面 114a:階底 114b:側壁 116:隔離結構 118:埋入式字元線 120:位元線 122、126:蓋層 124:間隙壁 128:絕緣層 300:保護層 302:開口 302a:內面 304:氧化層 306:接觸窗洞 308:柱頭 310:柱座 312:柱身 d1、d2:孔徑 D1:第一方向 D2:第二方向 D3:第三方向 w1、w2、w3、w4、w5:寬度 100: base 102: active area 104, 130: Dielectric layer 106: contact window 108: middle section 108a: Location 110: top 112: bottom 114: Stepped section 114a: bottom 114b: sidewall 116: isolation structure 118: Embedded character line 120: bit line 122, 126: cover layer 124: Clearance Wall 128: insulating layer 300: protective layer 302: open 302a: Inside 304: oxide layer 306: contact window hole 308: Stigma 310: column base 312: Column d1, d2: aperture D1: First direction D2: second direction D3: Third party w1, w2, w3, w4, w5: width

圖1是依照本發明的一實施例的一種半導體元件的上視示意圖。圖2A是圖1的I-I線段的剖面示意圖。圖2B是圖1的II-II線段的剖面示意圖。圖3A至圖3G是依照本發明的一實施例的一種半導體元件的製造流程剖面示意圖。 FIG. 1 is a schematic top view of a semiconductor device according to an embodiment of the invention. Fig. 2A is a schematic cross-sectional view of the line I-I in Fig. 1. FIG. 2B is a schematic cross-sectional view of line II-II in FIG. 1. 3A to 3G are schematic cross-sectional views of a manufacturing process of a semiconductor device according to an embodiment of the invention.

100:基底 100: base

102:主動區域 102: active area

104:介電層 104: Dielectric layer

106:接觸窗 106: contact window

108:中段部 108: middle section

108a:部位 108a: Location

110:頂部 110: top

112:底部 112: bottom

114:階梯狀剖面 114: Stepped section

114a:階底 114a: bottom

114b:側壁 114b: sidewall

116:隔離結構 116: isolation structure

118:埋入式字元線 118: Embedded character line

122:蓋層 122: cap layer

w1、w2、w3:寬度 w1, w2, w3: width

Claims

一種半導體元件，包括：基底，具有多數個主動區域；多個隔離結構，位於基底中，以定義出所述多數個主動區域；多條埋入式字元線，貫穿部分所述多個隔離結構；至少一介電層，形成於所述基底上；多數個接觸窗，位於所述介電層中並連接至所述多數個主動區域，其中各所述接觸窗是桶狀結構，所述桶狀結構具有中段部、頂部以及底部，其中所述頂部的周長小於所述中段部的周長，所述底部的周長小於所述中段部的所述周長；以及電容結構，位於所述接觸窗上並與所述接觸窗連接。 A semiconductor device includes: a substrate with a plurality of active regions; a plurality of isolation structures located in the substrate to define the plurality of active regions; a plurality of buried character lines penetrating part of the plurality of isolation structures At least one dielectric layer, formed on the substrate; a plurality of contact windows located in the dielectric layer and connected to the plurality of active regions, wherein each of the contact windows is a barrel structure, the barrel The shape structure has a middle section, a top and a bottom, wherein the circumference of the top is smaller than the circumference of the middle section, and the circumference of the bottom is smaller than the circumference of the middle section; and a capacitor structure located at the On and connected to the contact window.

如申請專利範圍第1項所述的半導體元件，其中所述中段部接近所述頂部的部位具有往所述頂部漸縮的寬度。 The semiconductor device according to the first item of the scope of patent application, wherein a portion of the middle section close to the top has a width that tapers toward the top.

如申請專利範圍第2項所述的半導體元件，其中所述中段部接近所述頂部的所述部位的寬度縮減比例在10%~25%之間。 The semiconductor device according to the second item of the scope of patent application, wherein the width reduction ratio of the portion of the middle section close to the top is between 10% and 25%.

如申請專利範圍第1項所述的半導體元件，其中所述中段部接近所述底部的部位有階梯狀剖面。 The semiconductor element described in the first item of the scope of patent application, wherein a portion of the middle section close to the bottom has a stepped cross section.

如申請專利範圍第1項所述的半導體元件，其中所述頂部的周長大於或等於所述底部的周長。 The semiconductor device according to claim 1, wherein the circumference of the top is greater than or equal to the circumference of the bottom.

如申請專利範圍第4項所述的半導體元件，其中所述階梯狀剖面包括階底與側壁，所述階底的面方向平行於所述底部的面方向，且所述側壁連接所述階底與所述桶狀結構的所述底部。 The semiconductor device according to claim 4, wherein the stepped cross-section includes a step bottom and a side wall, the surface direction of the step bottom is parallel to the surface direction of the bottom, and the side wall connects the step bottom With the bottom of the barrel structure.

如申請專利範圍第6項所述的半導體元件，其中所述階梯狀剖面的所述側壁為錐形側壁。 According to the semiconductor device described in claim 6, wherein the side wall of the stepped cross-section is a tapered side wall.

一種半導體元件的製造方法，包括：在基底中定義多數個主動區域；在所述基底上形成至少一介電層；在所述至少一介電層內形成多數個開口並露出所述多數個主動區域；通入第一氧電漿與第一氟電漿，以去除所述多數個開口內的副產物並氧化所述多數個開口的內面；通入第二氧電漿與第二氟電漿，以去除經氧化的所述內面而擴大所述多數個開口並同時修補所述主動區域；通入第三氧電漿，以氧化經擴大的所述多數個開口的內面而形成一氧化層；去除所述氧化層，以形成多數個接觸窗洞，其中兩相鄰所述接觸窗洞之剖面結構包括柱頭(Capital)、柱座(Base)以及介於所述柱頭與所述柱座之間的柱身(shaft)，且所述柱身的寬度小於所述柱座的寬度以及小於所述柱頭的寬度；於所述基底上沉積導體材料並填滿所述多數個接觸窗洞；以及平坦化所述導體材料，以於所述多數個接觸窗洞內形成多數個接觸窗。 A method for manufacturing a semiconductor device includes: defining a plurality of active regions in a substrate; forming at least one dielectric layer on the substrate; forming a plurality of openings in the at least one dielectric layer and exposing the plurality of active regions Area; pass the first oxygen plasma and the first fluorine plasma to remove the by-products in the plurality of openings and oxidize the inner surface of the plurality of openings; pass the second oxygen plasma and the second fluorine plasma To remove the oxidized inner surface to expand the plurality of openings and repair the active area at the same time; pass a third oxygen plasma to oxidize the inner surface of the enlarged plurality of openings to form a Oxide layer; remove the oxide layer to form a plurality of contact window holes, wherein the cross-sectional structure of the two adjacent contact window holes includes a column head (Capital), a column base (Base) and between the column head and the column base Between the shaft, and the width of the shaft is smaller than the width of the column base and smaller than the width of the column head; depositing conductive material on the substrate and filling the plurality of contact window holes; and flat The conductive material is formed to form a plurality of contact windows in the plurality of contact window holes.

如申請專利範圍第8項所述的半導體元件的製造方法，其中各所述接觸窗洞的孔徑是各所述開口的所述孔徑的1.05倍~2倍。 According to the method for manufacturing a semiconductor device described in item 8 of the scope of patent application, the aperture of each contact hole is 1.05 to 2 times the aperture of each opening.

如申請專利範圍第8項所述的半導體元件的製造方法，其中產生所述第二氟電漿的氣體流量大於產生所述第一氟電漿的氣體流量。 The method for manufacturing a semiconductor element as described in claim 8, wherein the gas flow rate for generating the second fluorine plasma is greater than the gas flow rate for generating the first fluorine plasma.

如申請專利範圍第8項所述的半導體元件的製造方法，其中各所述接觸窗洞在所述柱座與所述柱身之間有階梯狀剖面。 According to the method for manufacturing a semiconductor device as described in item 8 of the scope of patent application, each of the contact holes has a stepped cross section between the column base and the column body.