TWI717820B - Device substrate and manufacturing method thereof - Google Patents

Device substrate and manufacturing method thereof Download PDF

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TWI717820B
TWI717820B TW108131643A TW108131643A TWI717820B TW I717820 B TWI717820 B TW I717820B TW 108131643 A TW108131643 A TW 108131643A TW 108131643 A TW108131643 A TW 108131643A TW I717820 B TWI717820 B TW I717820B
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layer
insulating layer
electrode
insulating
wire
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TW108131643A
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TW202111914A (en
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董哲維
林煒力
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友達光電股份有限公司
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Priority to CN202010311204.2A priority patent/CN111477636B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

A device substrate and a manufacturing method thereof are provided. The device substrate includes a substrate, a first conductive layer, a first insulating layer, a second insulating layer, a semiconductor layer, and a second conductive layer. The first conductive layer includes a first wire and a first electrode. The first wire is located on the wiring area. The first electrode is located on the active area. The first insulating layer covers the first conductive layer. The second insulating layer covers the first insulating layer, and the second insulating layer has an opening that overlaps the first electrode. The semiconductor layer is located in the opening. The second conductive layer includes a second wire and a second electrode. The second wire is located on the second insulating layer and partially overlaps the first wire. The second electrode is located on the semiconductor layer.

Description

元件基板及其製造方法Element substrate and manufacturing method thereof

本發明是有關於一種元件基板及其製造方法，且特別是有關於一種半導體層位於絕緣層開口中的元件基板。The invention relates to a device substrate and a manufacturing method thereof, and more particularly to a device substrate with a semiconductor layer located in an opening of an insulating layer.

元件基板通常包括自主動區延伸至周邊區的絕緣層。絕緣層可以用來隔離不同層別的導線，使不同層別的導線彼此間不會短路。為了因應市場需求，許多顯示裝置的廠商致力於提升顯示裝置的解析度或顯示裝置的尺寸。然而，為了提升顯示裝置的解析度或顯示裝置的尺寸，元件基板中不同層別的導線之間的電容容易因為導線加粗或導線密度提升而增加。若導線之間的電容太高，將會大幅影響顯示裝置的品質。The device substrate usually includes an insulating layer extending from the active area to the peripheral area. The insulating layer can be used to isolate the wires of different layers, so that the wires of different layers will not short-circuit with each other. In order to meet market demands, many display device manufacturers are dedicated to improving the resolution or size of the display device. However, in order to increase the resolution of the display device or the size of the display device, the capacitance between wires of different layers in the device substrate is likely to increase due to thicker wires or increased wire density. If the capacitance between the wires is too high, the quality of the display device will be greatly affected.

本發明提供一種元件基板，能改善導線之間電容值過大的問題，並能減少製造成本。The invention provides a component substrate, which can improve the problem of excessive capacitance between wires and reduce the manufacturing cost.

本發明提供一種元件基板的製造方法，能改善導線之間電容值過大的問題，並能減少製造成本。The invention provides a method for manufacturing a component substrate, which can improve the problem of excessive capacitance between wires and reduce the manufacturing cost.

本發明的至少一實施例提供一種元件基板。元件基板包括基板、第一導電層、第一絕緣層、第二絕緣層、半導體層以及第二導電層。基板包括線路區以及主動區。第一導電層包括第一導線以及第一電極。第一導線位於線路區上。第一電極位於主動區上。第一絕緣層覆蓋第一導電層。第二絕緣層覆蓋第一絕緣層，且第二絕緣層具有重疊於第一電極的開口。半導體層位於開口中，且與第一電極之間夾有第一絕緣層。第二導電層包括第二導線以及第二電極。第二導線位於第二絕緣層上，且部分重疊於第一導線，其中第二導線與第一導線之間夾有第一絕緣層以及第二絕緣層。第二電極位於半導體層上。At least one embodiment of the present invention provides a device substrate. The element substrate includes a substrate, a first conductive layer, a first insulating layer, a second insulating layer, a semiconductor layer, and a second conductive layer. The substrate includes a circuit area and an active area. The first conductive layer includes a first wire and a first electrode. The first wire is located on the line area. The first electrode is located on the active area. The first insulating layer covers the first conductive layer. The second insulating layer covers the first insulating layer, and the second insulating layer has an opening overlapping the first electrode. The semiconductor layer is located in the opening, and a first insulating layer is sandwiched between the semiconductor layer and the first electrode. The second conductive layer includes a second wire and a second electrode. The second wire is located on the second insulating layer and partially overlaps the first wire, wherein a first insulating layer and a second insulating layer are sandwiched between the second wire and the first wire. The second electrode is located on the semiconductor layer.

本發明的至少一實施例提供一種元件基板的製造方法，包括提供基板、形成第一導電層於基板上、形成第一絕緣層於第一導電層上、形成第二絕緣層、形成半導體層以及形成第二導電層。基板包括線路區以及主動區。第一導電層包括位於線路區上的第一導線以及位於主動區上的第一電極。形成第二絕緣材料層於第一絕緣層上；圖案化第二絕緣材料層以形成第二絕緣層。第二絕緣層覆蓋第一絕緣層，且第二絕緣層具有重疊於第一電極的開口。形成半導體材料層於第二絕緣層上；圖案化半導體材料層，以形成半導體層於開口中，其中半導體層與第一電極之間夾有第一絕緣層。第二導電層包括位於第二絕緣層上的第二導線以及位於半導體層上的第二電極。第二導線部分重疊於第一導線，且第二導線與第一導線之間夾有第一絕緣層以及第二絕緣層。At least one embodiment of the present invention provides a method for manufacturing a device substrate, including providing a substrate, forming a first conductive layer on the substrate, forming a first insulating layer on the first conductive layer, forming a second insulating layer, forming a semiconductor layer, and A second conductive layer is formed. The substrate includes a circuit area and an active area. The first conductive layer includes a first wire located on the circuit area and a first electrode located on the active area. A second insulating material layer is formed on the first insulating layer; the second insulating material layer is patterned to form the second insulating layer. The second insulating layer covers the first insulating layer, and the second insulating layer has an opening overlapping the first electrode. A semiconductor material layer is formed on the second insulating layer; the semiconductor material layer is patterned to form the semiconductor layer in the opening, wherein a first insulating layer is sandwiched between the semiconductor layer and the first electrode. The second conductive layer includes a second wire on the second insulating layer and a second electrode on the semiconductor layer. The second wire partially overlaps the first wire, and a first insulating layer and a second insulating layer are sandwiched between the second wire and the first wire.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

圖1至圖11是依照本發明的一實施例的一種元件基板的製造方法的剖面示意圖。1 to 11 are schematic cross-sectional views of a method of manufacturing a device substrate according to an embodiment of the present invention.

請參考圖1，提供基板100，基板100包括線路區110以及主動區120。在一些實施例中，線路區110例如為顯示面板的邊框區，而主動區120例如為顯示面板的顯示區，但本發明不以此為限。在其他實施例中，線路區110與主動區120可以皆位於顯示區中。基板100之材質可為玻璃、石英、有機聚合物、不透光和/或反射材料，例如：導電材料、金屬、晶圓、陶瓷或是其他適用的材料。根據其他實施例，可在基板100之表面上進一步形成一層或多層緩衝層。Please refer to FIG. 1, a substrate 100 is provided. The substrate 100 includes a circuit area 110 and an active area 120. In some embodiments, the line area 110 is, for example, the frame area of the display panel, and the active area 120 is, for example, the display area of the display panel, but the invention is not limited thereto. In other embodiments, the circuit area 110 and the active area 120 may both be located in the display area. The material of the substrate 100 can be glass, quartz, organic polymer, opaque and/or reflective materials, such as conductive materials, metals, wafers, ceramics, or other suitable materials. According to other embodiments, one or more buffer layers may be further formed on the surface of the substrate 100.

形成第一導電層200於基板100上。第一導電層200包括位於線路區110上的第一導線210以及位於主動區120上的第一電極220。第一導電層200例如為金屬材料、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物、其它合適的材料、或是金屬材料與其他導電材料的堆疊層。第一導電層200例如為單層或多層結構。A first conductive layer 200 is formed on the substrate 100. The first conductive layer 200 includes a first wire 210 located on the circuit area 110 and a first electrode 220 located on the active area 120. The first conductive layer 200 is, for example, a metal material, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, other suitable materials, or a stacked layer of a metal material and other conductive materials. The first conductive layer 200 is, for example, a single-layer or multi-layer structure.

請參考圖2，形成第一絕緣層300於第一導電層200上。第一絕緣層300覆蓋第一導線210以及第一電極220。在一些實施例中，第一絕緣層300的材料為包含無機材料（例如：氧化矽、氮化矽、氮氧化矽、其他合適的材料或上述至少二種材料的堆疊層）或有機材料或其它合適的材料或上述的組合。在一些實施例中，第一絕緣層300的介電係數為6至6.5。在一些實施例中，第一絕緣層300的厚度T1為2500微米至3500微米。Please refer to FIG. 2, a first insulating layer 300 is formed on the first conductive layer 200. The first insulating layer 300 covers the first wire 210 and the first electrode 220. In some embodiments, the material of the first insulating layer 300 includes inorganic materials (for example, silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a stacked layer of at least two of the foregoing materials) or organic materials or other materials. Suitable materials or a combination of the above. In some embodiments, the dielectric constant of the first insulating layer 300 is 6 to 6.5. In some embodiments, the thickness T1 of the first insulating layer 300 is from 2500 μm to 3500 μm.

請參考圖3，形成第二絕緣材料層400於第一絕緣層300上。在一些實施例中，第二絕緣材料層400的材料為包含無機材料（例如：氧化矽、氮化矽、氮氧化矽、其他合適的材料或上述至少二種材料的堆疊層）或有機材料或其它合適的材料或上述的組合。在一些實施例中，第二絕緣材料層400的介電係數為4至4.5。在一些實施例中，第二絕緣材料層400的厚度T1為500微米至1500微米。Referring to FIG. 3, a second insulating material layer 400 is formed on the first insulating layer 300. In some embodiments, the material of the second insulating material layer 400 includes inorganic materials (for example: silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a stacked layer of at least two of the foregoing materials) or organic materials or Other suitable materials or combinations of the above. In some embodiments, the dielectric constant of the second insulating material layer 400 is 4 to 4.5. In some embodiments, the thickness T1 of the second insulating material layer 400 is 500 μm to 1500 μm.

在一些實施例中，第二絕緣材料層400的材料不同於該第一絕緣層300的材料，第二絕緣材料層400的介電係數小於該第一絕緣層300的介電係數。舉例來說，第二絕緣材料層400的材料的介電係數為4，而第一絕緣層300的材料的介電係數為6.2。在一些實施例中，第二絕緣層400的材料為氧化矽，且第一絕緣層300的材料為氮化矽。藉此，能進一步減少第一導線210與其他導線之間的電容值。In some embodiments, the material of the second insulating material layer 400 is different from the material of the first insulating layer 300, and the dielectric constant of the second insulating material layer 400 is smaller than that of the first insulating layer 300. For example, the dielectric constant of the material of the second insulating material layer 400 is 4, and the dielectric constant of the material of the first insulating layer 300 is 6.2. In some embodiments, the material of the second insulating layer 400 is silicon oxide, and the material of the first insulating layer 300 is silicon nitride. In this way, the capacitance between the first wire 210 and other wires can be further reduced.

請參考圖4至圖6，圖案化第二絕緣材料層400以形成第二絕緣層400a。第二絕緣層400a的介電係數小於第一絕緣層300的介電係數。在本實施例中，以第一光罩M1圖案化第二絕緣材料層400。舉例來說，形成負光阻材料層PR1於第二絕緣材料層400上；以第一光罩M1為罩幕圖案化負光阻材料層PR1，以形成圖案化的負光阻層PR1a；以圖案化的負光阻層PR1a為罩幕，圖案化第二絕緣材料層400，以形成第二絕緣層400a。4-6, the second insulating material layer 400 is patterned to form the second insulating layer 400a. The dielectric constant of the second insulating layer 400 a is smaller than the dielectric constant of the first insulating layer 300. In this embodiment, the second insulating material layer 400 is patterned with the first mask M1. For example, a negative photoresist material layer PR1 is formed on the second insulating material layer 400; the negative photoresist material layer PR1 is patterned using the first photomask M1 as a mask to form a patterned negative photoresist layer PR1a; The patterned negative photoresist layer PR1a is a mask, and the second insulating material layer 400 is patterned to form the second insulating layer 400a.

在本實施例中，圖案化的負光阻層PR1a具有開口C1，其中開口C1的位置對應於第一光罩M1的開口C2。In this embodiment, the patterned negative photoresist layer PR1a has an opening C1, wherein the position of the opening C1 corresponds to the opening C2 of the first mask M1.

第二絕緣層400a覆蓋第一絕緣層300，且第二絕緣層400a具有重疊於第一電極220的開口O。開口O的位置對應於圖案化的負光阻層PR1a的開口C1以及第一光罩M1的開口C2。The second insulating layer 400 a covers the first insulating layer 300, and the second insulating layer 400 a has an opening O overlapping the first electrode 220. The position of the opening O corresponds to the opening C1 of the patterned negative photoresist layer PR1a and the opening C2 of the first photomask M1.

在一些實施例中，第二絕緣層400a的開口O的寬度W1小於第一電極220的寬度W2。In some embodiments, the width W1 of the opening O of the second insulating layer 400a is smaller than the width W2 of the first electrode 220.

形成開口O的方法例如包括蝕刻。在形成開口O後，移除圖案化的負光阻層PR1a。The method of forming the opening O includes, for example, etching. After the opening O is formed, the patterned negative photoresist layer PR1a is removed.

請參考圖7，形成半導體材料層500於第二絕緣層400a上。在本實施例中，半導體材料層500填入第二絕緣層400a的開口O。半導體材料層500為單層或多層結構，其包含非晶矽、多晶矽、微晶矽、單晶矽、有機半導體材料、氧化物半導體材料(例如：銦鋅氧化物、銦鎵鋅氧化物或是其它合適的材料或上述之組合)或其它合適的材料或含有摻雜物(dopant)於上述材料中或上述之組合。Referring to FIG. 7, a semiconductor material layer 500 is formed on the second insulating layer 400a. In this embodiment, the semiconductor material layer 500 fills the opening O of the second insulating layer 400a. The semiconductor material layer 500 is a single-layer or multi-layer structure, which includes amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (for example: indium zinc oxide, indium gallium zinc oxide or Other suitable materials or a combination of the above) or other suitable materials or containing dopants in the above materials or a combination of the above.

請參考圖8至圖10，圖案化半導體材料層500，以形成半導體層500a於開口O中。在本實施例中，以第一光罩M1圖案化半導體材料層500。舉例來說，形成正光阻材料層PR2於第二絕緣層400a上；以第一光罩M1為罩幕圖案化正光阻材料層PR2，以形成圖案化的正光阻層PR2a；以圖案化的正光阻層PR2a為罩幕，圖案化半導體材料層500，以形成半導體層500a。8-10, the semiconductor material layer 500 is patterned to form the semiconductor layer 500a in the opening O. In this embodiment, the semiconductor material layer 500 is patterned by the first mask M1. For example, a positive photoresist material layer PR2 is formed on the second insulating layer 400a; the positive photoresist material layer PR2 is patterned using the first photomask M1 as a mask to form a patterned positive photoresist layer PR2a; and a patterned positive light The resist layer PR2a is a mask, and the semiconductor material layer 500 is patterned to form the semiconductor layer 500a.

在本實施例中，圖案化的正光阻層PR2a具有遮罩P，其中遮罩P的位置對應於第一光罩M1的開口C2以及第二絕緣層400a的開口O。半導體層500a重疊於遮罩P。In this embodiment, the patterned positive photoresist layer PR2a has a mask P, where the position of the mask P corresponds to the opening C2 of the first mask M1 and the opening O of the second insulating layer 400a. The semiconductor layer 500a overlaps the mask P.

形成半導體層500a的方法例如包括蝕刻。在形成半導體層500a後，移除圖案化的正光阻層PR2a。The method of forming the semiconductor layer 500a includes, for example, etching. After the semiconductor layer 500a is formed, the patterned positive photoresist layer PR2a is removed.

在一些實施例中，半導體層500a的寬度W3小於第一電極220的寬度W2。In some embodiments, the width W3 of the semiconductor layer 500a is smaller than the width W2 of the first electrode 220.

在本實施例中，由於半導體層500a以及第二絕緣層400a的開口O都是以第一光罩M1為罩幕而形成，因此，半導體層500a的垂直投影於基板100上的形狀與開口O垂直投影於基板100上的形狀相同。在本實施例中，半導體層500a的寬度W3小於或等於第二絕緣層400a的開口O的寬度W1。在本實施例中，半導體層500a垂直投影於基板100上的面積小於或等於開口O的底面積。In this embodiment, since the opening O of the semiconductor layer 500a and the second insulating layer 400a are formed by using the first mask M1 as a mask, the shape of the semiconductor layer 500a perpendicularly projected on the substrate 100 and the opening O The shapes projected vertically on the substrate 100 are the same. In this embodiment, the width W3 of the semiconductor layer 500a is less than or equal to the width W1 of the opening O of the second insulating layer 400a. In this embodiment, the area of the semiconductor layer 500a projected vertically on the substrate 100 is less than or equal to the bottom area of the opening O.

藉由同一個第一光罩M1形成半導體層500a以及第二絕緣層400a的開口O，可以減少製造元件基板所需的光罩數量，並減少製造成本。By forming the opening O of the semiconductor layer 500a and the second insulating layer 400a by the same first photomask M1, the number of photomasks required for manufacturing the device substrate can be reduced, and the manufacturing cost can be reduced.

雖然在圖10中，半導體層500a的頂表面為平面，但本發明不以此為限。在一些實施例中，半導體層500a的部分頂表面（例如是半導體層500a靠近開口O側壁的部分）會突起。Although in FIG. 10, the top surface of the semiconductor layer 500a is flat, the present invention is not limited to this. In some embodiments, part of the top surface of the semiconductor layer 500a (for example, the part of the semiconductor layer 500a close to the sidewall of the opening O) is protruding.

請參考圖11，形成第二導電層600。第二導電層600包括位於第二絕緣層400a上的第二導線610、位於半導體層500a上的第二電極620以及位於半導體層500a上的第三電極630。Referring to FIG. 11, the second conductive layer 600 is formed. The second conductive layer 600 includes a second wire 610 on the second insulating layer 400a, a second electrode 620 on the semiconductor layer 500a, and a third electrode 630 on the semiconductor layer 500a.

第二導電層600例如為金屬材料、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物、其它合適的材料、或是金屬材料與其他導電材料的堆疊層。第二導電層600例如為單層或多層結構。The second conductive layer 600 is, for example, a metal material, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, other suitable materials, or a stacked layer of a metal material and other conductive materials. The second conductive layer 600 is, for example, a single-layer or multi-layer structure.

第二導線610部分重疊於第一導線210。第二導線610的延伸方向與第一導線210的延伸方向相同或不同。在一些實施例中，第二導線610與第一導線210彼此交錯。The second wire 610 partially overlaps the first wire 210. The extending direction of the second wire 610 is the same as or different from the extending direction of the first wire 210. In some embodiments, the second wire 610 and the first wire 210 are interlaced with each other.

第三電極630與第二電極620分離，其中第一電極220、第二電極620、第三電極630以及半導體層500a分別構成主動元件T的閘極、源極、汲極以及通道層。The third electrode 630 is separated from the second electrode 620, wherein the first electrode 220, the second electrode 620, the third electrode 630 and the semiconductor layer 500a constitute the gate, source, drain and channel layer of the active device T, respectively.

在一些實施例中，於形成第二導電層600之前，先於半導體層500a表面形成歐姆接觸層（未繪出），藉此能避免形成第二導電層600時對半導體層500a造成損傷。In some embodiments, before forming the second conductive layer 600, an ohmic contact layer (not shown) is formed on the surface of the semiconductor layer 500a, so as to avoid damage to the semiconductor layer 500a when the second conductive layer 600 is formed.

至此，元件基板10大致完成。元件基板10包括基板100、第一導電層200、第一絕緣層300、第二絕緣層400a、半導體層500a以及第二導電層600。So far, the element substrate 10 is substantially completed. The element substrate 10 includes a substrate 100, a first conductive layer 200, a first insulating layer 300, a second insulating layer 400a, a semiconductor layer 500a, and a second conductive layer 600.

綜上所述，由於第二導線610與第一導線210之間夾有第一絕緣層300以及第二絕緣層400a，因此，可以降低第二導線610與第一導線210之間的電容值。此外，由於半導體層500a位於第二絕緣層400a的開口中，因此，主動元件T能維持良好的電性。另外，藉由同一個第一光罩形成半導體層500a以及第二絕緣層400a的開口O，可以減少製造元件基板10所需的光罩數量，並減少製造成本。In summary, since the first insulating layer 300 and the second insulating layer 400a are sandwiched between the second wire 610 and the first wire 210, the capacitance value between the second wire 610 and the first wire 210 can be reduced. In addition, since the semiconductor layer 500a is located in the opening of the second insulating layer 400a, the active device T can maintain good electrical properties. In addition, by forming the opening O of the semiconductor layer 500a and the second insulating layer 400a by the same first photomask, the number of photomasks required for manufacturing the device substrate 10 can be reduced, and the manufacturing cost can be reduced.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10:元件基板 100:基板 110:線路區 120:主動區 200:第一導電層 210:第一導線 220:第一電極 300:第一絕緣層 400:第二絕緣材料層 400a:第二絕緣層 500:半導體材料層 500a:半導體層 600:第二導電層 610:第二導線 620:第二電極 630:第三電極 C1、C2:開口 M1:第一光罩 O:開口 T:主動元件 W1、W2、W3:寬度 10: Component substrate 100: substrate 110: Line area 120: active area 200: the first conductive layer 210: first wire 220: first electrode 300: first insulating layer 400: second insulating material layer 400a: second insulating layer 500: semiconductor material layer 500a: semiconductor layer 600: second conductive layer 610: second wire 620: second electrode 630: third electrode C1, C2: opening M1: The first mask O: opening T: Active component W1, W2, W3: width

圖1至圖11是依照本發明的一實施例的一種元件基板的製造方法的剖面示意圖。1 to 11 are schematic cross-sectional views of a method of manufacturing a device substrate according to an embodiment of the present invention.

10:元件基板 10: Component substrate

100:基板 100: substrate

110:線路區 110: Line area

120:主動區 120: active area

200:第一導電層 200: the first conductive layer

210:第一導線 210: first wire

220:第一電極 220: first electrode

300:第一絕緣層 300: first insulating layer

400a:第二絕緣層 400a: second insulating layer

500a:半導體層 500a: semiconductor layer

600:第二導電層 600: second conductive layer

610:第二導線 610: second wire

620:第二電極 620: second electrode

630:第三電極 630: third electrode

O:開口 O: opening

T:主動元件 T: Active component

Claims (13)

一種元件基板，包括：一基板，包括一線路區以及一主動區；一第一導電層，包括：一第一導線，位於該線路區中之該基板上；以及一第一電極，位於該主動區中之該基板上；一第一絕緣層，覆蓋該第一導電層；一第二絕緣層，覆蓋該第一絕緣層，且該第二絕緣層具有重疊於該第一電極的一開口；一半導體層，位於該開口中，且與該第一電極之間夾有該第一絕緣層；以及一第二導電層，包括：一第二導線，位於該第二絕緣層上，且部分重疊於該第一導線，其中該第二導線與該第一導線之間夾有該第一絕緣層以及該第二絕緣層；以及一第二電極，位於該半導體層上。 A device substrate includes: a substrate including a circuit area and an active area; a first conductive layer including: a first wire located on the substrate in the circuit area; and a first electrode located on the active area On the substrate in the region; a first insulating layer covering the first conductive layer; a second insulating layer covering the first insulating layer, and the second insulating layer has an opening overlapping the first electrode; A semiconductor layer located in the opening and sandwiching the first insulating layer with the first electrode; and a second conductive layer including: a second wire located on the second insulating layer and partially overlapping On the first wire, the first insulating layer and the second insulating layer are sandwiched between the second wire and the first wire; and a second electrode located on the semiconductor layer. 如申請專利範圍第1項所述的元件基板，其中該第二導電層，更包括：一第三電極，位於該半導體層上，且與該第二電極分離，其中該第一電極、該第二電極以及該第三電極分別構成一主動元件的一閘極、一源極以及一汲極。 According to the device substrate described in claim 1, wherein the second conductive layer further includes: a third electrode located on the semiconductor layer and separated from the second electrode, wherein the first electrode and the second electrode The two electrodes and the third electrode respectively constitute a gate, a source and a drain of an active device. 如申請專利範圍第1項所述的元件基板，其中該半導體層垂直投影於該基板上的面積小於或等於該開口的底面積。 According to the device substrate described in claim 1, wherein the area of the semiconductor layer projected vertically on the substrate is less than or equal to the bottom area of the opening. 如申請專利範圍第1項所述的元件基板，其中該開口的寬度小於該第一電極的寬度。 According to the device substrate described in claim 1, wherein the width of the opening is smaller than the width of the first electrode. 如申請專利範圍第1項所述的元件基板，其中該第二絕緣層的介電係數小於該第一絕緣層的介電係數。 According to the device substrate described in claim 1, wherein the dielectric constant of the second insulating layer is less than the dielectric constant of the first insulating layer. 如申請專利範圍第5項所述的元件基板，其中該第二絕緣層的介電係數為4至4.5，且該第一絕緣層的介電係數為6至6.5。 In the device substrate according to item 5 of the scope of patent application, the dielectric constant of the second insulating layer is 4 to 4.5, and the dielectric constant of the first insulating layer is 6 to 6.5. 如申請專利範圍第5項所述的元件基板，其中該第二絕緣層的材料為氧化矽，且該第一絕緣層的材料為氮化矽。 According to the device substrate described in claim 5, the material of the second insulating layer is silicon oxide, and the material of the first insulating layer is silicon nitride. 如申請專利範圍第5項所述的元件基板，其中該開口貫穿該第二絕緣層且不貫穿該第一絕緣層。 According to the device substrate described in item 5 of the scope of patent application, the opening penetrates the second insulating layer and does not penetrate the first insulating layer. 一種元件基板的製造方法，包括：提供一基板，其中該基板包括一線路區以及一主動區；形成一第一導電層於該基板上，其中該第一導電層包括：一第一導線，位於該線路區中之該基板上；以及一第一電極，位於該主動區中之該基板上；形成一第一絕緣層於該第一導電層上；形成一第二絕緣材料層於該第一絕緣層上；圖案化該第二絕緣材料層，以形成一第二絕緣層，其中該第二絕緣層覆蓋該第一絕緣層，且該第二絕緣層具有重疊於該第一 電極的一開口；形成一半導體材料層於該第二絕緣層上；圖案化該半導體材料層，以形成一半導體層於該開口中，其中該半導體層與該第一電極之間夾有該第一絕緣層；以及形成一第二導電層，該第二導電層包括：一第二導線，位於該第二絕緣層上，且部分重疊於該第一導線，其中該第二導線與該第一導線之間夾有該第一絕緣層以及該第二絕緣層；以及一第二電極，位於該半導體層上。 A method for manufacturing a component substrate includes: providing a substrate, wherein the substrate includes a circuit area and an active area; forming a first conductive layer on the substrate, wherein the first conductive layer includes: a first wire located On the substrate in the circuit area; and a first electrode located on the substrate in the active area; forming a first insulating layer on the first conductive layer; forming a second insulating material layer on the first On the insulating layer; pattern the second insulating material layer to form a second insulating layer, wherein the second insulating layer covers the first insulating layer, and the second insulating layer has overlapped with the first insulating layer Forming an opening of the electrode; forming a semiconductor material layer on the second insulating layer; patterning the semiconductor material layer to form a semiconductor layer in the opening, wherein the first electrode is sandwiched between the semiconductor layer and the first electrode An insulating layer; and forming a second conductive layer, the second conductive layer comprising: a second wire located on the second insulating layer and partially overlapping the first wire, wherein the second wire and the first wire The first insulating layer and the second insulating layer are sandwiched between the wires; and a second electrode is located on the semiconductor layer. 如申請專利範圍第9項所述的元件基板的製造方法，其中以一第一光罩圖案化該第二絕緣材料層，且以該第一光罩圖案化該半導體材料層。 According to the manufacturing method of the device substrate described in the scope of patent application, the second insulating material layer is patterned by a first photomask, and the semiconductor material layer is patterned by the first photomask. 如申請專利範圍第10項所述的元件基板的製造方法，其中以該第一光罩圖案化該第二絕緣材料層的方法包括：形成一負光阻材料層於該第二絕緣材料層上；以該第一光罩為罩幕圖案化該負光阻材料層，以形成一圖案化的負光阻層；以該圖案化的負光阻層為罩幕，圖案化該第二絕緣材料層，以形成該第二絕緣層。 The method for manufacturing a device substrate according to claim 10, wherein the method of patterning the second insulating material layer with the first mask includes: forming a negative photoresist material layer on the second insulating material layer Use the first photomask as a mask to pattern the negative photoresist material layer to form a patterned negative photoresist layer; use the patterned negative photoresist layer as a mask to pattern the second insulating material Layer to form the second insulating layer. 如申請專利範圍第10項所述的元件基板的製造方法，其中以該第一光罩圖案化該半導體材料層的方法包括：形成一正光阻材料層於該第二絕緣層上； 以該第一光罩為罩幕圖案化該正光阻材料層，以形成一圖案化的正光阻層；以該圖案化的正光阻層為罩幕，圖案化該半導體材料層，以形成該半導體層。 The method for manufacturing a device substrate according to claim 10, wherein the method of patterning the semiconductor material layer with the first photomask includes: forming a positive photoresist material layer on the second insulating layer; Use the first photomask as a mask to pattern the positive photoresist material layer to form a patterned positive photoresist layer; use the patterned positive photoresist layer as a mask to pattern the semiconductor material layer to form the semiconductor Floor. 如申請專利範圍第9項所述的元件基板的製造方法，其中該第二導電層，更包括：一第三電極，位於該半導體層上，且與該第二電極分離，其中該第一電極、該第二電極以及該第三電極分別構成一主動元件的一閘極、一源極以及一汲極。 According to the method for manufacturing a device substrate according to claim 9, wherein the second conductive layer further includes: a third electrode located on the semiconductor layer and separated from the second electrode, wherein the first electrode , The second electrode and the third electrode respectively constitute a gate, a source and a drain of an active device.
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