TWI712220B

TWI712220B - Trace anywhere interconnect

Info

Publication number: TWI712220B
Application number: TW105121901A
Authority: TW
Inventors: 湯瑪斯Ｐ瓦維克; 德哈南嘉亞圖普塞瑪; 詹姆士Ｖ羅素
Original assignee: 美商Ｒ＆Ｄ電路公司
Priority date: 2015-08-20
Filing date: 2016-07-12
Publication date: 2020-12-01
Also published as: TW201729470A

Abstract

The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side.

Description

無論何處的跡線互連 Wherever the traces are interconnected

本申請案係有關於一種用於產生不受習知的互連技術限制的互連之方法及結構。尤其，本發明係有關於在兩個或多個離散的接觸點之間形成一電互連機構，該些接觸點例如但不限於在兩個或多個平行的電路平面內的電路墊，其中電路係被形成在前述兩個或多個電路平面之間的三維空間中，以便於容許有兩個或多個電性裝置透過該互連裝置的電性耦接。 This application relates to a method and structure for generating interconnections that are not restricted by conventional interconnection technologies. In particular, the present invention relates to forming an electrical interconnection mechanism between two or more discrete contact points, such as but not limited to circuit pads in two or more parallel circuit planes, wherein The circuit is formed in the three-dimensional space between the aforementioned two or more circuit planes so as to allow two or more electrical devices to be electrically coupled through the interconnection device.

習知的互連技術係將藉由導電跡線的電路的繞線限制到x-y平面。這些跡線係接著在z軸上，透過垂直於該些跡線所形成且對準在該些跡線之上的孔洞(貫孔)來加以連接。這些貫孔係接著被塗覆或電鍍一金屬化，其係部分或完全地被填入，此係將該些跡線連接至被形成在該x-y平面之上及之下的電路。 The conventional interconnection technology restricts the winding of the circuit through the conductive trace to the x-y plane. These traces are then connected on the z-axis through holes (through holes) formed perpendicular to the traces and aligned above the traces. The through holes are then coated or plated with a metallization, which is partially or completely filled in, which connects the traces to the circuits formed above and below the x-y plane.

對於這些互連結構而言，在該結構的外部主要的表面的任一側上以及偶爾甚至是在該結構的較小的側或表面上具有一陣列的接觸墊是正常的。這些接觸墊係意謂要和在該些外表面上的電子構件電耦接。當在每一側上有大量的接觸墊或點待被電耦接時，內部的電路層會變成非常密集的，而且需要大量的繞線層。這些層的每一個傳統上係以兩層成對地加以形成，其係被夾設在一介電片的兩側上。這些片係同時加以製造，接著和額外的介電片層一起接合，此係形成多層的結構。貫孔係接著穿過或是部分地穿過這些層堆疊而被形成及金屬化，此係做成所需的z軸互連。在將該些層接合在一起之前，部分或埋入式貫孔可以在每一個層對上加以形成及金屬化。 For these interconnect structures, it is normal to have an array of contact pads on either side of the outer major surface of the structure and occasionally even on the smaller side or surface of the structure. These contact pads are meant to be electrically coupled with electronic components on the outer surface. When there are a large number of contact pads or points to be electrically coupled on each side, the internal circuit layers become very dense, and a large number of winding layers are required. Each of these layers is traditionally added in two layers in pairs In order to form, it is sandwiched on both sides of a dielectric sheet. These sheets are manufactured at the same time and then joined together with additional layers of dielectric sheets to form a multilayer structure. Through holes are then formed and metallized through or partially through these layer stacks, which make the required z-axis interconnections. Before joining the layers together, partial or buried vias can be formed and metallized on each layer pair.

或者是，為了改善繞線密度，介電層以及電路層可以依序彼此堆疊地加以建立，其中盲貫孔只被形成在必要之處。此係消除對於佔據在該x-y平面中的在其中該些貫孔是不重要的層上的繞線空間之穿透貫孔的需求。此種到處貫孔的方法係大為改善繞線密度，但是卻遭受到依序地建構這些層的時間及人工的成本。 Or, in order to improve the winding density, the dielectric layer and the circuit layer can be built up on top of each other in sequence, and the blind through holes are formed only where necessary. This eliminates the need for penetrating through holes occupying the winding space in the x-y plane on the layer where the through holes are not important. This method of perforating everywhere greatly improves the winding density, but it suffers from the time and labor costs of constructing these layers sequentially.

本發明係提供一種其中一電互連機構係被形成之方法及結構，該電互連機構係具有在兩個或多個離散的接觸點之間複雜的連接，該些接觸點例如是但不限於在兩個或多個平行的電路平面之內的電路墊，其中電路係被形成在前述的兩個或多個電路平面之間的三維的空間中。以此種方式，本發明係提供兩個或多個電性裝置透過該互連裝置的電性耦接。 The present invention provides a method and structure in which an electrical interconnection mechanism is formed. The electrical interconnection mechanism has a complex connection between two or more discrete contact points, such as but not It is limited to the circuit pads in two or more parallel circuit planes, where the circuit is formed in the three-dimensional space between the aforementioned two or more circuit planes. In this way, the present invention provides the electrical coupling of two or more electrical devices through the interconnection device.

尤其，本發明係提供一種用於在該兩個或多個平行的電路平面上的離散的點之間形成三維地繞線的介電線之方法及結構。這些線可以被自由地繞線在三維的空間中，以在該兩個或多個平行的電路平面上的兩個任意界定的點之間產生最有效率的繞線。金屬化這些三維的介電線的外表面係電耦接該些離散的線至其個別的離散的接觸點。這些線中的兩個或多個可以是彼此緊密接觸的，此係將彼此電耦接並且電耦接至兩個或多個離散的接觸墊。這些電耦接的接觸墊可以是在該結構的相反側上、或是在相同側上，並且該些形成的金屬化的線可以是源自於一側上並且終止在另一側上、或是源自並且終止於相同側。選配的是，在該些離散的線的金屬化的表面上形成一第二介電質的塗層至一特定的厚度，以便於近似一同軸線。這些經形成且金屬化的介電線可以透過該金屬化製程而被電耦接至該兩個或多個平面上的離散的金屬的電路、或是該些離散的平行的電路可以被形成為該些形成的介電線的一整體的部分，並且接著和該些介電線一起被金屬化。本發明的其它實施例及變化係在以下加以描述。 In particular, the present invention provides a method and structure for forming a three-dimensionally wound dielectric wire between discrete points on the two or more parallel circuit planes. These wires can be wound freely in a three-dimensional space to produce the most efficient winding between two arbitrarily defined points on the two or more parallel circuit planes. The outer surfaces of these three-dimensional dielectric wires are metalized to electrically couple the discrete wires to their individual discrete contact points. Two or more of these lines can be in close contact with each other, this system will be electrically coupled to each other and electrically coupled to two or more Discrete contact pads. The electrically coupled contact pads can be on the opposite side of the structure or on the same side, and the formed metallized lines can originate on one side and terminate on the other side, or It originates from and ends on the same side. What is optional is to form a second dielectric coating to a specific thickness on the metalized surfaces of the discrete wires so as to approximate the coaxial line. The formed and metalized dielectric wires can be electrically coupled to the discrete metal circuits on the two or more planes through the metalization process, or the discrete parallel circuits can be formed as the These are formed as an integral part of the dielectric wires, and then are metalized together with the dielectric wires. Other embodiments and variations of the present invention are described below.

1‧‧‧互連(電互連機構) 1.‧‧Interconnection (electrical interconnection mechanism)

3‧‧‧金屬化(金屬化的介電質) 3‧‧‧Metalization (Metalized Dielectric)

3a‧‧‧第二金屬化的塗層 3a‧‧‧Second metalized coating

3b‧‧‧固體的金屬線 3b‧‧‧Solid metal wire

3c‧‧‧金屬化的塗層 3c‧‧‧Metalized coating

5‧‧‧互連裝置(電互連機構、結構) 5‧‧‧Interconnection device (electrical interconnection mechanism, structure)

6‧‧‧信號線(電路、介電線) 6‧‧‧Signal wire (circuit, dielectric wire)

6a‧‧‧第二介電質的塗層 6a‧‧‧Second dielectric coating

6b‧‧‧介電質的塗層 6b‧‧‧Dielectric coating

7‧‧‧電路平面 7‧‧‧Circuit plane

7a‧‧‧非共面的表面 7a‧‧‧Non-coplanar surface

8‧‧‧電路(電路元件、信號墊、電性裝置) 8‧‧‧Circuits (circuit components, signal pads, electrical devices)

8a‧‧‧接地墊 8a‧‧‧Grounding pad

8c‧‧‧電源墊 8c‧‧‧Power Pad

10‧‧‧接觸點(電路元件) 10‧‧‧Contact points (circuit components)

10a‧‧‧電路墊(接觸墊) 10a‧‧‧Circuit pad (contact pad)

14‧‧‧介電質(填充材料) 14‧‧‧Dielectric (filling material)

15‧‧‧介電壁(平面) 15‧‧‧Dielectric wall (flat)

16‧‧‧剛性主體 16‧‧‧rigid body

17a‧‧‧支架(介電塊) 17a‧‧‧Support (dielectric block)

17b‧‧‧非導電的介電支架 17b‧‧‧Non-conductive dielectric support

19‧‧‧彈性體 19‧‧‧Elastomer

21‧‧‧貫穿 21‧‧‧through

22‧‧‧空氣介電質 22‧‧‧Air dielectric

23‧‧‧電子構件 23‧‧‧Electronic components

24‧‧‧端子點 24‧‧‧Terminal point

25‧‧‧杯形 25‧‧‧Cup

圖1a係展示本發明的一第一實施例的立體圖；圖1b是其中加入構件或電性裝置的圖1a的截面圖；圖2a-2c是圖1a的本發明的三個額外的實施例的截面圖，其係具有用於該些介電線及接觸點之金屬化的外層；圖3a-3d係展示圖1a的介電線的替代實施例；圖4是本發明的另一實施例；圖5a及5b係展示本發明的替代實施例；圖6a-6c係展示本發明的三個額外的實施例；圖7a係展示本發明的另一實施例，其中本發明係具有一被形成在兩個或多個電路平面之間並且被填入一介電質的剛性主體，其中該填充材料係延伸至該些電路元件的頂端；圖7b係展示本發明的另一實施例，其中本發明係具有一被形成在兩個或多個電路平面之間並且被填入一介電質的剛性主體，其中該填充材料係延伸至該些電路元件的底部；圖8是本發明的另一實施例，其中本發明的互連的電路平面中之一係作用為一用於藉由該些形成的線連接的下一個依序堆積的平面之平面；圖9是本發明的另一實施例，其係展示一非共平面的互連；圖10是本發明的另一實施例，其中環氧樹脂支架(scaffolding)係維持在每一個電路元件的X軸與Y軸以及z軸位置上的對準；圖11a是本發明的另一實施例，其中該互連係被設置有一介電質的支架、介電柱或是一介電塊，其係具有用於該些線的穿過的貫穿；圖11b是本發明的另一實施例，其中該互連係被設置有一介電質的支架、介電柱或是一介電塊，其係具有用於該些線的穿過的貫穿，並且其係展示該互連結構當被填入一種彈性體的材料時，具有用於該些線的穿過的貫穿之介電質的支架、介電柱或是一介電塊係提供該互連結構的一固定的壓縮止擋；圖12a、12b及12c係展示本發明的替代實施例，其中：圖12a係展示本發明的非導電的介電支架的格子結構，其係具有突出的電路元件；圖12b係展示本發明的非導電的介電支架的格子結構，其係具有一空氣介電質；圖12c係展示本發明的非導電的介電支架的格子結構，其係具有齊平的電路元件；圖13係展示本發明的另一實施例，其係用於將一例如但不限於一電阻器、電容器或電感器的電子構件23的兩個或多個端子點附加及電耦接至該些形成的線以及該些對應的平面7之對應的電路元件10，其中每一個點將耦接至其在該互連結構中之對應指定的電源、接地、或是信號線6及/或電路元件10。 Fig. 1a is a perspective view showing a first embodiment of the present invention; Fig. 1b is a cross-sectional view of Fig. 1a in which components or electrical devices are added; Figs. 2a-2c are three additional embodiments of the present invention of Fig. 1a A cross-sectional view with a metalized outer layer for the dielectric wires and contact points; Figures 3a-3d show alternative embodiments of the dielectric wires of Figure 1a; Figure 4 is another embodiment of the invention; Figure 5a And 5b show alternative embodiments of the present invention; Figures 6a-6c show three additional embodiments of the present invention; Figure 7a shows another embodiment of the present invention, in which the present invention has one formed in two Or between multiple circuit planes and filled with a dielectric rigid body, wherein the filling material extends to the top of the circuit elements; FIG. 7b shows another embodiment of the present invention, wherein the present invention has One is formed in two Or between multiple circuit planes and filled with a dielectric rigid body, wherein the filling material extends to the bottom of the circuit elements; FIG. 8 is another embodiment of the present invention, wherein the interconnection of the present invention One of the circuit planes is used as a plane for the next sequentially stacked planes connected by the lines formed; Figure 9 is another embodiment of the present invention, which shows a non-coplanar Interconnection; Figure 10 is another embodiment of the present invention, in which the epoxy scaffolding (scaffolding) is maintained in the alignment of the X-axis, Y-axis and z-axis position of each circuit element; Figure 11a is the present invention In another embodiment, the interconnection system is provided with a dielectric support, a dielectric pillar, or a dielectric block, which has penetrations for the passage of the wires; Figure 11b is another embodiment of the present invention For example, the interconnection system is provided with a dielectric support, a dielectric pillar, or a dielectric block, which has penetrations for the passage of the lines, and it shows that the interconnection structure is filled in When an elastomeric material is used, there is a dielectric support, a dielectric column or a dielectric block for the penetration of the wires to provide a fixed compression stop for the interconnection structure; Figure 12a, 12b and 12c show alternative embodiments of the present invention, in which: Figure 12a shows the grid structure of the non-conductive dielectric support of the present invention, which has protruding circuit elements; Figure 12b shows the non-conductive dielectric of the present invention The lattice structure of the electric support, which has an air dielectric; Figure 12c shows the lattice structure of the non-conductive dielectric support of the present invention, which has flush circuit elements; Figure 13 shows another of the present invention Embodiment, which is used to connect a resistor such as but not limited to Two or more terminal points of the electronic component 23 of the device, capacitor or inductor are attached and electrically coupled to the formed lines and the corresponding circuit elements 10 of the corresponding planes 7, each of which will be coupled to It corresponds to the designated power, ground, or signal line 6 and/or circuit element 10 in the interconnect structure.

圖14是本發明的另一實施例，其中該些線6係延伸超出該互連1的剛性主體，其係具有有助於彎曲的彈簧形狀，例如但不限於線圈、懸臂、S形，其係具有有助於接觸各種形狀的電性裝置的端點，其例如是但不限於尖點、冠狀尖端或是杯形，其係作用為耦接兩個非共面的電性裝置的一柔性的互連。 Figure 14 is another embodiment of the present invention, in which the wires 6 extend beyond the rigid body of the interconnection 1, which has a spring shape that facilitates bending, such as but not limited to coils, cantilevers, S-shaped, and It has an end point that facilitates contact with various shapes of electrical devices, such as but not limited to a sharp point, a crown tip, or a cup shape, which acts as a flexible coupling between two non-coplanar electrical devices Interconnection.

現在參照圖1a-14的圖式，圖1a係展示本發明的一第一實施例，其中一電互連機構5係形成在兩個或多個平行的電路平面7之內的兩個或多個離散的接觸點10(其例如但不限於電路墊10a(圖1b)、或是如同在圖3a-3d中所示的離散的平行的電路8、以及如同在圖4及圖13中所示的信號墊8、電源墊8c及接地墊8a，其係類似於如同在圖1b中所示的離散的電路元件8以及電路墊10a)之間的複雜的連接，其中電路6係被形成在前述的兩個或多個電路平面7之間的三維的空間中，以便於透過該互連裝置5來提供圖1b的兩個或多個電性裝置8的電性耦接。 Referring now to the drawings of Figs. 1a-14, Fig. 1a shows a first embodiment of the present invention, in which an electrical interconnection mechanism 5 is formed in two or more parallel circuit planes 7 Discrete contact points 10 (such as but not limited to circuit pads 10a (FIG. 1b), or discrete parallel circuits 8 as shown in FIGS. 3a-3d, and as shown in FIGS. 4 and 13 The signal pad 8, the power pad 8c and the ground pad 8a are similar to the complex connection between the discrete circuit elements 8 and the circuit pad 10a) as shown in Figure 1b, in which the circuit 6 is formed in the aforementioned In the three-dimensional space between the two or more circuit planes 7 in order to provide the electrical coupling of the two or more electrical devices 8 of FIG. 1b through the interconnection device 5.

如同在圖1a中所示，三維繞線的介電線6係被形成在該兩個或多個平行的電路平面7上的離散的點10之間。這些線6可以在三維的空間中被自由地繞線，以在該兩個或多個平行的電路平面7上的兩個任意界定的點10之間產生最有效率的繞線。 As shown in FIG. 1a, three-dimensionally wound dielectric wires 6 are formed between discrete points 10 on the two or more parallel circuit planes 7. These wires 6 can be wound freely in a three-dimensional space to produce the most efficient winding between two arbitrarily defined points 10 on the two or more parallel circuit planes 7.

在將該些離散的線6電耦接至其個別的離散的接觸點10之前，這些三維的介電線6的外表面應該被金屬化3(參見圖2)。選配的是，該些三維的介電線6(圖2)可以是具有一選配的介電質的塗層6b(圖6b)以及一在該介電質上的選配的金屬化的塗層3c(圖6c)之固體的金屬線3b(圖6a)、或者可以是具有一第二介電質的塗層6a(圖3c)的一金屬化的介電質3(圖3d)、或是亦可包含一第二介電質的塗層6a(圖3b)以及一第二金屬化的塗層3a(圖3b)。這些線6中的兩個或多個(圖2c)可被設置成彼此緊密接觸的，其係將彼此以及兩個或多個離散的接觸墊10a(圖2c)電耦接。這些電耦接的接觸墊10a可以是在該結構5(圖1a)的相反側上(圖2a)、或是在相同側上(圖2b)。選配的是，一第二介電質的塗層6a可被形成在該些離散的線6的金屬化的表面上至一特定的厚度，以便於近似一同軸線(參見圖3a-3b)。這些經形成且金屬化的介電線可以如同在(圖3c)中的透過該金屬化製程而被電耦接至在該兩個或多個平面7上的離散的金屬的電路、或者是該些離散的平行的電路8(圖3d)可被形成為該些形成的介電線6的一整體的部分，並且接著和該些介電線6一起被金屬化(參見圖3d)。 Before electrically coupling the discrete wires 6 to their individual discrete contact points 10, the outer surfaces of the three-dimensional dielectric wires 6 should be metalized 3 (see FIG. 2). Optionally, the three-dimensional dielectric wires 6 (Figure 2) can have an optional dielectric coating 6b (Figure 6b) and an optional metalized coating on the dielectric. The solid metal wire 3b (Figure 6a) of layer 3c (Figure 6c), or a metallized dielectric 3 (Figure 3d) with a second dielectric coating 6a (Figure 3c), or It can also include a second dielectric coating 6a (Figure 3b) and a second metalized coating 3a (Figure 3b). Two or more of these wires 6 (FIG. 2c) can be arranged in close contact with each other, which electrically couple each other and two or more discrete contact pads 10a (FIG. 2c). The electrically coupled contact pads 10a can be on the opposite side of the structure 5 (Figure 1a) (Figure 2a), or on the same side (Figure 2b). Optionally, a second dielectric coating 6a can be formed on the metalized surface of the discrete wires 6 to a specific thickness so as to approximate the coaxial line (see FIGS. 3a-3b). These formed and metallized dielectric wires can be electrically coupled to discrete metal circuits on the two or more planes 7 through the metallization process as in (Figure 3c), or these Discrete parallel circuits 8 (Figure 3d) can be formed as an integral part of the formed dielectric wires 6, and then metalized together with the dielectric wires 6 (see Figure 3d).

在針對於該些線6的選配地形成的第二介電質的塗層6a及金屬化3a的實施例中，在該些塗覆後的線6上的第二金屬化3a係被限制為剛好不夠接觸到在任一平面7上的離散的電路元件(圖3a)。此金屬化應該從該些離散的電路元件凹陷在1μm至50μm的範圍中(見於本發明的圖3a的實施例)。 In the embodiment of the second dielectric coating 6a and metallization 3a formed selectively for the wires 6, the second metallization 3a on the coated wires 6 is limited It is just not enough to touch the discrete circuit elements on any plane 7 (Figure 3a). This metallization should be recessed from the discrete circuit elements in the range of 1 μm to 50 μm (see the embodiment of FIG. 3a of the present invention).

在本發明的另一實施例中，在該些形成的介電線上的第二金屬化塗層及/或第二介電層係和彼此緊密接觸，其係將該外部的金屬化彼此電耦接，並且耦接至在該些外表面電路平面上的一或多個點。此將會具有提供接地屏蔽及/或同軸線的效果(參見圖4)。 In another embodiment of the present invention, the second metallization coating and/or the second dielectric layer on the formed dielectric wires are in close contact with each other, and the external metallizations are in close contact with each other. Electrically coupled, and coupled to one or more points on the outer surface circuit plane. This will have the effect of providing ground shielding and/or coaxial lines (see Figure 4).

替代被形成在該些離散的電路線6的周圍的接地屏蔽的是，一介電壁15或是平面15可以替代地在該結構中，在該z軸上或是垂直地加以形成，被轉置(transposed)在該些外表面電路平面7之間，在端點是電耦接至一或兩個平面上的離散的電路圖案8、8a(圖5a)下被金屬化。將這些垂直的平面連結到接地8a將會提供相鄰繞線的電路線的屏蔽、以及控制這些線的阻抗的能力，即如同在圖5a及5b中所示者。 Instead of the ground shield formed around the discrete circuit lines 6, a dielectric wall 15 or a flat surface 15 may alternatively be formed in the structure on the z-axis or vertically, and be turned Transposed between the outer surface circuit planes 7, the ends are electrically coupled to discrete circuit patterns 8, 8a (FIG. 5a) on one or two planes, and are metalized. Connecting these vertical planes to ground 8a will provide shielding of adjacent winding circuit wires and the ability to control the impedance of these wires, as shown in Figures 5a and 5b.

圖7a及7b係展示兩個實施例，其中一剛性主體16係被形成在這兩個或多個電路平面7之間，其係藉由利用一例如但不限於環氧樹脂的介電質14來填入在該些平面之間的區域。此填充材料14可以延伸至該電路元件的底部(參見圖7b)，此係使得該元件是在該填充介電質之上的、或是其可以延伸至該電路元件的頂端(參見圖7a)，此係使得該元件與該填充材料齊平的。 Figures 7a and 7b show two embodiments, in which a rigid body 16 is formed between the two or more circuit planes 7 by using a dielectric material 14 such as but not limited to epoxy resin. To fill in the area between these planes. The filling material 14 can extend to the bottom of the circuit element (see Figure 7b), which makes the element on the filling dielectric or it can extend to the top of the circuit element (see Figure 7a) This system makes the component flush with the filling material.

重覆先前敘述的實施例之先前敘述的製程中的一或多個，其中先前形成的互連1的電路平面7中之一是作用為用於藉由這些形成的線6連接的下一個依序形成的堆積的電路平面7的平面中之一(參見圖8的實施例)。 Repeat one or more of the previously described process of the previously described embodiment, wherein one of the circuit planes 7 of the previously formed interconnection 1 is used for the next connection of the wires 6 formed by these One of the planes of the stacked circuit plane 7 formed sequentially (see the embodiment of FIG. 8).

圖9是展示本發明的另一實施例，其中並非是利用例如是環氧樹脂14的剛性材料來填充前述的互連機構1，而是該互連結構1係被填入一種例如是彈性體19的柔性材料，以維持該些三維的線6以及電路端點至其所要的位置的對準，並且容許有z軸的柔性，以便於容許兩個打算藉由該電互連機構1耦接的非共面的表面7a的電性耦接。 FIG. 9 shows another embodiment of the present invention. Instead of using a rigid material such as epoxy resin 14 to fill the aforementioned interconnection mechanism 1, the interconnection structure 1 is filled with an elastomer, for example. 19 flexible materials to maintain the alignment of the three-dimensional lines 6 and the circuit endpoints to their desired positions, and allow z-axis flexibility, so as to allow two plans to borrow The non-coplanar surfaces 7a coupled by the electrical interconnection mechanism 1 are electrically coupled.

圖10係展示本發明的另一實施例，其中並非是利用一環氧樹脂來填充該互連機構的整個內部的區域，而是利用最小的例如是一環氧樹脂的材料量來形成一支架17a，其係緊密接觸在該些平面的每一個上的電路元件的每一個，被轉置在兩個電路平面之間，其係維持在每一個平面之間的z軸間隔以及該些電路元件的每一個的x-y位置。此支架結構將會提供該互連1一種剛性結構，同時將空氣維持在該些形成的電路線的周圍。 FIG. 10 shows another embodiment of the present invention, in which instead of using an epoxy resin to fill the entire internal area of the interconnection mechanism, a minimum amount of material such as an epoxy resin is used to form a bracket 17a, each of the circuit elements in close contact with each of these planes is transposed between two circuit planes, and it is maintained at the z-axis interval between each plane and the circuit elements The xy position of each of them. This support structure will provide a rigid structure for the interconnect 1 while maintaining air around the formed circuit lines.

圖11a係展示本發明的另一實施例，其中一介電質的支架、介電柱或是一固體的介電塊17a是在該互連的周圍。圖11b係展示本發明的一類似的實施例，但是其係具有被設置以允許該些線6的進入的貫穿21之介電質的支架、介電柱或是一固體的介電塊。當結合一填充彈性體的材料而被使用時，該介電結構係提供該互連結構1的一固定的壓縮止擋，以避免由於過度壓縮而損壞到該些線6(圖11b)。 FIG. 11a shows another embodiment of the present invention, in which a dielectric support, a dielectric pillar, or a solid dielectric block 17a is around the interconnection. Fig. 11b shows a similar embodiment of the present invention, but with a dielectric support, a dielectric pillar, or a solid dielectric block through 21 that is configured to allow the entry of the wires 6. When used in combination with an elastomer-filled material, the dielectric structure provides a fixed compression stop for the interconnect structure 1 to avoid damage to the wires 6 due to excessive compression (Figure 11b).

設計該些三維地形成的前述的線的自由流動，以具有例如但不限於線圈、懸臂及S形的形狀，以提供類似彈簧的特徵以容許有該些線的柔性，同時抵抗在該金屬及/或介電質中的應力破裂(參見圖1a)。 The free flow of the aforementioned three-dimensionally formed wires is designed to have shapes such as but not limited to coils, cantilevers and S-shapes to provide spring-like features to allow the flexibility of these wires while resisting the metal and / Or stress cracks in the dielectric (see Figure 1a).

圖12a係展示本發明的另一實施例，其中被轉置在該兩個電路平面7之間的非導電的介電支架17b的一格子結構係被設置，該格子結構係緊密接觸在該些電路平面7之內的電路元件，其係提供該些個別的接觸點或電路元件10在該些電路平面7之內的對準，並且提供剛性給整個結構1、或是容許有該整個結構在該z軸上的一些柔性，同時其亦選配地容許空氣介電質22在前述的線的周圍(參見圖12b)。圖12a係展示具有電路元件在該介電質之上的實施例，並且圖12c係展示具有齊平的電路元件之實施例。該支架可以是具有機械工程技術中已知的不同的結構，以提供上述所要的性質。 Fig. 12a shows another embodiment of the present invention, in which a lattice structure of the non-conductive dielectric support 17b transposed between the two circuit planes 7 is arranged, and the lattice structure is in close contact with the The circuit elements within the circuit plane 7 provide the individual contact points or the alignment of the circuit elements 10 within the circuit planes 7, and provide rigidity to the entire structure 1, or allow the entire structure to be in There is some flexibility on the z-axis, and it also optionally allows the air dielectric 22 to surround the aforementioned line (see Figure 12b). Figure 12a shows the circuit components in The embodiment above the dielectric, and Figure 12c shows an embodiment with flush circuit elements. The bracket may have different structures known in mechanical engineering technology to provide the desired properties described above.

圖13係展示將一例如但不限於一電阻器、電容器或電感器的電子構件23的兩個或多個端子點24附加及電耦接至該些形成的線以及該些對應的平面7之對應的電路元件。每一個點係耦接至其在該互連結構1中之對應指定的電源、接地、或是信號線6及/或電路元件10。以此種方式，電容、電阻、電感、或是任何其它的電子功能係被提供至該互連1所欲耦接到的電性裝置的點(見於圖13)。 FIG. 13 shows the attachment and electrical coupling of two or more terminal points 24 of an electronic component 23 such as, but not limited to, a resistor, capacitor, or inductor to the formed lines and the corresponding planes 7 Corresponding circuit components. Each point is coupled to its corresponding designated power, ground, or signal line 6 and/or circuit element 10 in the interconnect structure 1. In this way, capacitance, resistance, inductance, or any other electronic function is provided to the point of the electrical device to which the interconnect 1 is to be coupled (see FIG. 13).

圖14係展示本發明的另一實施例，其中該些線6係延伸超出該互連1的剛性主體，其係具有例如但不限於線圈、懸臂及S形的形狀，以提供類似彈簧的特徵以容許有該些線的柔性，同時抵抗在該金屬及/或介電質中的應力破裂、以及有助於接觸各種形狀的電性裝置的端點，其例如是但不限於尖點、冠狀尖端或是杯形25，其係作用為耦接兩個非共面的電性裝置的一柔性的互連。其係提供在一整合的結構中的間距轉換及接腳重新對映、以及柔性的探測之能力。 Fig. 14 shows another embodiment of the present invention, in which the wires 6 extend beyond the rigid body of the interconnect 1, which has shapes such as but not limited to coils, cantilevers and S-shaped to provide spring-like features In order to allow the flexibility of these lines, while resisting the stress cracking in the metal and/or dielectric, and helping to contact the endpoints of various shapes of electrical devices, such as but not limited to sharp points, crowns The tip or cup 25 serves as a flexible interconnect for coupling two non-coplanar electrical devices. It provides the ability of pitch conversion and pin remapping, and flexible detection in an integrated structure.

再者，本發明的前述實施例的每一個都可以利用一或多個矽晶圓IC來加以建構，此係產生相互連接該兩個或多個IC的多晶片模組，其中一矽層是該基底電路平面。 Furthermore, each of the foregoing embodiments of the present invention can be constructed using one or more silicon wafer ICs, which generates a multi-chip module interconnecting the two or more ICs, in which a silicon layer is The substrate circuit plane.

再者，本發明的前述實施例的每一個都可以利用一或多個矽晶圓IC來加以建構，此係產生用於該IC的重分佈封裝。 Furthermore, each of the foregoing embodiments of the present invention can be constructed using one or more silicon wafer ICs, which creates a redistribution package for the IC.

再者，本發明的前述實施例的每一個都可以被建構在一撓性的電路基底上。 Furthermore, each of the foregoing embodiments of the present invention can be constructed in a flexible On the circuit substrate.

用於上述實施例的結構之方法係如下：在本發明的一種具有介電核心線的無論何處的跡線之互連的情形中，開始點是具有一平坦載體的玻璃、陶瓷、或是某種其它平滑且平坦的材料，例如是但不限於平滑的金屬塊。接著，吾人應該利用一種例如但不限於黏著劑或蠟的適當的接合材料來暫時接合一片較佳的是Cu的金屬箔至該平坦的材料載體，以保持該Cu為平坦的。此箔的厚度應該是在10μm到35μm的範圍中，但是並不限於該範圍。接著，在該Cu箔的頂端上，利用在此項技術中已知的市售的3D列印技術，以形成附接至該Cu箔的介電線，其係從在該箔上的預設的位置，在該z軸上生長到在自由空間中的預設的位置。該箔可以透過微蝕刻的電漿或是此項技術中已知的其它的表面處理來加以處理，以提升該些介電線的黏著。這些線在直徑上通常將會是在1μm到50μm的範圍中。這些線將會被建構到高於所計畫的互連機構的通常從100μm到0.200"厚的整體高度一大約25μm到100μm的z軸高度。 The method used for the structure of the above embodiment is as follows: In the case of the interconnection of traces anywhere with a dielectric core line according to the present invention, the starting point is glass, ceramic, or glass with a flat carrier Some other smooth and flat material, such as but not limited to a smooth metal block. Next, we should use a suitable bonding material such as but not limited to adhesive or wax to temporarily bond a piece of metal foil, preferably Cu, to the flat material carrier to keep the Cu flat. The thickness of this foil should be in the range of 10 μm to 35 μm, but is not limited to this range. Then, on the top of the Cu foil, a commercially available 3D printing technology known in the art is used to form a dielectric wire attached to the Cu foil, which is derived from a preset on the foil The position, which grows to a preset position in free space on the z-axis. The foil can be treated with micro-etched plasma or other surface treatments known in the art to improve the adhesion of the dielectric wires. These wires will generally be in the range of 1 μm to 50 μm in diameter. These lines will be constructed to a z-axis height of approximately 25 μm to 100 μm higher than the overall height of the planned interconnection mechanism, which is usually from 100 μm to 0.200" thick.

接著，從該Cu片延伸的自由形成的線係利用電鍍、無電的電鍍、化學氣相沉積、濺鍍塗覆、或是此項技術中已知的任何其它技術而被金屬化。此金屬化的厚度通常將會是在1μm到25μm的範圍中。此金屬化實際上將會塗覆該些介電線以及該基底箔的露出的表面區域，此係使得該基底箔以及該些經塗覆的線變成電耦接的。 Then, the freely formed wires extending from the Cu sheet are metalized by electroplating, electroless electroplating, chemical vapor deposition, sputtering coating, or any other technique known in the art. The thickness of this metallization will generally be in the range of 1 μm to 25 μm. This metallization will actually coat the dielectric wires and the exposed surface area of the base foil, which makes the base foil and the coated wires electrically coupled.

選配的是，該些金屬化的介電線可以經由一浸漬操作、矽化學氣相沉積(SCVD)、二氧化矽脈衝層沉積(PLD)、二氧化鈦原子層沉積(ALD)、或是此項技術中已知的其它技術，而被再次塗覆一介電質。在此製程期間，該基底箔金屬化的頂端側也可被塗覆，此係將其與進一步的製程電性隔離。 Optionally, these metalized dielectric wires can be subjected to a dipping operation, silicon chemical vapor deposition (SCVD), silicon dioxide pulsed layer deposition (PLD), titanium dioxide atomic layer deposition (ALD), or this technology Other techniques known in, and are again coated with a dielectric. In this system During the process, the metalized top side of the base foil can also be coated, which electrically isolates it from further processes.

該些塗覆後的線係接著(選配地)經由先前敘述的技術而被金屬化。此金屬化將會有將該些形成的線的全部表面短路在一起的效果。將此金屬化連結到一或多個接地線或是外部的電路層實際上係產生用於所有的線的接地屏蔽，並且近似用於所有的信號線的同軸線。耦接此接地的金屬化可以在該互連最終耦接兩個或多個電子裝置時，透過從被設計來接地的線或是基底銅的區域，經由雷射剝蝕、研磨或是此項技術中已知的某種其它技術來選擇性的移除外部的介電質塗層而被達成。 The coated wires are then (optionally) metalized using the technique described previously. This metallization will have the effect of short-circuiting all the surfaces of the lines formed. Connecting this metallization to one or more ground wires or external circuit layers actually creates a ground shield for all wires and approximately coaxial wires for all signal wires. The metallization of the coupling to the ground can be achieved by laser ablation, grinding, or this technology when the interconnect is finally coupled to two or more electronic devices, from the wire or the area of the substrate copper that is designed to be grounded Some other technology is known in the paper to selectively remove the external dielectric coating.

既然該些線在具有或是不具有一第二介電質以及第二金屬化下加以形成，該結構可以經由一模製操作(此項技術中通常已知的)而被填入一例如但不限於環氧樹脂的介電質，其係將該環氧樹脂固化成為一剛性基板。將會最佳的是將該環氧樹脂包覆模製超出該些形成的線的頂端端點約25μm-100μm。此係允許有用於一種經由研磨、砂磨、研光、或是在此項技術中已知的其它技術的平坦化製程之足夠的材料。 Since the lines are formed with or without a second dielectric substance and a second metallization, the structure can be filled with an example of but not limited by a molding operation (commonly known in the art). It is not limited to the dielectric material of epoxy resin, and it cures the epoxy resin into a rigid substrate. It would be best to overmold the epoxy resin by about 25 μm-100 μm beyond the top end of the formed lines. This system allows sufficient materials to be used in a planarization process by grinding, sanding, polishing, or other techniques known in the art.

在該些線具有一第二介電質以及第二金屬化的實施例中，該些線的頂端尖端可被塗覆一例如是蠟或是一臨時的聚合物之臨時的塗層，以避免金屬化(通常)在該第二介電層上形成最後的25μm到100μm。 In the embodiments where the wires have a second dielectric and a second metallization, the top tips of the wires can be coated with a temporary coating such as wax or a temporary polymer to avoid Metallization (usually) forms the final 25 μm to 100 μm on this second dielectric layer.

平坦化亦露出該些金屬化的線的頂端，此係提供在將一第二電路層電耦接至該些線以及該基底箔時，建構該電路層的機會。若該些塗覆後的線的尖端已經免於次要的金屬化，則仔細地控制該互連基板的在該z軸上的平坦化將會露出該形成的線的第一金屬化的層，此係在不耦接該形成的線的前述選配的第二金屬化至該第二電路平面層之下，將其露出以電耦接至前述第二電路平面的形成。 The planarization also exposes the tops of the metalized lines, which provides an opportunity to construct the circuit layer when electrically coupling a second circuit layer to the lines and the base foil. If the tips of the coated wires are already free from secondary metallization, careful control of the planarization of the interconnect substrate on the z-axis will expose the first metallized layer of the formed wire , This is not coupled to the shape The aforementioned optional second metallization of the formed line is under the second circuit plane layer and exposed to be electrically coupled to the formation of the aforementioned second circuit plane.

前述的第二電路平面層接著可以經由無電的電鍍、化學氣相沉積、濺鍍塗覆、電鍍、或是此項技術中已知的任何其它技術來加以形成。此導電的金屬化較佳的是Cu、Au或是任何其它適當的導電材料、及/或多層不同的材料。 The aforementioned second circuit plane layer can then be formed by electroless plating, chemical vapor deposition, sputtering coating, electroplating, or any other technique known in the art. The conductive metallization is preferably Cu, Au or any other suitable conductive material, and/or multiple layers of different materials.

在將該互連從該平滑的基板抬起之後，該主要的底部金屬層以及該次要的頂端層現在可以透過此項技術中已知的一傳統的微影蝕刻製程，而被形成為離散的電路。透過此電路化製程所形成的接觸點或墊可以額外被電鍍適當的金屬的合金，以用於例如但不限於抗磨損或是可焊性之所要的應用。 After lifting the interconnect from the smooth substrate, the primary bottom metal layer and the secondary top layer can now be formed as discrete layers through a conventional lithographic etching process known in the art Circuit. The contact points or pads formed through the circuitization process can be additionally electroplated with appropriate metal alloys for applications such as but not limited to anti-wear or solderability.

或者是，替代在前述線中的一介電核心的是，一金屬核心可以透過負型3D列印技術的使用來加以取代，其係利用(但不限於)此項技術中已知的負型工作的光敏的環氧樹脂，藉此除了其中該核心線金屬化將被形成之處以外，一臨時的介電質係被形成到該互連的整個主動區域。接著，該金屬化係透過電鍍、無電的電鍍、化學氣相沉積、濺鍍塗覆或是此項技術中已知的其它技術而被形成，以形成一固體的金屬的線結構。或者是，具有變化的厚度之各種的金屬可被形成在該環氧樹脂層內的中空的結構的內壁上，此係提供所期望的電性及機械性質給終端的應用。接著，該臨時的環氧樹脂係透過此項技術中已知的剝除技術而被移除，並且獨立式的金屬的線或管係留下以用於上述後續的處理。 Alternatively, instead of a dielectric core in the aforementioned line, a metal core can be replaced by the use of negative 3D printing technology, which uses (but is not limited to) the known negative type in this technology. The working photosensitive epoxy resin, whereby a temporary dielectric is formed to the entire active area of the interconnection except where the core wire metallization will be formed. Then, the metallization is formed by electroplating, electroless electroplating, chemical vapor deposition, sputtering coating, or other techniques known in the art to form a solid metal line structure. Alternatively, various metals with varying thicknesses can be formed on the inner wall of the hollow structure in the epoxy resin layer, which provides the desired electrical and mechanical properties for terminal applications. Then, the temporary epoxy resin is removed through the peeling technique known in the art, and the free-standing metal wire or tube is left for the above-mentioned subsequent processing.

或者是，具有或是不具有額外的介電質及金屬化的層以用於屏蔽或是同軸貫孔之介電核心的、金屬核心的、或是金屬的管可以透過電鍍、無電的電鍍、化學氣相沉積、濺鍍塗覆、或是任何此項技術中已知的其它技術，而被形成於預先被形成在該平滑的玻璃或平滑的陶瓷或是其它適當的材料上的離散的金屬墊或電路上。使得其尺寸是透過在此項技術中常見的一臨時的微影製程來加以界定的。再者，這些墊或是電路可以利用一雷射製版製程而被形成，藉此一金屬的箔係利用一黏著劑或蠟而被臨時黏著至該平滑且平坦的基底材料，並且前述用於線的形成的技術可以建構在該離散的墊或是電路的頂端上。 Or, with or without additional dielectric and metallized layers for Shielding or coaxial through-hole dielectric core, metal core, or metal tube can be through electroplating, electroless plating, chemical vapor deposition, sputtering coating, or any other known in the art Technology, and is formed on discrete metal pads or circuits previously formed on the smooth glass or smooth ceramic or other suitable materials. The size is defined by a temporary lithography process commonly used in this technology. Furthermore, these pads or circuits can be formed using a laser plate making process, whereby a metal foil is temporarily adhered to the smooth and flat base material using an adhesive or wax, and the aforementioned is used for wire The formation technology can be built on the discrete pad or the top of the circuit.

再者，當該些形成的線的端點被形成時，具有變化的幾何形狀之離散的墊及/或電路可以根據該互連之所要的應用而被形成。具有變化的形狀以用於接觸電性端子之可焊的墊或是接腳可以是如同先前所敘述地加以形成且金屬化。該些形成的線的端點在一步驟中的此種形成以及金屬化係節省額外的處理時間，並且結合該些離散的墊在該基底金屬層上的形成係提供一旦前述的環氧樹脂模製製程完成後，在該互連的兩端上有齊平的電路墊的機會。 Furthermore, when the end points of the formed lines are formed, discrete pads and/or circuits with varying geometric shapes can be formed according to the desired application of the interconnection. The solderable pads or pins with varying shapes for contacting the electrical terminals can be formed and metalized as previously described. The formation and metallization of the end points of the formed lines in one step saves extra processing time, and the formation of the discrete pads on the base metal layer provides the epoxy resin mold After the manufacturing process is completed, there is an opportunity for flush circuit pads on both ends of the interconnection.

或者是，在上述的實施例的任一個中，一彈性體或橡膠化合物灌封(potting)材料可以取代一剛性灌封化合物，此係提供該些互連端子柔性以用於配接非共面的電子元件的表面。藉由改變該灌封材料的硬度以及該些形成的線材料、厚度、長度及形狀，吾人可以控制該些形成的線配接端子的每一個的總柔性量、力以及壽命。 Alternatively, in any of the above embodiments, an elastomer or rubber compound potting material can replace a rigid potting compound, which provides the flexibility of the interconnect terminals for mating non-coplanar The surface of the electronic components. By changing the hardness of the potting material and the formed wire material, thickness, length and shape, we can control the total flexibility, force and life span of each of the formed wire mating terminals.

或者是，在一種前述的柔性互連的情形中，一具有一種例如但不限於環氧樹脂的適當硬的材料的格子結構、柱、或是一固體的塊可被形成在該互連未被該些形成的線或是柔性的灌封材料所佔據的開放空間內。這些結構可以透過相同的3D列印技術，而被形成在該互連主體的開放空間中，其係具有一高度是稍微薄於該互連的整體厚度(~10μm到200μm)，其係提供該互連結構一種硬的壓縮止擋，以對抗打算電耦接的裝置之兩個配接的表面。此將會避免該互連結構的過度壓縮及損壞。 Or, in the case of the aforementioned flexible interconnection, a lattice structure, pillars, or a solid block of a suitably hard material such as but not limited to epoxy resin can be used The interconnection is formed in an open space not occupied by the formed lines or flexible potting materials. These structures can be formed in the open space of the interconnect body through the same 3D printing technology, which has a height slightly thinner than the overall thickness of the interconnect (~10μm to 200μm), which provides the The interconnect structure is a hard compression stop to counter the two mating surfaces of the device intended to be electrically coupled. This will avoid excessive compression and damage to the interconnect structure.

儘管目前較佳的實施例已經為了本揭露內容的目的來加以敘述，但是熟習此項技術者可以在方法步驟以及設備部件的配置上做成許多的改變。此種改變係被涵括在如同藉由所附的申請專利範圍所界定的本發明的精神內。 Although the current preferred embodiments have been described for the purpose of this disclosure, those skilled in the art can make many changes in the method steps and the configuration of the equipment components. Such changes are included in the spirit of the present invention as defined by the scope of the attached patent application.

7‧‧‧電路平面 7‧‧‧Circuit plane

Claims

一種用於形成一電互連機構之方法，其係包括：在兩個或多個電路平面之內設置兩個或多個例如但不限於電路墊之離散的接觸點；以及利用三維的介電線以自由地繞線在該兩個或多個電路平面上的該些離散的點之間，該些離散的點定位為沿著該兩個或多個電路平面中每一者的任一側的無論何處，以便於透過該互連機構來提供兩個或多個電性裝置的電性耦接，以及提供該些線的自由繞線，該些介電線係具有一導電的塗層並且該些離散的點包含接觸墊，以及該兩個或多個線被設置成緊密接觸該些電極中的每一者，以將彼此耦接並且耦接至該些離散的接觸墊中的兩個或多個。 A method for forming an electrical interconnection mechanism, which includes: arranging two or more discrete contact points such as but not limited to circuit pads within two or more circuit planes; and using three-dimensional dielectric wires To freely wind between the discrete points on the two or more circuit planes, the discrete points are positioned along either side of each of the two or more circuit planes Wherever possible, in order to provide the electrical coupling of two or more electrical devices through the interconnection mechanism and provide free winding of the wires, the dielectric wires have a conductive coating and the The discrete points include contact pads, and the two or more wires are arranged to closely contact each of the electrodes to couple each other and to two or more of the discrete contact pads. Multiple.

根據申請專利範圍第1項之方法，其中該些電路平面係實質平行於彼此的。 According to the method of item 1 of the scope of patent application, the circuit planes are substantially parallel to each other.

根據申請專利範圍第1項之方法，其進一步包括利用任意有機或無機的導電材料來金屬化該些介電線的外表面，其係電性耦接至其之個別的離散的接觸點。 According to the method of item 1 of the scope of the patent application, it further comprises using any organic or inorganic conductive material to metalize the outer surface of the dielectric wires, which are electrically coupled to their individual discrete contact points.

根據申請專利範圍第3項之方法，其中該導電材料是銅、銀、金、或是導電的聚合物。 According to the method of item 3 of the scope of patent application, the conductive material is copper, silver, gold, or a conductive polymer.

根據申請專利範圍第1項之方法，其中該些電耦接的接觸墊可以是在該結構的相反側上、或是在一相同側上，並且該些形成的金屬化的線可以源自於一側上並且終止在另一側上、或是源自並且終止於相同側。 According to the method of claim 1, wherein the electrically coupled contact pads can be on the opposite side of the structure or on the same side, and the formed metalized lines can be derived from On one side and terminate on the other side, or originate and terminate on the same side.

根據申請專利範圍第1項之方法，其中一第二介電質的塗層係被形成在該些離散的線的金屬化的表面上，以近似一同軸線。 According to the method described in item 1 of the scope of patent application, a second dielectric coating is formed On the metalized surface of the discrete lines, they are approximately coaxial.

根據申請專利範圍第1項之方法，其中該些經形成且金屬化的介電線係透過該金屬化製程來電耦接至該兩個或多個平面上的離散的金屬的電路、或是該些離散的平行的電路係被形成為該些形成的介電線的一整體的部分，並且接著和該些介電線一起被金屬化。 According to the method of claim 1, wherein the formed and metallized dielectric wires are electrically coupled to the discrete metal circuits on the two or more planes through the metallization process, or the Discrete parallel circuits are formed as an integral part of the formed dielectric wires and then metalized together with the dielectric wires.

根據申請專利範圍第6項之方法，其中該些線的該形成的第二介電質的塗層以及金屬化，在該塗覆後的線上的該第二金屬化係被限制於剛好不足以接觸在該些平面的任一個上的該些離散的電路元件。 According to the method of item 6 of the scope of patent application, wherein the formed second dielectric coating and metallization of the wires, the second metallization on the coated wires is limited to just insufficient The discrete circuit elements contacting any one of the planes.

根據申請專利範圍第8項之方法，其中該金屬化係從該些離散的電路元件凹陷在一個1μm到50μm的範圍中。 According to the method of item 8 of the scope of patent application, the metallization is recessed from the discrete circuit elements in a range of 1 μm to 50 μm.

根據申請專利範圍第1項之方法，其進一步包括以下步驟：在該結構中，相鄰該些離散的電路線在該z軸上或是垂直地形成一介電壁或平面，而不是在該些離散的電路線周圍形成接地屏蔽，該介電壁或平面係被轉置在該些外表面電路平面之間，被金屬化而使得該些端點電耦接至在一或兩個平面上的該些離散的電路圖案。 According to the method of item 1 of the scope of the patent application, it further includes the following steps: in the structure, adjacent discrete circuit lines form a dielectric wall or plane on the z-axis or perpendicularly instead of on the A grounding shield is formed around the discrete circuit lines, and the dielectric wall or plane is transposed between the outer surface circuit planes, and is metalized so that the terminals are electrically coupled to one or two planes Of these discrete circuit patterns.

根據申請專利範圍第10項之方法，其進一步包括將這些垂直的平面連結至接地的步驟，以提供相鄰地繞線的電路線的屏蔽、以及控制這些線的阻抗的能力。 According to the method of claim 10, it further includes the step of connecting these vertical planes to the ground, so as to provide shielding of the circuit wires wound adjacent to the ground and the ability to control the impedance of these wires.

根據申請專利範圍第1項之方法，其中該些線係利用一取代介電質的金屬的核心來加以形成，並且接著一介電質係被塗覆在其上。 According to the method of item 1 in the scope of the patent application, the wires are formed by using a core of metal replacing the dielectric, and then a dielectric is coated on it.

根據申請專利範圍第12項之方法，其中在該些線係利用一取代介電質的金屬的核心來加以形成，並且一介電質係被塗覆在其上之後，其接著是被金屬化。 According to the method of item 12 of the scope of patent application, after the wires are formed by using a core of a metal instead of a dielectric, and a dielectric is coated thereon, they are then It is metalized.

根據申請專利範圍第1項之方法，其中一剛性主體係藉由利用一介電質以填充一在該些平面之間的區域，而被形成在該兩個或多個電路平面之間。 According to the method of claim 1, wherein a rigid main system is formed between the two or more circuit planes by using a dielectric substance to fill an area between the planes.

根據申請專利範圍第14項之方法，其中該介電質係包含環氧樹脂以及空氣。 According to the method of item 14 of the scope of patent application, the dielectric substance includes epoxy resin and air.

根據申請專利範圍第14項之方法，其中該介電質是環氧樹脂。 According to the method of item 14 of the scope of patent application, the dielectric substance is epoxy resin.

根據申請專利範圍第14項之方法，其中該填充材料係延伸至該些電路元件的一底部，此係使得該些元件突出的。 According to the method of claim 14, wherein the filling material extends to a bottom of the circuit elements, which makes the elements protrude.

根據申請專利範圍第14項之方法，其中該填充材料係延伸至該些電路元件的一頂端，此係使得該些元件與該填充材料齊平的。 According to the method of item 14 of the scope of patent application, the filling material extends to a top of the circuit components, which makes the components and the filling material flush.

根據申請專利範圍第14項之方法，其中前述的製程係被重複，其中該先前形成的互連的該些電路平面中之一是作用為用於藉由該些形成的線連接的下一個依序形成的堆積的電路平面的平面中之一。 According to the method of claim 14, wherein the aforementioned process is repeated, wherein one of the circuit planes of the previously formed interconnection is used as the next dependency connected by the lines formed One of the planes of stacked circuit planes formed sequentially.

根據申請專利範圍第1項之方法，其中一柔性的主體係藉由利用一種柔性材料以填充一在該些平面之間的區域而被形成在該兩個或多個電路平面之間，以提供該些三維的線以及電路端點的對準至其所要的位置，並且容許有z軸的柔性以便於容許兩個打算藉由該電互連機構耦接的非共面的表面的電性耦接。 According to the method of item 1 of the scope of patent application, a flexible main system is formed between the two or more circuit planes by using a flexible material to fill an area between the planes to provide The alignment of the three-dimensional lines and the circuit endpoints to their desired positions, and allows the flexibility of the z-axis to allow the electrical coupling of two non-coplanar surfaces intended to be coupled by the electrical interconnection mechanism Pick up.

根據申請專利範圍第20項之方法，其中該柔性材料是一種彈性體的材料。 According to the method of item 20 of the scope of patent application, the flexible material is an elastomer material.

根據申請專利範圍第1項之方法，其中一支架係利用一最小量的材料而被形成在該互連中或是在該互連的周圍，其係緊密接觸在該些平面的每一個上的該些電路元件的每一個，被轉置在兩個電路平面之間，其係維持在每一個平面之間的z軸間隔以及該些電路元件的每一個的x-y位置，該支架結構係提供該互連一種剛性結構，同時將一較大量的空氣維持在該些形成的電路線的周圍。 According to the method in item 1 of the scope of patent application, one of the brackets uses a minimum amount of material The material is formed in the interconnect or around the interconnect, each of the circuit elements in close contact on each of the planes is transposed between two circuit planes, It maintains the z-axis spacing between each plane and the xy position of each of the circuit elements. The support structure provides a rigid structure for the interconnection while maintaining a relatively large amount of air in the formed Around the circuit line.

根據申請專利範圍第22項之方法，其中該較大量的空氣在該些電路元件之間的區域內可以是比固體的環氧樹脂填充多範圍在1%到99%之間的空氣。 According to the method of item 22 of the scope of patent application, the larger amount of air in the area between the circuit elements can be filled with more air ranging from 1% to 99% than the solid epoxy resin.

根據申請專利範圍第22項之方法，其中該最小量的材料是環氧樹脂。 According to the method of item 22 of the scope of patent application, the minimum amount of material is epoxy resin.

根據申請專利範圍第1項之方法，其中在該互連之內或是在該互連的周圍有一介電質的支架、介電柱或是一固體的介電塊，其係比該些平行的電路平面的該z軸高度短的，其中貫穿係被設置在該支架中以允許該些線的進入，使得當結合一填入的彈性體的材料而被使用時，該介電結構係提供該互連結構的一固定的壓縮止擋，以避免該些線由於過度壓縮的損壞。 According to the method of item 1 in the scope of the patent application, there is a dielectric support, a dielectric pillar, or a solid dielectric block within or around the interconnection, which is larger than the parallel The z-axis height of the circuit plane is short, and the through system is provided in the bracket to allow the entry of the wires, so that when used in combination with a filled elastomer material, the dielectric structure provides the A fixed compression stop of the interconnect structure to avoid damage to the wires due to excessive compression.

根據申請專利範圍第1項之方法，其中該些線係被配置為該些三維地形成的線的一自由流動，其係藉由被形成具有S曲線、懸臂的形狀或是捲繞的形狀，以容許有該些線的柔性，同時抵抗在該金屬及/或介電質中的應力破裂。 According to the method of claim 1, wherein the lines are configured as a free flow of the three-dimensionally formed lines, which are formed to have an S-curve, cantilever shape or a winding shape, In order to allow the flexibility of the wires, while resisting the stress cracking in the metal and/or dielectric.

根據申請專利範圍第1項之方法，其中被轉置在該兩個電路平面之間的非導電的介電支架的一格子結構係被設置，該格子結構係緊密接觸在該些電路平面之內的該些電路元件，其係提供該些個別的接觸點或電路元件在該些電路平面之內的對準，並且提供剛性給整個結構、或是容許有該整個結構在該z軸上的一些柔性，同時其亦容許空氣介電質在前述的線的周圍。 According to the method of item 1 of the scope of patent application, a lattice structure of the non-conductive dielectric support transposed between the two circuit planes is arranged, and the lattice structure is in close contact with the circuit planes The circuit components provide the alignment of the individual contact points or circuit components within the circuit planes, and provide rigidity to the entire structure, or allow the The whole structure has some flexibility in the z-axis, and it also allows air dielectric around the aforementioned line.

根據申請專利範圍第1項之方法，其進一步包括將一電子構件的兩個或多個端子點附加及電耦接至該些形成的線以及該些對應的平面之對應的電路元件的步驟，每一個點係耦接至其在該互連結構中之對應指定的電源、接地、或是信號線及/或電路元件，以此種方式，該電子構件的功能係被提供至該互連所欲耦接到的電性裝置的點。 According to the method of item 1 of the scope of patent application, it further includes the step of attaching and electrically coupling two or more terminal points of an electronic component to the formed lines and the corresponding circuit elements of the corresponding planes, Each point is coupled to its corresponding designated power, ground, or signal line and/or circuit element in the interconnect structure. In this way, the function of the electronic component is provided to the interconnection. The point of the electrical device to be coupled to.

根據申請專利範圍第28項之方法，其中該電子構件是一電容器。 According to the method of item 28 of the scope of patent application, the electronic component is a capacitor.

根據申請專利範圍第28項之方法，其中該電子構件是一電阻器。 According to the method of item 28 of the scope of patent application, the electronic component is a resistor.

根據申請專利範圍第28項之方法，其中該電子構件是一電感器。 According to the method of item 28 of the scope of patent application, the electronic component is an inductor.

根據申請專利範圍第28項之方法，其中該些電子構件的端子點係耦接至其在該互連結構中之對應的電源、接地、或是信號線，使得該些構件的端子點係被提供至該互連所欲耦接到的電性裝置的點。 According to the method of item 28 of the scope of patent application, the terminal points of the electronic components are coupled to their corresponding power, ground, or signal lines in the interconnection structure, so that the terminal points of the components are Provide a point to the electrical device to which the interconnect is to be coupled.

根據申請專利範圍第1項之方法，其中該些線係延伸超出該互連的剛性主體，其係具有有助於彎曲的形狀、以及有助於接觸各種形狀的電性裝置的端點，其係作用為耦接兩個非共面的電性裝置的一柔性的互連，其係提供在一整合的結構中的間距轉換及接腳重新對映、以及柔性的探測之能力。 According to the method of item 1 of the scope of patent application, the wires extend beyond the rigid body of the interconnection, which have shapes that facilitate bending and end points that facilitate contact with various shapes of electrical devices. It is a flexible interconnection that couples two non-coplanar electrical devices. It provides the ability of pitch conversion, pin remapping, and flexible detection in an integrated structure.

根據申請專利範圍第1項之方法，其中該互連結構係利用一或多個矽晶圓IC來加以建構，此係產生相互連接該兩個或多個IC的多晶片模組，其中一矽層是該基底電路平面。 According to the method of claim 1, wherein the interconnect structure is constructed by using one or more silicon wafer ICs, this is to generate a multi-chip module interconnecting the two or more ICs, in which one silicon wafer The layer is the substrate circuit plane.

根據申請專利範圍第1項之方法，其中該互連結構係利用一或多個矽晶圓IC來加以建構，此係產生一用於該IC的重分佈封裝。 According to the method of item 1 of the scope of patent application, the interconnection structure utilizes one or more The silicon wafer IC is constructed, which produces a redistribution package for the IC.

根據申請專利範圍第1項之方法，其中該互連結構係被建構在一撓性的電路基底上。 According to the method of item 1 of the scope of patent application, the interconnection structure is constructed on a flexible circuit substrate.

一種電互連機構，其係包括：在兩個或多個電路平面之內的兩個或多個離散的接觸點，其例如是但不限於電路墊；以及三維的介電線，其係自由地被繞線在該兩個或多個電路平面上的該些離散的點之間，該些離散的點定位為沿著該兩個或多個電路平面中每一者的任一側的無論何處，以便於透過該互連機構來提供兩個或多個電性裝置的電性耦接，以及提供該些線的自由繞線，該些介電線係具有一導電的塗層並且該些離散的點包含接觸墊，以及該兩個或多個線被設置成緊密接觸該些電極中的每一者，以將彼此耦接並且耦接至該些離散的接觸墊中的兩個或多個。 An electrical interconnection mechanism, which includes: two or more discrete contact points in two or more circuit planes, such as but not limited to circuit pads; and three-dimensional dielectric wires, which are freely Be routed between the discrete points on the two or more circuit planes, the discrete points positioned along any side of each of the two or more circuit planes In order to provide the electrical coupling of two or more electrical devices through the interconnection mechanism, and provide free winding of the wires, the dielectric wires have a conductive coating and the discrete wires The point of includes a contact pad, and the two or more wires are arranged to closely contact each of the electrodes to couple each other and to two or more of the discrete contact pads .

根據申請專利範圍第37項之互連機構，其中該些電路平面係實質平行於彼此的。 According to the 37th interconnection mechanism in the scope of patent application, the circuit planes are substantially parallel to each other.

根據申請專利範圍第37項之互連機構，其進一步包括該些介電線的外表面係利用任意有機或無機的導電材料而被金屬化，以用於電性耦接至其之個別的離散的接觸點。 According to the 37th interconnection mechanism in the scope of the patent application, it further includes that the outer surfaces of the dielectric wires are metalized using any organic or inorganic conductive material for electrical coupling to the individual discrete Contact point.

根據申請專利範圍第39項之互連機構，其中該導電材料是銅、銀、金、或是導電的聚合物。 According to the 39th interconnection mechanism in the scope of patent application, the conductive material is copper, silver, gold, or a conductive polymer.

根據申請專利範圍第37項之互連機構，其中該些電耦接的接觸墊可以是在該結構的相反側上、或是在一相同側上，並且該些形成的金屬化的線可以源自於一側上並且終止在另一側上、或是源自並且終止於相同側。 According to the 37th interconnection mechanism of the scope of patent application, the electrically coupled contact pads can be on the opposite side of the structure or on the same side, and the formed metallization The lines can originate on one side and terminate on the other side, or originate and terminate on the same side.

根據申請專利範圍第37項之互連機構，其中一第二介電質的塗層係被形成在該些離散的線的金屬化的表面上，以近似一同軸線。 According to the 37th interconnection mechanism in the scope of the patent application, a second dielectric coating is formed on the metalized surfaces of the discrete wires to approximate the coaxial line.

根據申請專利範圍第37項之互連機構，其中該些經形成且金屬化的介電線係透過該金屬化製程來電耦接至該兩個或多個平面上的離散的金屬的電路、或是該些離散的平行的電路係被形成為該些形成的介電線的一整體的部分，並且接著和該些介電線一起被金屬化。 According to the 37th interconnection mechanism of the scope of patent application, the formed and metalized dielectric wires are electrically coupled to the discrete metal circuits on the two or more planes through the metalization process, or The discrete parallel circuits are formed as an integral part of the formed dielectric wires, and then metalized together with the dielectric wires.

根據申請專利範圍第42項之互連機構，其中該些線的該形成的第二介電質的塗層以及金屬化，在該塗覆後的線上的該第二金屬化係被限制於剛好不足以接觸在該些平面的任一個上的該些離散的電路元件。 According to the interconnection mechanism of item 42 of the scope of patent application, the formed second dielectric coating and metallization of the lines are limited to just the second metallization on the coated lines It is not enough to contact the discrete circuit elements on any of the planes.

根據申請專利範圍第44項之互連機構，其中該金屬化係從該些離散的電路元件凹陷在一個1μm到50μm的範圍中。 According to the interconnection mechanism of item 44 of the scope of patent application, the metallization is recessed from the discrete circuit elements in a range of 1 μm to 50 μm.

根據申請專利範圍第37項之互連機構，其進一步包括以下步驟：一介電壁或平面係在該結構中，在該z軸上或是垂直地相鄰該些離散的電路線來加以形成，而不是在該些離散的電路線周圍形成接地屏蔽，該介電壁或平面係被轉置在該些外表面電路平面之間，被金屬化而使得該些端點電耦接至在一或兩個平面上的該些離散的電路圖案。 According to the 37th interconnection mechanism in the scope of the patent application, it further includes the following steps: a dielectric wall or plane is formed in the structure and formed on the z-axis or vertically adjacent to the discrete circuit lines Instead of forming a ground shield around the discrete circuit lines, the dielectric wall or plane is transposed between the outer surface circuit planes, and is metalized so that the terminals are electrically coupled to a Or the discrete circuit patterns on two planes.

根據申請專利範圍第46項之互連機構，其進一步包括這些垂直的平面係連結至接地，以提供相鄰地繞線的電路線的屏蔽、以及控制這些線的阻抗的能力。 According to the 46th interconnection mechanism in the scope of the patent application, it further includes that these vertical planes are connected to the ground to provide shielding of the circuit wires wound adjacent to the ground and the ability to control the impedance of these wires.

根據申請專利範圍第37項之互連機構，其中該些線係利用一取代介電質的金屬的核心來加以形成，並且接著一介電質係被塗覆在其上。 According to the 37th interconnection mechanism in the scope of the patent application, the wires are formed by using a core of metal instead of dielectric, and then a dielectric is coated on it.

根據申請專利範圍第48項之互連機構，其中該些線係利用一取代介電質的金屬的核心來加以形成，並且被塗覆介電質，並且接著該些線係被金屬化。 According to the 48th interconnection mechanism of the scope of patent application, the wires are formed by using a core of a metal replacing the dielectric, and are coated with a dielectric, and then the wires are metalized.

根據申請專利範圍第37項之互連機構，其中一剛性主體係藉由利用一介電質以填充一在該些平面之間的區域，而被形成在該兩個或多個電路平面之間。 According to the 37th interconnection mechanism of the scope of patent application, a rigid main system is formed between the two or more circuit planes by using a dielectric substance to fill an area between the planes .

根據申請專利範圍第50項之互連機構，其中該介電質係包含環氧樹脂以及空氣。 According to the 50th interconnection mechanism in the scope of patent application, the dielectric includes epoxy resin and air.

根據申請專利範圍第50項之互連機構，其中該介電質是環氧樹脂。 According to the 50th interconnection mechanism in the scope of patent application, the dielectric material is epoxy resin.

根據申請專利範圍第50項之互連機構，其中該填充材料係延伸至該些電路元件的一底部，此係使得該些元件突出的。 According to the 50th interconnection mechanism in the scope of patent application, the filling material extends to a bottom of the circuit elements, which makes the elements protrude.

根據申請專利範圍第50項之互連機構，其中該填充材料係延伸至該些電路元件的一頂端，此係使得該些元件與該填充材料齊平的。 According to the 50th interconnection mechanism in the scope of patent application, the filling material extends to a top of the circuit elements, which makes the elements and the filling material flush.

根據申請專利範圍第50項之互連機構，其中前述的製程係被重複，其中該先前形成的互連的該些電路平面的中之一是作用為用於藉由該些形成的線連接的下一個依序形成的堆積的電路平面的平面中之一。 According to the 50th interconnection mechanism in the scope of patent application, the aforementioned process is repeated, and one of the circuit planes of the previously formed interconnection is used to connect by the formed wires One of the planes of the next stacked circuit plane formed in sequence.

根據申請專利範圍第37項之互連機構，其中一柔性的主體係藉由利用一種柔性材料以填充一在該些平面之間的區域而被形成在該兩個或多個電路平面之間，以提供該些三維的線以及電路端點的對準至其所要的位置，並且容許有z軸的柔性以便於容許兩個打算藉由該電互連機構耦接的非共面的表面的電性耦接。 According to the 37th interconnection mechanism of the scope of patent application, a flexible main system is formed between the two or more circuit planes by filling an area between the planes with a flexible material, In order to provide the alignment of the three-dimensional lines and the circuit endpoints to their desired positions, and allow the flexibility of the z-axis to allow the electrical connection of two non-coplanar surfaces to be coupled by the electrical interconnection mechanism Sexual coupling.

根據申請專利範圍第56項之互連機構，其中該柔性材料是一種彈性體的材料。 According to the 56th interconnection mechanism in the scope of patent application, the flexible material is an elastic Body material.

一種電互連機構，其係包括：在兩個或多個電路平面之內的兩個或多個離散的接觸點，其例如是但不限於電路墊；以及三維的介電線，其係自由地被繞線在該兩個或多個電路平面上的該些離散的點之間，該些離散的點定位為沿著該兩個或多個電路平面中每一者的任一側的無論何處，以便於透過該互連機構來提供兩個或多個電性裝置的電性耦接，以及提供該些線的自由繞線，該些介電線係具有一導電的塗層並且該些離散的點包含接觸墊，以及該兩個或多個線被設置成緊密接觸該些電極中的每一者，以將彼此耦接並且耦接至該些離散的接觸墊中的兩個或多個，且進一步包括一利用一最小量的材料而被形成在該互連中或是在該互連的周圍的支架，其係緊密接觸在該些平面的每一個上的該些電路元件的每一個，被轉置在兩個電路平面之間，其係維持在每一個平面之間的z軸間隔以及該些電路元件的每一個的x-y位置，該支架結構係提供該互連一種剛性結構，同時將一較大量的空氣維持在該些形成的電路線的周圍。 An electrical interconnection mechanism, which includes: two or more discrete contact points in two or more circuit planes, such as but not limited to circuit pads; and three-dimensional dielectric wires, which are freely Be routed between the discrete points on the two or more circuit planes, the discrete points positioned along any side of each of the two or more circuit planes In order to provide the electrical coupling of two or more electrical devices through the interconnection mechanism, and provide free winding of the wires, the dielectric wires have a conductive coating and the discrete wires The point of includes a contact pad, and the two or more wires are arranged to closely contact each of the electrodes to couple each other and to two or more of the discrete contact pads , And further includes a bracket formed in or around the interconnection using a minimum amount of material, which is in close contact with each of the circuit elements on each of the planes , Is transposed between two circuit planes, which maintains the z-axis spacing between each plane and the xy position of each of the circuit elements. The support structure provides a rigid structure for the interconnection, while Maintain a relatively large amount of air around the formed circuit lines.

根據申請專利範圍第58項之互連機構，其中該較大量的空氣在該些電路元件之間的區域內可以是比固體的環氧樹脂填充多範圍在1%到99%之間的空氣。 According to the interconnection mechanism of item 58 of the scope of patent application, the larger amount of air in the area between the circuit elements can be filled with air in the range of 1% to 99% more than the solid epoxy resin.

根據申請專利範圍第58項之互連機構，其中該最小量的材料是環氧樹脂。 According to the 58th interconnection mechanism in the scope of patent application, the smallest amount of material is epoxy resin.

根據申請專利範圍第58項之互連機構，其中在該互連之內或是在該互連的周圍有一介電質的支架、介電柱或是一固體的介電塊，其係比該些平行的電路平面的該z軸高度短的，其中貫穿係被設置在該支架中以允許該些線的進入，使得當結合一填入的彈性體的材料而被使用時，該介電結構係提供該互連結構的一固定的壓縮止擋，以避免該些線由於過度壓縮的損壞。 According to the interconnection mechanism of item 58 of the scope of patent application, which is within the interconnection or within the There is a dielectric support, a dielectric pillar or a solid dielectric block around the interconnection, which is shorter than the z-axis height of the parallel circuit planes, and the penetration is provided in the support to allow The entry of the wires allows the dielectric structure to provide a fixed compression stop for the interconnection structure when used in combination with a filled elastomeric material to avoid damage to the wires due to excessive compression .

根據申請專利範圍第58項之互連機構，其中該些線係被配置為該些三維地形成的線的一自由流動，其係藉由被形成具有S曲線、懸臂的形狀或是捲繞的形狀，以容許有該些線的柔性，同時抵抗在該金屬及/或介電質中的應力破裂。 According to the interconnection mechanism of item 58 of the scope of patent application, the wires are configured as a free flow of the three-dimensionally formed wires by being formed to have an S-curve, cantilever shape or a winding Shape to allow flexibility of the wires while resisting stress cracking in the metal and/or dielectric.

根據申請專利範圍第58項之互連機構，其中被轉置在該兩個電路平面之間的非導電的介電支架的一格子結構係被設置，該格子結構係緊密接觸在該些電路平面之內的該些電路元件，其係提供該些個別的接觸點或電路元件在該些電路平面之內的對準，並且提供剛性給整個結構、或是容許有該整個結構在該z軸上的一些柔性，同時其亦容許空氣介電質在前述的線的周圍。 According to the interconnection mechanism of item 58 of the scope of patent application, a lattice structure of a non-conductive dielectric support transposed between the two circuit planes is arranged, and the lattice structure is in close contact with the circuit planes The circuit elements inside provide the alignment of the individual contact points or circuit elements within the circuit planes, and provide rigidity to the entire structure, or allow the entire structure to be on the z-axis Some flexibility, and it also allows air dielectric around the aforementioned line.

根據申請專利範圍第58項之互連機構，其進一步包括被附加及電耦接至該些形成的線以及該些對應的平面之對應的電路元件的一電子構件的兩個或多個端子點，每一個點係耦接至其在該互連結構中之對應指定的電源、接地、或是信號線及/或電路元件，使得該電子構件的功能係被提供至該互連所欲耦接到的電性裝置的點。 The interconnection mechanism according to item 58 of the scope of patent application, which further includes two or more terminal points of an electronic component attached to and electrically coupled to the formed lines and the corresponding circuit elements of the corresponding planes , Each point is coupled to its corresponding designated power, ground, or signal line and/or circuit element in the interconnection structure, so that the function of the electronic component is provided to the interconnection to be coupled To the point of the electrical device.

根據申請專利範圍第64項之互連機構，其中該電子構件是一電容器。 According to the 64th interconnection mechanism in the scope of patent application, the electronic component is a capacitor.

根據申請專利範圍第64項之互連機構，其中該電子構件是一電阻器。 According to the 64th interconnection mechanism in the scope of patent application, the electronic component is a resistor.

根據申請專利範圍第64項之互連機構，其中該電子構件是一電感器。 According to the 64th interconnection mechanism in the scope of patent application, the electronic component is an inductor.

根據申請專利範圍第64項之互連機構，其中該些電子構件的端子點係耦接至其在該互連結構中之對應的電源、接地、或是信號線，使得該些構件的端子點係被提供至該互連所欲耦接到的電性裝置的點。 According to the 64th interconnection mechanism of the scope of patent application, the terminal points of the electronic components are coupled to their corresponding power, ground, or signal lines in the interconnection structure, so that the terminal points of the components It is provided to the point of the electrical device to which the interconnect is to be coupled.

根據申請專利範圍第58項之互連機構，其中該些線係延伸超出該互連的剛性主體，其係具有有助於彎曲的形狀、以及有助於接觸各種形狀的電性裝置的端點，其係作用為耦接兩個非共面的電性裝置的一柔性的互連，其係提供在一整合的結構中的間距轉換及接腳重新對映、以及柔性的探測之能力。 According to the interconnection mechanism of item 58 of the scope of patent application, the lines extend beyond the rigid body of the interconnection, which have a shape that facilitates bending and an end point that facilitates contact with various shapes of electrical devices It functions as a flexible interconnection coupling two non-coplanar electrical devices, and it provides the capability of pitch conversion, pin remapping, and flexible detection in an integrated structure.

根據申請專利範圍第58項之互連機構，其中該互連結構係利用一或多個矽晶圓IC來加以建構，此係產生相互連接該兩個或多個IC的多晶片模組，其中一矽層是該基底電路平面。 According to the 58th interconnection mechanism of the scope of patent application, the interconnection structure is constructed by using one or more silicon wafer ICs, which generates a multi-chip module interconnecting the two or more ICs, wherein A silicon layer is the substrate circuit plane.

根據申請專利範圍第58項之互連機構，其中該互連結構係利用一或多個矽晶圓IC來加以建構，此係產生一用於該IC的重分佈封裝。 According to the 58th interconnection mechanism in the scope of patent application, the interconnection structure is constructed using one or more silicon wafer ICs, which generates a redistribution package for the IC.

根據申請專利範圍第58項之互連機構，其中該互連結構係被建構在一撓性的電路基底上。 According to the 58th interconnection mechanism in the scope of patent application, the interconnection structure is constructed on a flexible circuit substrate.

一種用於製造一互連機構或裝置之方法，其係包括以下步驟：提供一平坦載體的玻璃、陶瓷或是某一其它平坦的金屬塊；利用包含黏著劑或蠟的一適當的接合材料來臨時接合較佳的是Cu的一片基底金屬箔至該平坦的材料載體，以保持該Cu為平坦的，該片箔具有在10μm到35μm的一範圍內的箔厚度；在該Cu箔的頂端上，以三維方式自由地繞線被附接至該Cu箔的介電線，其係從該箔上生長並且該箔上自由地被繞線在該兩個或多個電路平面上的離散的點之間；透過微蝕刻電漿或是其它的表面處理以處理該箔來提升該些介電線的黏著，該些線在直徑上是在一1μm到50μm的範圍內，並且被建構到高於所計畫的互連機構的從100μm到0.200"厚的一範圍內的整體高度一大約25μm到100μm的z軸高度；利用電鍍、無電的電鍍、化學氣相沉積、或是濺鍍塗覆來金屬化從該Cu片延伸的自由形成的線，此金屬化的厚度通常將會是在1μm到20μm的範圍內；該金屬化係塗覆該些介電線以及該基底箔的露出的表面區域，此係使得該基底箔以及該些經塗覆的線變成電耦接的。 A method for manufacturing an interconnection mechanism or device, which includes the following steps: providing a flat carrier of glass, ceramic or some other flat metal block; using a suitable bonding material containing adhesive or wax It is preferable to bond a piece of base metal foil of Cu to the flat material carrier to keep the Cu flat. The piece of foil has a foil thickness in a range of 10 μm to 35 μm; on the top of the Cu foil , Freely winding in a three-dimensional manner is attached to the dielectric of the Cu foil Wire, which is grown from the foil and is freely wound on the foil between discrete points on the two or more circuit planes; the foil is treated by micro-etching plasma or other surface treatment To improve the adhesion of the dielectric wires, the wires are in the range of 1μm to 50μm in diameter, and are constructed to be higher than the planned interconnection mechanism from 100μm to 0.200" thick. The overall height is a z-axis height of about 25μm to 100μm; electroplating, electroless electroplating, chemical vapor deposition, or sputter coating is used to metalize the freely formed line extending from the Cu sheet. The thickness of the metallization is usually Will be in the range of 1 μm to 20 μm; the metallization coats the dielectric wires and the exposed surface area of the base foil, which makes the base foil and the coated wires become electrically coupled .

根據申請專利範圍第73項之方法，其中該些金屬化的介電線要再次被塗覆一介電質。 According to the method of item 73 of the scope of patent application, the metalized dielectric wires are again coated with a dielectric substance.

根據申請專利範圍第74項之方法，其中該介電質的該塗覆係經由一浸漬操作、矽化學氣相沉積(SCVD)、二氧化矽脈衝層沉積(PLD)、或是二氧化鈦原子層沉積(ALD)來加以完成。 According to the method of item 74 in the scope of patent application, the coating of the dielectric substance is through a dipping operation, silicon chemical vapor deposition (SCVD), silicon dioxide pulsed layer deposition (PLD), or titanium dioxide atomic layer deposition (ALD) to complete it.

根據申請專利範圍第73項之方法，其中在此塗覆步驟期間，該基底箔金屬化的頂端側也可被塗覆，此係將其與進一步的製程電性隔離。 According to the method of item 73 of the scope of patent application, during this coating step, the metalized top side of the base foil can also be coated, which is to electrically isolate it from further processes.

根據申請專利範圍第73項之方法，其中該些塗覆後的介電線係接著被金屬化，以將該些形成的線的全部表面短路在一起。 According to the method of item 73 of the scope of patent application, the coated dielectric wires are then metalized to short-circuit all the surfaces of the formed wires together.

根據申請專利範圍第77項之方法，其中將此金屬化耦接到一或多個接地線或是外部的電路層係產生用於所有的線的接地屏蔽，並且近似用於所有的信號線的同軸線。 According to the method of item 77 in the scope of the patent application, the metallization is coupled to one or more ground wires or an external circuit layer to produce a ground shield for all wires, and is approximately used for all signal wires. Coaxial.

根據申請專利範圍第78項之方法，其中耦接該接地的金屬化可以在該互連最終耦接兩個或多個電子裝置時，透過從被設計來接地的線或是基底銅的區域，或是經由雷射剝蝕來選擇性的移除外部的介電質塗層而被達成。 According to the method of item 78 in the scope of the patent application, the metallization for coupling to the ground can be achieved through a wire designed to be grounded or an area of the substrate copper when the interconnect is finally coupled to two or more electronic devices. Or it can be achieved by selectively removing the external dielectric coating by laser ablation.

根據申請專利範圍第79項之方法，其中該些金屬化的線係接著在具有或是不具有一第二介電質以及第二金屬化下加以形成，並且該結構可以經由一模製操作而被填入包含環氧樹脂的一介電質，其係將該環氧樹脂固化成為一剛性基板，且將該環氧樹脂包覆模製超出所形成的該些線的頂端端點約25μm-100μm，藉此經由研磨、砂磨、或是研光而允許用於一平坦化製程之足夠的材料。 According to the method of item 79 in the scope of patent application, the metallized lines are then formed with or without a second dielectric and second metallization, and the structure can be formed by a molding operation Filled with a dielectric containing epoxy resin, the epoxy resin is cured into a rigid substrate, and the epoxy resin is overmolded by approximately 25 μm beyond the top end of the lines formed. 100μm, thereby allowing sufficient material for a planarization process through grinding, sanding, or polishing.

根據申請專利範圍第80項之方法，其中該些金屬化的線係具有一第二介電質以及第二金屬化，該些線的頂端尖端可被塗覆一例如是蠟或是一臨時的聚合物之臨時的塗層，以避免金屬化在一第二介電層上形成最後的25μm到100μm。 According to the method of claim 80, the metalized wires have a second dielectric and a second metallization, and the tips of the wires can be coated with a wax, for example, or a temporary Temporary coating of polymer to avoid metallization to form the final 25μm to 100μm on a second dielectric layer.

根據申請專利範圍第80項之方法，其中平坦化亦露出該些金屬化的線的頂端，此係在將一第二電路層電耦接至該些線以及該基底箔時提供用以建構該電路層的機會，而使得若該些塗覆後的線的尖端已經免於次要的金屬化，則仔細地控制該互連基板的在該z軸上的平坦化將會露出該形成的線的第一金屬化的層，此係在不耦接該形成的線的前述選配的第二金屬化至該第二電路平面層之下，將其露出以電耦接至前述第二電路平面的形成。 According to the method of item 80 in the scope of patent application, the planarization also exposes the tops of the metallized lines, which is provided for constructing the structure when a second circuit layer is electrically coupled to the lines and the base foil If the tips of the coated wires have been free from secondary metallization, carefully controlling the planarization of the interconnect substrate on the z-axis will expose the formed wires. The first metallized layer, which is under the second circuit plane layer of the aforementioned optional second metallization that is not coupled to the formed line, is exposed to be electrically coupled to the aforementioned second circuit plane Formation.

根據申請專利範圍第82項之方法，其中該第二電路平面層係接著經由無電的電鍍、化學氣相沉積、濺鍍塗覆、或是電鍍來加以形成。 According to the method of item 82 of the scope of patent application, the second circuit plane layer is then It is formed by electroless plating, chemical vapor deposition, sputter coating, or electroplating.

根據申請專利範圍第73項之方法，其中該導電的金屬化較佳的是Cu或是Au。 According to the method described in item 73 of the scope of patent application, the conductive metallization is preferably Cu or Au.

根據申請專利範圍第82項之方法，其中在將該互連基板從該平坦的基板抬起之後，一主要的底部金屬層以及一次要的頂端層係透過一標準的微影蝕刻製程而被形成為離散的電路。 According to the method of item 82 in the scope of patent application, after lifting the interconnect substrate from the flat substrate, a main bottom metal layer and a primary top layer are formed by a standard lithographic etching process It is a discrete circuit.

根據申請專利範圍第85項之方法，其中該些接觸點或墊是透過此電路化製程所形成的，其係額外被電鍍有金屬的合金，以用於包含抗磨損或是可焊性之一所選應用。 According to the method of item 85 in the scope of the patent application, the contact points or pads are formed through the circuitization process, and they are additionally electroplated with metal alloys to include one of anti-wear or solderability The selected application.

根據申請專利範圍第74項之方法，其中替代在該些線中的一介電核心的是，一金屬核心係透過負型3D列印技術的使用來加以取代，其係利用包含負型工作的光敏的環氧樹脂，藉此除了其中該核心線金屬化將被形成之處以外，一臨時的介電質係被形成到該互連的整個主動區域，接著該金屬化係透過電鍍、無電的電鍍、化學氣相沉積、或是濺鍍塗覆而被形成，以形成一固體的金屬的線結構。 According to the method of item 74 of the scope of patent application, in which a dielectric core in these lines is replaced, a metal core is replaced by the use of negative type 3D printing technology, which utilizes a negative type work A photosensitive epoxy resin, whereby a temporary dielectric is formed to the entire active area of the interconnection except where the core line metallization will be formed, and then the metallization is electroplated, electroless It is formed by electroplating, chemical vapor deposition, or sputter coating to form a solid metal line structure.

根據申請專利範圍第87項之方法，其中具有變化的厚度之各種的金屬係被形成在環氧樹脂層內的中空的結構的內壁上，此係提供所選的電性及機械性質給該互連機構，該臨時的環氧樹脂接著是透過剝除技術而被移除，並且獨立式的金屬的線或管係留下以用於後續的處理。 According to the method of item 87 in the scope of patent application, various metals with varying thickness are formed on the inner wall of the hollow structure in the epoxy resin layer, which provides selected electrical and mechanical properties to the For the interconnection mechanism, the temporary epoxy resin is then removed by stripping technology, and the free-standing metal wire or tube is left for subsequent processing.

根據申請專利範圍第87項之方法，其進一步包括提供具有或是不具有額外的介電質及金屬化的層以用於屏蔽或是同軸貫孔之介電核心的、金屬核心的、或是金屬的管透過電鍍、無電的電鍍、化學氣相沉積、或是濺鍍塗覆，而被形成於預先被形成在該平坦的玻璃或平坦的陶瓷上的離散的金屬墊或電路上。 According to the method of item 87 of the scope of patent application, it further includes providing a layer with or without additional dielectric and metallization for shielding or coaxial through-hole dielectric core, metal core, or Metal tubes are electroplated, electroless plating, chemical vapor deposition, or splashing It is formed on discrete metal pads or circuits previously formed on the flat glass or flat ceramic.

根據申請專利範圍第89項之方法，其中該些貫孔的尺寸是透過一臨時的微影製程來加以界定的，並且這些墊或是電路係利用一雷射製版製程而被形成，藉此一金屬的箔係利用一黏著劑或蠟而被臨時黏著至該平坦的基底材料，以供線的形成可以被建構在該離散的墊或是電路的頂端上。 According to the method of item 89 in the scope of patent application, the size of the through holes is defined by a temporary lithography process, and the pads or circuits are formed by a laser plate making process, thereby a The metal foil is temporarily adhered to the flat base material with an adhesive or wax, so that wire formation can be constructed on the discrete pad or the top of the circuit.

根據申請專利範圍第87項之方法，其中該些形成的線具有端點，其是根據該互連之一所選的應用而被形成之具有變化的幾何形狀之離散的墊及/或電路，以及被形成且金屬化以用於接觸電性端子之具有變化的形狀之可焊的墊或是接腳。 According to the method of item 87 of the scope of patent application, the formed lines have end points, which are discrete pads and/or circuits with varying geometric shapes formed according to a selected application of the interconnection, And solderable pads or pins of varying shapes that are formed and metalized for contacting electrical terminals.

根據申請專利範圍第91項之方法，其中該些形成的線的該些端點在一步驟中加以形成以及金屬化，從而節省額外的處理時間並且一旦該環氧樹脂模製製程完成後提供在該互連的兩端上有齊平的電路墊的機會。 According to the method of item 91 of the scope of patent application, the endpoints of the formed lines are formed and metalized in one step, thereby saving additional processing time and providing the epoxy resin molding process once the epoxy resin molding process is completed. There are opportunities for flush circuit pads on both ends of the interconnect.

根據申請專利範圍第73項之方法，其中一彈性體或橡膠化合物灌封材料係取代一撓性灌封化合物，此係提供該些互連端子柔性，以用於配接非共面的電子元件的表面，並且藉由改變該灌封材料的硬度以及該些形成的線材料、厚度、長度及形狀，該些形成的線配接端子的每一個的總柔性量、力以及壽命係被控制。 According to the method of item 73 of the scope of patent application, an elastomer or rubber compound potting material replaces a flexible potting compound, which provides the flexibility of the interconnect terminals for mating non-coplanar electronic components And by changing the hardness of the potting material and the formed wire material, thickness, length and shape, the total flexibility, force and life of each of the formed wire mating terminals are controlled.

根據申請專利範圍第73項之方法，其中針對一柔性的互連，具有包含環氧樹脂的一適當耐久的材料的一格子結構、柱、或是一固體的塊係被形成在該互連中未被該些形成的線或是柔性的灌封化合物所佔據的開放空間內。 According to the method of item 73 of the scope of patent application, for a flexible interconnection, a lattice structure, pillars, or a solid block having a suitably durable material containing epoxy resin is formed in the interconnection In the open space not occupied by the formed lines or the flexible potting compound.

根據申請專利範圍第94項之方法，其中具有一適當耐久的材料的該些格子結構、柱、或是一固體的塊結構係透過3D列印技術而被形成在該互連主體的開放空間中，其係具有一高度薄於該互連的整體厚度一個10μm到200μm的範圍內，其係形成具有一硬的壓縮止擋的該互連結構，以對抗打算電耦接的裝置之兩個配接的表面，藉此避免該互連結構的過度壓縮及損壞。 According to the method of claim 94, the lattice structures, pillars, or a solid block structure with a suitable durable material are formed in the open space of the interconnection body through 3D printing technology , Which has a height that is thinner than the overall thickness of the interconnect and a range of 10 μm to 200 μm, which forms the interconnect structure with a hard compression stop to resist the two configurations of the device intended to be electrically coupled To avoid excessive compression and damage to the interconnection structure.