TWI711922B - System function test device - Google Patents

System function test device Download PDF

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TWI711922B
TWI711922B TW108113336A TW108113336A TWI711922B TW I711922 B TWI711922 B TW I711922B TW 108113336 A TW108113336 A TW 108113336A TW 108113336 A TW108113336 A TW 108113336A TW I711922 B TWI711922 B TW I711922B
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timer
power
unit
transistor
output
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TW202040360A (en
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張順凱
黃彥舜
鄭君伍
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上銀科技股份有限公司
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Abstract

本發明的系統功能測試裝置包括第一計時器、第二計時器及處理器。第二計時器耦接第一計時器。處理器耦接第一計時器及第二計時器，且接收系統信號。第一計時器及第二計時器建立開機及關機測試時序。在開機及關機測試時序中，且系統信號包括錯誤訊息時，處理器鎖定第一計時器的狀態，且停止開機及關機測試時序。The system function test device of the present invention includes a first timer, a second timer and a processor. The second timer is coupled to the first timer. The processor is coupled to the first timer and the second timer, and receives system signals. The first timer and the second timer establish the power-on and power-off test sequence. During the startup and shutdown test sequence, and the system signal includes an error message, the processor locks the state of the first timer, and stops the startup and shutdown test sequence.

Description

系統功能測試裝置System function test device

本發明與機械設備有關，特別是指一種機械設備的系統功能測試裝置。The invention relates to mechanical equipment, and particularly refers to a system function test device for mechanical equipment.

機械系統(設備)在出廠前會先經過嚴謹地功能測試以驗證各種功能是否正常，透過執行機械系統的開機作業及關機作業可以有效率地測試系統功能。傳統在進行開機作業及關機作業測試是透過操作人員反覆對機械系統執行開機功能及關機功能，如此，不僅需要耗費人力及大量時間，且無法有效率地保留錯誤的原因，因此，錯誤發生後需由人員詳細檢查整個機械系統，而使錯誤排除的效率不佳。The mechanical system (equipment) will undergo rigorous functional tests before leaving the factory to verify whether various functions are normal. The system functions can be tested efficiently by performing the startup and shutdown operations of the mechanical system. Traditionally, the start-up and shutdown test is performed by the operator repeatedly performing the start-up and shutdown functions on the mechanical system. This not only requires labor and a lot of time, but also cannot efficiently retain the cause of the error. Therefore, it is necessary after the error occurs. The entire mechanical system is inspected in detail by personnel, which makes the efficiency of error elimination poor.

雖然，目前測試也有採用硬體、軟體或兩者組合來進行，但仍無法在錯誤發生時，適時地停止開機作業及關機作業的測試，因此，目前的技術不能保留錯誤原因，也無法有效率地排除錯誤。Although the current test also uses hardware, software, or a combination of the two, it is still unable to stop the boot operation and shutdown operation test in a timely manner when an error occurs. Therefore, the current technology cannot retain the cause of the error, nor is it efficient Correctly eliminate errors.

有鑑於上述缺失，本發明的系統功能測試裝置可以在系統發生錯誤狀態時，適時地停止開機作業及關機作業的測試，以保留錯誤原因，有利於將錯誤排除。In view of the above-mentioned deficiencies, the system function testing device of the present invention can stop the test of the startup operation and shutdown operation in a timely manner when an error state occurs in the system, so as to retain the cause of the error and help eliminate the error.

為了達成上述目的，本發明的系統功能測試裝置包括第一計時器、第二計時器及處理器。第二計時器耦接第一計時器。處理器耦接第一計時器及第二計時器，且接收系統信號。第一計時器及第二計時器建立開機及關機測試時序。在開機及關機測試時序中，且系統信號包括錯誤訊息時，處理器鎖定第一計時器的狀態，且停止開機及關機測試時序。In order to achieve the above objective, the system function testing device of the present invention includes a first timer, a second timer, and a processor. The second timer is coupled to the first timer. The processor is coupled to the first timer and the second timer, and receives system signals. The first timer and the second timer establish the power-on and power-off test sequence. During the startup and shutdown test sequence, and the system signal includes an error message, the processor locks the state of the first timer, and stops the startup and shutdown test sequence.

因此，透過開機及關機測試時序可以有效率地測試系統(例如機械運作系統)的功能，以便於驗證系統的功能是否正常。再者，當系統的系統信號出現錯誤訊息時，本發明的系統功能測試裝置能透過處理器鎖住錯誤的狀態，以保留系統的錯誤狀態，所以，本發明的系統功能測試裝置可以有效率地排除錯誤。Therefore, the functions of the system (such as the mechanical operation system) can be tested efficiently through the start-up and shutdown test sequence, so as to verify whether the system functions normally. Furthermore, when an error message appears in the system signal of the system, the system function test device of the present invention can lock the error state through the processor to retain the error state of the system. Therefore, the system function test device of the present invention can efficiently Eliminate errors.

有關本發明所提供之系統功能測試裝置的組成、特點、電路或方法，將於後續的實施方式詳細說明中予以描述。然而，在本發明領域中具有通常知識者應能瞭解，該等詳細說明以及實施本發明所列舉的特定實施例，僅係用於說明本發明，並非用以限制本發明之專利申請範圍。The composition, characteristics, circuits, or methods of the system function test device provided by the present invention will be described in the detailed description of the following implementation manners. However, those with ordinary knowledge in the field of the present invention should be able to understand that these detailed descriptions and specific examples for implementing the present invention are only used to illustrate the present invention, and are not intended to limit the scope of the patent application of the present invention.

以下，茲配合各圖式列舉對應之較佳實施例來對本發明的系統功能測試裝置的技術特徵及達成功效來作說明。然各圖式中系統功能測試裝置的運作、組成及電路僅用來說明本發明的技術特徵，而非對本發明構成限制。Hereinafter, the corresponding preferred embodiments are listed in conjunction with the drawings to illustrate the technical features and effects of the system function testing device of the present invention. However, the operation, composition, and circuit of the system function test device in each figure are only used to illustrate the technical features of the present invention, but not to limit the present invention.

如圖1所示，圖1是本發明的系統功能測試裝置連接電源及系統的方塊圖。功能測試是測試系統的開機作業及關機作業。開機作業是系統300執行的運作包括電源依序產生、資料初始化及系統載入等。關機作業是系統300執行的運作包括啟動關機流程、資料儲存及電源依序關閉等。系統300可以是自動化設備、機器手臂、或其他機械運作的運行。As shown in FIG. 1, FIG. 1 is a block diagram of the system function test device of the present invention connected to the power supply and the system. The functional test is to test the startup and shutdown operations of the system. The booting operation is the operations performed by the system 300 including sequential power generation, data initialization, and system loading. The shutdown operation is operations performed by the system 300, including initiation of the shutdown process, data storage, and sequential shutdown of the power supply. The system 300 may be an operation of automated equipment, robotic arms, or other mechanical operations.

系統功能測試裝置100是透過開機及關機作業驗證系統300的功能，來確保系統300的品質。系統功能測試裝置100包括第一計時器110、第二計時器130及處理器150。第二計時器130耦接第一計時器110。處理器150耦接第一計時器110及第二計時器130。The system function test device 100 verifies the function of the system 300 through the startup and shutdown operations to ensure the quality of the system 300. The system function test device 100 includes a first timer 110, a second timer 130 and a processor 150. The second timer 130 is coupled to the first timer 110. The processor 150 is coupled to the first timer 110 and the second timer 130.

第一計時器110及第二計時器130建立開機及關機測試時序，以使系統300依開機及關機測試時序進行連續地開機作業及關機作業的測試。The first timer 110 and the second timer 130 establish the power-on and power-off test sequence, so that the system 300 performs continuous power-on and power-off tests according to the power-on and power-off test sequence.

第一計時器110包括電源切換單元111、第一時序選擇單元113及輸出單元115。電源切換單元111連接第一時序選擇單元113及系統電源路徑，系統電源路徑是電源310連接至系統電源供應器330的線路。輸出單元115的輸入端連接第一時序選擇單元113，輸出單元115的輸出端連接電源切換單元111及第二計時器130，輸出單元115透過第一時序選擇單元113充電，且依據第一時序選擇單元113的充電狀態輸出第一輸出信號S U1來控制電源切換單元111及第二計時器130的運作。電源切換單元111的運作包括導通及切斷。在輸出單元115控制電源切換單元111導通時，電源310的電力可供應給系統電源供應器330，在輸出單元115控制電源切換單元111切斷時，電源310的電力不能供應給系統電源供應器330。 The first timer 110 includes a power switching unit 111, a first timing selection unit 113 and an output unit 115. The power switching unit 111 is connected to the first timing selection unit 113 and the system power path, and the system power path is the line connecting the power source 310 to the system power supply 330. The input terminal of the output unit 115 is connected to the first timing selection unit 113, and the output terminal of the output unit 115 is connected to the power switching unit 111 and the second timer 130. The output unit 115 is charged through the first timing selection unit 113 and is charged according to the first timing selection unit 113. The charging state of the timing selection unit 113 outputs the first output signal S U1 to control the operation of the power switching unit 111 and the second timer 130. The operation of the power switching unit 111 includes turning on and off. When the output unit 115 controls the power switching unit 111 to be turned on, the power of the power supply 310 can be supplied to the system power supply 330. When the output unit 115 controls the power switching unit 111 to cut off, the power of the power supply 310 cannot be supplied to the system power supply 330 .

第二計時器130接收第一輸出信號S U1，並依據第一輸出信號S U1運作。第二計時器130輸出第二輸出信號S U2。 The second timer 130 receives the first output signal S U1 and operates according to the first output signal S U1 . The second timer 130 outputs the second output signal S U2 .

處理器150接收第二輸出信號S U2及系統信號S S。正常情況下，在開機及關機測試時序中，且系統信號S S沒有錯誤訊息時，處理器150依據開機及關機測試時序連續地進行開機作業及關機作業的測試。有異常時，在開機及關機測試時序中，且系統信號S S有錯誤訊息時，處理器150鎖定第一計時器110的運作狀態，也就是中斷測試時序，以保留錯誤狀態，供檢查系統300錯誤發生的原因。 The processor 150 receives the second output signal S U2 and the system signal S S. Normally, during the startup and shutdown test sequence and the system signal S S has no error message, the processor 150 continuously performs the startup operation and shutdown operation test according to the startup and shutdown test sequence. When there is an abnormality, during the startup and shutdown test sequence and the system signal S S has an error message, the processor 150 locks the operating state of the first timer 110, that is, interrupts the test sequence to keep the error state for inspection of the system 300 The reason for the error.

系統300的錯誤訊息在開機狀態時的原因包括系統電源未正常啟動、系統資料初始化失敗(例如電源時序、雜訊干擾、電源突波、軟體設計等錯誤)、系統設定載入(例如電源時序、雜訊干擾、電源突波、軟體設計等錯誤)。系統300的錯誤訊息在關機狀態時的原因包括系統啟動關機流程失敗(電路硬體問題、系統軟體當機)、系統資料儲存失敗(未正確執行關機程序、電路記憶元件故障或損壞)、系統電源依序關閉失效(電路硬體問題、系統軟體當機)等。The reasons for the error message of the system 300 in the boot state include the system power supply not starting normally, the system data initialization failure (such as power sequence, noise interference, power surge, software design, etc.), system setting loading (such as power sequence, Noise interference, power surge, software design and other errors). The reasons for the error message of the system 300 in the shutdown state include the failure of the system to start the shutdown process (circuit hardware problem, system software crash), system data storage failure (the shutdown process is not performed correctly, the circuit memory component is faulty or damaged), and the system power supply Sequential shutdown failure (circuit hardware problem, system software crash), etc.

如圖2所示，圖2是本發明的系統功能測試裝置的電路圖，其他實施例中，系統功能測試裝置的電路圖也可以透過其他元件或電路組成，因此，系統功能測試裝置的電路圖不以圖2所繪為限。As shown in Figure 2, Figure 2 is a circuit diagram of the system function test device of the present invention. In other embodiments, the circuit diagram of the system function test device can also be composed of other components or circuits. Therefore, the circuit diagram of the system function test device is not shown 2 is only limited.

電源切換單元111包括第一電晶體Q1及電源開關SW。第一時序選擇單元113包括第一選擇開關SS1、第一電阻器R1、第二電阻器R2、第三電阻器R3、第二電晶體Q2、第三電晶體Q3及第四電晶體Q4。輸出單元115包括第一電容器C1、第四電阻器R4及第一比較器U1。The power switching unit 111 includes a first transistor Q1 and a power switch SW. The first timing selection unit 113 includes a first selection switch SS1, a first resistor R1, a second resistor R2, a third resistor R3, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4. The output unit 115 includes a first capacitor C1, a fourth resistor R4, and a first comparator U1.

第一電晶體Q1的汲極連接電源Vcc，第一電晶體Q1的閘極連接第一選擇開關SS1的共點，第一電晶體Q1的源極連接電源開關SW。電源開關SW用以控制電源310是否供應給系統電源供應器330。The drain of the first transistor Q1 is connected to the power supply Vcc, the gate of the first transistor Q1 is connected to the common point of the first selection switch SS1, and the source of the first transistor Q1 is connected to the power switch SW. The power switch SW is used to control whether the power 310 is supplied to the system power supply 330.

電源Vcc串聯連接第一電阻器R1、第二電阻器R2及第三電阻器R3。第一選擇開關SS1的三個輸出端分別連接第二電晶體Q2的閘極、第三電晶體Q3的閘極及第四電晶體Q4的閘極。第二電晶體Q2的源極連接第一電阻器R1與第二電阻器R2串聯的線路，第三電晶體Q3的源極連接第二電阻器R2與第三電阻器R3串聯的線路，第四電晶體Q4的源極連接第三電阻器R3。第一電容器C1的一端連接第二電晶體Q2的汲極、第三電晶體Q3汲極及第四電晶體Q4的汲極，第一電容器C1的另一端連接至接地端。第四電阻器R4連接第一電容器C1及第一比較器U1的正極(+)輸入端。第一比較器U1的負極(-)輸入端接收第一參考訊號S R1，第一參考訊號S R1是第一比較器U1的轉態電壓值，電壓值可以是固定值。第一比較器U1的輸出端連接第一電晶體Q1的閘極及第一選擇開關SS1的共點。 The power source Vcc is connected in series with the first resistor R1, the second resistor R2, and the third resistor R3. The three output terminals of the first selection switch SS1 are respectively connected to the gate of the second transistor Q2, the gate of the third transistor Q3, and the gate of the fourth transistor Q4. The source of the second transistor Q2 is connected to the line connecting the first resistor R1 and the second resistor R2 in series, the source of the third transistor Q3 is connected to the line connecting the second resistor R2 and the third resistor R3 in series, and the fourth The source of the transistor Q4 is connected to the third resistor R3. One end of the first capacitor C1 is connected to the drain of the second transistor Q2, the drain of the third transistor Q3 and the drain of the fourth transistor Q4, and the other end of the first capacitor C1 is connected to the ground. The fourth resistor R4 is connected to the first capacitor C1 and the positive (+) input terminal of the first comparator U1. The negative (-) input terminal of the first comparator U1 receives the first reference signal S R1 . The first reference signal S R1 is the transition voltage value of the first comparator U1, and the voltage value may be a fixed value. The output terminal of the first comparator U1 is connected to the common point of the gate of the first transistor Q1 and the first selection switch SS1.

第二計時器130包括充電單元131及第二時序選擇單元133。充電單元131連接輸出單元115的輸出端、第二時序選擇單元133及處理器150，第一輸出信號S U1控制充電單元131充電，充電單元131透過第二時序選擇單元133放電。在充電單元131是放電狀態，且系統信號S S沒有錯誤訊息時，處理單元150允許輸出單元115放電。系統信號S S有錯誤訊息時，處理單元150不允許輸出單元115放電。 The second timer 130 includes a charging unit 131 and a second timing selection unit 133. The charging unit 131 is connected to the output terminal of the output unit 115, the second timing selection unit 133 and the processor 150. The first output signal S U1 controls the charging unit 131 to charge, and the charging unit 131 discharges through the second timing selection unit 133. When the charging unit 131 is in a discharging state and the system signal S S has no error message, the processing unit 150 allows the output unit 115 to discharge. When the system signal S S has an error message, the processing unit 150 does not allow the output unit 115 to discharge.

充電單元131包括第五電阻器R5、第五電晶體Q5及第二電容器C2。第五電阻器R5串聯連接電源Vcc及第五電晶體Q5的源極。第五電晶體Q5的閘極連接第一比較器U1的輸出端。第二電容器C2串聯連接第五電晶體Q5的汲極及接地端。The charging unit 131 includes a fifth resistor R5, a fifth transistor Q5, and a second capacitor C2. The fifth resistor R5 is connected in series with the power source Vcc and the source of the fifth transistor Q5. The gate of the fifth transistor Q5 is connected to the output terminal of the first comparator U1. The second capacitor C2 is connected in series to the drain of the fifth transistor Q5 and the ground terminal.

第二時序選擇單元133包括第六電阻器R6、第七電阻器R7、第八電阻器R8、第六電晶體Q6、第七電晶體Q7、第八電晶體Q8及第二選擇開關SS2。The second timing selection unit 133 includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, and a second selection switch SS2.

第六電晶體Q6的汲極、第七電晶體Q7的汲極、第八電晶體Q8的汲極連接第二電容器C2。第六電晶體Q6的源極串聯連接第六電阻器R6、第七電阻器R7、第八電阻器R8及接地端。第七電晶體Q7的源極連接第六電阻器R6及第七電阻器R7的串聯路徑。第八電晶體Q8的源極連接第七電阻器R7及第八電阻器R8的串聯路徑。第六電晶體Q6的閘極、第七電晶體Q7的閘極及第八電晶體Q8的閘極分別連接第二選擇開關SS2的輸出接點。第二選擇開關SS2的共點連接第一比較器U1的輸出端。The drain of the sixth transistor Q6, the drain of the seventh transistor Q7, and the drain of the eighth transistor Q8 are connected to the second capacitor C2. The source of the sixth transistor Q6 is connected in series with the sixth resistor R6, the seventh resistor R7, the eighth resistor R8 and the ground terminal. The source of the seventh transistor Q7 is connected to the series path of the sixth resistor R6 and the seventh resistor R7. The source of the eighth transistor Q8 is connected to the series path of the seventh resistor R7 and the eighth resistor R8. The gate of the sixth transistor Q6, the gate of the seventh transistor Q7, and the gate of the eighth transistor Q8 are respectively connected to the output contact of the second selection switch SS2. The common point of the second selection switch SS2 is connected to the output terminal of the first comparator U1.

處理器150包括第二比較器U2、第一二極體D1、第二二極體D2、第九電阻器R9、第十電阻器R10、第十一電阻器R11、第十二電阻器R12、第九電晶體Q9、第十電晶體Q10。The processor 150 includes a second comparator U2, a first diode D1, a second diode D2, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, The ninth transistor Q9 and the tenth transistor Q10.

第二比較器U2的正極(+)輸入端連接第二電容器C2。第二比較器U2的負極(-)輸入端連接第二參考訊號S R2，第二參考訊號S R2是第二比較器U2的轉態電壓值，電壓值可以是固定值。第一二極體D1串聯連接第二比較器U2的輸出端及第九電阻器R9。第二二極體D2連接系統300及第九電阻器R9，且接收系統信號S S。第十電阻器R10連接第九電阻器R9及接地端。第九電晶體Q9的基極連接第九電阻器R9，第九電晶體Q9的射極連接接地端。第十一電阻器R11連接電源Vcc及第九電晶體Q9的集極。第九電晶體Q9的集極連接第十電晶體Q10的閘極。第十二電阻器R12連接第十電晶體Q10的源極及接地端。第十電晶體Q10的汲極連接第一電容器C1。 The positive (+) input terminal of the second comparator U2 is connected to the second capacitor C2. The negative (-) input terminal of the second comparator U2 is connected to the second reference signal S R2 . The second reference signal S R2 is the transition voltage value of the second comparator U2, and the voltage value may be a fixed value. The first diode D1 is connected in series with the output terminal of the second comparator U2 and the ninth resistor R9. The second diode D2 is connected to the system 300 and the ninth resistor R9, and receives the system signal S S. The tenth resistor R10 is connected to the ninth resistor R9 and the ground terminal. The base of the ninth transistor Q9 is connected to the ninth resistor R9, and the emitter of the ninth transistor Q9 is connected to the ground terminal. The eleventh resistor R11 is connected to the power source Vcc and the collector of the ninth transistor Q9. The collector of the ninth transistor Q9 is connected to the gate of the tenth transistor Q10. The twelfth resistor R12 is connected to the source and ground of the tenth transistor Q10. The drain of the tenth transistor Q10 is connected to the first capacitor C1.

開機及關機測試時序可以透過第一計時器110及第二計時器130來調整，開機及關機測試時序包括開機時間及關機時間，開機時間及關機時間可透過第一計時器110及第二計時器130來調整比率。本實施例中是透過調整第一時序選擇單元113的第一選擇開關SS1及第二時序選擇單元133的第二選擇開關SS2來調整，調整第一選擇開關SS1可以改變第一電容器C1的充電時間，調整第二選擇開關可以改變第二電容器C2的放電時間。因此，進行功能測試前可先決定第一計時器110及第二計時器130的計時時間。其他實施例中，第一計時器110及第二計時器130的計時方式也可以透過其他計時電路或積體電路來達成。The power-on and power-off test sequence can be adjusted through the first timer 110 and the second timer 130. The power-on and power-off test sequence includes the power-on time and the power-off time. The power-on time and the power-off time can be adjusted through the first timer 110 and the second timer 130 to adjust the ratio. In this embodiment, it is adjusted by adjusting the first selection switch SS1 of the first timing selection unit 113 and the second selection switch SS2 of the second timing selection unit 133. Adjusting the first selection switch SS1 can change the charging of the first capacitor C1. Time, adjusting the second selection switch can change the discharge time of the second capacitor C2. Therefore, the timing of the first timer 110 and the second timer 130 can be determined before performing the function test. In other embodiments, the timing methods of the first timer 110 and the second timer 130 can also be achieved through other timing circuits or integrated circuits.

準備功能測試前，第一電容器C1及第二電容器C2的初始電壓都是0伏特(V)，本實施例中，電源Vcc依據第一選擇開關SS1選擇第二電晶體Q2作為第一電容器C1的充電路徑，第二選擇開關SS2選擇第六電晶體Q6作為第二電容器C2的放電路徑，透過圖2的電路圖能理解改變第一時序選擇器113及第二時序選擇器133的電阻值可以有效調整開機及關機測試時序的開機時間及關機時間的比率。Before preparing for the functional test, the initial voltages of the first capacitor C1 and the second capacitor C2 are both 0 volts (V). In this embodiment, the power supply Vcc selects the second transistor Q2 as the first capacitor C1 according to the first selection switch SS1. The charging path, the second selector switch SS2 selects the sixth transistor Q6 as the discharge path of the second capacitor C2. It can be understood from the circuit diagram of FIG. 2 that changing the resistance values of the first timing selector 113 and the second timing selector 133 can be effective Adjust the ratio of power-on time and power-off time of the power-on and power-off test sequence.

如圖3所示，初始時，第一比較器U1的輸出是低準位(例如0)，因此，第一電容器C1的電壓V C1建立透過第一電阻器R1的電流I R1充電，電流I R1流過第一電阻器R1及第二電晶體Q2形成路徑從0V充電至高電壓準位，觸發第一比較器U1從低準位轉態為高準位(例如1)，轉態代表第一電容器C1的電壓值超過第一參考訊號S R1，而使第一選擇開關SS1觸發第二電晶體Q2被關閉，即停止第一電容器C1的充電。 As shown in Fig. 3, initially, the output of the first comparator U1 is at a low level (for example, 0). Therefore, the voltage V C1 of the first capacitor C1 establishes the charging of the current I R1 through the first resistor R1 , and the current I R1 flows through the first resistor R1 and the second transistor Q2 to form a path that charges from 0V to a high voltage level, triggering the first comparator U1 to transition from a low level to a high level (for example, 1). The transition represents the first The voltage value of the capacitor C1 exceeds the first reference signal S R1 , and the first selection switch SS1 triggers the second transistor Q2 to be turned off, that is, the charging of the first capacitor C1 is stopped.

在第一比較器U1從低準位轉態為高準位時，第一電晶體Q1被觸發而導通，以控制電源開關SW允許電源310供應給系統電源供應器330，隨後即開始進行功能測試。在第一比較器U1從低準位轉態為高準位時，是進行開機及關機測試程序的開機時間T ON。 When the first comparator U1 transitions from a low level to a high level, the first transistor Q1 is triggered and turned on to control the power switch SW to allow the power supply 310 to be supplied to the system power supply 330, and then the functional test will begin . When the first comparator U1 transitions from a low level to a high level, it is the turn-on time T ON for the startup and shutdown test procedures.

初始同時，第一比較器U1的輸出是低準位，第五電晶體Q5是導通，以使第二電容器C2建立電壓V C2，電壓V C2的建立是第五電阻器R5的電流I R5向第二電容器C2充電，電流I R5流過第五電晶體Q5及第五電阻器R5向第二電容器C2充電，第二電容C2的電壓值是控制第二比較器U2是否轉態。之後在第一比較器U1從低準位轉態為高準位後，第五電晶體Q5是截止，即停止第二電容器C2的充電，並觸發第六電晶體Q6導通，而使第六電晶體Q6、第六電阻器R6、第七電阻器R7及第八電阻器R8形成第二電容器C2的放電路徑。 Initial Meanwhile, the output of the first comparator U1 is a low level, the fifth transistor Q5 is turned on, so that the second capacitor C2 Establishment voltage V C2, the voltage V C2 is the fifth resistor R5 of the current to the I R5 The second capacitor C2 is charged, and the current I R5 flows through the fifth transistor Q5 and the fifth resistor R5 to charge the second capacitor C2. The voltage value of the second capacitor C2 controls whether the second comparator U2 is switched. After the first comparator U1 transitions from a low level to a high level, the fifth transistor Q5 is turned off, that is, the charging of the second capacitor C2 is stopped, and the sixth transistor Q6 is triggered to turn on, so that the sixth transistor Q6 is turned on. The crystal Q6, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 form a discharge path of the second capacitor C2.

隨後，系統300沒有產生或輸出錯誤訊息(ERR)的系統信號S S，且第二電容器C2透過第二時序選擇單元133放電至相對低的電壓值時，第二比較器U2從高準位轉態為低準位時，觸發第九電晶體Q9截止(如圖3中第九電晶體Q9的V CEQ9變化，是集極-射極間的電壓變化)，使得電源Vcc觸發第十電晶體Q10導通，讓第一電容器C1透過導通的第十電晶體Q10及第十二電阻器R12進行放電(如圖3中第十二電阻器R12的電流I R12)，隨後，第一電容器C1從充飽電的高電壓放電至低電壓，讓第一比較器U1從高準位轉態為低準位，而進入開機及關機測試程序的關機時間T OFF，隨後，重複上述步驟再次對第一電容器C1及第二電容器C2充電，以持續執行開機及關機測試程序。 Subsequently, when the system 300 does not generate or output the error message (ERR) system signal S S and the second capacitor C2 is discharged to a relatively low voltage value through the second timing selection unit 133, the second comparator U2 is switched from the high level When the state is at a low level, the ninth transistor Q9 is triggered to turn off (the change in V CEQ9 of the ninth transistor Q9 in Figure 3 is the voltage change between the collector and the emitter), so that the power supply Vcc triggers the tenth transistor Q10 Turn on, allowing the first capacitor C1 to discharge through the turned-on tenth transistor Q10 and the twelfth resistor R12 (as shown in Figure 3 for the current I R12 of the twelfth resistor R12 ), and then the first capacitor C1 is fully charged The high voltage of the electricity is discharged to a low voltage, so that the first comparator U1 transitions from a high level to a low level, and enters the shutdown time T OFF of the power-on and shutdown test program, and then repeats the above steps again to the first capacitor C1 And the second capacitor C2 is charged to continuously perform the startup and shutdown test procedures.

如圖4所示，當系統300產生或輸出存在錯誤訊息(ERR)的系統信號S S時，圖中錯誤訊息ERR從低準位轉態為高準位，系統信號S S透過第二二極體D2及第九電阻器R9優先觸發第九電晶體Q9導通，如此，充飽電的第一電容器C1是不能透過處理器150來放電，也就是處理器150不允許輸出單元115放電，因此，轉態後，第一電阻器R1的電流I R1、第一電容器C1的電壓V C1及第一比較器U1的輸出準位都維持在轉態時的狀態，且第十二電阻器R12的電流I R12沒有發生放電現象，如此，停止開機及關機測試時序，第一計時器的狀態被鎖住，也就是鎖住系統的錯誤訊息。 As shown in Figure 4, when the system 300 generates or outputs a system signal S S with an error message (ERR), the error message ERR in the figure transitions from a low level to a high level, and the system signal S S passes through the second diode The body D2 and the ninth resistor R9 preferentially trigger the ninth transistor Q9 to turn on, so that the fully charged first capacitor C1 cannot be discharged through the processor 150, that is, the processor 150 does not allow the output unit 115 to discharge. Therefore, After the transition, the current I R1 of the first resistor R1 , the voltage V C1 of the first capacitor C1 and the output level of the first comparator U1 are all maintained at the state at the transition, and the current of the twelfth resistor R12 I R12 does not discharge. In this way, the power-on and power-off test sequence is stopped, and the state of the first timer is locked, that is, the system error message is locked.

綜上所述，本發明的系統功能測試裝置可以透過調整第一計時器及第二計時器而改變開機及關機測試時序的開機時間及關機時間的比率，且可透過處理器實現重複執行系統開機作業及系統關機作業，並可在系統發生錯誤時，鎖住系統錯誤訊息，以供判斷錯誤原因，來提高系統的測試及錯誤排除的效率。To sum up, the system function test device of the present invention can change the ratio of the power-on time and the power-off time of the power-on and power-off test sequence by adjusting the first timer and the second timer, and can repeatedly perform system booting through the processor. Operation and system shutdown operations, and when a system error occurs, the system error message can be locked for determining the cause of the error, so as to improve the efficiency of system testing and error elimination.

最後，再次強調，本發明於前揭實施例中所揭露的步驟順序、構成元件，僅為舉例說明，並非用來限制本案之範圍，其他步驟順序的改變、等效元件的替代或變化，亦應為本案之申請專利範圍所涵蓋。Finally, it is emphasized again that the sequence of steps and constituent elements disclosed in the previous embodiments of the present invention are merely examples and are not intended to limit the scope of the case. Changes in the sequence of other steps, substitutions or changes of equivalent elements are also applicable. It should be covered by the scope of patent application in this case.

100系統功能測試裝置        110第一計時器               111電源切換單元 113第一時序選擇單元        115輸出單元                   130第二計時器 131充電單元                       133第二時序選擇單元   150處理器 300系統                               310電源                          330系統電源供應器 S U1第一輸出信號                S U2第二輸出信號            S S系統信號 R1第一電阻器                     R2第二電阻器                R3第三電阻器 R4第四電阻器                     R5第五電阻器                R6第六電阻器 R7第七電阻器                     R8第八電阻器                R9第九電阻器 R10第十電阻器                   R11第十一電阻器           R12第十二電阻器 Q1第一電晶體                     Q2第二電晶體                Q3第三電晶體 Q4第四電晶體                     Q5第五電晶體                Q6第六電晶體 Q7第七電晶體                     Q8第八電晶體                Q9第九電晶體 Q10第十電晶體                   C1第一電容器                C2第二電容器 U1第一比較器                     U2第二比較器                D1第一二極體 D2第二二極體                     SW電源開關                   SS1第一選擇開關 SS2第二選擇開關               Vcc電源 ERR錯誤訊息                      T ON開機時間                   T OFF關機時間 100 system function test device 110 first timer 111 power switching unit 113 first timing selection unit 115 output unit 130 second timer 131 charging unit 133 second timing selection unit 150 processor 300 system 310 power supply 330 system power supply S U1 first output signal S U2 second output signal S S system signal R1 first resistor R2 second resistor R3 third resistor R4 fourth resistor R5 fifth resistor R6 sixth resistor R7 seventh resistor Resistor R8 eighth resistor R9 ninth resistor R10 tenth resistor R11 eleventh resistor R12 twelfth resistor Q1 first transistor Q2 second transistor Q3 third transistor Q4 fourth transistor Q5 Five Transistor Q6 Sixth Transistor Q7 Seventh Transistor Q8 Eighth Transistor Q9 Ninth Transistor Q10 Tenth Transistor C1 First Capacitor C2 Second Capacitor U1 First Comparator U2 Second Comparator D1 First Two Polar body D2 second diode SW power switch SS1 first selection switch SS2 second selection switch Vcc power supply ERR error message T ON power-on time T OFF power-off time

圖1是本發明的系統功能測試裝置連接系統的方塊示意圖。 圖2是圖1中本發明的系統功能測試裝置的電路圖。 圖3是圖1中本發明的系統功能測試裝置在系統信號沒有錯誤訊息的時序圖。 圖4是圖1中本發明的系統功能測試裝置在系統信號有錯誤訊息的時序圖。Fig. 1 is a block diagram of the connection system of the system function test device of the present invention. Fig. 2 is a circuit diagram of the system function test device of the present invention in Fig. 1. 3 is a timing diagram of the system function test device of the present invention in FIG. 1 when there is no error message in the system signal. FIG. 4 is a timing diagram of the system function test device of the present invention in FIG. 1 when the system signal has an error message.

100系統功能測試裝置        110第一計時器               111電源切換單元 113第一時序選擇單元        115輸出單元                   130第二計時器 150處理器                           300系統                          310電源 330系統電源供應器 S U1第一輸出信號                S U2第二輸出信號            S S系統信號 100 system function test device 110 first timer 111 power switching unit 113 first timing selection unit 115 output unit 130 second timer 150 processor 300 system 310 power supply 330 system power supply S U1 first output signal S U2 Two output signal S S system signal

Claims (7)

一種系統功能測試裝置，包括： 　　一第一計時器； 　　一第二計時器，耦接該第一計時器；及 　　一處理器，耦接該第一計時器及該第二計時器，且接收一系統信號，其中，該第一計時器及該第二計時器建立一開機及關機測試時序，在該開機及關機測試時序中，且該系統信號包括一錯誤訊息時，該處理器鎖定該第一計時器的狀態，且停止該開機及關機測試時序。A system function testing device includes: a first timer; a second timer coupled to the first timer; and a processor coupled to the first timer and the second timer, and receives a System signal, wherein the first timer and the second timer establish a power-on and power-off test sequence, in the power-on and power-off test sequence, and the system signal includes an error message, the processor locks the first The state of the timer, and stop the startup and shutdown test sequence. 如申請專利範圍第1項所述的系統功能測試裝置，其中，在該系統信號不包括該錯誤訊息時，該第二計時器通知該處理器允許該第一計時器持續執行該開機及關機測試時序。For example, the system function test device described in claim 1, wherein, when the system signal does not include the error message, the second timer informs the processor to allow the first timer to continue to perform the power-on and power-off test Timing. 如申請專利範圍第1項所述的系統功能測試裝置，其中，該開機及關機測試時序包括一開機時間及一關機時間，該開機時間是定義一系統執行一開機作業，該關機時間是定義該系統執行一關機作業。For example, the system function test device described in item 1 of the scope of patent application, wherein the startup and shutdown test sequence includes a startup time and a shutdown time. The startup time defines a system to perform a startup operation, and the shutdown time defines the The system performs a shutdown operation. 如申請專利範圍第3項所述的系統功能測試裝置，其中，該第一計時器包括一第一時序選擇單元，該第二計時器包括一第二時序選擇單元，該第一時序選擇單元及該第二時序選擇單元是透過調整電阻值來改變該開機時間及該關機時間。The system function test device according to item 3 of the scope of patent application, wherein the first timer includes a first timing selection unit, the second timer includes a second timing selection unit, and the first timing selection The unit and the second timing selection unit change the power-on time and the power-off time by adjusting the resistance value. 如申請專利範圍第4項所述的系統功能測試裝置，其中，該第一計時器還包括一電源切換單元及一輸出單元，該電源切換單元連接該第一時序選擇單元及一系統電源路徑，該輸出單元的輸入端連接該第一時序選擇單元，該輸出單元的輸出端連接該電源切換單元及該第二計時器，該輸出單元透過該第一時序選擇單元充電，且依據充電狀態輸出一第一輸出信號控制該電源切換單元及該第二計時器。According to the system function test device described in claim 4, the first timer further includes a power switching unit and an output unit, and the power switching unit is connected to the first timing selection unit and a system power path , The input end of the output unit is connected to the first timing selection unit, the output end of the output unit is connected to the power switching unit and the second timer, the output unit is charged through the first timing selection unit, and is charged according to the charging The state outputs a first output signal to control the power switching unit and the second timer. 如申請專利範圍第5項所述的系統功能測試裝置，其中，該第二計時器還包括一充電單元，該充電單元連接該輸出單元的輸出端、該第二時序選擇單元及該處理器，該第一輸出信號控制該充電單元充電，該充電單元透過該第二時序選擇單元放電。For the system function test device described in item 5 of the scope of patent application, the second timer further includes a charging unit connected to the output terminal of the output unit, the second timing selection unit and the processor, The first output signal controls the charging unit to charge, and the charging unit discharges through the second timing selection unit. 如申請專利範圍第6項所述的系統功能測試裝置，其中，在該充電單元是放電狀態，且該系統信號沒有該錯誤訊息時，該處理單元允許該輸出單元放電，該系統信號有該錯誤訊息時，該處理單元不允許該輸出單元放電。For example, the system function test device described in item 6 of the scope of patent application, wherein, when the charging unit is in a discharged state and the system signal does not have the error message, the processing unit allows the output unit to discharge, and the system signal has the error When sending a message, the processing unit does not allow the output unit to discharge.
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