TWI710823B - Display apparatus - Google Patents
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- TWI710823B TWI710823B TW109125703A TW109125703A TWI710823B TW I710823 B TWI710823 B TW I710823B TW 109125703 A TW109125703 A TW 109125703A TW 109125703 A TW109125703 A TW 109125703A TW I710823 B TWI710823 B TW I710823B
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Abstract
Description
本發明是有關於一種電子裝置,且特別是有關於一種顯示裝置。The present invention relates to an electronic device, and more particularly to a display device.
隨著科技產業日益發達,例如是行動電話(mobile phone)、平板電腦(tablet computer)或電子書(eBook)等顯示裝置已被廣泛應用於日常生活中。尤其近年來,隨著立體顯示(stereoscopic display)及虛擬實境(virtual reality)等多媒體應用的出現,為了提供令人驚豔的視覺效果,具超高解析度的顯示裝置的需求逐漸增加。With the development of the technology industry, display devices such as mobile phones, tablet computers, or eBooks have been widely used in daily life. Especially in recent years, with the emergence of multimedia applications such as stereoscopic display and virtual reality, in order to provide stunning visual effects, the demand for ultra-high-resolution display devices has gradually increased.
在顯示裝置解析度不斷地提高下,將驅動電路以疊層的架構設計在顯示元件層的下方,以解決驅動電路之可佈局空間的不足,是目前的解決方案之一。然而,利用疊層架構的方式,勢必會增加製造的難度與生產成本。因此,在驅動電路的設計採用疊層架構下,如何降低製造的難度與生產成本是一個重要的課題。As the resolution of the display device continues to improve, it is one of the current solutions to design the driving circuit in a stacked structure below the display element layer to solve the shortage of the layout space of the driving circuit. However, the use of a stacked structure is bound to increase the difficulty of manufacturing and production costs. Therefore, how to reduce the manufacturing difficulty and production cost is an important issue when the design of the driving circuit adopts a stacked structure.
本發明提供一種顯示裝置,易製造。The invention provides a display device which is easy to manufacture.
本發明一實施例的顯示裝置,包括基底、第一電路層、第一黏著層、第二電路層、第一導電元件及顯示元件層。第一電路層設置於基底上。第一黏著層設置於第一電路層上。第二電路層設置於第一黏著層上。第一導電元件設置於第二電路層上,且電性連接至第二電路層。第一黏著層具有第一開口,而第一導電元件透過第一黏著層的第一開口電性連接至第一電路層。顯示元件層設置於第二電路層上,且電性連接至第二電路層。The display device of an embodiment of the present invention includes a substrate, a first circuit layer, a first adhesive layer, a second circuit layer, a first conductive element, and a display element layer. The first circuit layer is arranged on the substrate. The first adhesive layer is disposed on the first circuit layer. The second circuit layer is arranged on the first adhesive layer. The first conductive element is disposed on the second circuit layer and is electrically connected to the second circuit layer. The first adhesive layer has a first opening, and the first conductive element is electrically connected to the first circuit layer through the first opening of the first adhesive layer. The display element layer is disposed on the second circuit layer and is electrically connected to the second circuit layer.
在本發明的一實施例中,上述的第二電路層包括薄膜電晶體,薄膜電晶體具有閘極、半導體圖案和設置於閘極與半導體圖案之間的絕緣子層,絕緣子層具有設置於半導體圖案外的第一開口;第一導電元件透過第二電路層之薄膜電晶體之絕緣子層的第一開口及第一黏著層的第一開口電性連接至第一電路層。In an embodiment of the present invention, the above-mentioned second circuit layer includes a thin film transistor. The thin film transistor has a gate, a semiconductor pattern, and an insulating sublayer disposed between the gate and the semiconductor pattern, and the insulating sublayer has a semiconductor pattern disposed on the semiconductor pattern. Outer first opening; the first conductive element is electrically connected to the first circuit layer through the first opening of the insulating sub-layer of the thin film transistor of the second circuit layer and the first opening of the first adhesive layer.
在本發明的一實施例中,上述的第二電路層之薄膜電晶體之絕緣子層的第一開口及第一黏著層的第一開口實質上對齊。In an embodiment of the present invention, the first opening of the insulating sub-layer of the thin film transistor of the second circuit layer and the first opening of the first adhesive layer are substantially aligned.
在本發明的一實施例中,上述的第一電路層包括薄膜電晶體,而第一導電元件電性連接至第一電路層的薄膜電晶體及第二電路層的薄膜電晶體。In an embodiment of the present invention, the above-mentioned first circuit layer includes a thin film transistor, and the first conductive element is electrically connected to the thin film transistor of the first circuit layer and the thin film transistor of the second circuit layer.
在本發明的一實施例中,上述的第一電路層更包括匯流線,第一電路層之薄膜電晶體電性連接至第一電路層的匯流線;第二電路層更包括匯流線,第二電路層之薄膜電晶體電性連接至第二電路層的匯流線。顯示裝置更包括第二導電元件,設置於第二電路層上,且電性連接至第二電路層的匯流線。第二電路層之薄膜電晶體的絕緣子層更具有設置於半導體圖案外的第二開口,第一黏著層更具有第二開口,且第二導電元件透過第二電路層之薄膜電晶體之絕緣子層的第二開口及第一黏著層的第二開口電性連接至第一電路層的匯流線。In an embodiment of the present invention, the above-mentioned first circuit layer further includes a bus line, the thin film transistor of the first circuit layer is electrically connected to the bus line of the first circuit layer; the second circuit layer further includes a bus line, The thin film transistors of the two circuit layers are electrically connected to the bus lines of the second circuit layer. The display device further includes a second conductive element disposed on the second circuit layer and electrically connected to the bus line of the second circuit layer. The insulating sublayer of the thin film transistor of the second circuit layer further has a second opening disposed outside the semiconductor pattern, the first adhesive layer further has a second opening, and the second conductive element penetrates the insulating sublayer of the thin film transistor of the second circuit layer The second opening of and the second opening of the first adhesive layer are electrically connected to the bus line of the first circuit layer.
在本發明的一實施例中,上述的顯示裝置,更包括第二黏著層、第三元件層以及第三導電元件。第二黏著層設置於第一電路層與基底之間。第三元件層包括匯流線,其中第三元件層的匯流線設置於第二黏著層與基底之間。第三導電元件設置於第一電路層上,且電性連接至第一電路層的薄膜電晶體。第三導電元件透過第二黏著層的開口電性連接至第三元件層的匯流線。In an embodiment of the present invention, the aforementioned display device further includes a second adhesive layer, a third element layer, and a third conductive element. The second adhesive layer is disposed between the first circuit layer and the substrate. The third element layer includes a bus line, wherein the bus line of the third element layer is disposed between the second adhesive layer and the substrate. The third conductive element is disposed on the first circuit layer and is electrically connected to the thin film transistor of the first circuit layer. The third conductive element is electrically connected to the bus line of the third element layer through the opening of the second adhesive layer.
在本發明的一實施例中,上述的第一電路層的薄膜電晶體具有閘極、半導體圖案和設置於閘極與半導體圖案之間的絕緣子層,第一電路層的絕緣子層具有設置於第一電路層之半導體圖案外的開口,第三導電元件透過第一電路層之薄膜電晶體之絕緣子層的開口及第二黏著層的開口電性連接至第三元件層的匯流線。In an embodiment of the present invention, the above-mentioned thin film transistor of the first circuit layer has a gate, a semiconductor pattern, and an insulating sublayer disposed between the gate and the semiconductor pattern, and the insulating sublayer of the first circuit layer has a An opening outside the semiconductor pattern of a circuit layer, the third conductive element is electrically connected to the bus line of the third element layer through the opening of the insulating sub-layer of the thin film transistor of the first circuit layer and the opening of the second adhesive layer.
在本發明的一實施例中,上述的第一電路層之薄膜電晶體之絕緣子層的開口及第二黏著層的開口實質上對齊。In an embodiment of the present invention, the openings of the insulating sub-layer of the thin film transistor of the first circuit layer and the openings of the second adhesive layer are substantially aligned.
在本發明的一實施例中,上述的第一電路層包括匯流線,而第一導電元件電性連接至第一電路層的匯流線及第二電路層的薄膜電晶體。In an embodiment of the present invention, the aforementioned first circuit layer includes a bus line, and the first conductive element is electrically connected to the bus line of the first circuit layer and the thin film transistor of the second circuit layer.
在本發明的一實施例中,上述的第一導電元件包括第一部及第二部。第一部至少設置於第一黏著層的第一開口。第二部至少設置於第二電路層之薄膜電晶體之絕緣子層的第一開口,其中第一部與第二部具有交界面。In an embodiment of the present invention, the aforementioned first conductive element includes a first part and a second part. The first part is at least disposed in the first opening of the first adhesive layer. The second part is disposed at least at the first opening of the insulating sub-layer of the thin film transistor of the second circuit layer, wherein the first part and the second part have an interface.
在本發明的一實施例中,上述的第二電路層的薄膜電晶體更具有第一電極和第二電極,分別電性連接至半導體圖案的不同兩區。第一導電元件的至少一部分、第二電路層之薄膜電晶體的第一電極及第二電路層之薄膜電晶體的第二電極形成於同一膜層。In an embodiment of the present invention, the above-mentioned thin film transistor of the second circuit layer further has a first electrode and a second electrode, which are respectively electrically connected to two different regions of the semiconductor pattern. At least a part of the first conductive element, the first electrode of the thin film transistor of the second circuit layer and the second electrode of the thin film transistor of the second circuit layer are formed on the same film layer.
在本發明的一實施例中,上述的顯示元件層包括畫素電極、畫素定義子層、有機電致發光材料以及共用電極。畫素電極設置於第二電路層上,且電性連接至第二電路層。畫素定義子層設置於畫素電極上,且具有與畫素電極重疊的開口。有機電致發光材料設置於畫素定義子層的開口。共用電極設置於有機電致發光材料上。第一導電元件的一部分設置於畫素定義子層與第二電路層之間。In an embodiment of the present invention, the above-mentioned display element layer includes a pixel electrode, a pixel defining sublayer, an organic electroluminescent material, and a common electrode. The pixel electrode is arranged on the second circuit layer and is electrically connected to the second circuit layer. The pixel definition sub-layer is disposed on the pixel electrode and has an opening overlapping the pixel electrode. The organic electroluminescent material is arranged in the opening of the pixel definition sublayer. The common electrode is arranged on the organic electroluminescent material. A part of the first conductive element is arranged between the pixel definition sublayer and the second circuit layer.
在本發明的一實施例中,上述的第一導電元件的一部分共形地設置於由第一黏著層之第一開口所定義的凹槽。In an embodiment of the present invention, a part of the above-mentioned first conductive element is conformally disposed in the groove defined by the first opening of the first adhesive layer.
本發明提供一種顯示裝置,具觸控功能且彎折耐受度佳。The invention provides a display device with touch function and good bending tolerance.
本發明一實施例的顯示裝置,包括基底、電路層、顯示元件層、接墊、第一黏著層、觸控元件層以及導電元件。電路層設置於基底上。顯示元件層設置於電路層上,且電性連接至電路層。接墊設置於基底上。第一黏著層設置於顯示元件層上。觸控元件層設置於第一黏著層上。導電元件設置於觸控元件層上,且電性連接至觸控元件層。第一黏著層具有開口,而導電元件透過第一黏著層的開口電性連接至接墊。A display device according to an embodiment of the present invention includes a substrate, a circuit layer, a display element layer, a pad, a first adhesive layer, a touch element layer, and a conductive element. The circuit layer is arranged on the substrate. The display element layer is disposed on the circuit layer and is electrically connected to the circuit layer. The pad is arranged on the base. The first adhesive layer is disposed on the display element layer. The touch element layer is disposed on the first adhesive layer. The conductive element is arranged on the touch element layer and is electrically connected to the touch element layer. The first adhesive layer has an opening, and the conductive element is electrically connected to the pad through the opening of the first adhesive layer.
在本發明的一實施例中,上述的觸控元件層包括感測電極、周邊線路及絕緣子層。感測電極及周邊線路彼此電性連接。絕緣子層設置於感測電極與第一黏著層之間以及周邊線路與第一黏著層之間,且具有開口。導電元件電性連接至周邊線路,且透過絕緣子層的開口及第一黏著層的開口電性連接至接墊。In an embodiment of the present invention, the aforementioned touch element layer includes a sensing electrode, a peripheral circuit, and an insulating sublayer. The sensing electrode and the peripheral circuit are electrically connected to each other. The insulating sub-layer is disposed between the sensing electrode and the first adhesive layer and between the peripheral circuit and the first adhesive layer, and has an opening. The conductive element is electrically connected to the peripheral circuit, and is electrically connected to the pad through the opening of the insulating sub-layer and the opening of the first adhesive layer.
在本發明的一實施例中,上述的絕緣子層的開口及第一黏著層的開口實質上對齊。In an embodiment of the present invention, the openings of the aforementioned insulating sub-layer and the openings of the first adhesive layer are substantially aligned.
在本發明的一實施例中,上述的導電元件包括第一部及第二部。第一部至少設置於第一黏著層的開口。第二部至少設置於絕緣子層的開口,其中第一部與第二部具有交界面。In an embodiment of the present invention, the aforementioned conductive element includes a first part and a second part. The first part is at least disposed in the opening of the first adhesive layer. The second part is at least disposed in the opening of the insulating sublayer, wherein the first part and the second part have an interface.
在本發明的一實施例中,上述的顯示裝置更包括第二黏著層及蓋板。第二黏著層設置於觸控元件層上,且導電元件的一部分設置於第二黏著層與觸控元件層之間。蓋板設置於第二黏著層上。In an embodiment of the present invention, the above-mentioned display device further includes a second adhesive layer and a cover plate. The second adhesive layer is arranged on the touch element layer, and a part of the conductive element is arranged between the second adhesive layer and the touch element layer. The cover plate is arranged on the second adhesive layer.
在本發明的一實施例中,上述的觸控元件層包括感測電極、周邊線路、絕緣子層及緩衝子層,感測電極及周邊線路彼此電性連接,感測電極及周邊線路設置於絕緣子層與緩衝子層之間,絕緣子層設置於感測電極與第一黏著層之間及周邊走線與第一黏著層之間,緩衝子層設置於感測電極與第二黏著層之間及周邊走線與第二黏著層之間,導電元件設置於緩衝子層上且透過緩衝子層的開口電性連接至周邊線路。In an embodiment of the present invention, the above-mentioned touch element layer includes a sensing electrode, a peripheral circuit, an insulating sublayer, and a buffer sublayer. The sensing electrode and the peripheral circuit are electrically connected to each other, and the sensing electrode and the peripheral circuit are disposed on the insulator. Between the layer and the buffer sub-layer, the insulating sub-layer is arranged between the sensing electrode and the first adhesive layer and between the peripheral traces and the first adhesive layer, the buffer sub-layer is arranged between the sensing electrode and the second adhesive layer and Between the peripheral wiring and the second adhesive layer, the conductive element is arranged on the buffer sublayer and is electrically connected to the peripheral circuit through the opening of the buffer sublayer.
在本發明的一實施例中,上述的導電元件的一部分係共形地設置於由第一黏著層之開口所定義的凹槽。In an embodiment of the present invention, a part of the above-mentioned conductive element is conformally arranged in the groove defined by the opening of the first adhesive layer.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.
現將詳細地參考本發明的示範性實施例,示範性實施例的實例說明於附圖中。只要有可能,相同元件符號在圖式和描述中用來表示相同或相似部分。Reference will now be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and descriptions to indicate the same or similar parts.
應當理解,當諸如層、膜、區域或基板的元件被稱為在另一元件“上”或“連接到”另一元件時,其可以直接在另一元件上或與另一元件連接,或者中間元件可以也存在。相反,當元件被稱為“直接在另一元件上”或“直接連接到”另一元件時,不存在中間元件。如本文所使用的,“連接”可以指物理及/或電性連接。再者,“電性連接”或“耦合”係可為二元件間存在其它元件。It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected" to another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connected" can refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that there are other elements between two elements.
本文使用的“約”、“近似”、或“實質上”包括所述值和在本領域普通技術人員確定的特定值的可接受的偏差範圍內的平均值,考慮到所討論的測量和與測量相關的誤差的特定數量(即,測量系統的限制)。例如,“約”可以表示在所述值的一個或多個標準偏差內,或±30%、±20%、±10%、±5%內。再者,本文使用的“約”、“近似”或“實質上”可依光學性質、蝕刻性質或其它性質,來選擇較可接受的偏差範圍或標準偏差,而可不用一個標準偏差適用全部性質。As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art, taking into account the measurement in question and the The specific amount of measurement-related error (ie, the limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the "about", "approximately" or "substantially" used herein can select a more acceptable range of deviation or standard deviation based on optical properties, etching properties, or other properties, instead of using one standard deviation for all properties .
除非另有定義,本文使用的所有術語(包括技術和科學術語)具有與本發明所屬領域的普通技術人員通常理解的相同的含義。將進一步理解的是,諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的含義,並且將不被解釋為理想化的或過度正式的意義,除非本文中明確地這樣定義。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.
圖1A~圖1E為本發明第一實施例之顯示裝置的製造流程剖面示意圖。1A to 1E are schematic cross-sectional views of the manufacturing process of the display device according to the first embodiment of the present invention.
請參照圖1A,首先,提供第一電路基板及第二電路基板。第一電路基板包括基底1及設置在基底1上的第一電路層100。第二電路基板包括基底2及設置在基底2上的第二電路層200。Referring to FIG. 1A, first, a first circuit substrate and a second circuit substrate are provided. The first circuit substrate includes a
在本實施例中,第一電路層100可包括薄膜電晶體T1。薄膜電晶體T1包括半導體圖案120、絕緣子層130、閘極141、第一電極161和第二電極162。絕緣子層130設置於閘極141與半導體圖案120之間。第一電極161和第二電極162分別電性連接至半導體圖案120的不同兩區。In this embodiment, the
在本實施例中,薄膜電晶體T1還可選擇性地包括絕緣子層150。絕緣子層150設置於絕緣子層130上,而第一電極161與第二電極162可設置於絕緣子層150上,但本發明不以此為限。In this embodiment, the thin film transistor T1 may also optionally include an insulating
在本實施例中,第一電路層100還可選擇性地包括緩衝子層110及絕緣子層170。緩衝子層110設置於基底1上,薄膜電晶體T1設置於緩衝子層110上,而絕緣子層170設置於薄膜電晶體T1上,但本發明不以此為限。In this embodiment, the
此外,在本實施例中,第一電路層100還可選擇性地包括匯流線142。第一電路層100之薄膜電晶體T1電性連接至第一電路層100的匯流線142。舉例而言,在本實施例中,匯流線142可與閘極141形成於同一膜層。然而,本發明不限於此,根據其它實施例,匯流線142也可與第一電極161及/或第二電極162形成於同一膜層。In addition, in this embodiment, the
類似地,在本實施例中,第二電路層200可包括薄膜電晶體T2。薄膜電晶體T2包括半導體圖案220、絕緣子層230、閘極241、第一電極261和第二電極262。絕緣子層230設置於閘極241與半導體圖案220之間。第一電極261和第二電極262分別電性連接至半導體圖案220的不同兩區。Similarly, in this embodiment, the
在本實施例中,薄膜電晶體T2還可選擇性地包括絕緣子層250。絕緣子層250設置於絕緣子層230上,而第一電極261與第二電極262可設置於絕緣子層250上,但本發明不以此為限。In this embodiment, the thin film transistor T2 may also optionally include an insulating
在本實施例中,第二電路層200還可選擇性地包括緩衝子層210及絕緣子層270。緩衝子層210設置於基底2上,薄膜電晶體T2設置於緩衝子層210上,而絕緣子層270設置於薄膜電晶體T2上,但本發明不以此為限。In this embodiment, the
此外,在本實施例中,第二電路層200還可選擇性地包括匯流線242。第二電路層200之薄膜電晶體T2電性連接至第二電路層200的匯流線242。舉例而言,在本實施例中,匯流線242可與閘極241形成於同一膜層。然而,本發明不限於此,根據其它實施例,匯流線242也可與第一電極261及/或第二電極262形成於同一膜層。In addition, in this embodiment, the
在本實施例中,基於導電性的考量,第一電路層100及第二電路層200的第一電極161、261、第二電極162、262、閘極141、241及匯流線142、242一般是使用金屬材料。但本發明不限於此,根據其他實施例,第一電路層100及第二電路層200的第一電極161、261、第二電極162、262、閘極141、241及匯流線142、242也可以使用其他導電材料。例如:合金、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物、或是金屬材料與其它導電材料的堆疊層。In this embodiment, based on the consideration of conductivity, the
在本實施例中,第一電路層100及第二電路層200的緩衝子層110、210及絕緣子層130、150、170、230、250、270可為無機材料(例如:氧化矽、氮化矽、氮氧化矽、或上述至少二種材料的堆疊層)、有機材料或上述之組合。In this embodiment, the
請參照圖1A及圖1B,接著,進行一貼合製程,亦即,利用第一黏著層300連接第一電路基板及第二電路基板。第一電路基板與第二電路基板連接後,第一黏著層300設置於第一電路層100上,且第二電路層200設置於第一黏著層300上。在本實施例中,第一黏著層300係為一絕緣黏著層。1A and 1B, then, a bonding process is performed, that is, the first circuit board and the second circuit board are connected by the first
第一電路層100的絕緣子層170具有背向半導體圖案120的表面170k。第二電路層200之絕緣子層270具有背向半導體圖案220的表面270k。舉例而言,在本實施例中,第一電路基板與第二電路基板連接後,第一電路層100之背向半導體圖案120的表面170k可選擇性地朝上,而第二電路層200之背向半導體圖案220的表面270k可選擇性地朝下,但本發明不以此為限。The insulating
請參照圖1B,接著,移除第二電路基板的基底2,而將第二電路基板的第二電路層200留在第一黏著層300上。Referring to FIG. 1B, then, the
請參照圖1C,接著,利用至少一次圖案化製程形成緩衝子層210的開口210a、210b、210c、210d、210e、絕緣子層230的開口230a、230b、230c、230d、230e、絕緣子層250的開口250a、250b、250c、250d、絕緣子層270的開口270a、270d、第一黏著層300的開口300a、300d、絕緣子層170的開口170a、170d及絕緣子層150的開口150d。1C, next, at least one patterning process is used to form
舉例而言,在本實施例中,上述圖案化製程可包括光阻塗佈、光阻曝光及顯影、蝕刻及去光阻等工序。For example, in this embodiment, the above-mentioned patterning process may include photoresist coating, photoresist exposure and development, etching, and photoresist removal.
在本實施例中,可利用同一個圖案化光阻為遮罩,蝕刻緩衝子層210、絕緣子層230、絕緣子層250、絕緣子層270、第一黏著層300、絕緣子層170及絕緣子層150。緩衝子層210的開口210a、絕緣子層230的開口230a、絕緣子層250的開口250a、絕緣子層270的開口270a、第一黏著層300的開口300a及絕緣子層170的開口170a實質上可對齊。緩衝子層210的開口210d、絕緣子層230的開口230d、絕緣子層250的開口250d、絕緣子層270的開口270d、第一黏著層300的開口300d、絕緣子層170的開口170d及絕緣子層150的開口150d實質上可對齊。In this embodiment, the same patterned photoresist can be used as a mask to etch the
在本實施例中,緩衝子層210的開口210a、絕緣子層230的開口230a、絕緣子層250的開口250a、絕緣子層270的開口270a、第一黏著層300的開口300a、絕緣子層170的開口170a及薄膜電晶體T1的一部分(例如但不限於:第一電極161)可定義凹槽U1。凹槽U1位於薄膜電晶體T2的半導體圖案220之外。也就是說,凹槽U1未與薄膜電晶體T2的半導體圖案220重疊。In this embodiment, the
在本實施例中,緩衝子層210的開口210b、絕緣子層230的開口230b、絕緣子層250的開口250b及薄膜電晶體T2的一部分(例如但不限於:第一電極261)可定義凹槽U2。凹槽U2位於薄膜電晶體T2的半導體圖案220之外。也就是說,凹槽U2未與薄膜電晶體T2的半導體圖案220重疊。In this embodiment, the
在本實施例中,緩衝子層210的開口210c、絕緣子層230的開口230c、絕緣子層250的開口250c及薄膜電晶體T2的一部分(例如:第二電極262)可定義的凹槽U3。凹槽U3位於薄膜電晶體T2的半導體圖案220之外。也就是說,凹槽U3未與薄膜電晶體T2的半導體圖案220重疊。In this embodiment, the
在本實施例中,緩衝子層210的開口210d、絕緣子層230的開口230d、絕緣子層250的開口250d、絕緣子層270的開口270d、第一黏著層300的開口300d、絕緣子層170的開口170d、絕緣子層150的開口150d及匯流線142可定義凹槽U4。凹槽U4位於薄膜電晶體T2的半導體圖案220及薄膜電晶體T1的半導體圖案120之外。也就是說,凹槽U4未與薄膜電晶體T2的半導體圖案220及薄膜電晶體T1的半導體圖案120重疊。In this embodiment, the
在本實施例中,緩衝子層210之開口210e、絕緣子層230之開口230e及匯流線242可定義凹槽U5。凹槽U5位於薄膜電晶體T2的半導體圖案220之外。也就是說,凹槽U5未與薄膜電晶體T2的半導體圖案220重疊。In this embodiment, the
請參照圖1D,接著,在第二電路層200上形成第一導電元件411、第二導電元件412及畫素電極510。1D, next, the first
第一導電元件411設置於第二電路層200上,且電性連接至第一電路層100及第二電路層200。舉例而言,在本實施例中,第一導電元件411可透過緩衝子層210的開口210a、210b、絕緣子層230的開口230a、230b、絕緣子層250的開口250a、250b、絕緣子層270的開口270a、第一黏著層300的開口300a及絕緣子層170的開口170a電性連接至第一電路層100的薄膜電晶體T1及第二電路層200的薄膜電晶體T2。The first
第二導電元件412設置於第二電路層200上。第二導電元件412透過緩衝子層210的開口210d、210e、絕緣子層230的開口230d、230e、絕緣子層250的開口250d、絕緣子層270的開口270d、第一黏著層300的開口300d、絕緣子層170的開口170d及絕緣子層150的開口150d電性連接至第一電路層100的匯流線142及第二電路層200的匯流線242。The second
畫素電極510設置於第二電路層200上,且電性連接至第二電路層200。舉例而言,在本實施例中,畫素電極510透過緩衝子層210的開口210c、絕緣子層230的開口230c及絕緣子層250的開口250c電性連接至第二電路層200的薄膜電晶體T2。The
在本實施例中,可利用一濺鍍(sputtering)工序形成第一導電元件411、第二導電元件412及畫素電極250。In this embodiment, a sputtering process may be used to form the first
因此,第一導電元件411的一部分可共形地設置於由緩衝子層210的開口210a、絕緣子層230的開口230a、絕緣子層250的開口250a、絕緣子層270的開口270a、第一黏著層300的開口300a、絕緣子層170的開口170a及薄膜電晶體T1的一部分(例如但不限於:第一電極161)所定義的凹槽U1。Therefore, a part of the first
第一導電元件411的另一部分可共形地設置於由緩衝子層210的開口210b、絕緣子層230的開口230b、絕緣子層250的開口250b及薄膜電晶體T2的一部分(例如但不限於:第一電極261)所定義的凹槽U2。The other part of the first
第二導電元件412的一部分可共形地設置於由緩衝子層210的開口210d、絕緣子層230的開口230d、絕緣子層250的開口250d、絕緣子層270的開口270d、第一黏著層300的開口300d、絕緣子層170的開口170d、絕緣子層150的開口150d及匯流線142所定義的凹槽U4。A part of the second
第二導電元件412的另一部分可共形地設置於由緩衝子層210之開口210e、絕緣子層230之開口230e及匯流線242所定義的凹槽U5。The other part of the second
畫素電極510的一部分可共形地設置於由緩衝子層210的開口210c、絕緣子層230的開口230c、絕緣子層250的開口250c及薄膜電晶體T2的一部分(例如:第二電極262)所定義的凹槽U3。A part of the
請參照圖1E,接著,於畫素電極510及第二電路層200上形成畫素定義子層520。畫素定義子層520設置於畫素電極510上,且具有與畫素電極510重疊的開口520a。接著,形成有機電致發光材料530,設置於畫素定義子層520的開口520a。然後,形成共用電極540,設置於有機電致發光材料530上。在本實施例中,顯示元件層500包括畫素電極510、畫素定義子層520、有機電致發光材料530及共用電極540。於此,便完成本實施例的顯示裝置10。Please refer to FIG. 1E. Next, a
在本實施例中,用以電性連接第一電路層100與第二電路層200之第一導電元件411的一部分設置於畫素定義子層520與第二電路層200(例如:第二電路層200的絕緣子層230)之間。用以電性連接第一電路層100與第二電路層200之第二導電元件412的一部分設置於畫素定義子層520與第二電路層200(例如:第二電路層200的絕緣子層230)之間。In this embodiment, a part of the first
值得一提的是,在本實施例中,用以電性連接第一電路層100與第二電路層200的第一導電元件411及第二導電元件412是在第一電路層100與第二電路層200貼合之後才形成在第二電路層200上、第二電路層200的內部及第一電路層100的內部。因此,即便第一電路層100與第二電路層200貼合精度不高,第一電路層100與第二電路層200仍能利用在貼合製程後方形成的第一導電元件411及第二導電元件412彼此電性連接,而大幅降低顯示裝置10的製造難度。It is worth mentioning that, in this embodiment, the first
在此必須說明的是,下述實施例沿用前述實施例的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,下述實施例不再重複贅述。It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.
圖2為本發明第二實施例之顯示裝置的剖面示意圖。圖2的顯示裝置10A與圖1E的顯示裝置10類似,兩者的差異在於:顯示裝置10A之第一電路層100的表面170k及顯示裝置10A之第二電路層200的表面270k皆朝上。2 is a schematic cross-sectional view of a display device according to a second embodiment of the invention. The
圖3為本發明第三實施例之顯示裝置的剖面示意圖。圖3的顯示裝置10B與圖1E的顯示裝置10類似,兩者的差異在於:顯示裝置10B之第一電路層100的絕緣子層170的表面170k及顯示裝置10B之第二電路層200的絕緣子層270的表面270k皆朝下。3 is a schematic cross-sectional view of a display device according to a third embodiment of the invention. The
圖4為本發明第四實施例之顯示裝置的剖面示意圖。圖4的顯示裝置10C與圖1E的顯示裝置10類似,兩者的差異在於:顯示裝置10C之第一電路層100的表面170k朝下,且顯示裝置10C之第二電路層200的表面270k朝上。4 is a schematic cross-sectional view of a display device according to a fourth embodiment of the invention. The
圖5為本發明第五實施例之顯示裝置的剖面示意圖。圖5的顯示裝置10D與圖4的顯示裝置10C類似,兩者的差異如下。請參照圖5,在本實施例中,薄膜電晶體T2的第一電極261C及第二電極262C是與第一導電元件411的至少一部分形成於同一膜層。也就是說,薄膜電晶體T2的第一電極261C及第二電極262C與第一導電元件411可以一起製作。因此,相較於圖4的顯示裝置10C,圖5的顯示裝置10D還具有簡化製程及降低製造成本的優點。5 is a schematic cross-sectional view of a display device according to a fifth embodiment of the invention. The
圖6為本發明第六實施例之顯示裝置的剖面示意圖。圖6的顯示裝置10E與圖1E的顯示裝置10D類似,兩者的差異如下。6 is a schematic cross-sectional view of a display device according to a sixth embodiment of the invention. The
請參照圖6,在顯示裝置10E的製程中,可先在第一電路層100上形成第一黏著層300;然後,在第二電路層200與第一電路層100貼合之前,形成第一黏著層300的開口300a、300d、第一電路層100之絕緣子層170的開口170a、170d及第一電路層100之絕緣子層150的開口150d,並預先在開口300a、170a內形成第一部411a,在開口300d、170d、150d內形成第一部412a;接著,才貼合第二電路層200與第一電路層100;然後,形成緩衝子層210的開口210a、210d、絕緣子層230的開口230a、230d、絕緣子層250的開口250a、250d及絕緣子層270的開口270a、270d;接著,於開口210a、230a、250a、270a內形成第二部411b,並於開口210d、230d、250d、270d內形成第二部412b,其中第二部411b與第一部411a連接成第一導電元件411,第二部412b與第一部412a連接成第二導電元件412。6, in the manufacturing process of the display device 10E, a first adhesive layer 300 may be formed on the first circuit layer 100; then, before the second circuit layer 200 is bonded to the first circuit layer 100, the first The openings 300a, 300d of the adhesive layer 300, the openings 170a, 170d of the insulating sublayer 170 of the first circuit layer 100, and the opening 150d of the insulating sublayer 150 of the first circuit layer 100, and the first portion 411a is formed in the openings 300a, 170a in advance , The first portion 412a is formed in the openings 300d, 170d, and 150d; then, the second circuit layer 200 and the first circuit layer 100 are bonded together; then, the openings 210a, 210d of the buffer sublayer 210 and the openings of the insulating sublayer 230 are formed 230a, 230d, the openings 250a, 250d of the insulating sublayer 250, and the openings 270a, 270d of the insulating sublayer 270; then, a second portion 411b is formed in the openings 210a, 230a, 250a, 270a, and the openings 210d, 230d, 250d, 270d A second portion 412b is formed inside, wherein the second portion 411b and the first portion 411a are connected to form a first conductive element 411, and the second portion 412b and the first portion 412a are connected to form a second conductive element 412.
由於第一導電元件411的第一部411a與第二部411b是在不同道製程中形成的,因此,第一導電元件411的第一部411a與第二部411b具有交界面S1。類似地,由於第二導電元件412的第一部412a與第二部412b是在不同道製程中形成的,因此,第二導電元件412的第一部412a與第二部412b具有交界面S2。Since the
顯示元件層500係由驅動電路來驅動,而所述驅動電路可由被至少一黏著層(例如:第一黏著層300)分隔開的多個電路層(例如:第一電路層100及第二電路層200)來組成。The
舉例而言,在前述的顯示裝置10、10A~10E中,用以驅動顯示元件層500的驅動電路可以是7個薄膜電晶體及1個電容器(7T1C)的架構,而第一電路層100之薄膜電晶體T1及第二電路層200之薄膜電晶體T2可以是7T1C驅動電路之其第一電極161、261彼此電性連接的兩個薄膜電晶體。For example, in the
然而,本發明不限於此,根據其它實施例,用以驅動顯示元件層500的驅動電路也可以是其它架構,及/或第一電路層100之薄膜電晶體T1及第二電路層200之薄膜電晶體T2也可以用其它方式電性連接,以下配合圖7舉例說明之。However, the present invention is not limited to this. According to other embodiments, the driving circuit for driving the
圖7為本發明第七實施例之顯示裝置的剖面示意圖。圖七的顯示裝置10F與圖1E的顯示裝置10類似,兩者的差異如下。7 is a schematic cross-sectional view of a display device according to a seventh embodiment of the invention. The
請參照圖7,舉例而言,在本實施例中,用以驅動顯示元件層520的驅動電路可以是2個薄膜電晶體及1個電容器(2T1C)的架構,第一電路層100之薄膜電晶體T1及第二電路層200之薄膜電晶體T2可分別是2T1C驅動電路的開關電晶體(switching TFT)及驅動電晶體(driving TFT),而第一電路層100之薄膜電晶體T1的第一電極161與第二電路層200之薄膜電晶體T2的閘極241利用第一導電元件411彼此電性連接。Referring to FIG. 7, for example, in this embodiment, the driving circuit used to drive the
此外,在本實施例中,顯示裝置10F更包括第二黏著層600、第三元件層700及第三導電元件413。第二黏著層600設置於第一電路層100與基底1之間。第三元件層700包括匯流線710。匯流線710設置於第二黏著層600與基底1之間。第三導電元件413設置於第一電路層100上,且電性連接至第一電路層100的薄膜電晶體T1,其中第三導電元件413透過第二黏著層600的開口600f電性連接至第三元件層700的匯流線710。In addition, in this embodiment, the
舉例而言,在本實施例中,絕緣子層170具有設置於半導體圖案120外的開口170f、絕緣子層150具有設置於半導體圖案120外的開口150f、絕緣子層130具有設置於半導體圖案120外的開口130f、緩衝子層110具有設置於半導體圖案120外的開口110f,而第三導電元件413可透過絕緣子層170的開口170f、絕緣子層150的開口150f、絕緣子層130的開口130f、緩衝子層110的開口110f及第二黏著層600的開口600f電性連接至第三元件層700的匯流線710。絕緣子層170的開口170f、絕緣子層150的開口150f、絕緣子層130的開口130f、緩衝子層110的開口110f及第二黏著層600的開口600f實質上對齊,但本發明不以此為限。For example, in this embodiment, the insulating
在本實施例中,絕緣子層170的開口170f、絕緣子層150的開口150f、絕緣子層130的開口130f、緩衝子層110的開口110f、第二黏著層600的開口600f及匯流線710可定義凹槽U6。凹槽U6設置於第一電路層100的半導體圖案120外,而第三導電元件413的一部分可共形地設置於凹槽U6。In this embodiment, the
圖8A~圖8D為本發明第八實施例之顯示裝置的製造流程剖面示意圖。8A to 8D are schematic cross-sectional views of the manufacturing process of the display device according to the eighth embodiment of the present invention.
請參照圖8A,首先,提供顯示基板及觸控基板。圖8A下方的顯示基板包括前述的基底1、第一電路層100、第二電路層200及顯示元件層500。圖8A係示意性地繪出前述的第一電路層100、第二電路層200及顯示元件層500,而省略其細部構造。圖8A上方的觸控基板包括基底3及設置於基底3上的觸控元件層800。圖8A之下方的顯示基板還包括設置於基底1上的接墊P1、P2。舉例而言,接墊P1、P2用以驅動晶片接合,進而使圖8A之上方的觸控元件層800能被驅動晶片驅動。Please refer to FIG. 8A. First, a display substrate and a touch substrate are provided. The display substrate below FIG. 8A includes the
須說明的是,為清楚說明起見,在圖8A中,接墊P1、P2係以繪在第二電路層200上為示例,然而,本發明不限於此,根據其它實施例,接墊P1、P2也可以設置在第一電路層100、第二電路層200或其組合的內部。It should be noted that, for clarity of description, in FIG. 8A, the pads P1 and P2 are drawn on the
請參照圖8A,舉例而言,在本實施例中,觸控元件層800可包括緩衝子層810、設置於緩衝子層810上的感測電極821a及周邊線路821b、841b、設置於感測電極821a及周邊線路821b、841b上的絕緣子層830、設置於絕緣子層830上的感測電極841a、和設置於感測電極841a上的絕緣子層850。感測電極821a電性連接至周邊線路821b。感測電極841a可透過絕緣子層830的開口833電性連接至周邊線路841b。8A, for example, in this embodiment, the
請參照圖8A及圖8B,接著,進行一貼合製程,亦即,利用第一黏著層930連接觸控基板及顯示基板。觸控基板及顯示基板連接後,第一黏著層930設置於顯示元件層500上及接墊P1、P2上,且觸控元件層800設置於第一黏著層930上。絕緣子層830、850設置於感測電極821a與第一黏著層930之間以及周邊線路841b、821b與第一黏著層930之間。Please refer to FIGS. 8A and 8B, and then, a bonding process is performed, that is, the first
請參照圖8A及圖8B,接著,移除觸控基板的基底3,而將觸控元件層800留在第一黏著層930上。Please refer to FIG. 8A and FIG. 8B. Then, the
請參照圖8C,接著,利用至少一次圖案化製程形成緩衝子層810的開口811a、811b、812a、812b、絕緣子層830的開口831、832、絕緣子層850的開口851、852及第一黏著層930的開口931、932。Referring to FIG. 8C, next, at least one patterning process is used to form the
舉例而言,在本實施例中,上述圖案化製程可包括光阻塗佈、光阻曝光及顯影、蝕刻及去光阻等工序。For example, in this embodiment, the above-mentioned patterning process may include photoresist coating, photoresist exposure and development, etching, and photoresist removal.
在本實施例中,可利用同一個圖案化的光阻為遮罩,蝕刻緩衝子層810、絕緣子層830、絕緣子層850及第一黏著層930。緩衝子層810的開口811a、絕緣子層830的開口831、絕緣子層850的開口851及第一黏著層930的開口931實質上可對齊。緩衝子層810的開口811a、絕緣子層830的開口831、絕緣子層850的開口851、第一黏著層930的開口931及接墊P1可定義凹槽U1’。緩衝子層810的開口812a、絕緣子層830的開口832、絕緣子層850的開口852及第一黏著層930的開口932實質上可對齊。緩衝子層810的開口812a、絕緣子層830的開口832、絕緣子層850的開口852及第一黏著層930的開口932及接墊P2可定義凹槽U2’。In this embodiment, the same patterned photoresist can be used as a mask to etch the
請參照圖8D,接著,在觸控元件層800上形成導電元件910及導電元件920。Please refer to FIG. 8D. Next, a
導電元件910、920設置於觸控元件層800上,且電性連接至觸控元件層800。舉例而言,在本實施例中,導電元件910可透過緩衝子層810的開口811b電性連接至周邊走線821b,而導電元件920可透過緩衝子層810的開口812b電性連接至周邊走線841b。The
導電元件910、920透過第一黏著層930的開口931、932電性連接至接墊P1、P2。舉例而言,在本實施例中,導電元件910、920可透過緩衝子層810的開口811a、絕緣子層830的開口831、絕緣子層850的開口851及第一黏著層930的開口931電性連接至接墊P1,而導電元件920可透過緩衝子層810的開口812a、絕緣子層830的開口832、絕緣子層850的開口852及第一黏著層930的開口932電性連接至接墊P2。The
在本實施例中,可利用一濺鍍(sputtering)工序形成導電元件910、920。因此,導電元件910的一部分可共形地設置於由緩衝子層810的開口811a、絕緣子層830的開口831、絕緣子層850的開口851、第一黏著層930的開口931及接墊P1所定義的凹槽U1’,且導電元件920的一部分可共形地設置於由緩衝子層810的開口812a、絕緣子層830的開口832、絕緣子層850的開口852及第一黏著層930的開口932及接墊P2所定義的凹槽U2’。In this embodiment, a sputtering process can be used to form the
請參照圖8D,接著,進行一貼合製程,亦即,利用第二黏著層940連接蓋板4及觸控元件層800。在蓋板4與觸控元件層800貼合後,第二黏著層940設置於觸控元件層800上,且各導電元件910、920的一部分設置於第二黏著層940與觸控元件層800之間。蓋板4設置於第二黏著層940上。於此,便完成了本實施例之具有觸控功能的顯示裝置20。Please refer to FIG. 8D, then, a bonding process is performed, that is, the second
在本實施例中,感測電極821a及周邊線路821b設置於絕緣子層830與緩衝子層810之間,絕緣子層830設置於感測電極821a與第一黏著層930之間及周邊走線821b與第一黏著層930之間,緩衝子層810設置於感測電極821a與第二黏著層940之間及周邊走線821b與第二黏著層940之間,導電元件910設置於緩衝子層810上且透過緩衝子層810的開口811b電性連接至周邊線路821b。In this embodiment, the
類似地,在本實施例中,感測電極841a及周邊線路841b設置於絕緣子層850與緩衝子層810之間,絕緣子層850設置於感測電極841a與第一黏著層930之間及周邊走線841b與第一黏著層930之間,緩衝子層810設置於感測電極841a與第二黏著層940之間及周邊走線841b與第二黏著層940之間,導電元件920設置於緩衝子層810上且透過緩衝子層810的開口812b電性連接至周邊線路841b。Similarly, in this embodiment, the
值得注意的是,在本實施例中,用以電性連接觸控元件層800與接墊P1、P2的導電元件910、920是在觸控元件層800與電路層100、200及顯示元件層500貼合之後才形成在觸控元件層800上、觸控元件層800的內部及第一黏著層930的內部。導電元件910、920能良好地電性連接觸控元件層800與接墊P1、P2,且導電元件910、920的彎折耐受度佳。It is worth noting that, in this embodiment, the
在此必須說明的是,下述實施例沿用前述實施例的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,下述實施例不再重複贅述。It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.
圖9為本發明第九實施例之顯示裝置的製造流程剖面示意圖。圖9的顯示裝置20A與圖8D的顯示裝置20類似,兩者的差異在於:圖9的顯示裝置20A可不包括圖8D的緩衝子層810,圖9之導電元件910的一部分可直接覆蓋在周邊線路821b上,且圖9之導電元件920的一部分可直接覆蓋在周邊線路841b上。9 is a schematic cross-sectional view of the manufacturing process of the display device according to the ninth embodiment of the present invention. The
圖10為本發明第十實施例之顯示裝置的製造流程剖面示意圖。圖10的顯示裝置20B與圖8D的顯示裝置20類似,兩者的差異如下。10 is a schematic cross-sectional view of a manufacturing process of a display device according to a tenth embodiment of the invention. The
請參照圖10,在顯示裝置20B的製程中,可在顯示元件層500及接墊P1、P2上形成第一黏著層930;然後,在觸控元件層800與顯示元件層500及接墊P1、P2貼合之前,形成第一黏著層930的開口931、932,並預先在開口931、932內形成第一部911、921;接著,才貼合觸控元件層800與顯示元件層500及接墊P1、P2;然後,形成緩衝子層810的開口811a、811b、絕緣子層830的開口831、832及絕緣子層850的開口851、852;接著,於開口811a、831、851內形成第二部912,並於開口812a、832、852內形成第二部922,其中第二部912與第一部911連接成導電元件910,第二部922與第一部921連接成導電元件920。10, in the manufacturing process of the
由於導電元件910的第一部911與第二部912是在不同道製程中形成的,因此,導電元件910的第一部911與第二部912具有交界面S1。類似地,由於導電元件920的第一部921與第二部922是在不同道製程中形成的,因此,第二導電元件920的第一部921與第二部922具有交界面S2。Since the
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.
1、2、3:基底 4:蓋板 10、10A、10B、10C、10D、10E、10F、20、20A、20B:顯示裝置 100:第一電路層 110、210、810:緩衝子層 120、220:半導體圖案 130、150、170、230、250、270、830、850:絕緣子層 141、241:閘極 142、242、710:匯流線 161、261、261C:第一電極 162、262、262C:第二電極 170k、270k:表面 200:第二電路層 110f、130f、150d、150f、170a、170d、170f、210a、210b、210c、210d、210e、230a、230b、230c、230d、230e、250a、250b、250c、250d、270a、270d、300a、300d、520a、600f、811a、811b、812a、812b、831、832、833、851、852、931、932:開口 300、930:第一黏著層 411:第一導電元件 411a、412a:第一部 411b、412b:第二部 412:第二導電元件 413:第三導電元件 500:顯示元件層 510:畫素電極 520:畫素定義子層 530:有機電致發光材料 540:共用電極 600:第二黏著層 700:第三元件層 800:觸控元件層 821a、841a:感測電極 821b、841b:周邊線路 910、920:導電元件 940:第二黏著層 P1、P2:接墊 S1、S2:交界面 T1、T2:薄膜電晶體 U1、U2、U3、U4、U5、U6、U1’、U2’ :凹槽1, 2, 3: base 4: cover 10, 10A, 10B, 10C, 10D, 10E, 10F, 20, 20A, 20B: display device 100: first circuit layer 110, 210, 810: buffer sublayer 120, 220: semiconductor pattern 130, 150, 170, 230, 250, 270, 830, 850: insulator layer 141, 241: Gate 142, 242, 710: Confluence line 161, 261, 261C: first electrode 162, 262, 262C: second electrode 170k, 270k: surface 200: second circuit layer 110f, 130f, 150d, 150f, 170a, 170d, 170f, 210a, 210b, 210c, 210d, 210e, 230a, 230b, 230c, 230d, 230e, 250a, 250b, 250c, 250d, 270a, 270d, 300a, 300d, 520a, 600f, 811a, 811b, 812a, 812b, 831, 832, 833, 851, 852, 931, 932: opening 300, 930: the first adhesive layer 411: first conductive element 411a, 412a: Part 1 411b, 412b: Part 2 412: second conductive element 413: third conductive element 500: display component layer 510: pixel electrode 520: pixel definition sublayer 530: organic electroluminescent materials 540: Common electrode 600: second adhesive layer 700: third component layer 800: Touch component layer 821a, 841a: sensing electrode 821b, 841b: peripheral lines 910, 920: conductive elements 940: second adhesive layer P1, P2: pad S1, S2: Interface T1, T2: thin film transistor U1, U2, U3, U4, U5, U6, U1’, U2’: Groove
圖1A~圖1E為本發明第一實施例之顯示裝置的製造流程剖面示意圖。 圖2為本發明第二實施例之顯示裝置的剖面示意圖。 圖3為本發明第三實施例之顯示裝置的剖面示意圖。 圖4為本發明第四實施例之顯示裝置的剖面示意圖。 圖5為本發明第五實施例之顯示裝置的剖面示意圖。 圖6為本發明第六實施例之顯示裝置的剖面示意圖。 圖7為本發明第七實施例之顯示裝置的剖面示意圖。 圖8A~圖8D為本發明第八實施例之顯示裝置的製造流程剖面示意圖。 圖9為本發明第九實施例之顯示裝置的製造流程剖面示意圖。 圖10為本發明第十實施例之顯示裝置的製造流程剖面示意圖。 1A to 1E are schematic cross-sectional views of the manufacturing process of the display device according to the first embodiment of the present invention. 2 is a schematic cross-sectional view of a display device according to a second embodiment of the invention. 3 is a schematic cross-sectional view of a display device according to a third embodiment of the invention. 4 is a schematic cross-sectional view of a display device according to a fourth embodiment of the invention. 5 is a schematic cross-sectional view of a display device according to a fifth embodiment of the invention. 6 is a schematic cross-sectional view of a display device according to a sixth embodiment of the invention. 7 is a schematic cross-sectional view of a display device according to a seventh embodiment of the invention. 8A to 8D are schematic cross-sectional views of the manufacturing process of the display device according to the eighth embodiment of the present invention. 9 is a schematic cross-sectional view of the manufacturing process of the display device according to the ninth embodiment of the present invention. 10 is a schematic cross-sectional view of a manufacturing process of a display device according to a tenth embodiment of the invention.
1:基底 1: base
10:顯示裝置 10: Display device
100:第一電路層 100: first circuit layer
110、210:緩衝子層 110, 210: buffer sublayer
120、220:半導體圖案 120, 220: semiconductor pattern
130、150、170、230、250、270:絕緣子層 130, 150, 170, 230, 250, 270: insulator layer
141、241:閘極 141, 241: Gate
142、242:匯流線 142, 242: Confluence line
161、261:第一電極 161, 261: first electrode
162、262:第二電極 162, 262: second electrode
170k、270k:表面 170k, 270k: surface
200:第二電路層 200: second circuit layer
150d、170a、170d、210a、210b、210c、210d、210e、230a、230b、230c、230d、230e、250a、250b、250c、250d、270a、270d、300a、300d、520a:開口 150d, 170a, 170d, 210a, 210b, 210c, 210d, 210e, 230a, 230b, 230c, 230d, 230e, 250a, 250b, 250c, 250d, 270a, 270d, 300a, 300d, 520a: opening
300:第一黏著層 300: The first adhesive layer
411:第一導電元件 411: first conductive element
412:第二導電元件 412: second conductive element
500:顯示元件層 500: display component layer
510:畫素電極 510: pixel electrode
520:畫素定義子層 520: pixel definition sublayer
530:有機電致發光材料 530: organic electroluminescent materials
540:共用電極 540: Common electrode
T1、T2:薄膜電晶體 T1, T2: thin film transistor
U1、U2、U3、U4、U5:凹槽 U1, U2, U3, U4, U5: groove
Claims (5)
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TW109125703A TWI710823B (en) | 2019-03-28 | 2019-03-28 | Display apparatus |
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TW109125703A TWI710823B (en) | 2019-03-28 | 2019-03-28 | Display apparatus |
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TWI710823B true TWI710823B (en) | 2020-11-21 |
TW202043864A TW202043864A (en) | 2020-12-01 |
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TW (1) | TWI710823B (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140319684A1 (en) * | 2005-03-15 | 2014-10-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and electronic device having the same |
CN104752484A (en) * | 2013-12-26 | 2015-07-01 | 乐金显示有限公司 | Organic Light Emitting Diode Display Device With Touch Screen And Method Of Fabricating The Same |
TW201606992A (en) * | 2014-06-25 | 2016-02-16 | 瑞薩電子股份有限公司 | Semiconductor device |
-
2019
- 2019-03-28 TW TW109125703A patent/TWI710823B/en active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140319684A1 (en) * | 2005-03-15 | 2014-10-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and electronic device having the same |
CN104752484A (en) * | 2013-12-26 | 2015-07-01 | 乐金显示有限公司 | Organic Light Emitting Diode Display Device With Touch Screen And Method Of Fabricating The Same |
TW201606992A (en) * | 2014-06-25 | 2016-02-16 | 瑞薩電子股份有限公司 | Semiconductor device |
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