TWI709907B - Micro-controller - Google Patents

Micro-controller Download PDF

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TWI709907B
TWI709907B TW108148541A TW108148541A TWI709907B TW I709907 B TWI709907 B TW I709907B TW 108148541 A TW108148541 A TW 108148541A TW 108148541 A TW108148541 A TW 108148541A TW I709907 B TWI709907 B TW I709907B
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microcontroller
access
slave
item
patent application
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TW108148541A
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TW202127234A (en
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馬紀哲
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新唐科技股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
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Abstract

A microcontroller including a slave device, a main device and a bus is provided. The slave device accesses a storage device according to an access command. The main device executes a program code to provide the access command. The bus is coupled between the slave device and the main device to transmit the access command to the slave. When a trigger event occurs, the main device detects the access state of the storage device to generate a detection result to an external device.

Description

微控制器Microcontroller

本發明係有關於一種微控制器，特別是有關於一種監控本身的儲存裝置的存取狀態的微控制器。The present invention relates to a microcontroller, in particular to a microcontroller that monitors the access status of its own storage device.

隨著科技的進步，電子裝置的種類及功能愈來愈多。一般電子裝置內部具有一微控制器。該微控制器係根據本身內部的程式碼而動作。當程式碼具有錯誤(bug)時，微控制器將無法正常工作。With the advancement of technology, there are more and more types and functions of electronic devices. Generally, an electronic device has a microcontroller inside. The microcontroller operates according to its own internal code. When there is a bug in the code, the microcontroller will not work properly.

本發明提供一種微控制器，包括一從裝置、一主裝置以及一匯流排。從裝置根據一存取指令，存取一儲存裝置。主裝置執行一程式碼，用以提供存取指令。匯流排耦接於從裝置與主裝置之間，用以傳送存取指令予從裝置。當一觸發事件發生時，主裝置監控儲存裝置的存取狀態，用以產生一監控結果予一外部裝置。The present invention provides a microcontroller including a slave device, a master device and a bus. The slave device accesses a storage device according to an access command. The main device executes a program code to provide access instructions. The bus is coupled between the slave device and the master device for sending access commands to the slave device. When a trigger event occurs, the main device monitors the access state of the storage device to generate a monitoring result to an external device.

為讓本發明之目的、特徵和優點能更明顯易懂，下文特舉出實施例，並配合所附圖式，做詳細之說明。本發明說明書提供不同的實施例來說明本發明不同實施方式的技術特徵。其中，實施例中的各元件之配置係為說明之用，並非用以限制本發明。另外，實施例中圖式標號之部分重覆，係為了簡化說明，並非意指不同實施例之間的關聯性。In order to make the purpose, features and advantages of the present invention more comprehensible, embodiments are specifically listed below, in conjunction with the accompanying drawings, for detailed description. The specification of the present invention provides different examples to illustrate the technical features of different embodiments of the present invention. Wherein, the configuration of each element in the embodiment is for illustrative purposes, and is not intended to limit the present invention. In addition, the part of the repetition of the drawing symbols in the embodiments is for simplifying the description and does not mean the relevance between different embodiments.

第1圖為本發明之操作系統的示意圖。如圖所示，操作系統100包括一外部裝置110、一連接器120以及一微控制器130。外部裝置110透過連接器120與微控制器130溝通。在本實施例中，外部裝置110分析微控制器130所提供的參數組，用以供使用者判斷微控制器130內部的程式碼的流程是否正確。本發明並不限定外部裝置110的種類。在一可能實施例中，外部裝置110係為一電腦設備。在此例中，外部裝置110可能安裝一監控應用程式。當使用者開啟監控應用程式時，外部裝置110便根據微控制器130所提供的參數組，呈現一分析畫面供使用者參考。Figure 1 is a schematic diagram of the operating system of the present invention. As shown in the figure, the operating system 100 includes an external device 110, a connector 120, and a microcontroller 130. The external device 110 communicates with the microcontroller 130 through the connector 120. In this embodiment, the external device 110 analyzes the parameter set provided by the microcontroller 130 for the user to determine whether the flow of the program code inside the microcontroller 130 is correct. The invention does not limit the type of external device 110. In a possible embodiment, the external device 110 is a computer device. In this example, the external device 110 may install a monitoring application. When the user opens the monitoring application, the external device 110 presents an analysis screen for the user's reference according to the parameter set provided by the microcontroller 130.

連接器120耦接於外部裝置110與微控制器130之間。在本實施例中，連接器120具有傳輸介面121與122。傳輸介面121用以耦接外部裝置110。傳輸介面122用以耦接微控制器130。本發明並不限定傳輸介面121及122的種類。在一可能實施例中，傳輸介面121係為一USB介面。在其它實施例中，傳輸介面121的種類可能相同或不同於傳輸介面122的種類。The connector 120 is coupled between the external device 110 and the microcontroller 130. In this embodiment, the connector 120 has transmission interfaces 121 and 122. The transmission interface 121 is used for coupling to the external device 110. The transmission interface 122 is used for coupling to the microcontroller 130. The invention does not limit the types of transmission interfaces 121 and 122. In one possible embodiment, the transmission interface 121 is a USB interface. In other embodiments, the type of the transmission interface 121 may be the same or different from the type of the transmission interface 122.

在一可能實施例中，連接器120係作為一金鑰(key)。透過連接器120，外部裝置110才能對微控制器130進行存取。同樣地，透過連接器120，微控制器130才會提供相關參數組予外部裝置110。在其它實施例中，連接器120可能整合於外部裝置110或微控制器130之中。在一些實施例中，連接器120可省略。在此例中，外部裝置110及微控制器130具有加密及解密功能，以提高安全性。In one possible embodiment, the connector 120 serves as a key. Through the connector 120, the external device 110 can access the microcontroller 130. Similarly, through the connector 120, the microcontroller 130 provides the relevant parameter set to the external device 110. In other embodiments, the connector 120 may be integrated in the external device 110 or the microcontroller 130. In some embodiments, the connector 120 may be omitted. In this example, the external device 110 and the microcontroller 130 have encryption and decryption functions to improve security.

微控制器130透過連接器120與外部裝置110溝通。當一觸發事件發生時，微控制器130監控本身內部的儲存裝置的存取狀態，並提供一監控結果予外部裝置110。在一可能實施例中，觸發事件係指一按鈕(未顯示)被按下。該按鈕可能設置於微控制器130之中。當使用者按下按鈕時，微控制器130便進行一監控操作。在另一可能實施例中，觸發事件係指外部裝置110發出一監控觸發。在此例中，當使用者開啟外部裝置110的一監控應用程式時，外部裝置110發出該監控觸發，用以命令微控制器130進行一監控操作。The microcontroller 130 communicates with the external device 110 through the connector 120. When a trigger event occurs, the microcontroller 130 monitors the access status of its internal storage device and provides a monitoring result to the external device 110. In one possible embodiment, the trigger event refers to a button (not shown) being pressed. The button may be provided in the microcontroller 130. When the user presses the button, the microcontroller 130 performs a monitoring operation. In another possible embodiment, the trigger event refers to the external device 110 issuing a monitoring trigger. In this example, when the user starts a monitoring application of the external device 110, the external device 110 issues the monitoring trigger to command the microcontroller 130 to perform a monitoring operation.

由於使用者根據微控制器130的監控結果，得知微控制器130內部的儲存裝置的存取狀態，故當微控制器130內部的儲存裝置的存取狀態不符合預設值時，使用者可快速地找出異常之處，並進行除錯(debug)。再者，由於微控制器130只監控儲存裝置的存取狀態，故只需二進位格式檔(binary file)，便可得知資料流(data flow)，並且外部裝置110並不需具有來源碼(source code)，便可重建出微控制器130所執行的程式流程，因而簡化除錯的過程。Since the user knows the access status of the storage device inside the microcontroller 130 according to the monitoring result of the microcontroller 130, when the access status of the storage device inside the microcontroller 130 does not meet the preset value, the user It can quickly find out the anomaly and perform debugging (debug). Furthermore, since the microcontroller 130 only monitors the access status of the storage device, it only needs a binary file to know the data flow, and the external device 110 does not need to have a source code (source code), the program flow executed by the microcontroller 130 can be reconstructed, thus simplifying the debugging process.

第2圖為本發明之微控制器的示意圖。如圖所示，微控制器200包括一主裝置210、從裝置220、230、匯流排240及250。主裝置210執行一程式碼PRC，用以發出存取指令CM 1及CM 2。本發明並不限定主裝置210的架構。任何可發出存取指令的裝置，均可作為主裝置210。在一可能實施例中，主裝置210係為一中央處理器(CPU)或是一週邊記憶體直接存取控制器(Peripheral Direct Memory Access controller；PDMA controller)。 Figure 2 is a schematic diagram of the microcontroller of the present invention. As shown in the figure, the microcontroller 200 includes a master device 210, slave devices 220 and 230, and bus bars 240 and 250. The main device 210 executes a program code PRC to issue access commands CM 1 and CM 2 . The present invention does not limit the structure of the main device 210. Any device that can issue access commands can serve as the master device 210. In one possible embodiment, the main device 210 is a central processing unit (CPU) or a Peripheral Direct Memory Access controller (PDMA controller).

從裝置220根據存取指令CM 1，存取一儲存裝置221。本發明並不限定儲存裝置的數量。在其它實施例中，從裝置220具有更多的儲存裝置。另外，在本實施例中，儲存裝置221係整合於從裝置220中，但並非用以限制本發明。在其它實施例中，儲存裝置221可能獨立於從裝置220之外。在一可能實施例中，儲存裝置221包括至少一暫存器(register)。 The slave device 220 accesses a storage device 221 according to the access command CM 1 . The invention does not limit the number of storage devices. In other embodiments, the slave device 220 has more storage devices. In addition, in this embodiment, the storage device 221 is integrated in the slave device 220, but it is not used to limit the present invention. In other embodiments, the storage device 221 may be independent of the slave device 220. In a possible embodiment, the storage device 221 includes at least one register.

從裝置230根據存取指令CM 2，存取儲存裝置231及232之至少一者。在其它實施例中，從裝置230具有更多或更少的儲存裝置。另外，在本實施例中，儲存裝置231及232係整合於從裝置230中，但並非用以限制本發明。在其它實施例中，儲存裝置231及232之至少一者獨立於從裝置230之外。在一可能實施例中，儲存裝置231及232均包括至少一暫存器(register)。 The slave device 230 accesses at least one of the storage devices 231 and 232 according to the access command CM 2 . In other embodiments, the slave device 230 has more or less storage devices. In addition, in this embodiment, the storage devices 231 and 232 are integrated in the slave device 230, but they are not used to limit the present invention. In other embodiments, at least one of the storage devices 231 and 232 is independent of the slave device 230. In a possible embodiment, the storage devices 231 and 232 both include at least one register.

本發明並不限定從裝置220及230的種類。從裝置220的種類可能相同或不同於從裝置230的種類。在一可能實施例中，從裝置220係為一積體電路間 (Inter-Integrated Circuit；I2C)電路，從裝置220係為一通用非同步收發傳輸器(Universal Asynchronous Receiver/Transmitter；UART)。The invention does not limit the types of slave devices 220 and 230. The type of the slave device 220 may be the same or different from the type of the slave device 230. In a possible embodiment, the slave device 220 is an Inter-Integrated Circuit (I2C) circuit, and the slave device 220 is a Universal Asynchronous Receiver/Transmitter (UART).

匯流排240耦接於從裝置220與主裝置210之間，用以傳送存取指令CM 1。匯流排250耦接於從裝置230與主裝置210之間，用以傳送存取指令CM 2。本發明並不限定匯流排240及250的種類。匯流排240及250的種類分別對應於從裝置220及230的傳輸介面。舉例而言，假設，從裝置220係為一I2C電路，並且從裝置220係為一UART。在此例中，匯流排240為一I2C匯流排，並且匯流排250為一UART匯流排。 The bus 240 is coupled between the slave device 220 and the master device 210 for transmitting the access command CM 1 . The bus 250 is coupled between the slave device 230 and the master device 210 for transmitting the access command CM 2 . The present invention does not limit the types of bus bars 240 and 250. The types of bus bars 240 and 250 correspond to the transmission interfaces of the slave devices 220 and 230, respectively. For example, suppose that the slave device 220 is an I2C circuit, and the slave device 220 is a UART. In this example, the bus 240 is an I2C bus, and the bus 250 is a UART bus.

本發明並不限定微控制器200的從裝置的數量。在其它實施例中，微控制器200可能具有更多或更少的從裝置。在此例中，匯流排的數量也會隨著從裝置的數量而變化。舉例而言，當微控制器200具有更多的從裝置時，微控制器200需要利用更多的匯流排傳送指令予從裝置。The present invention does not limit the number of slave devices of the microcontroller 200. In other embodiments, the microcontroller 200 may have more or fewer slave devices. In this example, the number of buses will also vary with the number of slave devices. For example, when the microcontroller 200 has more slave devices, the microcontroller 200 needs to use more buses to transmit commands to the slave devices.

在其它實施例中，微控制器200更包括一記憶體260。記憶體260用以儲存程式碼PRC。在主裝置210執行程式碼PRC時，主裝置210產生存取指令CM 1及CM 2，用以存取儲存裝置221、231及232。當一第一觸發事件發生時，主裝置210監控儲存裝置221、231及232的存取狀態，用以產生一監控結果S M。在一可能實施例中，主裝置210直接輸出監控結果S M予外部裝置110。在另一可能實施例中，微控制器200更包括一記憶體270。記憶體270用以儲存監控結果S M。在此例中，主裝置210先將監控結果S M儲存於記憶體270中，並在一特定時間，讀取記憶體270的監控結果S M，並輸出監控結果S M予外部裝置110。本發明並不限定記憶體270的種類。記憶體270可能是一揮發性記憶體或是一非揮發性記憶體。在一可能實施例中，記憶體270係為一靜態隨機存取記憶體(SRAM)。 In other embodiments, the microcontroller 200 further includes a memory 260. The memory 260 is used to store the program code PRC. When the main device 210 executes the program code PRC, the main device 210 generates access commands CM 1 and CM 2 to access the storage devices 221, 231 and 232. When a first trigger event occurs, the main device 210 monitors the access status of the storage devices 221, 231, and 232 to generate a monitoring result S M. In a possible embodiment, the main device 210 directly outputs the monitoring result SM to the external device 110. In another possible embodiment, the microcontroller 200 further includes a memory 270. The memory 270 is used to store the monitoring result S M. In this embodiment, the master device 210 first monitoring result S M stored in the memory 270, and at a particular time, reads the monitoring result memory 270 of the S M, S M and outputs the monitoring result to the external device 110. The invention does not limit the type of the memory 270. The memory 270 may be a volatile memory or a non-volatile memory. In one possible embodiment, the memory 270 is a static random access memory (SRAM).

在其它實施例中，當一第二觸發事件發生時，主裝置210停止監控儲存裝置221、231及232的存取狀態。在此例中，主裝置210可能讀取記憶體270所儲存的監控結果S M，並提供監控結果S M予外部裝置110。外部裝置110分析監控結果S M，用以產生一分析畫面。在此例中，使用者根據外部裝置110的分析畫面，判斷程式碼PRC的流程是否正確。 In other embodiments, when a second trigger event occurs, the main device 210 stops monitoring the access status of the storage devices 221, 231, and 232. In this example, the main device 210 may read the monitoring result S M stored in the memory 270 and provide the monitoring result S M to the external device 110. The external device 110 analyzes the monitoring result S M to generate an analysis screen. In this example, the user judges whether the flow of the code PRC is correct according to the analysis screen of the external device 110.

本發明並不限定第一及第二觸發事件的種類。在一可能實施例中，主裝置210判斷一第一按鈕(未顯示)以及一第二按鈕(未顯示)是否被按下。當第一按鈕被按下時，表示發生第一觸發事件。因此，主裝置210進行監控操作。當第二按鈕被按下時，表示發生第二觸發事件。因此，主裝置210停止監控操作。The invention does not limit the types of the first and second trigger events. In one possible embodiment, the main device 210 determines whether a first button (not shown) and a second button (not shown) are pressed. When the first button is pressed, it indicates that the first trigger event has occurred. Therefore, the main device 210 performs a monitoring operation. When the second button is pressed, it indicates that a second trigger event has occurred. Therefore, the main device 210 stops the monitoring operation.

在另一可能實施例中，當使用者開啟外部裝置110的一監控應用程式(未顯示)，並點選一監控選項時，外部裝置110發出一第一觸發信號予主裝置210。主裝置210根據第一觸發信號開始監控儲存裝置221、231及232的存取狀態。當使用者點選一停止選項時，外部裝置110發出一第二觸發信號予主裝置210。主裝置210根據第二觸發信號停止監控儲存裝置221、231及232的存取狀態。在此例中，當使用者點選一傳送選項時，外部裝置110發出一第三觸發信號予主裝置210。主裝置210根據第三觸發信號回報監控結果S M。在其它實施例中，當主裝置210執行程式碼，並執行到一斷點時，表示第二觸發事件發生。因此，主裝置210停止監控。 In another possible embodiment, when the user opens a monitoring application (not shown) of the external device 110 and clicks a monitoring option, the external device 110 sends a first trigger signal to the main device 210. The main device 210 starts to monitor the access status of the storage devices 221, 231, and 232 according to the first trigger signal. When the user clicks a stop option, the external device 110 sends a second trigger signal to the main device 210. The main device 210 stops monitoring the access status of the storage devices 221, 231, and 232 according to the second trigger signal. In this example, when the user clicks a transmission option, the external device 110 sends a third trigger signal to the main device 210. The main device 210 reports the monitoring result S M according to the third trigger signal. In other embodiments, when the main device 210 executes the program code and reaches a breakpoint, it means that the second trigger event occurs. Therefore, the main device 210 stops monitoring.

第3圖為本發明之微控制器的另一示意圖。第3圖相似第2圖，不同之處在於第3圖的存取指令CM 1及CM 2係由不同的主裝置(如310及320)所提供。在本實施例中，主裝置310透過匯流排350傳送存取指令CM 1予從裝置330。從裝置330根據存取指令CM 1存取儲存裝置331。另外，主裝置320透過匯流排360傳送存取指令CM 2予從裝置340。從裝置340根據存取指令CM 2存取儲存裝置341。 Figure 3 is another schematic diagram of the microcontroller of the present invention. Figure 3 is similar to Figure 2, except that the access commands CM 1 and CM 2 in Figure 3 are provided by different master devices (such as 310 and 320). In this embodiment, the master device 310 transmits the access command CM 1 to the slave device 330 through the bus 350. Device 330 from accessing storage access command CM 1 The apparatus 331. In addition, the master device 320 transmits the access command CM 2 to the slave device 340 through the bus 360. The slave device 340 accesses the storage device 341 according to the access command CM 2 .

在一可能實施例中，主裝置310係為一中央處理器，並且主裝置320係為一PDMA控制器。當一第一觸發事件發生時，主裝置310監控從裝置330的存取操作，用以產生一監控結果S MA。當一第二觸發事件發生時，主裝置310停止監控從裝置330的存取操作。當一第三觸發事件發生時，主裝置320監控從裝置340的存取操作，用以產生一監控結果S MB。當一第四觸發事件發生時，主裝置320停止監控從裝置340的存取操作。 In a possible embodiment, the main device 310 is a central processing unit, and the main device 320 is a PDMA controller. When a first trigger event occurs, the master device 310 monitors the access operation of the slave device 330 to generate a monitoring result S MA . When a second trigger event occurs, the master device 310 stops monitoring the access operation of the slave device 330. When a third trigger event occurs, the master device 320 monitors the access operation of the slave device 340 to generate a monitoring result S MB . When a fourth trigger event occurs, the master device 320 stops monitoring the access operation of the slave device 340.

在一可能實施例中，主裝置310及320可能分別儲存監控結果S MA及S MB於記憶模組370中。在其它實施例中，主裝置310及320之至少一者係直接輸出監控結果(S MA及/或S MB)予一外部裝置。在本實施例中，記憶模組370具有至少一記憶體(未顯示)，用以儲存程式碼及監控結果S MA及S MB。由於從裝置330、340、匯流排350、360的特性與第2圖的從裝置220、230、匯流排240、250的特性相似，故不再贅述。 In a possible embodiment, the main devices 310 and 320 may store the monitoring results S MA and S MB in the memory module 370, respectively. In other embodiments, at least one of the main devices 310 and 320 directly outputs the monitoring results (S MA and/or S MB ) to an external device. In this embodiment, the memory module 370 has at least one memory (not shown) for storing program codes and monitoring results S MA and S MB . Since the characteristics of the slave devices 330, 340, and the bus bars 350, 360 are similar to the characteristics of the slave devices 220, 230, and the bus bars 240, 250 in FIG. 2, they will not be repeated.

在一些實施例中，主裝置310執行記憶模組370所儲存的一程式碼，用以產生一控制指令CM 3。主裝置320根據控制指令CM 3，產生存取指令CM 2，用以存取從裝置340。在其它實施例中，主裝置320係直接執行記憶模組370所儲存的程式碼，用以產生存取指令CM 2。在一可能實施例中，記憶模組370具有一非揮發性記憶體，用以儲存程式碼。在此例中，記憶模組370更具有一揮發性記憶體，用以儲存監控結果S MA及S MB。在其它實施例中，監控結果S MA及S MB係儲存於非揮發性記憶體中。 In some embodiments, the main device 310 executes a program code stored in the memory module 370 to generate a control command CM 3 . The master device 320 generates an access command CM 2 according to the control command CM 3 to access the slave device 340. In other embodiments, the main device 320 directly executes the program code stored in the memory module 370 to generate the access command CM 2 . In one possible embodiment, the memory module 370 has a non-volatile memory for storing program codes. In this example, the memory module 370 further has a volatile memory for storing the monitoring results S MA and S MB . In other embodiments, the monitoring results S MA and S MB are stored in non-volatile memory.

第4圖為本發明之記憶模組370的內部示意圖。如圖所示，記憶模組370包括記憶庫(bank)411~418，但並非用以限制本發明。在其它實施例中，記憶模組370具有更多或更少的記憶庫。在本實施例中，記憶庫411~414用以儲存監控結果S MA，而記憶庫415~418用以儲存監控結果S MB。 FIG. 4 is an internal schematic diagram of the memory module 370 of the present invention. As shown in the figure, the memory module 370 includes banks 411 to 418, but it is not used to limit the present invention. In other embodiments, the memory module 370 has more or less memory banks. In this embodiment, the memory banks 411 to 414 are used to store the monitoring results S MA , and the memory banks 415 to 418 are used to store the monitoring results S MB .

記憶庫411用以儲存監控結果S MA裡的位址參數組addr_A。舉例而言，當主裝置310針對儲存裝置331的位址0x4007003x及0x4007000c的資料進行存取時，主裝置310記錄位址0x4007003x及0x4007000c於記憶庫411中。 Memory 411 for storing the monitoring result S MA in the address parameters addr_A. For example, when the host device 310 accesses the data at the addresses 0x4007003x and 0x4007000c of the storage device 331, the host device 310 records the addresses 0x4007003x and 0x4007000c in the memory bank 411.

記憶庫412用以儲存監控結果S MA裡的資料參數組DA_A。在一可能實施例中，資料參數組DA_A用以表示主裝置310寫入位址0x4007003x及0x4007000c的資料數值，或是主裝置310從位址0x4007003x及0x4007000c所得到的資料數值。 The memory bank 412 is used to store the data parameter group DA_A in the monitoring result S MA . In one possible embodiment, the data parameter group DA_A is used to represent the data values written to the addresses 0x4007003x and 0x4007000c by the master device 310, or the data values obtained by the master device 310 from the addresses 0x4007003x and 0x4007000c.

記憶庫413用以儲存監控結果S MA裡的時間參數組TMS_A。舉例而言，主裝置310可能在一操作頻率的第五個週期及第六個週期存取儲存裝置331。在此例中，主裝置310將週期cycle5及cycle6記錄於記憶庫413中。 Memory 413 for storing the monitoring result S MA in the time parameter set TMS_A. For example, the main device 310 may access the storage device 331 in the fifth and sixth cycles of an operating frequency. In this example, the main device 310 records the cycles cycle5 and cycle6 in the memory bank 413.

記憶庫414用以儲存監控結果S MA裡的存取參數組RorW_A。舉例而言，主裝置310可能寫入兩資料分別寫入儲存裝置331中。因此，記憶庫414記錄兩次的寫入操作Write。 Memory 414 for storing the results of the monitoring in the access parameter S MA group RorW_A. For example, the main device 310 may write two data into the storage device 331 respectively. Therefore, the memory bank 414 records two write operations Write.

記憶庫415~418分別記錄監控結果S MB裡的位址參數組addr_B、資料參數組DA_B、時間參數組TMS_B及存取參數組RorW_B。由於位址參數組addr_B、資料參數組DA_B、時間參數組TMS_B及存取參數組RorW_B的特性與位址參數組addr_A、資料參數組DA_A、時間參數組TMS_A及存取參數組RorW_A的特性相同，故不再贅述。在其它實施例中，位址參數組addr_B、資料參數組DA_B、時間參數組TMS_B及存取參數組RorW_B可能分別儲存於記憶庫411~414中。 Memory banks 415~418 respectively record the address parameter group addr_B, data parameter group DA_B, time parameter group TMS_B and access parameter group RorW_B in the monitoring result S MB . Since the characteristics of the address parameter group addr_B, data parameter group DA_B, time parameter group TMS_B, and access parameter group RorW_B are the same as those of address parameter group addr_A, data parameter group DA_A, time parameter group TMS_A, and access parameter group RorW_A, Therefore, I will not repeat it. In other embodiments, the address parameter group addr_B, the data parameter group DA_B, the time parameter group TMS_B, and the access parameter group RorW_B may be stored in the memory banks 411 to 414, respectively.

由於主裝置僅監控儲存裝置(如暫存器)的存取狀態，故監控結果S MA及S MB只是單純的二進制格式檔。外部裝置(如電腦設備)分析監控結果S MA及S MB，用以產生易讀的格式(如波形)供使用者參考，以便使用者快速地得知程式碼的流程是否正確。 Since the main device only monitors the access status of the storage device (such as a register), the monitoring results S MA and S MB are only simple binary format files. External devices (such as computer equipment) analyze the monitoring results S MA and S MB to generate easy-to-read formats (such as waveforms) for users to refer to, so that users can quickly know whether the code flow is correct.

除非另作定義，在此所有詞彙(包含技術與科學詞彙)均屬本發明所屬技術領域中具有通常知識者之一般理解。此外，除非明白表示，詞彙於一般字典中之定義應解釋為與其相關技術領域之文章中意義一致，而不應解釋為理想狀態或過分正式之語態。Unless otherwise defined, all vocabulary (including technical and scientific vocabulary) herein belong to the general understanding of persons with ordinary knowledge in the technical field of the present invention. In addition, unless clearly stated, the definition of a word in a general dictionary should be interpreted as consistent with the meaning in the article in its related technical field, and should not be interpreted as an ideal state or an overly formal voice.

雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾。舉例來說，本發明實施例所述之系統、裝置或是方法可以硬體、軟體或硬體以及軟體的組合的實體實施例加以實現。因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed as above in preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. . For example, the system, device, or method described in the embodiments of the present invention can be implemented in a physical embodiment of hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100:操作系統 110:外部裝置 120:連接器 130、200、300:微控制器 121、122:傳輸介面 210、310、320:主裝置 220、230、330、340:從裝置 240、250、350、60:匯流排 CM1、CM2:存取指令 CM3:控制指令 221、231、232、331、341:儲存裝置 260、270:記憶體 370:記憶模組 PRC:程式碼 SM、SMA、SMB:監控結果 411~418:記憶庫 addr_A、addr_B:位址參數組 DA_A、DA_B:資料參數組 TMS_A、TMS_B:時間參數組 RorW_A、RorW_B:存取參數組100: Operating system 110: External device 120: Connector 130, 200, 300: Microcontroller 121, 122: Transmission interface 210, 310, 320: Master device 220, 230, 330, 340: Slave device 240, 250, 350 , 60: bus CM 1 , CM 2 : access command CM 3 : control command 221, 231, 232, 331, 341: storage device 260, 270: memory 370: memory module PRC: code S M , S MA , S MB : monitoring results 411~418: memory addr_A, addr_B: address parameter group DA_A, DA_B: data parameter group TMS_A, TMS_B: time parameter group RorW_A, RorW_B: access parameter group

第1圖為本發明之操作系統的示意圖。 第2圖為本發明之微控制器的示意圖。 第3圖為本發明之微控制器的另一示意圖。 第4圖為本發明之記憶模組的內部示意圖。 Figure 1 is a schematic diagram of the operating system of the present invention. Figure 2 is a schematic diagram of the microcontroller of the present invention. Figure 3 is another schematic diagram of the microcontroller of the present invention. Figure 4 is an internal schematic diagram of the memory module of the present invention.

200:微控制器 200: Microcontroller

210:主裝置 210: main device

220、230:從裝置 220, 230: slave device

240、250:匯流排 240, 250: bus

CM1、CM2:存取指令 CM 1 , CM 2 : Access commands

221、231、232:儲存裝置 221, 231, 232: storage device

260、270:記憶體 260, 270: Memory

PRC:程式碼 PRC: Code

SM:監控結果 S M : Monitoring result

Claims (10)

一種微控制器，包括： 一第一從裝置，根據一第一存取指令，存取一第一儲存裝置； 一主裝置，執行一程式碼，用以提供該第一存取指令；以及 一第一匯流排，耦接於該第一從裝置與該主裝置之間，用以傳送該第一存取指令予該第一從裝置； 其中，當一第一觸發事件發生時，該主裝置監控該第一儲存裝置的存取狀態，用以產生一監控結果予一外部裝置。 A microcontroller including: A first slave device accesses a first storage device according to a first access command; A host device executes a program code to provide the first access command; and A first bus, coupled between the first slave device and the master device, for transmitting the first access command to the first slave device; Wherein, when a first trigger event occurs, the main device monitors the access state of the first storage device to generate a monitoring result to an external device. 如申請專利範圍第1項所述之微控制器，更包括： 一第二從裝置，根據一第二存取指令，存取一第二儲存裝置；以及 一第二匯流排，耦接於該第二從裝置與該主裝置之間，用以傳送該第二存取指令予該第二從裝置，其中該主裝置執行該程式碼，用以提供該第二存取指令。 The microcontroller as described in item 1 of the scope of patent application includes: A second slave device accesses a second storage device according to a second access command; and A second bus, coupled between the second slave device and the master device, for transmitting the second access command to the second slave device, wherein the master device executes the code to provide the The second access instruction. 如申請專利範圍第2項所述之微控制器，其中該第一從裝置係為一通用非同步收發傳輸器(UART)，該第二匯流排係為一積體電路間匯流排(I2C bus)。For the microcontroller described in item 2 of the scope of patent application, the first slave device is a universal asynchronous transceiver (UART), and the second bus is an inter-integrated circuit bus (I2C bus). ). 如申請專利範圍第1項所述之微控制器，其中該主裝置係為一中央處理器(CPU)或是一週邊記憶體直接存取器(PDMA)。As for the microcontroller described in the first item of the patent application, the main device is a central processing unit (CPU) or a peripheral memory direct access device (PDMA). 如申請專利範圍第1項所述之微控制器，更包括： 一記憶體，用以儲存該監控結果。 The microcontroller as described in item 1 of the scope of patent application includes: A memory is used to store the monitoring result. 如申請專利範圍第1項所述之微控制器，其中該主裝置直接輸出該監控結果予該外部裝置。For the microcontroller described in item 1 of the scope of patent application, the main device directly outputs the monitoring result to the external device. 如申請專利範圍第1項所述之微控制器，更包括： 一按鈕，當該按鈕被按下時，表示發生該第一觸發事件。 The microcontroller as described in item 1 of the scope of patent application includes: A button, when the button is pressed, it means that the first trigger event occurs. 如申請專利範圍第1項所述之微控制器，其中當一第二觸發事件發生時，該主裝置停止監控該第一儲存裝置的存取狀態。For the microcontroller described in claim 1, wherein when a second trigger event occurs, the main device stops monitoring the access state of the first storage device. 如申請專利範圍第8項所述之微控制器，其中該程式碼具有一斷點，當該主裝置執行到該斷點時，表示該第二觸發事件發生。For the microcontroller described in item 8 of the scope of patent application, the program code has a breakpoint, and when the main device executes to the breakpoint, it means that the second trigger event occurs. 如申請專利範圍第8項所述之微控制器，其中該第一及第二觸發事件係由該外部裝置所引起。The microcontroller described in item 8 of the scope of patent application, wherein the first and second trigger events are caused by the external device.
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