TWI707468B

TWI707468B - Magnetic memory structure

Info

Publication number: TWI707468B
Application number: TW108125273A
Authority: TW
Inventors: 哈曼羅; 王藝蓉; 魏拯華
Original assignee: 財團法人工業技術研究院
Priority date: 2019-07-17
Filing date: 2019-07-17
Publication date: 2020-10-11
Also published as: TW202105713A

Abstract

A magnetic memory cell having spin-orbit torque (SOT) and voltage controlled magnetic anisotropy (VCMA) effects are provided. A magnetic memory cell according to an embodiment of the invention includes a heavy-metal layer and the magnetic tunneling junction element including a free-layer, a barrier layer, and a pinned-layer. A heavy-metal layer lies under the free magnetic layer and a copper pad is placed outside of the magnetic tunneling junction element and along the heavy-metal layer. The barrier layer, the free-layer and the heavy-metal layer extend out, larger than an elliptic shape top electrode layer pinned-layer. The present embodiment magnetic memory cell structure enlarge the process window over conventional devices and the copper pad which is stitched to the heavy-metal layer serves to lower the cell write voltage. An in-plane charge current is applied to the heavy-metal layer via copper pad, the positive charge current drives the both SOT and VCMA magnetic memory cell into a high-resistance state, that is, parallel to anti-parallel state, while the negative current drives into a low-resistance state, that is, anti-parallel to parallel state.

Description

磁性記憶體結構 Magnetic memory structure

本發明是有關於一種磁性隨機存取記憶體(magnetic random access memory,MARM)結構，且特別是有關於一種具有電壓控制磁性異向性(voltage controlled magnetic anisotropy)特性之自旋軌道轉矩(spin-orbit torque,SOT)磁性記憶體結構。 The present invention relates to a magnetic random access memory (MARM) structure, and more particularly to a spin-orbit torque (spin orbit torque) with voltage controlled magnetic anisotropy characteristics. -orbit torque, SOT) magnetic memory structure.

基於磁穿隧結構(magnetic tunnel junction,MTJ)儲存單元的磁隨機存取記憶體(MRAM)，由一個阻障層隔開2個鐵磁性(ferromagnetic)層組成，已成為未來高性能非揮發性記憶體及邏輯應用非常前景可期的選擇。特別地，自旋轉移轉矩磁隨機存取記憶體(STT-MRAM)由於其CMOS兼容性、優異的非揮發性、高寫入與讀取速度、高耐用性以及更低功耗而引起了眾多關注。它更被認定為新興更具競爭力之非揮發性記憶體，且具有小型化、系統化晶片(system-on-chip)、快速系統操作(Instant on System)等之嵌入式記憶體等的理想選擇，並且對於物聯網(Internet of Things,IoT)設備之類的應用，或各類可攜式電子產品應用等，為備受矚目的理想新世代記憶體。 A magnetic random access memory (MRAM) based on a magnetic tunnel junction (MTJ) storage unit, consisting of a barrier layer separating two ferromagnetic layers, has become a high-performance non-volatile in the future Memory and logic applications are very promising choices. In particular, Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is caused by its CMOS compatibility, excellent non-volatility, high writing and reading speed, high durability, and lower power consumption. Many concerns. It is also recognized as a new and more competitive non-volatile memory, and has the ideals of miniaturization, system-on-chip, and fast system operation (Instant on System) such as embedded memory. Choose, and for applications such as Internet of Things (IoT) devices, or various portable electronic product applications, etc., it is an ideal new-generation memory that has attracted much attention.

儘管STT-MRAM由於其獨特特徵而在全球引起了相當大的關注，但是在技術商業化前須解決一些重大挑戰。該技術已經成熟到矽鑄廠能生產它們的階段。儘管已成熟，然仍有進一步提高其穩健性(robustness)的空間。STT-MRAM技術的主要缺點之一是其可靠性問題，例如：由於相同讀/寫存取路徑，易有讀/寫干擾與錯誤問題，經使用次數增加，也會有阻障層氧化物被擊穿(oxide breakdown)等問題。 Although STT-MRAM has attracted considerable attention worldwide due to its unique characteristics, some major challenges must be solved before the technology can be commercialized. The technology has matured to the stage where silicon foundries can produce them. Although mature, there is still room for further improvement of its robustness. One of the main shortcomings of STT-MRAM technology is its reliability. For example, due to the same read/write access path, it is prone to read/write interference and error problems. After the number of uses increases, the barrier layer oxide will be destroyed. Problems such as oxide breakdown.

為了減輕STT-MRAM的可靠性問題，具有讀/寫不同路徑的自旋軌道轉矩MRAM(SOT-MRAM)被視為是可能的解決方案。相較於二端點型的STT-MRAM，三端點型的SOT-MRAM的優點在於讀寫路徑彼此垂直，這本質上解決了可靠性及穿隧阻障層劣化問題，為記憶體可靠度與耐用性應用提供了新的途徑。 In order to alleviate the reliability problems of STT-MRAM, a spin-orbit torque MRAM (SOT-MRAM) with different read/write paths is considered as a possible solution. Compared with the two-terminal type STT-MRAM, the three-terminal type SOT-MRAM has the advantage that the read and write paths are perpendicular to each other, which essentially solves the problem of reliability and deterioration of the tunnel barrier layer, which is the reliability of the memory. And durability applications provide new ways.

本發明一實施例提出一種磁性記憶體結構磁性記憶體結構包括一磁穿隧結構(magnetic tunneling junction,MJT)及一重金屬層。磁穿隧結構包括一固定層、一阻障層及一自由層。阻障層形成於固定層下方。自由層形成於阻障層下方。重金屬層形成於自由層下方。其中，阻障層具有一第一上表面，固定層具有一下表面，且第一上表面的面積大於下表面的面積。 An embodiment of the present invention provides a magnetic memory structure. The magnetic memory structure includes a magnetic tunneling junction (MJT) and a heavy metal layer. The magnetic tunneling structure includes a fixed layer, a barrier layer and a free layer. The barrier layer is formed under the fixed layer. The free layer is formed under the barrier layer. The heavy metal layer is formed under the free layer. Wherein, the barrier layer has a first upper surface, the fixed layer has a lower surface, and the area of the first upper surface is larger than the area of the lower surface.

本發明另一實施例提出一種磁性記憶體結構磁性記憶體結構包括一磁穿隧結構、一重金屬層及一導電層。重金屬層形成於磁穿隧結構層下方。導電層形成於重金屬層下方。其中，導電層的導電率高於重金屬層的導電率。 Another embodiment of the present invention provides a magnetic memory structure. The magnetic memory structure includes a magnetic tunneling structure, a heavy metal layer, and a conductive layer. Heavy metal layer formation Under the magnetic tunnel structure layer. The conductive layer is formed under the heavy metal layer. Among them, the conductivity of the conductive layer is higher than the conductivity of the heavy metal layer.

為了對本發明之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式詳細說明如下： In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

100、200:磁性記憶體結構 100, 200: Magnetic memory structure

110:頂部電極 110: Top electrode

110s:側表面 110s: side surface

120:磁穿隧結構 120: Magnetic tunneling structure

121:固定層 121: fixed layer

121b:下表面 121b: lower surface

121s:側表面 121s: side surface

122:阻障層 122: barrier layer

122s:第一側表面 122s: the first side surface

122u:第一上表面 122u: the first upper surface

123:自由層 123: free layer

123s:第二側表面 123s: second side surface

130:重金屬層 130: heavy metal layer

130s:第三側表面 130s: third side surface

140:導電層 140: conductive layer

140u:第二上表面 140u: second upper surface

141:第一導電部 141: The first conductive part

141a、142a:渠溝 141a, 142a: Ditch

142:第二導電部 142: The second conductive part

150:介電材料層 150: Dielectric material layer

C11、C12、C21、C22、C31、C32:曲線 C11, C12, C21, C22, C31, C32: Curve

L1、L2:電流 L1, L2: current

V_R:讀取電壓 V _R : Read voltage

SP1:間隔 SP1: interval

V_M:調變電壓 V _M : Modulation voltage

TR1:第一電晶體 TR1: The first transistor

TR2:第二電晶體 TR2: second transistor

第1及2圖繪示依照本發明一實施例之磁性記憶體結構的功能方塊圖。 FIGS. 1 and 2 show functional block diagrams of a magnetic memory structure according to an embodiment of the invention.

第3圖繪示第1圖之磁性記憶體結構的電阻對電流密度(R-J)曲線的示意圖。 FIG. 3 is a schematic diagram of the resistance versus current density (R-J) curve of the magnetic memory structure of FIG. 1. FIG.

第4~9圖繪示依照本揭露另一實施例的磁性記憶體結構的示意圖。 FIGS. 4-9 are schematic diagrams of a magnetic memory structure according to another embodiment of the disclosure.

第10圖繪示磁性記憶體結構100的電阻對電流密度(R-J)曲線的示意圖。 FIG. 10 is a schematic diagram of the resistance versus current density (R-J) curve of the magnetic memory structure 100.

第11圖繪示依照本揭露另一實施例的磁性記憶體結構的示意圖。 FIG. 11 is a schematic diagram of a magnetic memory structure according to another embodiment of the disclosure.

請參照第1~3圖，第1及2圖繪示依照本發明一實施例之磁性記憶體結構100的功能方塊圖，而第3圖繪示第1圖之磁性記憶體結構100的電阻對電流密度(R-J)曲線的示意圖。 Please refer to Figures 1 to 3. Figures 1 and 2 illustrate a functional block diagram of the magnetic memory structure 100 according to an embodiment of the present invention, and Figure 3 illustrates the resistance pair of the magnetic memory structure 100 of Figure 1 Schematic representation of the current density (RJ) curve.

磁性記憶體結構100是一種磁隨機存取記憶體(MRAM)，例如是自旋軌道轉矩(SOT)式磁隨機存取記憶體。磁性記憶體結構100包括頂部電極110、磁穿隧結構120、重金屬層130、導電層140和介電材料層150。 The magnetic memory structure 100 is a magnetic random access memory (MRAM), such as a spin-orbit torque (SOT) type magnetic random access memory. magnetic The sexual memory structure 100 includes a top electrode 110, a magnetic tunnel structure 120, a heavy metal layer 130, a conductive layer 140, and a dielectric material layer 150.

頂部電極110形成在磁穿隧結構120的上方。頂部電極110用以接收由一電壓源(未示出)施加的讀取電壓V_R，以讀取磁穿隧結構120的狀態。 The top electrode 110 is formed above the magnetic tunneling structure 120. The top electrode 110 is used to receive a read voltage V _R applied by a voltage source (not shown) to read the state of the magnetic tunneling structure 120.

磁穿隧結構120包括固定層(pinned-layer)121，阻障層(barrier-layer)122和自由層(free-layer)123。阻障層122形成在固定層121下方，且自由層123形成在阻障層122下方，即阻障層122位於固定層121和自由層123之間。 The magnetic tunneling structure 120 includes a pinned-layer 121, a barrier-layer 122 and a free-layer 123. The barrier layer 122 is formed under the fixed layer 121, and the free layer 123 is formed under the barrier layer 122, that is, the barrier layer 122 is located between the fixed layer 121 and the free layer 123.

磁穿隧結構120的頂部電極110和固定層121分別具有側表面110s及側表面121s。在一個蝕刻製程中，通過同一個光罩(Mask)蝕刻出頂部電極110和固定層121，以形成側表面110s及121s，因此側表面110s及121s大致上彼此對齊。如第1圖所示，頂部電極110與固定層121形成為相同的橢圓形狀。在另一實施例中，頂部電極110的端面形狀可以例如是圓形或多邊形，如正方形、矩形或長方形等。 The top electrode 110 and the fixed layer 121 of the magnetic tunneling structure 120 respectively have a side surface 110s and a side surface 121s. In an etching process, the top electrode 110 and the fixed layer 121 are etched through the same mask to form the side surfaces 110s and 121s, so the side surfaces 110s and 121s are substantially aligned with each other. As shown in FIG. 1, the top electrode 110 and the fixed layer 121 are formed in the same elliptical shape. In another embodiment, the shape of the end surface of the top electrode 110 may be, for example, a circle or a polygon, such as a square, a rectangle, or a rectangle.

此外，阻障層122具有第一上表面122u，固定層121具有下表面121b，其中第一上表面122u的面積大於下表面121b的面積。如第1圖所示，固定層121的下表面121b整個位於阻障層122的第一上表面122u。 In addition, the barrier layer 122 has a first upper surface 122u, and the fixed layer 121 has a lower surface 121b, wherein the area of the first upper surface 122u is larger than the area of the lower surface 121b. As shown in FIG. 1, the lower surface 121b of the fixed layer 121 is entirely located on the first upper surface 122u of the barrier layer 122.

頂部電極110也作為磁穿隧結構120蝕刻結構之硬遮罩(Hard mask)，由於頂部電極110與阻障層122和固定層121不同的材料且具高蝕刻選擇比特性，阻障層122可用作蝕刻停止層(etching stop layer)，利用蝕刻高選擇比特性獲得固定層121及阻障層122的精確厚度。為了提供磁穿隧結構蝕刻停止層，阻障層122的第一上表面122u的面積大於固定層121的下表面121b的面積。在一實施例中，阻障層122由包括氧化鎂(MgO)或其組合的絕緣材料所製成，其不同於被固定層121的磁性材料。 The top electrode 110 is also used as a hard mask for the etching structure of the magnetic tunneling structure 120, due to the different materials of the top electrode 110, the barrier layer 122 and the fixed layer 121 Moreover, it has a high etching selectivity. The barrier layer 122 can be used as an etching stop layer, and the precise thickness of the fixed layer 121 and the barrier layer 122 can be obtained by using the high etching selectivity. In order to provide an etch stop layer of the magnetic tunnel structure, the area of the first upper surface 122u of the barrier layer 122 is larger than the area of the lower surface 121b of the fixed layer 121. In an embodiment, the barrier layer 122 is made of an insulating material including magnesium oxide (MgO) or a combination thereof, which is different from the magnetic material of the fixed layer 121.

如第1圖所示，重金屬層130形成在自由層123下方。阻障層122、自由層123及重金屬層130分別具有第一側表面122s、第二側表面123s及第三側表面130s。在一蝕刻製程中，通過同一個光罩蝕刻出阻障層122、自由層123及重金屬層130，以形成第一側表面122s、第二側表面123s及第三側表面130s。因此，第一側表面122s、第二側表面123s與第三側表面130s大致上彼此對齊(或齊平)。如第1圖所示，阻障層122、自由層123及重金屬層130形成為相同的多邊形形狀，例如是矩形或正方形，然亦可為橢圓形或圓形。 As shown in FIG. 1, the heavy metal layer 130 is formed under the free layer 123. The barrier layer 122, the free layer 123 and the heavy metal layer 130 respectively have a first side surface 122s, a second side surface 123s, and a third side surface 130s. In an etching process, the barrier layer 122, the free layer 123 and the heavy metal layer 130 are etched through the same photomask to form the first side surface 122s, the second side surface 123s, and the third side surface 130s. Therefore, the first side surface 122s, the second side surface 123s, and the third side surface 130s are substantially aligned (or flush) with each other. As shown in FIG. 1, the barrier layer 122, the free layer 123, and the heavy metal layer 130 are formed in the same polygonal shape, such as a rectangle or a square, but can also be an ellipse or a circle.

在一些實施例中，固定層121可包括單層或複合層。在一些實施例中，固定層121可包括單層，例如，鈷鐵(CoFe)合金，鈷鐵硼(CoFeB)合金或鈷鎳(CoNi)合金。在一些實施例中，固定層121可包括複合層，例如，鈷(Co)層/鉑(Pt)層，鈷(Co)層/鎳(Ni)層或鈷(Co)層/鈀(Pd)層。 In some embodiments, the fixing layer 121 may include a single layer or a composite layer. In some embodiments, the fixed layer 121 may include a single layer, for example, a cobalt iron (CoFe) alloy, a cobalt iron boron (CoFeB) alloy, or a cobalt nickel (CoNi) alloy. In some embodiments, the fixed layer 121 may include a composite layer, for example, a cobalt (Co) layer/platinum (Pt) layer, a cobalt (Co) layer/nickel (Ni) layer or a cobalt (Co) layer/palladium (Pd) Floor.

在一些實施例中，阻障層122可包括氧化鎂(MgO)或氧化鋁(AlOx)。在一些實施例中，阻障層122的厚度T1可介於約0.5奈米(nm)至2奈米的範圍內。 In some embodiments, the barrier layer 122 may include magnesium oxide (MgO) or aluminum oxide (AlOx). In some embodiments, the thickness T1 of the barrier layer 122 may be in the range of about 0.5 nanometers (nm) to 2 nanometers.

在一些實施例中，自由層123可包括單層或複合層。在一些實施例中，自由層123可包括單層，例如，鐵(Fe)、鈷(Co)、鎳(Ni)、釓(Gd)、鋱(Tb)、鈷鐵硼(CoFeB)合金或鈷鐵(CoFe)合金。在一些實施例中，自由層123可包括複合層，例如，鈷鐵硼(CoFeB)合金/鉭(Ta)/鈷鐵硼(CoFeB)合金或鈷鐵(CoFe)合金/鉭(Ta)/鈷鐵(CoFe)。另外，在一些實施例中，自由層123的厚度T2介於約1nm至約3nm的範圍內。 In some embodiments, the free layer 123 may include a single layer or a composite layer. In some embodiments, the free layer 123 may include a single layer, for example, iron (Fe), cobalt (Co), nickel (Ni), gamma (Gd), po (Tb), cobalt iron boron (CoFeB) alloy, or cobalt Iron (CoFe) alloy. In some embodiments, the free layer 123 may include a composite layer, for example, cobalt iron boron (CoFeB) alloy/tantalum (Ta)/cobalt iron boron (CoFeB) alloy or cobalt iron (CoFe) alloy/tantalum (Ta)/cobalt Iron (CoFe). In addition, in some embodiments, the thickness T2 of the free layer 123 is in the range of about 1 nm to about 3 nm.

在一些實施例中，重金屬層130可以由包括鉭(Ta)，鎢(W)、鉑(Pt)、鈀(Pd)、鉿(Hf)、鈮(Nb)、鉬(Mo)、金(Au)、鋯金屬(Zr)或其合金所製成，但不限於此。在一些實施例中，重金屬層130的厚度T3可小於10nm。 In some embodiments, the heavy metal layer 130 may be made of tantalum (Ta), tungsten (W), platinum (Pt), palladium (Pd), hafnium (Hf), niobium (Nb), molybdenum (Mo), gold (Au ), zirconium metal (Zr) or its alloy, but not limited to this. In some embodiments, the thickness T3 of the heavy metal layer 130 may be less than 10 nm.

導電層140形成在重金屬層130下方。導電層140包括彼此分離的第一導電部141及第二導電部142，且第一導電部141及第二導電部142連接於重金屬層130之二端。導電層140的導電率高於重金屬層130的導電率。與沒有導電層140的結構相比，本實施例之導電層140能增加重金屬層130與導電層140之整體的導電率，因此可降低第1圖電流L1及第2圖電流L2的驅動電壓。另外，在一實施例中，導電層140由例如是銀、金、銅、鋁或其組合的材料製成。 The conductive layer 140 is formed under the heavy metal layer 130. The conductive layer 140 includes a first conductive portion 141 and a second conductive portion 142 separated from each other, and the first conductive portion 141 and the second conductive portion 142 are connected to two ends of the heavy metal layer 130. The conductivity of the conductive layer 140 is higher than the conductivity of the heavy metal layer 130. Compared with the structure without the conductive layer 140, the conductive layer 140 of this embodiment can increase the overall conductivity of the heavy metal layer 130 and the conductive layer 140, and therefore can reduce the driving voltage of the current L1 in the first diagram and the current L2 in the second diagram. In addition, in an embodiment, the conductive layer 140 is made of a material such as silver, gold, copper, aluminum or a combination thereof.

如第1圖所示。在一寫入編程中，施加電流L1以流過第一導電部141、重金屬層130及第二導電部142，以便切換磁穿隧結構120的自由層123從狀態“0”至狀態“1”(或從狀態“1”到狀態“0”)，其中狀態“0”表示固定層121與自由層123的磁化方向例如是相同的，而狀態“1”表示例如固定層121與自由層123的磁化方向例如是相反。 As shown in Figure 1. In a write programming, a current L1 is applied to flow through the first conductive portion 141, the heavy metal layer 130, and the second conductive portion 142 to switch the free layer 123 of the magnetic tunneling structure 120 from state "0" to state "1" (Or from the state "1" to the state "0"), where the state "0" represents the magnetization directions of the fixed layer 121 and the free layer 123, for example Are the same, and the state “1” indicates that, for example, the magnetization directions of the fixed layer 121 and the free layer 123 are opposite, for example.

如第2圖所示，在另一寫入編程中，施加反向之電流L2流過第二導電部142、重金屬層130及第一導電部141，以便切換磁穿隧結構120的自由層123從狀態“1”至狀態“0”(或從狀態“0”到狀態“1”)。 As shown in Figure 2, in another write programming, a reverse current L2 is applied to flow through the second conductive portion 142, the heavy metal layer 130, and the first conductive portion 141 to switch the free layer 123 of the magnetic tunneling structure 120 From state "1" to state "0" (or from state "0" to state "1").

如第1~3圖所示，讀取電壓V_R施加在頂部電極110及第一導電部141之間或頂部電極110與第二導電部142之間，以在一寫入操作中讀取平行狀態(P state)電阻或反平行狀態(AP state)電阻。在一實施例中，所需的讀取電壓V_R例如是0.1伏特(Volt)，更多或更少。 As shown in FIGS. 1 to 3, the read voltage V _R is applied between the top electrode 110 and the first conductive portion 141 or top electrode 110 and the second conductive portion 142, to read a write operation in parallel State (P state) resistance or anti-parallel state (AP state) resistance. In one embodiment, the desired read voltage V _R, for example, 0.1 volts (the Volt), more or less.

由於阻障層122為磁穿隧結構之蝕刻停止層，且阻障層122的第一上表面122u的面積大於固定層121的下表面121b的面積，因此可完整保護磁穿隧結構區的重金屬層均勻性，而不被蝕刻電漿影響其厚度均勻性，使重金屬層130的厚度可精確控制。在一實施例中，重金屬層130的厚度T3可精確地控制在約3nm~約10nm之間。 Since the barrier layer 122 is an etch stop layer of the magnetic tunneling structure, and the area of the first upper surface 122u of the barrier layer 122 is larger than the area of the lower surface 121b of the fixed layer 121, it can completely protect the heavy metals in the magnetic tunneling structure area The layer uniformity is not affected by the etching plasma, so that the thickness of the heavy metal layer 130 can be accurately controlled. In an embodiment, the thickness T3 of the heavy metal layer 130 can be accurately controlled between about 3 nm and about 10 nm.

如第1圖所示，導電層140具有從重金屬層130露出的第二上表面140u。換句話說，如第1圖所示，導電層140延伸超出重金屬層130的側表面130s、阻障層122的第一側表面122s及自由層123的第二側表面123s。 As shown in FIG. 1, the conductive layer 140 has a second upper surface 140u exposed from the heavy metal layer 130. In other words, as shown in FIG. 1, the conductive layer 140 extends beyond the side surface 130s of the heavy metal layer 130, the first side surface 122s of the barrier layer 122, and the second side surface 123s of the free layer 123.

如第1圖所示，介電材料層150蝕刻定義出渠溝141a與142a，並將渠溝填入導電材料，經過平坦化製程處理後，形成第一導電部141、第二導電部142及第一導電部141與第二導電部142之間的間隔SP1。 As shown in Figure 1, the dielectric material layer 150 etches trenches 141a and 142a to define trenches 141a and 142a, and fills the trenches with conductive material. After a planarization process, a first conductive material is formed. The electrical part 141, the second conductive part 142, and the space SP1 between the first conductive part 141 and the second conductive part 142.

請參照第4~10圖所示，第4~9圖繪示依照本揭露另一實施例的磁性記憶體結構100的示意圖，而第10圖示繪示磁性記憶體結構100的電阻對電流密度(R-J)曲線的示意圖。 Please refer to FIGS. 4-10. FIGS. 4-9 show a schematic diagram of a magnetic memory structure 100 according to another embodiment of the present disclosure, and the 10th diagram shows the resistance versus current density of the magnetic memory structure 100 (RJ) Schematic diagram of the curve.

如第4~9圖所示，由外部電壓源施加調變電壓V_M以調變磁穿隧結構120的能障(energy barrier)。相同地，將讀取電壓V_R施加在頂部電極110與第一導電部141之間或頂部電極110與第二導電部142之間，以在寫入操作中讀取P狀態電阻(低阻態)或AP狀態電阻(高阻態)。 As shown in FIGS. 4-9, an external voltage source applies a modulating voltage V _M to modulate the energy barrier of the magnetic tunneling structure 120. Similarly, the read voltage V _R is applied between the top electrode 110 and the first conductive portion 141 or top electrode 110 and the second conductive portion 142, to read the resistance of the P state in a write operation (low resistance state ) Or AP state resistance (high impedance state).

如第4圖所示，在寫入編程中，施加電流L1流過第一導電部141，重金屬層130和第二導電部142，以切換磁穿隧結構120的自由層123從狀態“0”至狀態“1”(或從狀態“1”至狀態“0”)，其中電壓V_M為0。 As shown in Fig. 4, during write programming, an applied current L1 flows through the first conductive portion 141, the heavy metal layer 130 and the second conductive portion 142 to switch the free layer 123 of the magnetic tunneling structure 120 from the state "0". To state "1" (or from state "1" to state "0"), where the voltage V _M is zero.

如第5圖所示，在另一寫入編程中，施加反向電流L2流經第二導電部142、重金屬層130及第一導電部141，以切換磁穿隧結構120的自由層123從狀態“1”至狀態“0”(或從狀態“0”至狀態“1”)，其中調變電壓V_M為0。 As shown in FIG. 5, in another write programming, a reverse current L2 is applied to flow through the second conductive portion 142, the heavy metal layer 130, and the first conductive portion 141 to switch the free layer 123 of the magnetic tunneling structure 120 from From state "1" to state "0" (or from state "0" to state "1"), the modulated voltage V _M is zero.

如第6圖所示，在一寫入編程中，施加電流L1流經第一導電部141、重金屬層130及第二導電部142，以切換磁穿隧結構120的自由層123從狀態“0”至狀態“1”(或從狀態“1”至狀態“0”)，其中電壓V_M為+0.5V。 As shown in Figure 6, in a write programming, an applied current L1 flows through the first conductive portion 141, the heavy metal layer 130, and the second conductive portion 142 to switch the free layer 123 of the magnetic tunneling structure 120 from the state "0". "To state "1" (or from state "1" to state "0"), where the voltage V _M is +0.5V.

如第7圖所示，在另一寫入編程中，施加反向電流L2流經第二導電部142、重金屬層130及第一導電部141，以切換磁穿隧結構120的自由層123從狀態“1”至狀態“0”(或從狀態“0”至狀態“1”)，其中電壓V_M為+0.5V。 As shown in FIG. 7, in another write programming, a reverse current L2 is applied to flow through the second conductive portion 142, the heavy metal layer 130, and the first conductive portion 141 to switch the free layer 123 of the magnetic tunneling structure 120 from From state "1" to state "0" (or from state "0" to state "1"), the voltage V _M is +0.5V.

如第8圖所示，在一寫入編程中，施加電流L1流經第一導電部141、重金屬層130及第二導電部142，以切換磁穿隧結構120的自由層123從狀態“0”至狀態“1”(或從狀態“1”至狀態“0”)，其中電壓V_M為-0.5V。 As shown in Figure 8, in a write programming, the applied current L1 flows through the first conductive portion 141, the heavy metal layer 130, and the second conductive portion 142 to switch the free layer 123 of the magnetic tunneling structure 120 from the state "0". "To state "1" (or from state "1" to state "0"), where the voltage V _M is -0.5V.

如第9圖所示，在另一寫入編程中，施加反向電流L2流經第二導電部142、重金屬層130及第一導電部141，以切換磁穿隧結構120的自由層123從狀態“1”至狀態“0”(或從狀態“0”至狀態“1”)，其中電壓V_M為-0.5V。 As shown in FIG. 9, in another write programming, a reverse current L2 is applied to flow through the second conductive portion 142, the heavy metal layer 130, and the first conductive portion 141 to switch the free layer 123 of the magnetic tunnel structure 120 from From state "1" to state "0" (or from state "0" to state "1"), the voltage V _M is -0.5V.

在SOT-MRAM記憶胞(cell)中，平面內電流(in-plane current)流過重金屬層130。由於重金屬層的自旋霍爾效應(Hall effect,SHE)，自旋極化電子累積在金屬層/自由層的接面處，導致橫向純自旋電流流入自由層。第10圖的曲線C11和C12所示，正電流(如曲線C11)將SOT-MRAM記憶胞驅動為高電阻狀態(high-resistance state,HRS)，而負電流(如曲線C12)驅動SOT-MRAM記憶胞進入低電阻狀態(low-resistance state,LRS)。因此，可藉由施加電流通過重金屬層來改變相鄰自由層之磁化狀態。如第10圖的曲線C11所示，當正電流的電流密度達到閾值(例如，第10圖所示的曲線C11為28MA/cm²)時，允許磁穿隧結構120的自由層123的狀態改變。當負電流的電流密度低於閾值(例如，第10圖所示的曲線C12為-28MA/cm²)時，允許磁穿隧結構120的自由層123的狀態改變。 In the SOT-MRAM cell, an in-plane current flows through the heavy metal layer 130. Due to the spin Hall effect (Hall effect, SHE) of the heavy metal layer, spin-polarized electrons accumulate at the junction of the metal layer/free layer, causing a lateral pure spin current to flow into the free layer. As shown by the curves C11 and C12 in Figure 10, the positive current (such as the curve C11) drives the SOT-MRAM memory cell into a high-resistance state (HRS), while the negative current (such as the curve C12) drives the SOT-MRAM The memory cell enters the low-resistance state (LRS). Therefore, the magnetization state of the adjacent free layer can be changed by applying current through the heavy metal layer. As shown by the curve C11 in Fig. 10, when the current density of the positive current reaches the threshold (for example, the curve C11 in Fig. 10 is 28 MA/cm ² ), the state of the free layer 123 of the magnetic tunneling structure 120 is allowed to change . When the current density of the negative current is lower than the threshold (for example, the curve C12 shown in FIG. 10 is -28 MA/cm ² ), the state of the free layer 123 of the magnetic tunneling structure 120 is allowed to change.

如第10圖的曲線C11及C12所示，當電壓V_M為0V或沒有偏壓(bias)施加時，從P狀態切換到AP狀態以及從AP狀態切換到P狀態的閾值類似如上述的SOT-MRAM單元的切換。 As shown by the curves C11 and C12 in Figure 10, when the voltage V _M is 0V or no bias is applied, the thresholds for switching from the P state to the AP state and from the AP state to the P state are similar to the above SOT -MRAM cell switching.

如第10圖的曲線C21及C22所示，當電壓V_M為-0.5V的偏壓時，從P狀態切換到AP狀態以及從AP狀態切換到P狀態的閾值下降，例如，從+28MA/cm²(如曲線C11)或-28MA/cm²(如曲線C12)至+26MA/cm²(如曲線C21)或-26MA/cm²(如曲線C22)。 As shown by the curves C21 and C22 in Figure 10, when the voltage V _M is biased at -0.5V, the threshold for switching from the P state to the AP state and from the AP state to the P state decreases, for example, from +28MA/ cm ² (such as curve C11) or -28MA/cm ² (such as curve C12) to +26MA/cm ² (such as curve C21) or -26MA/cm ² (such as curve C22).

如第10圖的曲線C31及C32所示，當電壓V_M為+0.5V的偏壓時，從P狀態切換到AP狀態以及從AP狀態切換到P狀態的閾值上升，例如，從+28MA/cm²(如曲線C11)或-28MA/cm²(如曲線C12)至+31MA/cm²(如曲線C31)或-31MA/cm²(如曲線C32)。 As shown by the curves C31 and C32 in Figure 10, when the voltage V _M is a bias of +0.5V, the threshold for switching from the P state to the AP state and from the AP state to the P state rises, for example, from +28MA/ cm ² (such as curve C11) or -28MA/cm ² (such as curve C12) to +31MA/cm ² (such as curve C31) or -31MA/cm ² (such as curve C32).

如第11圖所示，其繪示依照本揭露另一實施例的磁性記憶體結構200的示意圖。如上所述的用於控制閾值調變效果的電壓V_M可應用於基於未來高密度非揮發性記憶體(NVM)領域的電壓控制磁異向性輔助型多位元SOT記憶胞結構(voltage controlled magnetic anisotropy(VCMA)-assisted multibit SOT cell structure)。 As shown in FIG. 11, it is a schematic diagram of a magnetic memory structure 200 according to another embodiment of the disclosure. The voltage V _M used to control the threshold modulation effect as described above can be applied to the voltage controlled magnetic anisotropy assisted multi-bit SOT memory cell structure based on the future high-density non-volatile memory (NVM) field. magnetic anisotropy(VCMA)-assisted multibit SOT cell structure).

如第11圖所示，一個頂部電極110形成在對應的磁穿隧結構120上方，且一個開關260與對應的頂部電極110電連接，用於判斷偏壓是否施加到頂部電極110。 As shown in FIG. 11, a top electrode 110 is formed above the corresponding magnetic tunneling structure 120, and a switch 260 is electrically connected to the corresponding top electrode 110 for determining whether a bias voltage is applied to the top electrode 110.

如第11圖所示，磁性記憶體結構200包括多個頂部電極110、多個磁穿隧結構120、重金屬層130、導電層140、介電材料層150及多個開關260。 As shown in FIG. 11, the magnetic memory structure 200 includes a plurality of top electrodes 110, a plurality of magnetic tunneling structures 120, a heavy metal layer 130, a conductive layer 140, a dielectric material layer 150 and a plurality of switches 260.

在本實施例中，重金屬層130形成在所有磁穿隧結構120下方，且磁穿隧結構120上下重疊於第一導電部141與第二導電部142間的間隔SP1。在磁性記憶體結構200中，藉由電流流經二個導電部(第一導電部141及第二導電部142)，多個磁穿隧結構120的多個狀態受到控制而改變。 In this embodiment, the heavy metal layer 130 is formed under all the magnetic tunneling structures 120, and the magnetic tunneling structure 120 overlaps the space SP1 between the first conductive portion 141 and the second conductive portion 142 up and down. In the magnetic memory structure 200, by the current flowing through two conductive portions (the first conductive portion 141 and the second conductive portion 142), the multiple states of the multiple magnetic tunneling structures 120 are controlled and changed.

如第11圖所示，介電材料層150蝕刻定義出渠溝141a與142b，並於渠溝141a及142b渠溝填入導電材料，經過平坦化製程處理後，形成第一導電部141、第二導電部142及與第一導電部141與第二導電部142部之間的間隔SP1。換句話說，沒有任何導電部設置於間隔SP1。此外，第一電晶體TR1與第一導電部141電連接，第二電晶體TR2與第二導電部142電連接。流向第一導電部141的電流L1的通過與否由第一電晶體TR1控制，而流向第二導電部142的電流L2的通過與否由第二電晶體TR2控制。在本實施例中，多個磁穿隧結構120的自由層123的狀態可以僅由二個電晶體(第一電晶體TR1及第二電晶體TR2)控制/切換。 As shown in Figure 11, the dielectric material layer 150 defines trenches 141a and 142b by etching, and the trenches 141a and 142b are filled with conductive materials. After a planarization process, first conductive portions 141 and The space SP1 between the two conductive portions 142 and the first conductive portion 141 and the second conductive portion 142. In other words, no conductive part is provided in the space SP1. In addition, the first transistor TR1 is electrically connected to the first conductive portion 141, and the second transistor TR2 is electrically connected to the second conductive portion 142. The passage of the current L1 to the first conductive portion 141 is controlled by the first transistor TR1, and the passage of the current L2 to the second conductive portion 142 is controlled by the second transistor TR2. In this embodiment, the state of the free layer 123 of the plurality of magnetic tunneling structures 120 can be controlled/switched by only two transistors (the first transistor TR1 and the second transistor TR2).

綜上所述，雖然本發明已以實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those who have ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100:磁性記憶體結構 100: Magnetic memory structure

110:頂部電極 110: Top electrode

110s:側表面 110s: side surface

120:磁穿隧結構 120: Magnetic tunneling structure

121:固定層 121: fixed layer

121b:下表面 121b: lower surface

121s:側表面 121s: side surface

122:阻障層 122: barrier layer

122s:第一側表面 122s: the first side surface

122u:第一上表面 122u: the first upper surface

123:自由層 123: free layer

123s:第二側表面 123s: second side surface

130:重金屬層 130: heavy metal layer

130s:第三側表面 130s: third side surface

140:導電層 140: conductive layer

141:第一導電部 141: The first conductive part

141a、142a:渠溝 141a, 142a: Ditch

142:第二導電部 142: The second conductive part

150:介電材料層 150: Dielectric material layer

V_R:讀取電壓 V _R : Read voltage

SP1:間隔 SP1: interval

Claims

一種磁性記憶體結構，包括：一磁穿隧結構(magnetic tunneling junction,MJT)，包括：一固定層(pinned-layer)；一阻障層(barrier-layer)，形成於該固定層下方；及一自由層(free-layer)，形成於該阻障層下方；一重金屬層，形成於該自由層下方；其中，該阻障層具有一第一上表面，該固定層具有一下表面，且該第一上表面的面積大於該下表面的面積。 A magnetic memory structure includes: a magnetic tunneling junction (MJT) structure, including: a pinned-layer; a barrier-layer formed under the pinned layer; and A free-layer is formed under the barrier layer; a heavy metal layer is formed under the free layer; wherein the barrier layer has a first upper surface, the fixed layer has a lower surface, and the The area of the first upper surface is greater than the area of the lower surface.

如申請專利範圍第1項所述之磁性記憶體結構，其中該固定層的該下表面整個位於該阻障層的該第一上表面上。 In the magnetic memory structure described in claim 1, wherein the lower surface of the fixed layer is entirely located on the first upper surface of the barrier layer.

如申請專利範圍第1項所述之磁性記憶體結構，其中該阻障層、該自由層及該重金屬層分別具有一第一側表面，一第二側表面及一第三側表面，該第一側表面、該第二側表面與該第三側表面互相對齊。 As for the magnetic memory structure described in claim 1, wherein the barrier layer, the free layer and the heavy metal layer respectively have a first side surface, a second side surface and a third side surface, the first One side surface, the second side surface and the third side surface are aligned with each other.

如申請專利範圍第1項所述之磁性記憶體結構，更包括：一導電層，形成在該重金屬層下方；其中，該導電層的導電率高於該重金屬層的導電率。 The magnetic memory structure described in item 1 of the scope of the patent application further includes: a conductive layer formed under the heavy metal layer; wherein the conductivity of the conductive layer is higher than that of the heavy metal layer.

如申請專利範圍第4項所述之磁性記憶體結構，其中該導電層包括一第一導電部及一第二導電部，該第一導電部及該第二導電部分別連接該重金屬層的二端。 According to the magnetic memory structure described in claim 4, the conductive layer includes a first conductive portion and a second conductive portion, and the first conductive portion and the second conductive portion are respectively connected to two of the heavy metal layer end.

如申請專利範圍第4項所述之磁性記憶體結構，其中該導電層具有一從該重金屬層露出的第二上表面。 According to the magnetic memory structure described in claim 4, the conductive layer has a second upper surface exposed from the heavy metal layer.

如申請專利範圍第4項所述之磁性記憶體結構，其中該重金屬層具有一側表面，該導電層延伸超出該重金屬層的該側表面。 In the magnetic memory structure described in claim 4, the heavy metal layer has a side surface, and the conductive layer extends beyond the side surface of the heavy metal layer.

如申請專利範圍第5項所述之磁性記憶體結構，更包括：一介電材料層，形成該第一導電部與該第二導電部之間的間隔。 The magnetic memory structure described in item 5 of the scope of the patent application further includes: a dielectric material layer forming a gap between the first conductive portion and the second conductive portion.

如申請專利範圍第5項所述之磁性記憶體結構，包括：複數個該磁穿隧結構；其中，該重金屬層形成在所有該些磁穿隧結構下方，且該些磁穿隧結構上下重疊該第一導電部與該第二導電部之間的間隔。 The magnetic memory structure described in item 5 of the scope of patent application includes: a plurality of the magnetic tunneling structures; wherein, the heavy metal layer is formed under all the magnetic tunneling structures, and the magnetic tunneling structures overlap up and down The interval between the first conductive portion and the second conductive portion.

如申請專利範圍第9項所述之磁性記憶體結構，其中沒有任何導電部設置在該第一導電部與該第二導電部之間的間隔。 According to the magnetic memory structure described in item 9 of the scope of patent application, there is no conductive portion provided in the interval between the first conductive portion and the second conductive portion.

一種磁性記憶體結構，包括：一磁穿隧結構；一重金屬層，形成於該磁穿隧結構下方；以及一導電層，形成於該重金屬層下方；其中，該導電層的導電率高於該重金屬層的導電率；其中，該導電層包括一第一導電部及一第二導電部，該第一導電部及該第二導電部分別連接該重金屬層的二端。 A magnetic memory structure includes: a magnetic tunnel structure; a heavy metal layer formed under the magnetic tunnel structure; and a conductive layer formed under the heavy metal layer; wherein the conductivity of the conductive layer is higher than the The conductivity of the heavy metal layer; The conductive layer includes a first conductive portion and a second conductive portion, and the first conductive portion and the second conductive portion are respectively connected to two ends of the heavy metal layer.

如申請專利範圍第11項所述之磁性記憶體結構，其中該磁穿隧結構包括一固定層、一阻障層及一自由層，且該阻障層位於該固定層與該自由層之間。 The magnetic memory structure according to claim 11, wherein the magnetic tunneling structure includes a fixed layer, a barrier layer and a free layer, and the barrier layer is located between the fixed layer and the free layer .

如申請專利範圍第12項所述之磁性記憶體結構，其中該阻障層具有一第一上表面，該固定層具有一下表面，該固定層的該下表面整個位於該阻障層的該第一上表面上。 According to the magnetic memory structure described in claim 12, the barrier layer has a first upper surface, the fixed layer has a lower surface, and the lower surface of the fixed layer is entirely located on the first surface of the barrier layer. One on the surface.

如申請專利範圍第12項所述之磁性記憶體結構，其中該阻障層、該自由層及該重金屬層分別具有一第一側表面，一第二側表面及一第三側表面，該第一側表面、該第二側表面與該第三側表面互相對齊。 As for the magnetic memory structure described in claim 12, the barrier layer, the free layer and the heavy metal layer respectively have a first side surface, a second side surface and a third side surface, and the first side surface One side surface, the second side surface and the third side surface are aligned with each other.

如申請專利範圍第11項所述之磁性記憶體結構，其中該導電層具有從該重金屬層露出的一第二上表面。 The magnetic memory structure described in claim 11, wherein the conductive layer has a second upper surface exposed from the heavy metal layer.

如申請專利範圍第11項所述之磁性記憶體結構，其中該重金屬層具有一側表面，該導電層延伸超出該重金屬層的該側表面。 The magnetic memory structure described in claim 11, wherein the heavy metal layer has a side surface, and the conductive layer extends beyond the side surface of the heavy metal layer.

如申請專利範圍第11項所述之磁性記憶體結構，更包括：一介電材料層，形成該第一導電部與該第二導電部之間的間隔。 The magnetic memory structure described in item 11 of the scope of the patent application further includes: a dielectric material layer forming an interval between the first conductive portion and the second conductive portion.

如申請專利範圍第11項所述之磁性記憶體結構，包括：複數個該磁穿隧結構；其中，該重金屬層形成在所有該些磁穿隧結構下方，且該些磁穿隧結構上下重疊該第一導電部與該第二導電部之間的間隔。 The magnetic memory structure described in item 11 of the scope of patent application includes: A plurality of the magnetic tunneling structures; wherein, the heavy metal layer is formed under all the magnetic tunneling structures, and the magnetic tunneling structures overlap the interval between the first conductive part and the second conductive part up and down.

如申請專利範圍第18項所述之磁性記憶體結構，其中沒有任何導電部設置在該第一導電部與該第二導電部之間的間隔。 According to the magnetic memory structure described in item 18 of the scope of patent application, there is no conductive portion provided in the interval between the first conductive portion and the second conductive portion.