TWI706534B - Esd protection structure and esd robust semiconductor device - Google Patents

Esd protection structure and esd robust semiconductor device Download PDF

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TWI706534B
TWI706534B TW107123354A TW107123354A TWI706534B TW I706534 B TWI706534 B TW I706534B TW 107123354 A TW107123354 A TW 107123354A TW 107123354 A TW107123354 A TW 107123354A TW I706534 B TWI706534 B TW I706534B
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substrate
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base
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TW107123354A
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TW202006921A (en
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陳樂凡
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新唐科技股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path

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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

An electrostatic discharge protection structure includes a substrate, a deep well region, a drain region, a p-top region, a field oxide region, a gate region, a base region and an extra region. The deep well region is disposed on the substrate. The drain region is disposed on the deep well region to act as an input terminal. The p-top region is disposed on the deep well region and adjacent to the drain region. The field oxide region is disposed on the p-top region and covers the p-top region and a part of the drain region. The gate region is disposed on the field oxide region and covers the part of the deep well region and the field oxide region to act as a control terminal. The base region is disposed on the substrate and adjacent to the gate region to act as a base terminal. The extra region is disposed on the substrate and is located on the side of the base region opposite to the other side of the base region adjacent to the gate region. The extra region is disposed away from the gate region to act as an output terminal. By means of the foregoing configuration, the parasitic transistor is formed between the extra region, the base region and the drain region to divert the electrostatic discharge away from the electrostatic discharge protection structure .

Description

靜電放電防護結構及靜電放電強健型半導體裝置 Electrostatic discharge protection structure and electrostatic discharge robust semiconductor device

本發明關於一種靜電放電防護結構，特別是，一種用於保護半導體元件免於靜電損害的靜電放電防護結構及其靜電放電強健型半導體裝置。 The present invention relates to an electrostatic discharge protection structure, in particular, an electrostatic discharge protection structure for protecting semiconductor elements from electrostatic damage and an electrostatic discharge robust semiconductor device.

靜電放電(electrostatic discharge,ESD)為表面電荷放電的現象，其造成積體電路、半導體元件及其組成之電路的損害。一般而言，靜電放電通常為人為造成的，舉例來說，電子元件或系統在製造、生產、組裝、測試、存放和搬運等的過程中，靜電會累積在人體、儀器及儲放設備等之中，甚至在電子元件本身也會累積靜電，而人們在不知情的情況下，使這些物體相互接觸，因而形成了放電路徑，使得電子元件或系統遭到靜電放電的破壞。 Electrostatic discharge (ESD) is a phenomenon in which surface charges are discharged, which causes damage to integrated circuits, semiconductor components, and circuits composed of them. Generally speaking, electrostatic discharge is usually caused by humans. For example, during the manufacturing, production, assembly, testing, storage and handling of electronic components or systems, static electricity will accumulate on the human body, instruments and storage equipment, etc. Among them, even the electronic components themselves accumulate static electricity, and people make these objects contact each other without knowing it, thus forming a discharge path, causing the electronic components or systems to be destroyed by electrostatic discharge.

因此，通常為了避免靜電放電的現象，會在現有的電路中外加靜電保護電路或元件。其中，橫向擴散金氧半導體(Laterally Diffused Metal Oxide Semiconductor,LDMOS)為常見的靜電保護元件，然而，現有的橫向擴散金氧半導體並未能承受2kV以上的高壓，且在多次使用後會於其閘極造成損害，導致整個橫向擴散金氧半導體的功能故障。 Therefore, in order to avoid electrostatic discharge, an electrostatic protection circuit or component is added to the existing circuit. Among them, Laterally Diffused Metal Oxide Semiconductor (LDMOS) is a common electrostatic protection element. However, the existing laterally diffused Metal Oxide Semiconductor cannot withstand the high voltage above 2kV. The gate causes damage, leading to a malfunction of the entire lateral diffusion metal oxide semiconductor.

美國公告號US7916439B2之專利前案為在橫向擴散金氧半導體附加一個雙極性電晶體，以降低多次使用後對其閘極的損害，然而，附加的雙 極性電晶體導致橫向擴散金氧半導體的元件長度變長，增加積體電路的尺寸，導致難以應用在要求微型化的積體電路中。 The pre-patent of US Publication No. US7916439B2 is to add a bipolar transistor to the laterally diffused metal oxide semiconductor to reduce the damage to its gate after multiple uses. However, the additional double Polar transistors cause the length of the laterally diffused metal oxide semiconductor components to become longer and increase the size of the integrated circuit, which makes it difficult to apply to the integrated circuit that requires miniaturization.

綜觀前所述，本發明之發明者思索並設計一種靜電放電防護結構及靜電放電強健型半導體裝置，以期針對習知技術之缺失加以改善，進而增進產業上之實施利用。 In summary, the inventor of the present invention considered and designed an electrostatic discharge protection structure and an electrostatic discharge robust semiconductor device, in order to improve the lack of conventional technology, and further enhance the industrial application.

有鑑於上述習知之問題，本發明的目的在於提供一種靜電放電防護結構及靜電放電強健型半導體裝置，用以解決習知技術中所面臨之問題。 In view of the above-mentioned conventional problems, the purpose of the present invention is to provide an electrostatic discharge protection structure and an electrostatic discharge robust semiconductor device to solve the problems faced by the conventional technology.

基於上述目的，本發明提供一種靜電放電防護結構，其包括基板、深井區、汲極區、頂摻雜區、氧化層區、閘極區、基體區以及擴增區。深井區設置於基板上；汲極區設置於深井區上以作為輸入端；頂摻雜區設置於深井區上且鄰近汲極區，且頂摻雜區係使汲極區、基體區以及擴增區之間的電場均勻化；氧化層區設置於頂摻雜區上並覆蓋頂摻雜區及部分汲極區；閘極區設置於氧化層區上並覆蓋部分深井區及氧化層區，以作為控制端；基體區設置於基板上，並鄰近閘極區以作為基體端；擴增區設置於基板上且位於基體區相對於閘極區的一側，並遠離閘極區以作為輸出端。其中，擴增區及汲極區係為第一導電類型，而基體區係為第二導電類型，擴增區、基體區與汲極區之間生成寄生電晶體。當靜電脈衝從輸入端輸入而流經閘極區時，由於擴增區遠離閘極區，而將寄生電晶體的電流路徑拉長，從而降低靜電脈衝對閘極區的傷害，並間接將靜電放電防護結構所能承受的電壓從1kV提升至2kV以上。 Based on the above objective, the present invention provides an electrostatic discharge protection structure, which includes a substrate, a deep well region, a drain region, a top doped region, an oxide layer region, a gate region, a base region, and an amplification region. The deep well region is arranged on the substrate; the drain region is arranged on the deep well region as an input terminal; the top doped region is arranged on the deep well region and is adjacent to the drain region, and the top doped region makes the drain region, the base region and the expansion The electric field between the increased areas is uniform; the oxide layer area is arranged on the top doped area and covers the top doped area and part of the drain area; the gate area is arranged on the oxide layer area and covers part of the deep well area and the oxide layer area, Used as a control terminal; the base area is arranged on the substrate and adjacent to the gate area as the base end; the amplification area is arranged on the substrate and is located on the side of the base area opposite to the gate area and far away from the gate area as the output end. Among them, the amplification region and the drain region are of the first conductivity type, and the base region is of the second conductivity type, and parasitic transistors are generated between the amplification region, the base region and the drain region. When the electrostatic pulse is input from the input terminal and flows through the gate area, since the amplification area is far away from the gate area, the current path of the parasitic transistor is elongated, thereby reducing the damage of the electrostatic pulse to the gate area and indirectly reducing the static electricity. The voltage that the discharge protection structure can withstand is increased from 1kV to more than 2kV.

較佳地，更包括導引區，導引區設置於基板上相對於深井區的一側，且擴增區及基體區係設置於導引區上，導引區和基體區為第二導電類型。 Preferably, it further includes a guide area, the guide area is arranged on the side of the substrate opposite to the deep well area, and the amplification area and the base area are arranged on the guide area, and the guide area and the base area are second conductive Types of.

較佳地，更包括宣洩區及導引區，導引區係設置於基板上相對於深井區的一側，宣洩區係設置於基板上而鄰近於導引區且遠離深井區，而基體區係設置於導引區上，擴增區係設置於宣洩區上。其中，基體區和導引區為第二導電類型，擴增區和宣洩區為第一導電類型，導引區的深度大於宣洩區的深度。 Preferably, it further includes a catharsis zone and a guide zone, the guide zone is arranged on the side of the substrate opposite to the deep well zone, the catharsis zone is arranged on the substrate and is adjacent to the guide zone and away from the deep well zone, and the base zone The line is set on the guide area, and the amplification zone is set on the catharsis area. Among them, the base area and the guide area are of the second conductivity type, the amplification area and the catharsis area are of the first conductivity type, and the depth of the guide area is greater than the depth of the catharsis area.

較佳地，擴增區及該基體區之間具有隔離件，隔離件防止擴增區及基體區導通。 Preferably, there is a spacer between the amplification region and the base region, and the spacer prevents the amplification region and the base region from conducting.

較佳地，汲極區包括井部及載子漂移部，載子漂移部位於井部上，井部則提供載子。 Preferably, the drain region includes a well portion and a carrier drift portion, the carrier drift portion is located on the well portion, and the well portion provides carriers.

基於上述目的，本發明提供一種靜電放電強健型半導體裝置，其包括受防護元件和靜電放電防護結構。靜電放電防護結構包括基板、深井區、汲極區、頂摻雜區、氧化層區、閘極區、基體區以及擴增區。深井區設置於基板上以阻隔基板的載子；汲極區設置於深井區上以作為輸入端，且輸入端連接受防護元件的接腳；頂摻雜區設置於深井區上且鄰近汲極區，且頂摻雜區係使汲極區、基體區以及擴增區之間的電場均勻化；氧化層區設置於深井區上並覆蓋頂摻雜區及部分汲極區；閘極區設置於氧化層區上並覆蓋部分深井區及氧化層區，以作為控制端；基體區設置於基板上，並鄰近閘極區以作為基體端；擴增區設置於基板上且位於基體區相對於閘極區的一側，並遠離閘極區以作為輸出端。其中，當靜電脈衝從受防護元件的接腳輸入且輸出端接地時，由於靜電放電防護結構為環狀配置且靜電脈衝大於靜電放電防護結構的閾值電壓，進而促使靜電放電防護結構導通，靜電脈衝則在輸出端宣洩以達到保護受防護元件免於因靜電脈衝而毀損之目的。 Based on the above objective, the present invention provides an electrostatic discharge robust semiconductor device, which includes a protected element and an electrostatic discharge protection structure. The electrostatic discharge protection structure includes a substrate, a deep well region, a drain region, a top doped region, an oxide layer region, a gate region, a base region, and an amplification region. The deep well region is arranged on the substrate to block the carriers of the substrate; the drain region is arranged on the deep well region as an input terminal, and the input terminal is connected to the pins of the protected component; the top doped region is arranged on the deep well region and is adjacent to the drain Region, and the top doped region homogenizes the electric field between the drain region, the base region and the amplification region; the oxide layer is arranged on the deep well region and covers the top doped region and part of the drain region; the gate region is set On the oxide layer area and covering part of the deep well area and the oxide layer area as the control end; the base area is arranged on the substrate and adjacent to the gate area as the base end; the amplification area is arranged on the substrate and is located opposite to the base area One side of the gate area and away from the gate area is used as an output terminal. Among them, when the electrostatic pulse is input from the pin of the protected component and the output terminal is grounded, the electrostatic discharge protection structure is configured in a ring shape and the electrostatic pulse is greater than the threshold voltage of the electrostatic discharge protection structure, thereby prompting the electrostatic discharge protection structure to conduct, and the electrostatic pulse It is discharged at the output end to achieve the purpose of protecting the protected components from damage due to electrostatic pulses.

較佳地，靜電放電防護結構更包括導引區，導引區設置於基板上相對於深井區的一側，且擴增區及基體區係設置於導引區上，導引區和基體區為第二導電類型，擴增區為第一導電類型。 Preferably, the electrostatic discharge protection structure further includes a guide area, the guide area is arranged on the side of the substrate opposite to the deep well area, and the amplification area and the base area are arranged on the guide area, the guide area and the base area It is the second conductivity type, and the amplified region is the first conductivity type.

較佳地，靜電放電防護結構更包括宣洩區及導引區，導引區係設置於基板上相對於深井區的一側，宣洩區係設置於基板上而鄰近於導引區且遠離深井區，而基體區係設置於導引區上，擴增區係設置於宣洩區上。其中，基體區和導引區為第二導電類型，擴增區和宣洩區為第一導電類型，導引區的深度大於宣洩區的深度。 Preferably, the electrostatic discharge protection structure further includes a catharsis zone and a guide zone. The guide zone is arranged on the side of the substrate opposite to the deep well zone. The catharsis zone is arranged on the substrate and is adjacent to the guide zone and away from the deep well zone. , And the matrix area is set on the guide area, and the amplification area is set on the catharsis area. Among them, the base area and the guide area are of the second conductivity type, the amplification area and the catharsis area are of the first conductivity type, and the depth of the guide area is greater than the depth of the catharsis area.

較佳地，擴增區和基體區之間具有隔離件，隔離件防止擴增區及基體區導通。 Preferably, there is a spacer between the amplification region and the base region, and the spacer prevents the amplification region and the base region from conducting.

較佳地，汲極區包括井部及載子漂移部，載子漂移部位於井部上，載子漂移部和井部提供載子。 Preferably, the drain region includes a well portion and a carrier drift portion, the carrier drift portion is located on the well portion, and the carrier drift portion and the well portion provide carriers.

承上所述，本發明之靜電放電防護結構及靜電放電強健型半導體裝置，透過擴增區的設置，將寄生電晶體的電流路徑拉長，降低靜電脈衝對閘極區的傷害，間接提高靜電放電防護結構所能承受的電壓。 In summary, the ESD protection structure and ESD robust semiconductor device of the present invention extend the current path of the parasitic transistor through the arrangement of the amplification zone, reduce the damage of the static pulse to the gate area, and indirectly increase the static electricity. The voltage that the discharge protection structure can withstand.

承上所述，本發明之靜電放電強健型半導體裝置及靜電放電強健型半導體裝置，透過靜電放電防護結構的環狀配置和擴增區，使靜電脈衝進入靜電放電防護結構而非受防護元件，以達到保護受防護元件免於受靜電脈衝毀損之目的。 Based on the above, the ESD robust semiconductor device and ESD robust semiconductor device of the present invention, through the annular configuration and amplification area of the ESD protection structure, make the electrostatic pulse enter the ESD protection structure instead of the protected component. In order to achieve the purpose of protecting the protected components from being damaged by electrostatic pulses.

1:靜電放電防護結構 1: Electrostatic discharge protection structure

2:受防護元件 2: Protected components

10、2_10:基板 10, 2_10: substrate

20、2_20:深井區 20, 2_20: deep well area

30、2_30:汲極區 30, 2_30: drain area

31:井部 31: Wellbe

32:載子漂移部 32: carrier drift part

40、2_40:頂摻雜區 40, 2_40: top doped area

50、2_50:氧化層區 50, 2_50: oxide layer area

60、TRAN_60:閘極區 60, TRAN_60: gate area

70、TRAN_70:基體區 70, TRAN_70: matrix area

80:擴增區 80: Amplification area

90:導引區 90: Guidance area

100:寄生電晶體 100: parasitic transistor

110、2_80:隔離件 110, 2_80: spacer

120:宣洩區 120: Catharsis

2_31:第一井部 2_31: The first well

2_32:第一載子漂移部 2_32: First carrier drift part

2_71:第二井部 2_71: The second well

2_72:第二載子飄移部 2_72: The second carrier drift part

2_D:汲極 2_D: Dip pole

2_S:源極 2_S: Source

B、2_B:基體端 B, 2_B: base end

B1:基極 B1: Base

CN:控制端 CN: Control terminal

C1:集極 C1: Collector

E1:射極 E1: emitter

IN:輸入端 IN: Input

OUT:輸出端 OUT: output terminal

第1圖為本發明之靜電放電強健型半導體裝置之俯視圖。 Figure 1 is a top view of the ESD robust semiconductor device of the present invention.

第2圖為本發明之靜電放電強健型半導體裝置中之靜電放電防護結構部分之第一實施例的剖面圖。 FIG. 2 is a cross-sectional view of the first embodiment of the electrostatic discharge protection structure in the electrostatic discharge robust semiconductor device of the present invention.

第3圖為本發明之靜電放電強健型半導體裝置中之受防護元件部分之剖面圖。 Figure 3 is a cross-sectional view of the protected component part of the ESD robust semiconductor device of the present invention.

第4圖為本發明之靜電放電防護結構部分之第二實施例的剖面圖。 Figure 4 is a cross-sectional view of the second embodiment of the electrostatic discharge protection structure of the present invention.

第5圖為本發明之靜電放電防護結構部分之第三實施例的剖面圖。 Figure 5 is a cross-sectional view of the third embodiment of the electrostatic discharge protection structure of the present invention.

第6圖為本發明之靜電放電防護結構部分之第四實施例的剖面圖。 Figure 6 is a cross-sectional view of the fourth embodiment of the electrostatic discharge protection structure of the present invention.

本發明之優點、特徵以及達到之技術方法將參照例示性實施例及所附圖式進行更詳細地描述而更容易理解，且本發明可以不同形式來實現，故不應被理解僅限於此處所陳述的實施例，相反地，對所屬技術領域具有通常知識者而言，所提供的實施例將使本揭露更加透徹與全面且完整地傳達本發明的範疇，且本發明將僅為所附加的申請專利範圍所定義。 The advantages, features, and technical methods of the present invention will be described in more detail with reference to exemplary embodiments and the accompanying drawings to make it easier to understand, and the present invention can be implemented in different forms, so it should not be understood to be limited to what is here. The stated embodiments, on the contrary, for those with ordinary knowledge in the technical field, the provided embodiments will make this disclosure more thorough, comprehensive and complete to convey the scope of the present invention, and the present invention will only be additional Defined by the scope of the patent application.

請參閱第1圖，其為本發明之靜電放電強健型半導體裝置之俯視圖。本發明之靜電放電強健型半導體裝置包括靜電放電防護結構1及受防護元件2。其中，經由受防護元件2接腳所饋入之靜電放電電流，可經由靜電放電防護結構1宣洩，詳細說明如下。 Please refer to FIG. 1, which is a top view of the ESD robust semiconductor device of the present invention. The ESD robust semiconductor device of the present invention includes an ESD protection structure 1 and a protected element 2. Among them, the electrostatic discharge current fed through the pins of the protected component 2 can be discharged through the electrostatic discharge protection structure 1, which is described in detail as follows.

請續參閱第2圖，其為本發明之靜電放電強健型半導體裝置中之靜電放電防護結構部分之第一實施例的剖面圖，其係從第1圖所示沿I-I’線段所 截取的剖面。靜電放電防護結構1包括基板(P-sub)10、深井區20(DNW)、汲極區30、頂摻雜區(PTOP)40、氧化層區50、閘極區(POLY1)60、基體區70(PPLUS)以及擴增區(NPLUS)80。深井區20設置於基板10上以阻隔基板10的載子。汲極區30設置於深井區20上以作為輸入端IN(M1)且輸入端IN(M1)連接受防護元件2之接腳，並包括井部31(NWELL)及載子漂移部(NPLUS)32，載子漂移部32位於井部31上，井部31則為第一導電類型井區並提供載子。頂摻雜區40設置於深井區20上且鄰近汲極區30，且頂摻雜區40係使汲極區30、基體區70以及擴增區80之間的電場均勻化。氧化層區50設置於深井區20上並覆蓋頂摻雜區40及部分汲極區30。閘極區60設置於氧化層區50上並覆蓋部分深井區20及氧化層區50，以作為控制端CN(M1)。基體區70設置於基板10上，並鄰近閘極區60以作為基體端B(M1)。擴增區80設置於基板10上且位於基體區70相對於閘極區60的一側，並遠離閘極區60以作為輸出端OUT(M1)。其中，擴增區80及汲極區30係為第一導電類型，而基體區70係為第二導電類型，擴增區80、基體區70與汲極區30之間生成寄生電晶體100。其中，當靜電脈衝從受防護元件2的接腳輸入且輸出端OUT接地時，由於靜電脈衝大於靜電放電防護結構1的閾值電壓，進而促使靜電放電防護結構1導通，靜電脈衝則在輸出端OUT宣洩以達到保護受防護元件2免於靜電脈衝之目的。 Please continue to refer to Figure 2, which is a cross-sectional view of the first embodiment of the electrostatic discharge protection structure in the ESD robust semiconductor device of the present invention, which is taken along the line I-I' shown in Figure 1. The intercepted section. The electrostatic discharge protection structure 1 includes a substrate (P-sub) 10, a deep well region 20 (DNW), a drain region 30, a top doped region (PTOP) 40, an oxide layer region 50, a gate region (POLY1) 60, and a base region 70 (PPLUS) and amplification area (NPLUS) 80. The deep well region 20 is disposed on the substrate 10 to block the carriers of the substrate 10. The drain region 30 is arranged on the deep well region 20 as an input terminal IN (M1) and the input terminal IN (M1) is connected to the pin of the protected component 2, and includes a well 31 (NWELL) and a carrier drifting part (NPLUS) 32. The carrier drift portion 32 is located on the well portion 31, and the well portion 31 is a well area of the first conductivity type and provides carriers. The top doped region 40 is disposed on the deep well region 20 and is adjacent to the drain region 30, and the top doped region 40 makes the electric field between the drain region 30, the base region 70 and the amplification region 80 uniform. The oxide layer region 50 is disposed on the deep well region 20 and covers the top doped region 40 and part of the drain region 30. The gate region 60 is disposed on the oxide layer region 50 and covers a part of the deep well region 20 and the oxide layer region 50 to serve as the control terminal CN (M1). The base region 70 is disposed on the substrate 10 and adjacent to the gate region 60 to serve as the base end B (M1). The amplification area 80 is disposed on the substrate 10 and is located at a side of the base area 70 opposite to the gate area 60 and far away from the gate area 60 to serve as the output terminal OUT (M1). Among them, the amplification region 80 and the drain region 30 are of the first conductivity type, and the base region 70 is of the second conductivity type, and a parasitic transistor 100 is generated between the amplification region 80, the base region 70 and the drain region 30. Among them, when the electrostatic pulse is input from the pin of the protected element 2 and the output terminal OUT is grounded, the electrostatic pulse is greater than the threshold voltage of the electrostatic discharge protection structure 1, and then the electrostatic discharge protection structure 1 is turned on, and the electrostatic pulse is at the output terminal OUT Drain to achieve the purpose of protecting the protected component 2 from electrostatic pulses.

此外，靜電放電防護結構1更包括導引區(PWELL)90，導引區90設置於基板10上相對於深井區20的一側並接觸閘極區60，且擴增區80及基體區70係設置於導引區90上，導引區90和基體區70為第二導電類型，且導引區90為井區以提供載子至基體區70。 In addition, the electrostatic discharge protection structure 1 further includes a guide area (PWELL) 90. The guide area 90 is disposed on the substrate 10 on the side opposite to the deep well area 20 and contacts the gate area 60, and the amplification area 80 and the base area 70 It is arranged on the guide area 90, the guide area 90 and the base area 70 are of the second conductivity type, and the guide area 90 is a well area to provide carriers to the base area 70.

請一併參閱第3圖，其為本發明之靜電放電強健型半導體裝置中之受防護元件部分之剖面圖。在此實施例中，受防護元件2可為接面場效電晶體(Junction Field Effect Transistor,JFET)，惟不以此為限。如第3圖所示，受防護元件2包括基板(P-sub)2_10、深井區(DNW)2_20、汲極區2_30、兩個頂摻雜區(PTOP)2_40、氧化層區2_50、源極區(NPLUS)2_60、基體區2_70。深井區2_20設置於基板2_10上以阻隔基板2_10的載子。汲極區2_30設置於深井區2_20上以作為汲極2_D(M1)，而汲極2_D係與靜電放電防護結構1之輸入端IN連接。汲極區2_30進一步包括第一井部(NWELL)2_31及第一載子漂移部(NPLUS)2_32，第一載子漂移部2_32位於第一井部2_31上，第一井部2_31則為第一導電類型井區並提供載子。兩個頂摻雜區2_40設置於深井區2_20上且鄰近汲極區2_30，且兩個頂摻雜區2_40使汲極區2_30和源極區2_60之間的電場均勻化。氧化層區2_50設置於深井區2_20上並覆蓋兩個頂摻雜區2_40及部分汲極區2_30，氧化層區2_50分別接觸兩個頂摻雜區2_40。源極區2_60設置於深井區2_20上以作為源極(M1)2_S。基體區2_70設置於基板2_10上並鄰近深井區2_20以作為基體端2_B(M1)，且包括第二井部(PWELL)2_71和第二載子漂移部(PPLUS)2_72，第二井部2_71則為第二導電類型井區並提供載子。其中，深井區2_20、汲極區2_30以及源極區2_60為第一導電類型，兩個頂摻雜區2_40和基體區2_70為第二導電類型，氧化層區2_50由二氧化矽組成，源極區2_60和第二載子漂移部2_72之間具有隔離件2_80以防止源極區2_60和基體區2_70導通。前述為接面場效電晶體的通常配置，當然也可根據實際需求而改變電晶體的種類，而並未侷限於本發明所列舉的範圍。如前所述，當靜電脈衝從受防護元件2的汲極2_D輸入且輸出端OUT接地時，由於靜電脈衝大於靜電放電防護結構1的閾值電壓， 進而促使靜電放電防護結構1導通，靜電脈衝則在輸出端OUT宣洩以達到保護受防護元件2免於靜電脈衝之目的。 Please also refer to FIG. 3, which is a cross-sectional view of the protected component part of the ESD robust semiconductor device of the present invention. In this embodiment, the protected element 2 can be a Junction Field Effect Transistor (JFET), but it is not limited to this. As shown in Figure 3, the protected component 2 includes a substrate (P-sub) 2_10, a deep well region (DNW) 2_20, a drain region 2_30, two top doped regions (PTOP) 2_40, an oxide layer region 2_50, and a source Area (NPLUS) 2_60, base area 2_70. The deep well region 2_20 is disposed on the substrate 2_10 to block the carriers of the substrate 2_10. The drain region 2_30 is disposed on the deep well region 2_20 as the drain 2_D (M1), and the drain 2_D is connected to the input terminal IN of the electrostatic discharge protection structure 1. The drain region 2_30 further includes a first well part (NWELL) 2_31 and a first carrier drift part (NPLUS) 2_32. The first carrier drift part 2_32 is located on the first well part 2_31, and the first well part 2_31 is the first well part 2_31. Conductivity type well area and provide carriers. Two top doped regions 2_40 are disposed on the deep well region 2_20 and adjacent to the drain region 2_30, and the two top doped regions 2_40 make the electric field between the drain region 2_30 and the source region 2_60 uniform. The oxide layer region 2_50 is disposed on the deep well region 2_20 and covers the two top doped regions 2_40 and part of the drain region 2_30. The oxide layer region 2_50 contacts the two top doped regions 2_40, respectively. The source region 2_60 is provided on the deep well region 2_20 as the source (M1) 2_S. The base area 2_70 is disposed on the substrate 2_10 and adjacent to the deep well area 2_20 as the base end 2_B (M1), and includes a second well (PWELL) 2_71 and a second carrier drifting portion (PPLUS) 2_72, and the second well 2_71 is Provide carriers for the second conductivity type well region. Among them, the deep well region 2_20, the drain region 2_30, and the source region 2_60 are of the first conductivity type, the two top doped regions 2_40 and the base region 2_70 are of the second conductivity type, and the oxide region 2_50 is composed of silicon dioxide. There is a spacer 2_80 between the region 2_60 and the second carrier drifting portion 2_72 to prevent the source region 2_60 and the base region 2_70 from conducting. The foregoing is the general configuration of the junction field effect transistor. Of course, the type of the transistor can also be changed according to actual needs, and is not limited to the scope of the present invention. As mentioned above, when the electrostatic pulse is input from the drain 2_D of the protected element 2 and the output terminal OUT is grounded, since the electrostatic pulse is greater than the threshold voltage of the electrostatic discharge protection structure 1, In turn, the electrostatic discharge protection structure 1 is promoted to conduct, and the electrostatic pulse is discharged at the output terminal OUT to achieve the purpose of protecting the protected component 2 from the electrostatic pulse.

需說明的是，受防護元件2的閘極和靜電放電防護結構1的閘極為共用，亦即，靜電放電防護結構1的閘極區60為和受防護元件2共用，控制端CN同時控制靜電放電防護結構1和受防護元件2的導通，因此，將受防護元件2的閘極省略標示。 It should be noted that the gate of the protected element 2 and the gate of the electrostatic discharge protection structure 1 are shared, that is, the gate area 60 of the electrostatic discharge protection structure 1 is shared with the protected element 2, and the control terminal CN controls static electricity at the same time. Since the discharge protection structure 1 and the protected element 2 are connected, the gate of the protected element 2 is omitted.

值得一提的是，靜電放電防護結構1可為環狀配置，而將大部分的靜電脈衝導入，以達到確實保護受防護元件2免於靜電脈衝之目的，更讓閘極區60在汲極區30、擴增區80及基體區70之間做有效地隔離，讓靜電脈衝順利地導向擴增區80輸出。另外，由於擴增區80遠離閘極區60，而將寄生電晶體100的電流路徑拉長，從而降低靜電脈衝對閘極區60的傷害，並可在相同的元件尺寸下，將靜電放電防護結構1所能承受的電壓從1kV提高至約2kV或以上 It is worth mentioning that the electrostatic discharge protection structure 1 can be configured in a ring shape, and most of the electrostatic pulses are introduced to achieve the purpose of actually protecting the protected component 2 from electrostatic pulses, and to allow the gate area 60 to be drained The area 30, the amplification area 80 and the base area 70 are effectively isolated, so that the electrostatic pulses can be smoothly directed to the amplification area 80 for output. In addition, since the amplified region 80 is far away from the gate region 60, the current path of the parasitic transistor 100 is elongated, thereby reducing the damage of the electrostatic pulse to the gate region 60, and can prevent electrostatic discharge under the same element size. Structure 1 can withstand voltage increased from 1kV to about 2kV or above

此外，對前述之靜電放電防護結構1的配置可設定如下：在此實施例中，第一導電類型為n型，第二導電類型為p型，當然也可根據實際需求而將第一導電類型改為p型和第二導電類型改為n型，並未限制於本發明所陳述的範圍；n型和p型的達成則為在半導體材料摻入雜質，而半導體材料為矽及雜質為第三族元素或第五族元素，摻入雜質則可透過離子佈值或分子束磊晶的方式達成。 In addition, the configuration of the aforementioned electrostatic discharge protection structure 1 can be set as follows: In this embodiment, the first conductivity type is n-type, and the second conductivity type is p-type. Of course, the first conductivity type can also be changed according to actual needs. Changing to p-type and second conductivity type to n-type is not limited to the scope stated in the present invention; n-type and p-type are achieved by doping impurities in the semiconductor material, and the semiconductor material is silicon and the impurities are the first Group III or Group V elements, doping with impurities can be achieved through ion placement or molecular beam epitaxy.

續言之，基板10為第二導電類型基板，並包括矽基板和矽基板上的第二導電類型磊晶層，第二導電類型磊晶層的厚度則根據實際配置的調整；載子則根據第一導電類型和第二導電類型的不同而為電子或電洞，於本此實施 例中，第一導電類型的載子為電子，第二導電類型的載子為電洞；井區的設置為先經過曝光顯影程序界定出井區所在的位置，接著摻入雜質於矽完成第一導電類型井區或第二導電類型井區的設置。後文中及其他實施例採用前述的配置設定，而不需再重複敘述配置設定。 In addition, the substrate 10 is a second conductivity type substrate and includes a silicon substrate and a second conductivity type epitaxial layer on the silicon substrate. The thickness of the second conductivity type epitaxial layer is adjusted according to the actual configuration; The difference between the first conductivity type and the second conductivity type is electrons or holes, which is implemented here In an example, the carriers of the first conductivity type are electrons, and the carriers of the second conductivity type are holes; the well region is set up to define the location of the well region through an exposure and development process, and then doping impurities in silicon to complete the first Setting of conductive type wells or second conductive type wells. In the following and other embodiments, the aforementioned configuration settings are used, without repeating the description of the configuration settings.

值得一提的是頂摻雜區40和氧化層區50的設置。頂摻雜區40為第二導電類型以提供電洞，進而平衡汲極區30的電子，以避免汲極區30的電場局部集中的現象，且透過最佳化頂摻雜區40和汲極區30的濃度和長度，達成汲極區30和頂摻雜區40的電荷平衡及降低靜電放電防護結構1的導通電阻。氧化層區50則設置於頂摻雜區40和閘極區60之間，可由二氧化矽組成，且氧化層區50接觸部分的閘極區60，由於氧化層區50和閘極區60的接觸，避免靜電脈衝直接擊穿閘極區60，同時改善汲極區30和導引區90之間的電流流動。 It is worth mentioning that the top doped region 40 and the oxide layer region 50 are arranged. The top doped region 40 is of the second conductivity type to provide holes to balance the electrons in the drain region 30 to avoid the phenomenon of local concentration of the electric field in the drain region 30, and by optimizing the top doped region 40 and the drain The concentration and length of the region 30 achieve the charge balance between the drain region 30 and the top doped region 40 and reduce the on-resistance of the electrostatic discharge protection structure 1. The oxide layer region 50 is arranged between the top doped region 40 and the gate region 60, and can be composed of silicon dioxide, and the oxide layer region 50 is in contact with the part of the gate region 60. Due to the difference between the oxide layer region 50 and the gate region 60 Contact to prevent the electrostatic pulse from directly breaking down the gate region 60, and at the same time improve the current flow between the drain region 30 and the guide region 90.

請參閱第4圖，其為本發明之靜電放電防護結構之第二實施例的配置圖。於本實施例中，相同元件符號之元件，其配置與前述類似，其類似處於此便不再加以贅述。如第4圖所示，第二實施例和第一實施例的不同之處為，第二實施例之靜電放電防護結構1在擴增區80和基體區70之間具有隔離件110，隔離件110由二氧化矽組成，以防止擴增區80及基體區70導通，使汲極區30、閘極區60、擴增區80和基體區70之間的電流流動更為順暢。 Please refer to FIG. 4, which is a configuration diagram of the second embodiment of the electrostatic discharge protection structure of the present invention. In this embodiment, the configuration of the components with the same component symbols is similar to the foregoing, and the similarities are not repeated here. As shown in Figure 4, the difference between the second embodiment and the first embodiment is that the electrostatic discharge protection structure 1 of the second embodiment has a spacer 110 between the amplification region 80 and the base region 70. 110 is composed of silicon dioxide to prevent the amplification area 80 and the base area 70 from conducting, so that the current flow between the drain area 30, the gate area 60, the amplification area 80 and the base area 70 is smoother.

請參閱第5圖，其為本發明之靜電放電防護結構之第三實施例的配置圖。於本實施例中，相同元件符號之元件，其配置與前述類似，其類似處於此便不再加以贅述。如第5圖所示，第三實施例之靜電放電防護結構1進一步包括宣洩區120，宣洩區120係設置於基板10上而鄰近於導引區90且遠離深井區20，而擴增區80係設置於宣洩區120上。其中，基體區70和導引區90為第 二導電類型，擴增區80和宣洩區120為第一導電類型，導引區90和宣洩區120皆為井區以提供電洞和電子至基體區70和擴增區80。 Please refer to FIG. 5, which is a configuration diagram of the third embodiment of the electrostatic discharge protection structure of the present invention. In this embodiment, the configuration of the components with the same component symbols is similar to the foregoing, and the similarities are not repeated here. As shown in FIG. 5, the electrostatic discharge protection structure 1 of the third embodiment further includes a catharsis area 120. The catharsis area 120 is disposed on the substrate 10 and is adjacent to the guide area 90 and far from the deep well area 20, and the amplification area 80 It is set on the catharsis area 120. Among them, the base area 70 and the guide area 90 are the Two conductivity types, the amplification zone 80 and the catharsis zone 120 are the first conductivity type, and the guide zone 90 and the catharsis zone 120 are both well zones to provide holes and electrons to the substrate zone 70 and the amplification zone 80.

宣洩區120設置的目的在於使靜電放電防護結構1所能承受的電壓上升，進一步說明如下：寄生電晶體100的增益值β關係式如下：

Figure 107123354-A0305-02-0013-1
其中，寄生電晶體100具備射極E1、基極B1及集極C1，NE為寄生電晶體100的射極E1的濃度，NB為寄生電晶體100的基極B1的濃度，透過調整射極E1的濃度大於基極B1的濃度，可以使增益值β的數值上升，進而使靜電放電防護結構1所能承受的電壓上升。宣洩區120鄰接設置於擴增區80周圍，而具有與擴增區80相同之導電類型，等同於調高射極E1的濃度NE，而達到提高靜電放電防護結構1所能承受電壓之目的。 The purpose of setting the catharsis area 120 is to increase the voltage that the electrostatic discharge protection structure 1 can withstand, which is further explained as follows: The relationship formula of the gain value β of the parasitic transistor 100 is as follows:
Figure 107123354-A0305-02-0013-1
 Wherein the parasitic transistor 100 includes an emitter E1, base B1 and collector C1, N E parasitic transistor exit 100 of the electrode E1 of the concentration, N B is a group of parasitic transistor 100 base B1 concentration, shot by adjusting The concentration of the electrode E1 is greater than the concentration of the base B1, which can increase the value of the gain value β, thereby increasing the voltage that the electrostatic discharge protection structure 1 can withstand. Vent area 120 disposed adjacent to the peripheral region 80 for amplification, and the same conductivity type having amplified region 80, the emitter E1 is equivalent to increase the concentration of N E, and to improve the electrostatic discharge protection structure can withstand a voltage purposes.

請參閱第6圖，其為本發明之靜電放電防護結構之第四實施例的配置圖。於本實施例中，相同元件符號之元件，其配置與前述類似，其類似處於此便不再加以贅述。如第6圖所示，第四實施例和第三實施例的不同之處為，第四實施例之導引區90為多個井區所構成，多個井區的設置為使導引區90的體積降低，從而使導引區90的濃度降低，降低寄生電晶體100的基極B1的濃度，使寄生電晶體100的增益值β上升，達到提高靜電放電防護結構1所能承受電壓之目的。 Please refer to FIG. 6, which is a configuration diagram of the fourth embodiment of the electrostatic discharge protection structure of the present invention. In this embodiment, the configuration of the components with the same component symbols is similar to the foregoing, and the similarities are not repeated here. As shown in Figure 6, the difference between the fourth embodiment and the third embodiment is that the guide area 90 of the fourth embodiment is composed of multiple wells, and the multiple wells are arranged so that the guide area The volume of 90 is reduced, so that the concentration of the guide region 90 is reduced, the concentration of the base B1 of the parasitic transistor 100 is reduced, and the gain value β of the parasitic transistor 100 is increased, so as to increase the voltage that the electrostatic discharge protection structure 1 can withstand. purpose.

綜上所述，本發明之靜電放電防護結構，透過擴增區80的設置，使寄生電晶體100的電流路徑拉長，且也未影響靜電放電防護結構1的長度，並 提高靜電放電防護結構1能承受的電壓至2kV。本發明之靜電放電強健型半導體裝置，透過靜電放電防護結構1的環狀配置和擴增區80，使靜電脈衝進入靜電放電防護結構1而非受防護元件2，達到保護受防護元件2之目的。總括而言，本發明之靜電放電防護結構和本發明之靜電放電強健型半導體裝置，具有如上述的優點，能承受2kV的電壓且降低對閘極區60的損害。 In summary, the ESD protection structure of the present invention, through the arrangement of the amplification zone 80, elongates the current path of the parasitic transistor 100 without affecting the length of the ESD protection structure 1. Increase the voltage that the electrostatic discharge protection structure 1 can withstand to 2kV. The ESD robust semiconductor device of the present invention, through the annular configuration of the ESD protection structure 1 and the amplification area 80, causes the electrostatic pulses to enter the ESD protection structure 1 instead of the protected element 2 to achieve the purpose of protecting the protected element 2 . In summary, the ESD protection structure of the present invention and the ESD robust semiconductor device of the present invention have the above-mentioned advantages, can withstand a voltage of 2kV and reduce damage to the gate region 60.

以上所述僅為舉例性，而非為限制性者。任何未脫離本發明之精神與範疇，而對其進行之等效修改或變更，均應包含於後附之申請專利範圍中。 The above description is only illustrative, and not restrictive. Any equivalent modifications or alterations that do not depart from the spirit and scope of the present invention should be included in the scope of the attached patent application.

1:靜電放電防護結構 1: Electrostatic discharge protection structure

10:基板 10: substrate

20:深井區 20: Deep Well District

30:汲極區 30: Drain region

31:井部 31: Wellbe

32:載子漂移部 32: carrier drift part

40:頂摻雜區 40: Top doped area

50:氧化層區 50: Oxide zone

60:閘極區 60: Gate area

70:基體區 70: matrix area

80:擴增區 80: Amplification area

90:導引區 90: Guidance area

100:寄生電晶體 100: parasitic transistor

B:基體端 B: base end

B1:基極 B1: Base

CN:控制端 CN: Control terminal

C1:集極 C1: Collector

E1:射極 E1: emitter

IN:輸入端 IN: Input

OUT:輸出端 OUT: output terminal

Claims (10)

一種靜電放電防護結構，其包括：一基板；一深井區，設置於該基板上；一汲極區，設置於該深井區上，以作為一輸入端；一頂摻雜區，設置於該深井區上，且鄰近於該汲極區；一氧化層區，設置於該頂摻雜區上，並覆蓋該頂摻雜區及一部分之該汲極區；一閘極區，設置於該氧化層區上，並覆蓋一部分之該深井區及該氧化層區，以作為一控制端；一基體區，設置於該基板上，並鄰近該閘極區，以作為一基體端；以及一擴增區，設置於該基板上，而位於該基體區相對於該閘極區的一側，並遠離該閘極區，以作為一輸出端；其中，該擴增區及該汲極區係為一第一導電類型，而該基體區係為一第二導電類型，該擴增區、該基體區與該汲極區之間生成一寄生電晶體，藉由該擴增區遠離該閘極區以將該寄生電晶體的電流路徑拉長。 An electrostatic discharge protection structure, comprising: a substrate; a deep well region arranged on the substrate; a drain region arranged on the deep well region as an input terminal; a top doped region arranged on the deep well On the region and adjacent to the drain region; an oxide layer region is provided on the top doped region and covers the top doped region and a part of the drain region; a gate region is provided on the oxide layer Area, and cover a part of the deep well area and the oxide layer area as a control end; a base area, arranged on the substrate and adjacent to the gate area, as a base end; and an amplification area , Disposed on the substrate, and located on the side of the base region opposite to the gate region and away from the gate region, as an output terminal; wherein, the amplification region and the drain region are a first One conductivity type, and the base region is a second conductivity type. A parasitic transistor is generated between the amplification region, the base region, and the drain region, and the amplification region is far away from the gate region to prevent The current path of the parasitic transistor is elongated. 如申請專利範圍第1項所述之靜電放電防護結構，其中，更包括一導引區，該導引區設置於該基板上相對於該深井區的一側，且該擴增區及該基體區係設置於該導引區上。 The electrostatic discharge protection structure described in item 1 of the scope of the patent application further includes a guiding area. The guiding area is disposed on the substrate on the side opposite to the deep well area, and the amplification area and the substrate The flora is set on the guide area. 如申請專利範圍第1項所述之靜電放電防護結構，其中，更包括一宣洩區及一導引區，該導引區係設置於該基板上相對於該 深井區的一側，該宣洩區係設置於該基板上而鄰近於該導引區且遠離該深井區，而該基體區係設置於該導引區上，該擴增區係設置於該宣洩區上。 For example, the electrostatic discharge protection structure described in item 1 of the scope of patent application further includes a catharsis area and a guide area, and the guide area is arranged on the substrate relative to the On one side of the deep well area, the catharsis area is arranged on the substrate, adjacent to the guide area and far away from the deep well area, the matrix area is arranged on the guide area, and the amplification area is arranged on the catharsis District. 如申請專利範圍第1項所述之靜電放電防護結構，其中，該擴增區和該基體區之間具有一隔離件，該隔離件防止該擴增區及該基體區導通。 According to the electrostatic discharge protection structure described in item 1 of the scope of patent application, there is a spacer between the amplification zone and the base zone, and the spacer prevents the amplification zone and the base zone from conducting. 如申請專利範圍第1項所述之靜電放電防護結構，其中，該汲極區包括一井部及一載子漂移部，該載子漂移部位於該井部上。 According to the electrostatic discharge protection structure described in item 1 of the patent application, the drain region includes a well and a carrier drifting portion, and the carrier drifting portion is located on the well. 一種靜電放電強健型半導體裝置，其包括：一受防護元件；以及一靜電放電防護結構，其包括：一基板；一深井區，設置於該基板上；一汲極區，設置於該深井區上，以作為一輸入端，且該輸入端連接該受防護元件的一接腳；一頂摻雜區，設置於該深井區上，且鄰近於該汲極區；一氧化層區，設置於該頂摻雜區上，並覆蓋該頂摻雜區及一部分之該汲極區；一閘極區，設置於該氧化層區上，並覆蓋一部分之該深井區及該氧化層區，以作為一控制端；一基體區，設置於該基板上，並鄰近該閘極區，以作為一基體端；以及 一擴增區，設置於該基板上，而位於該基體區相對於該閘極區的一側，並遠離該閘極區，以作為一輸出端；其中，該擴增區及該汲極區係為一第一導電類型，而該基體區係為一第二導電類型，該擴增區、該基體區與該汲極區之間生成一寄生電晶體，藉由該擴增區遠離該閘極區以將該寄生電晶體的電流路徑拉長，其中，當一靜電脈衝從該受防護元件的該接腳輸入且該輸出端接地時，而該靜電脈衝大於該靜電放電防護結構的一閾值電壓，促使該靜電放電防護結構導通，該靜電脈衝從而在該輸出端宣洩。 An electrostatic discharge robust semiconductor device, which includes: a protected element; and an electrostatic discharge protection structure, which includes: a substrate; a deep well area arranged on the substrate; a drain area arranged on the deep well area , As an input terminal, and the input terminal is connected to a pin of the protected element; a top doped region is disposed on the deep well region and adjacent to the drain region; an oxide region is disposed on the On the top doped region and cover the top doped region and a part of the drain region; a gate region is arranged on the oxide region and covers a part of the deep well region and the oxide region as a Control end; a base area, which is disposed on the substrate and adjacent to the gate area, as a base end; and An amplification region is disposed on the substrate, and is located on the side of the base region opposite to the gate region and away from the gate region to serve as an output terminal; wherein, the amplification region and the drain region Is a first conductivity type, and the base region is a second conductivity type. A parasitic transistor is generated between the amplification region, the base region, and the drain region, and the amplification region is far away from the gate The polar region is used to elongate the current path of the parasitic transistor, wherein when an electrostatic pulse is input from the pin of the protected element and the output terminal is grounded, the electrostatic pulse is greater than a threshold of the electrostatic discharge protection structure The voltage causes the electrostatic discharge protection structure to conduct, and the electrostatic pulse is discharged at the output terminal. 如申請專利範圍第6項所述之靜電放電強健型半導體裝置，其中，該靜電放電防護結構更包括一導引區，該導引區設置於該基板上相對於該深井區的一側，且該擴增區及該基體區係設置於該導引區上。 According to the ESD robust semiconductor device described in item 6 of the scope of patent application, the ESD protection structure further includes a guide area, and the guide area is disposed on the substrate on the side opposite to the deep well area, and The amplification zone and the matrix zone are arranged on the guide zone. 如申請專利範圍第6項所述之靜電放電強健型半導體裝置，其中，該靜電放電防護結構更包括一宣洩區及一導引區，該導引區係設置於該基板上相對於該深井區的一側，該宣洩區係設置於該基板上而鄰近於該導引區且遠離該深井區，而該基體區係設置於該導引區上，該擴增區係設置於該宣洩區上。 According to the ESD robust semiconductor device described in the scope of patent application, wherein the ESD protection structure further includes a catharsis area and a guide area, and the guide area is disposed on the substrate relative to the deep well area On one side of the vent area, the catharsis area is arranged on the substrate, adjacent to the guide area and far from the deep well area, the matrix area is arranged on the guide area, and the amplification area is arranged on the catharsis area . 如申請專利範圍第6項所述之靜電放電強健型半導體裝置，其中，該擴增區和該基體區之間具有一隔離件，該隔離件防止該擴增區及該基體區導通。 According to the ESD robust semiconductor device described in claim 6, wherein a spacer is provided between the amplification region and the base region, and the spacer prevents the amplification region and the base region from conducting. 如申請專利範圍第6項所述之靜電放電強健型半導體裝置，其中，該汲極區包括一井部及一載子漂移部，該載子漂移部位於 該井部上。 According to the ESD robust semiconductor device described in claim 6, wherein the drain region includes a well portion and a carrier drifting portion, and the carrier drifting portion is located On the well.
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