TWI704771B - Transient enhancing circuit and constant-on-time converter using the same - Google Patents

Transient enhancing circuit and constant-on-time converter using the same Download PDF

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TWI704771B
TWI704771B TW108130011A TW108130011A TWI704771B TW I704771 B TWI704771 B TW I704771B TW 108130011 A TW108130011 A TW 108130011A TW 108130011 A TW108130011 A TW 108130011A TW I704771 B TWI704771 B TW I704771B
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circuit
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hold circuit
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TW202110088A (en
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張耀仁
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晶豪科技股份有限公司
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Abstract

The present invention provides a transient enhancing circuit for a constant-on-time converter. The constant-on-time converter includes an error amplifier and a comparator. The transient enhancing circuit includes a first sample-and-hold circuit and a zero-current detection circuit. The first sample-and-hold circuit has an input terminal and an output terminal. The input terminal of the first sample-and-hold circuit is coupled to an output terminal of the error amplifier, and the output terminal of the first sample-and-hold circuit is coupled to a second input terminal of the comparator. The zero-current detection circuit is coupled to the first sample-and-hold circuit and arranged for outputting a control signal when current flowing through a load of the constant-on-time converter is detected to be zero. The present invention provides a constant-on-time converter using the said transient enhancing circuit.

Description

暫態增強電路與使用該暫態增強電路的恆定導通時間轉換器Transient enhancement circuit and constant on-time converter using the transient enhancement circuit

本發明涉及一種用於恆定導通時間轉換器的電子電路，更具體地，涉及一種能夠增強恆定導通時間轉換器的負載暫態的電子電路。The present invention relates to an electronic circuit for a constant on-time converter, and more particularly, to an electronic circuit capable of enhancing the load transient of the constant on-time converter.

該降壓轉換器（buck converter）是直流轉直流的功率轉換器，其將電壓從其輸入（電源）降壓到其輸出（負載）。無論其控制模式如何，如圖1所示，該降壓轉換器由三個元件組成：一個脈衝調變器，它將輸入電壓的脈衝序列產生為高位準，而接地電壓產生為低位準訊號；一LC濾波器，用於平均脈衝調變器輸出的脈衝序列；和一迴路補償電路，通常透過一誤差放大器比較其輸出電壓和一內部參考電壓來產生控制訊號VC。該脈衝調變器將輸入電壓V IN作為脈衝序列前饋。該LC濾波器將該脈衝序列從該調制器轉換為適當的輸出電壓。 The buck converter is a DC to DC power converter that steps down the voltage from its input (power supply) to its output (load). Regardless of its control mode, as shown in Figure 1, the buck converter is composed of three components: a pulse modulator, which generates a pulse train of input voltage as a high-level signal, and ground voltage as a low-level signal; An LC filter is used to average the pulse sequence output by the pulse modulator; and a loop compensation circuit, which usually compares its output voltage with an internal reference voltage through an error amplifier to generate the control signal VC. The pulse modulator feeds forward the input voltage V IN as a pulse sequence. The LC filter converts the pulse train from the modulator to an appropriate output voltage.

在圖1中，該LC濾波器平均V SW的高/低密度，從而產生大致經過調節的該輸出電壓V OUT。在電壓模式（VM）或電流模式（CM）中使用脈衝寬度調製（PWM）控制時，此密度稱為PWM的工作週期。輸入電壓V IN和該輸出電壓V OUT之間的關係可以粗略地用下式來描述：DxV IN=V OUT（1），其中D是PWM的工作週期。 In FIG. 1, the LC filter averages the high/low density of V SW , thereby generating the output voltage V OUT that is roughly adjusted. When pulse width modulation (PWM) control is used in voltage mode (VM) or current mode (CM), this density is called the duty cycle of PWM. The relationship between the input voltage V IN and the output voltage V OUT can be roughly described by the following formula: DxV IN =V OUT (1), where D is the duty cycle of the PWM.

另外，為了使該降壓轉換器運作，必須將開關頻率F SW保持在遠高於其LC濾波器的截止頻率點F LC的位置。否則，脈衝序列不會很好地平均，這會導致該輸出電壓V OUT的波形產生的巨大的紋波。 In addition, in order for the buck converter to operate, the switching frequency F SW must be maintained at a position much higher than the cut-off frequency point F LC of the LC filter. Otherwise, the pulse sequence will not be well averaged, which will cause huge ripples in the waveform of the output voltage V OUT .

在圖1的系統中，當負載電流I OUT值改變時（在圖3的負載塊中），會產生該輸出電壓V OUT的擾動，這通常稱為負載暫態。如圖2所示，當I OUT增加時，V OUT將暫時下降然後再回升。另一方面，當I OUT減小時，V OUT將暫時上升然後再下降。 In the system of Fig. 1, when the value of the load current I OUT changes (in the load block of Fig. 3), a disturbance of the output voltage V OUT will be generated, which is usually called a load transient. As shown in Figure 2, when I OUT increases, V OUT will temporarily decrease and then rise again. On the other hand, when I OUT decreases, V OUT will temporarily rise and then fall again.

如上所述，當恆定導通時間轉換器連接到輕負載時，負載電流很小，這不能有效地釋放存儲在LC濾波器中的能量。因此，該輸出電壓V OUT將略微升高。稍微升高的V OUT將會反饋到恆定導通時間轉換器的迴路補償電路的誤差放大器。如果反饋電壓高於參考電壓，則誤差放大器的輸出電壓將下降，使得該輸出電壓V OUT下降回其原始位準。由於該輸出電壓V OUT恢復所需的“額外”時間，當恆定導通時間轉換器的負載從非常低到高時，這種擾動特別影響負載暫態。 As described above, when the constant on-time converter is connected to a light load, the load current is small, which cannot effectively release the energy stored in the LC filter. Therefore, the output voltage V OUT will rise slightly. The slightly increased V OUT will be fed back to the error amplifier of the loop compensation circuit of the constant on-time converter. If the feedback voltage is higher than the reference voltage, the output voltage of the error amplifier will drop, causing the output voltage V OUT to drop back to its original level. Due to the “extra” time required for the output voltage V OUT to recover, this disturbance particularly affects the load transient when the load of the constant on-time converter goes from very low to high.

因此，本發明的目的是提供一種暫態增強電路和恆定導通時間轉換器，其使得當恆定導通時間轉換器的負載從非常低增加至高的情況下增加時可以增強負載的暫態。Therefore, the object of the present invention is to provide a transient enhancement circuit and a constant on-time converter, which can enhance the transient state of the load when the load of the constant on-time converter increases from very low to high.

為了實現上述目的，根據本發明的一個方面，提出了一種用於一恆定導通時間轉換器的暫態增強電路，該恆定導通時間轉換器包括一誤差放大器和一比較器，該暫態增強電路包括：一第一採樣並保持電路，具有一輸入端和一輸出端，其中該第一採樣並保持電路的輸入端耦接該誤差放大器的輸出端，該第一採樣並保持電路的輸出端耦接到該比較器的一第一輸入端；以及一零電流檢測電路，耦接到該第一個採樣並保持電路，其中該零電流檢測電路用來於檢測到流過耦接至該恆定導通時間轉換器的負載電流為零時，輸出一控制訊號。In order to achieve the above objective, according to one aspect of the present invention, a transient enhancement circuit for a constant on-time converter is proposed. The constant on-time converter includes an error amplifier and a comparator, and the transient enhancement circuit includes : A first sample and hold circuit with an input terminal and an output terminal, wherein the input terminal of the first sample and hold circuit is coupled to the output terminal of the error amplifier, and the output terminal of the first sample and hold circuit is coupled to To a first input terminal of the comparator; and a zero current detection circuit, coupled to the first sample and hold circuit, wherein the zero current detection circuit is used to detect that the current is coupled to the constant on-time When the load current of the converter is zero, a control signal is output.

在根據上述實施例的該暫態增強電路中，該暫態增強電路還包括一第二採樣並保持電路，具有一輸入端和一輸出端，其中該第二採樣並保持電路的輸入端耦接該第一採樣並保持電路的輸出端，該第二採樣並保持電路的輸出端連接到該比較器的第一輸入端；以及一箝位電路，具有一第一端和一第二端，其中該箝位電路的第一端耦接該第二採樣並保持電路的輸出端，該箝位電路的第二端耦接地，其中該零電流檢測電路耦接到該第二採樣並保持電路。In the transient enhancement circuit according to the foregoing embodiment, the transient enhancement circuit further includes a second sample and hold circuit having an input terminal and an output terminal, wherein the input terminal of the second sample and hold circuit is coupled to The output terminal of the first sample and hold circuit, the output terminal of the second sample and hold circuit is connected to the first input terminal of the comparator; and a clamp circuit having a first terminal and a second terminal, wherein The first end of the clamp circuit is coupled to the output end of the second sample and hold circuit, the second end of the clamp circuit is coupled to ground, and the zero current detection circuit is coupled to the second sample and hold circuit.

在根據上述任一實施例的該暫態增強電路中，該第一採樣並保持電路包括一第一開關，連接在該第一採樣並保持電路的輸入端和輸出端之間；以及一第一電容器，耦接在該第一採樣並保持電路的輸出端和地之間，其中在每個工作循環期間，該第一開關因響應該控制訊號而被打開。In the transient enhancement circuit according to any one of the above embodiments, the first sample and hold circuit includes a first switch connected between the input terminal and the output terminal of the first sample and hold circuit; and a first The capacitor is coupled between the output terminal of the first sample and hold circuit and the ground, wherein during each working cycle, the first switch is opened in response to the control signal.

在根據上述任一實施例的該暫態增強電路中，該第一採樣並保持電路被設置為因響應該控制訊號而保持從該誤差放大器輸出的誤差電壓的採樣電壓位準。In the transient enhancement circuit according to any one of the above embodiments, the first sampling and holding circuit is configured to maintain the sampling voltage level of the error voltage output from the error amplifier in response to the control signal.

在根據上述任一實施例的該暫態增強電路中，該第二採樣並保持電路包括一第二開關，耦接在該第二採樣並保持電路的輸入端和輸出端之間；以及一第二電容器，耦接在該第二採樣並保持電路的輸入端和地之間，其中在每個工作循環期間，該第二開關因嚮應該控制訊號而被打開。In the transient enhancement circuit according to any one of the above embodiments, the second sample and hold circuit includes a second switch coupled between the input terminal and the output terminal of the second sample and hold circuit; and a first Two capacitors are coupled between the input terminal of the second sample and hold circuit and the ground, wherein during each working cycle, the second switch is turned on due to the control signal.

在根據上述任一實施例的該暫態增強電路中，該第二採樣並保持電路被設置為保持從該誤差放大器輸出的一誤差電壓的一採樣電壓位準，然後該箝位電路因響應於該控制訊號而箝位所述採樣電壓位準。In the transient enhancement circuit according to any one of the foregoing embodiments, the second sample and hold circuit is configured to maintain a sample voltage level of an error voltage output from the error amplifier, and then the clamp circuit responds to The control signal clamps the sampling voltage level.

在根據上述任一實施例的該暫態增強電路中，該暫態增強電路還包括具有一第一輸入端、一第二輸入端及一輸出端的一微分器，其中該微分器的第二輸入端耦接到該第二採樣並保持電路的輸出端，該微分器的輸出端耦接到該比較器的第一輸入端。In the transient enhancement circuit according to any one of the above embodiments, the transient enhancement circuit further includes a differentiator having a first input terminal, a second input terminal, and an output terminal, wherein the second input of the differentiator The terminal is coupled to the output terminal of the second sample and hold circuit, and the output terminal of the differentiator is coupled to the first input terminal of the comparator.

在根據上述任一實施例的該暫態增強電路中，箝位電路包括多個二極管串聯耦接在該箝位電路的第一端和該箝位電路的第二端之間。In the transient enhancement circuit according to any of the foregoing embodiments, the clamping circuit includes a plurality of diodes coupled in series between the first end of the clamping circuit and the second end of the clamping circuit.

在根據上述任一實施例的該暫態增強電路中，該暫態增強電路還包括一補償電路，耦接在該第一採樣並保持電路的輸出端與地之間。In the transient enhancement circuit according to any one of the above embodiments, the transient enhancement circuit further includes a compensation circuit coupled between the output terminal of the first sample and hold circuit and ground.

在根據上述任一實施例的該暫態增強電路中，補償電路包括一電阻器；以及一個電容器，其中該電阻器和該電容器串聯耦接在該第一採樣並保持電路的輸出端和地之間。In the transient enhancement circuit according to any one of the foregoing embodiments, the compensation circuit includes a resistor; and a capacitor, wherein the resistor and the capacitor are coupled in series between the output terminal of the first sample and hold circuit and the ground. between.

為了實現上述目的，根據本發明的另一方面，提出了一種恆定導通時間(COT)轉換器，包括：一誤差放大器，具有該第一輸入端，該第二輸入端和輸出端，其中該第二輸入端耦接參考電壓；一比較器，具有一第一輸入端，一第二輸入端及一輸出端；一降壓轉換器，具有一輸入端和一輸出端，其中該降壓轉換器的輸出端耦接該誤差放大器的第一輸入端、該比較器的第二輸入端以及一負載；一個恆定導通時間控制器，耦接該降壓轉換器的輸入端和該比較器的輸出端之間；一暫態增強電路，包括：一第一採樣並保持電路，具有一輸入端和一輸出端，其中該第一採樣並保持電路的輸入端耦接該誤差放大器的輸出端且該第一採樣並保持電路的輸出端耦接到該比較器的第一輸入端；以及一零電流檢測電路，耦接到該第一採樣並保持電路，其中該零電流檢測電路用來於檢測到流過耦接至該恆定導通時間轉換器的負載電流為零時，輸出一控制訊號。In order to achieve the above objective, according to another aspect of the present invention, a constant on-time (COT) converter is proposed, including: an error amplifier having the first input terminal, the second input terminal and the output terminal, wherein the first Two input terminals are coupled to the reference voltage; a comparator with a first input terminal, a second input terminal and an output terminal; a buck converter with an input terminal and an output terminal, wherein the buck converter The output terminal is coupled to the first input terminal of the error amplifier, the second input terminal of the comparator, and a load; a constant on-time controller is coupled to the input terminal of the buck converter and the output terminal of the comparator Between; a transient enhancement circuit, including: a first sample and hold circuit, having an input and an output, wherein the input of the first sample and hold circuit is coupled to the output of the error amplifier and the first The output terminal of a sample and hold circuit is coupled to the first input terminal of the comparator; and a zero current detection circuit is coupled to the first sample and hold circuit, wherein the zero current detection circuit is used to detect the current When the load current over-coupled to the constant on-time converter is zero, a control signal is output.

在根據上述實施例的該COT轉換器中，該COT轉換器還包括：一第二採樣並保持電路，具有一輸入端和一輸出端，其中該第二採樣並保持電路的輸入端耦接該第一採樣並保持電路的輸出端，該第二採樣並保持電路的輸出端耦接到該比較器的該第一輸入端；以及一箝位電路，耦接在該第二採樣並保持電路的輸出端和地之間，其中該零電流檢測電路耦接到該第二採樣並保持電路。In the COT converter according to the aforementioned embodiment, the COT converter further includes: a second sample and hold circuit having an input terminal and an output terminal, wherein the input terminal of the second sample and hold circuit is coupled to the The output terminal of the first sample and hold circuit, the output terminal of the second sample and hold circuit is coupled to the first input terminal of the comparator; and a clamp circuit, which is coupled to the second sample and hold circuit Between the output terminal and the ground, the zero current detection circuit is coupled to the second sample and hold circuit.

在根據上述任一實施例的該COT轉換器中，該第一採樣並保持電路包括一第一開關，連接在該第一採樣並保持電路的輸入端和輸出端之間；以及一第一電容器，耦接在該第一採樣並保持電路的輸出端和地之間，其中在每個工作循環期間，該第一開關因響應該控制訊號而被打開。In the COT converter according to any one of the above embodiments, the first sample and hold circuit includes a first switch connected between the input terminal and the output terminal of the first sample and hold circuit; and a first capacitor , Is coupled between the output terminal of the first sample and hold circuit and the ground, wherein during each working cycle, the first switch is opened in response to the control signal.

在根據上述任一實施例的方法中，該第一採樣並保持電路被設置為因響應該控制訊號而保持從該誤差放大器輸出的誤差電壓的採樣電壓位準。In the method according to any of the foregoing embodiments, the first sample and hold circuit is configured to maintain the sampling voltage level of the error voltage output from the error amplifier in response to the control signal.

在根據上述任一實施例的該COT轉換器中，該第二採樣並保持電路包括一第二開關，耦接在該第二採樣並保持電路的輸入端和輸出端之間；以及一第二電容器，耦接在該第二採樣並保持電路的輸入端和地之間，其中在每個工作循環期間，該第二開關因嚮應該控制訊號而被打開。In the COT converter according to any of the above embodiments, the second sample and hold circuit includes a second switch coupled between the input terminal and the output terminal of the second sample and hold circuit; and a second The capacitor is coupled between the input terminal of the second sample-and-hold circuit and the ground, wherein during each working cycle, the second switch is turned on due to the control signal.

在根據上述任一實施例的該COT轉換器中，該第二採樣並保持電路被設置為保持從該誤差放大器輸出的一誤差電壓的一採樣電壓位準，然後該箝位電路因響應於該控制訊號而箝位所述採樣電壓位準。In the COT converter according to any one of the above embodiments, the second sample-and-hold circuit is configured to maintain a sampled voltage level of an error voltage output from the error amplifier, and then the clamp circuit responds to the The control signal clamps the sampling voltage level.

在根據上述任一實施例的該COT轉換器中，箝位電路包括多個二極管串聯耦接在該箝位電路的第一端和該箝位電路的第二端之間。In the COT converter according to any one of the above embodiments, the clamping circuit includes a plurality of diodes coupled in series between the first end of the clamping circuit and the second end of the clamping circuit.

在根據上述任一實施例的該COT轉換器中，該COT轉換器還包括一補償電路，耦接在該第一採樣並保持電路的輸出端與地之間。In the COT converter according to any one of the above embodiments, the COT converter further includes a compensation circuit coupled between the output terminal of the first sample and hold circuit and ground.

在根據上述任一實施例的該COT轉換器中，補償電路包括一電阻器；以及一個電容器，其中該電阻器和該電容器串聯耦接在該第一採樣並保持電路的輸出端和地之間。In the COT converter according to any one of the foregoing embodiments, the compensation circuit includes a resistor; and a capacitor, wherein the resistor and the capacitor are coupled in series between the output terminal of the first sample and hold circuit and ground .

在根據上述任一實施例的該COT轉換器中，該COT轉換器還包括具有一第一輸入端、一第二輸入端及一輸出端的一微分器，其中該微分器的第二輸入端耦接到該第二採樣並保持電路的輸出端，該微分器的輸出端耦接到該比較器的第一輸入端。In the COT converter according to any one of the above embodiments, the COT converter further includes a differentiator having a first input terminal, a second input terminal and an output terminal, wherein the second input terminal of the differentiator is coupled Connected to the output terminal of the second sample and hold circuit, and the output terminal of the differentiator is coupled to the first input terminal of the comparator.

利用這種設置，該暫態增強電路和使用該暫態增強電路的COT轉換器可以在工作週期期間當負載低時採樣並保持由該誤差放大器輸出的電壓位準，亦即，當負載增加時防止該COT轉換器的輸出電壓下降，以避免增加負載暫態。With this arrangement, the transient enhancement circuit and the COT converter using the transient enhancement circuit can sample and maintain the voltage level output by the error amplifier when the load is low during the duty cycle, that is, when the load increases Prevent the output voltage of the COT converter from dropping to avoid increasing the load transient.

在以下針對本發明具體實施例的描述和相關圖式中公開了本發明的各方面。在不脫離本發明的精神或範圍的情況下，可以設計出替換實施例。另外，將不詳細描述本發明的示例性實施例的公知元件，或者將省略這些元件，以免模糊本發明的相關細節。此外，為了便於理解描述，下面討論了幾個術語。Various aspects of the present invention are disclosed in the following description of specific embodiments of the present invention and related drawings. Alternative embodiments may be devised without departing from the spirit or scope of the present invention. In addition, well-known elements of the exemplary embodiments of the present invention will not be described in detail, or these elements will be omitted so as not to obscure the relevant details of the present invention. In addition, to facilitate understanding of the description, several terms are discussed below.

如本文所使用的，詞語“示例性”意味著“用作示例，實例或說明”。本文描述的實施例不是限制性的，而僅是示例性的。應該理解的是，所描述的實施例不必被解釋為比其他實施例更較佳或更具優勢。此外，術語“本發明的實施例”、“實施例”或“發明”不要求本發明的所有實施例都包括所討論的特徵、優點或操作模式。As used herein, the word "exemplary" means "serving as an example, instance, or illustration." The embodiments described herein are not limitative, but only exemplary. It should be understood that the described embodiments need not be construed as better or more advantageous than other embodiments. In addition, the terms "embodiments of the invention", "embodiments" or "invention" do not require that all embodiments of the invention include the discussed feature, advantage or mode of operation.

此外，本文描述的許多實施例是根據要由例如計算機設備的元件來執行的動作序列描述的。本領域技術人員應可理解這裡描述的各種動作序列可以由特定電路（例如專用集成電路（ASIC））和/或由至少一個處理器執行的程序指令來執行。另外，本文描述的動作序列可以完全在任何形式的非暫時性計算機可讀存儲媒體內實現，使得動作序列的執行使能至少一個處理器來執行本文描述的功能。此外，這裡描述的動作序列可以以硬件和軟件的組合來體現。因此，本發明的各個方面可以以多種不同的形式體現，所有這些形式都被認為是在所要求保護的主題的範圍內。另外，對於本文描述的每個實施例，任何這樣的實施例的對應形式可以在本文中被描述為例如“被配置為”執行所描述的動作的計算機。Furthermore, many of the embodiments described herein are described in terms of sequences of actions to be performed by elements such as computer equipment. Those skilled in the art should understand that the various action sequences described herein may be executed by a specific circuit (for example, an application specific integrated circuit (ASIC)) and/or program instructions executed by at least one processor. In addition, the sequence of actions described herein may be completely implemented in any form of non-transitory computer-readable storage medium, so that the execution of the sequence of actions enables at least one processor to perform the functions described herein. In addition, the sequence of actions described here can be embodied in a combination of hardware and software. Therefore, various aspects of the present invention may be embodied in a variety of different forms, all of which are considered to be within the scope of the claimed subject matter. In addition, for each embodiment described herein, the corresponding form of any such embodiment may be described herein as, for example, a computer "configured to" perform the described actions.

現在將通過本發明的一些較佳實施例並參考圖式來描述本發明。The present invention will now be described through some preferred embodiments of the present invention with reference to the drawings.

圖3示出了根據本發明實施例的恆定導通時間（COT）轉換器1的方塊圖。該COT轉換器1包括一暫態增強電路10，一降壓轉換器20，一COT控制器30，一誤差放大器40和一比較器50。該比較器50具有一第一輸入端、一第二輸入端以及一輸出端。該COT控制器30耦接到該降壓轉換器20。該降壓轉換器20耦接到一負載和該誤差放大器40以及該比較器50的第二輸入端。該誤差放大器40耦接到該暫態增強電路10。該暫態增強電路10耦接到該比較器50的第一輸入端。該比較器50的輸出端耦接到該COT控制器30。FIG. 3 shows a block diagram of a constant on-time (COT) converter 1 according to an embodiment of the present invention. The COT converter 1 includes a transient enhancement circuit 10, a buck converter 20, a COT controller 30, an error amplifier 40 and a comparator 50. The comparator 50 has a first input terminal, a second input terminal and an output terminal. The COT controller 30 is coupled to the buck converter 20. The buck converter 20 is coupled to a load, the error amplifier 40 and the second input terminal of the comparator 50. The error amplifier 40 is coupled to the transient enhancement circuit 10. The transient enhancement circuit 10 is coupled to the first input terminal of the comparator 50. The output terminal of the comparator 50 is coupled to the COT controller 30.

該COT控制器30經由該第一控制訊號S_C1控制該降壓轉換器20。該降壓轉換器20耦接到該誤差放大器40，以便為該COT轉換器1提供反饋路徑，其中該降壓轉換器20的一輸出電壓V OUT（即降壓電壓）被饋送到該誤差放大器40並與一參考電壓V REF進行比較，該參考電壓V REF係為精確的內部參考目標電壓。比較的結果從該誤差放大器40輸出，然後通過該暫態增強電路10和該比較器50反饋到該COT控制器30。然後，該COT控制器30因響應該反饋而產生該第一控制訊號S_C1。 The COT controller 30 controls the buck converter 20 via the first control signal S_C1. The step-down converter 20 is coupled to the error amplifier 40 to provide a feedback path for the COT converter 1, wherein an output voltage V OUT (ie, step-down voltage) of the step-down converter 20 is fed to the error amplifier 40 and compared with a reference voltage V REF, the reference voltage V REF based target precise internal reference voltage. The result of the comparison is output from the error amplifier 40 and then fed back to the COT controller 30 through the transient enhancement circuit 10 and the comparator 50. Then, the COT controller 30 generates the first control signal S_C1 in response to the feedback.

詳細地，該誤差放大器40具有一第一輸入端，一第二輸入端和一輸出端。該第二輸入端耦接到該參考電壓V REF。該第一輸入端耦接到該降壓轉換器20，以便透過一電阻分壓器接收該輸出電壓V OUT或該輸出電壓V OUT的分壓。這並非為本發明的限制條件。使用者應該能夠根據實際的需求選擇任一種電路設計。然後該誤差放大器40比較該反饋電壓和該參考電壓V REF，並相應地透過輸出端將電壓位準輸出到該暫態增強電路10。當該反饋電壓高於該參考電壓V REF時，輸出電壓位準將減小。 In detail, the error amplifier 40 has a first input terminal, a second input terminal and an output terminal. The second input terminal is coupled to the reference voltage V REF . The first input terminal is coupled to the buck converter 20 so as to receive the output voltage V OUT or the divided voltage of the output voltage V OUT through a resistor divider. This is not a limitation of the present invention. Users should be able to choose any circuit design according to actual needs. Then the error amplifier 40 compares the feedback voltage and the reference voltage V REF , and accordingly outputs the voltage level to the transient enhancement circuit 10 through the output terminal. When the feedback voltage is higher than the reference voltage V REF , the output voltage level will decrease.

參照圖4，其示出了根據本發明實施例的該暫態增強電路的方塊圖。在該實施例中，該暫態增強電路10包括一第一採樣並保持電路11和一零電流檢測電路12。該第一採樣並保持電路11具有一輸入端和一輸出端。該第一採樣並保持電路11的輸入端耦接該誤差放大器40的輸出端，該第一採樣並保持電路11的輸出端耦接該比較器50的第一輸入端。該零電流檢測電路12還耦接到該第一採樣並保持電路11。該零電流檢測電路12用來於檢測到流過負載的電流為零時，亦即耦接到該COT轉換器1的負載極低或不存在時，將該第二控制訊號S_C2輸出到該第一採樣並保持電路11。當該第一採樣並保持電路11接收該第二控制訊號S_C2時，該第一採樣並保持電路11將採樣並保持從該誤差放大器40輸出的電壓位準，並且將所保持的電壓向前饋送到該比較器50的第一輸入端。這樣，當耦接到該COT轉換器1的負載低時，反饋電壓會增加，並且從該誤差放大器40輸出的電壓會減小，該第一採樣並保持電路11可以在該誤差放大器40進一步下降之前將從該誤差放大器40輸出的電壓位準保持在相對高的位置，然後在下一個工作週期期間保持電壓前饋的結果，如果發生負載瞬變，即耦接到該COT轉換器1的負載變高，則負載暫態週期將縮短，因為負載暫態的低點是相對高於在先前的工作週期期間沒有該第一採樣並保持電路11時發生的低點。換句話說，該輸出電壓V OUT將花費更少的時間來升高，從而增強負載的暫態。 4, which shows a block diagram of the transient enhancement circuit according to an embodiment of the present invention. In this embodiment, the transient enhancement circuit 10 includes a first sample and hold circuit 11 and a zero current detection circuit 12. The first sample and hold circuit 11 has an input terminal and an output terminal. The input terminal of the first sample and hold circuit 11 is coupled to the output terminal of the error amplifier 40, and the output terminal of the first sample and hold circuit 11 is coupled to the first input terminal of the comparator 50. The zero current detection circuit 12 is also coupled to the first sample and hold circuit 11. The zero current detection circuit 12 is used to output the second control signal S_C2 to the second control signal S_C2 when it detects that the current flowing through the load is zero, that is, when the load coupled to the COT converter 1 is extremely low or does not exist A sample and hold circuit 11. When the first sample and hold circuit 11 receives the second control signal S_C2, the first sample and hold circuit 11 will sample and hold the voltage level output from the error amplifier 40, and feed the held voltage forward To the first input terminal of the comparator 50. In this way, when the load coupled to the COT converter 1 is low, the feedback voltage will increase and the voltage output from the error amplifier 40 will decrease, and the first sample and hold circuit 11 can further decrease in the error amplifier 40. Previously, the voltage level output from the error amplifier 40 was maintained at a relatively high position, and then the voltage feedforward result was maintained during the next operating cycle. If a load transient occurs, the load coupled to the COT converter 1 is changed. High, the load transient period will be shortened, because the low point of the load transient is relatively higher than the low point that occurred without the first sample and hold circuit 11 during the previous working cycle. In other words, the output voltage V OUT will take less time to rise, thereby enhancing the transient state of the load.

參照圖5，其示出了根據本發明實施例的該暫態增強電路的方塊圖。在該實施例中，該第一採樣並保持電路11包括一第一開關112和一第一電容器114。該第一開關112耦接在該第一採樣並保持電路11的輸入端和輸出端之間。該第一電容器114耦接在該第一採樣並保持電路11的輸出端與地之間。該第一開關112還耦接到該零電流檢測電路12。當該第一開關112接收該第二控制訊號S_C2時，該第一開關112打開。在閱讀以上段落之後，本領域技術人員應該容易理解該實施例的操作。為簡潔起見，此處將不再贅述。Referring to FIG. 5, it shows a block diagram of the transient enhancement circuit according to an embodiment of the present invention. In this embodiment, the first sample and hold circuit 11 includes a first switch 112 and a first capacitor 114. The first switch 112 is coupled between the input terminal and the output terminal of the first sample and hold circuit 11. The first capacitor 114 is coupled between the output terminal of the first sample and hold circuit 11 and ground. The first switch 112 is also coupled to the zero current detection circuit 12. When the first switch 112 receives the second control signal S_C2, the first switch 112 is turned on. After reading the above paragraphs, those skilled in the art should easily understand the operation of this embodiment. For the sake of brevity, I will not repeat them here.

參照圖6，其示出了根據本發明另一實施例的該暫態增強電路的方塊圖。在一個實施例中，該暫態增強電路10更包括一第二採樣並保持電路13和一箝位電路14。該第二採樣並保持電路13具有一輸入端和一輸出端。該第二採樣並保持電路13的輸入端耦接到該第一採樣並保持電路11的輸出端，該第二採樣並保持電路13的輸出端耦接到該比較器50的第一輸入端。該第二採樣並保持電路13還耦接到該零電流檢測電路12。該第二採樣並保持電路13的操作與該第一採樣並保持電路11的操作基本相同。當該第二採樣並保持電路13從該零電流檢測電路12接收該第二控制訊號S_C2時，該第二採樣並保持電路13將採樣並保持從該第一採樣並保持電路11輸出的電壓，以在電壓繼續下降之前將電壓保持在相對高的位準。然後將保持的電壓位準前饋到該比較器50的第一輸入端。箝位電路14具有一第一端以及一第二端，分別耦接在該第二採樣並保持電路13的輸出端與地之間。Referring to FIG. 6, it shows a block diagram of the transient enhancement circuit according to another embodiment of the present invention. In one embodiment, the transient enhancement circuit 10 further includes a second sample and hold circuit 13 and a clamp circuit 14. The second sample and hold circuit 13 has an input terminal and an output terminal. The input terminal of the second sample and hold circuit 13 is coupled to the output terminal of the first sample and hold circuit 11, and the output terminal of the second sample and hold circuit 13 is coupled to the first input terminal of the comparator 50. The second sample and hold circuit 13 is also coupled to the zero current detection circuit 12. The operation of the second sample and hold circuit 13 is basically the same as the operation of the first sample and hold circuit 11. When the second sample and hold circuit 13 receives the second control signal S_C2 from the zero current detection circuit 12, the second sample and hold circuit 13 will sample and hold the voltage output from the first sample and hold circuit 11. To keep the voltage at a relatively high level before the voltage continues to drop. Then the maintained voltage level is fed forward to the first input terminal of the comparator 50. The clamp circuit 14 has a first terminal and a second terminal, which are respectively coupled between the output terminal of the second sample and hold circuit 13 and the ground.

箝位電路14用於將該比較器50的輸入電壓保持在一定位準，以防止該比較器50進入飽和狀態。然而，由於從箝位電路14汲入的微小電流，該第一採樣並保持電路11保持的電壓位準將略微下降。該第二採樣並保持電路13可透過提供一第二電壓保持機制來減輕這種影響，這將進一步增強負載的暫態。The clamp circuit 14 is used to maintain the input voltage of the comparator 50 at a certain level to prevent the comparator 50 from entering the saturation state. However, due to the small current drawn from the clamp circuit 14, the voltage level maintained by the first sample and hold circuit 11 will drop slightly. The second sample-and-hold circuit 13 can mitigate this effect by providing a second voltage holding mechanism, which will further enhance the transient state of the load.

參照圖7，其示出了根據本發明另一實施例的該暫態增強電路的方塊圖。在該實施例中，該第二採樣並保持電路13包括一第二開關132和一第二電容器134。該第二開關132耦接在該第二採樣並保持電路13的輸入端和輸出端之間。該第二電容器134耦接在該第二採樣並保持電路13的輸出端與地之間。該第二開關132還耦接到該零電流檢測電路12。當該第二開關132接收該第二控制訊號S_C2時，該第二開關132打開。在閱讀以上段落之後，本領域技術人員應該容易理解該實施例的操作。為簡潔起見，此處將不再贅述。Referring to FIG. 7, it shows a block diagram of the transient enhancement circuit according to another embodiment of the present invention. In this embodiment, the second sample and hold circuit 13 includes a second switch 132 and a second capacitor 134. The second switch 132 is coupled between the input terminal and the output terminal of the second sample and hold circuit 13. The second capacitor 134 is coupled between the output terminal of the second sample and hold circuit 13 and ground. The second switch 132 is also coupled to the zero current detection circuit 12. When the second switch 132 receives the second control signal S_C2, the second switch 132 is turned on. After reading the above paragraphs, those skilled in the art should easily understand the operation of this embodiment. For the sake of brevity, I will not repeat them here.

在圖5或圖6的實施例中，該箝位電路14可以通過串聯耦接多個二極管或者透過將多個NMOS串聯耦接(其中每個NMOS的漏極和柵極連接)於該箝位電路14的第一端與第二端之間來實現。In the embodiment of FIG. 5 or FIG. 6, the clamp circuit 14 may be connected to the clamp by coupling a plurality of diodes in series or by coupling a plurality of NMOSs in series (where the drain and gate of each NMOS are connected). The circuit 14 is implemented between the first end and the second end.

參照圖8，其示出了根據本發明又一實施例的該暫態增強電路的方塊圖。在該實施例中，該暫態增強電路10還包括一微分器15。微分器15具有一第一輸入端，一第二輸入端和一輸出端。微分器15的第一輸入端耦接該降壓轉換器20的輸出端，該微分器15的第二輸入端耦接該第二採樣並保持電路13的輸出端，該微分器15的輸出端耦接該比較器50的第一輸入端。該微分器15用來於該第二採樣並保持電路13的輸出電壓饋入該比較器50的第一輸入端之前，進一步增加來該第二採樣並保持電路13的輸出電壓的“紋波”，以便提供更明顯的訊號。Referring to FIG. 8, it shows a block diagram of the transient enhancement circuit according to another embodiment of the present invention. In this embodiment, the transient enhancement circuit 10 further includes a differentiator 15. The differentiator 15 has a first input terminal, a second input terminal and an output terminal. The first input terminal of the differentiator 15 is coupled to the output terminal of the buck converter 20, the second input terminal of the differentiator 15 is coupled to the output terminal of the second sample and hold circuit 13, and the output terminal of the differentiator 15 The first input terminal of the comparator 50 is coupled. The differentiator 15 is used to further increase the "ripple" of the output voltage of the second sample and hold circuit 13 before the output voltage of the second sample and hold circuit 13 is fed into the first input terminal of the comparator 50 In order to provide a more obvious signal.

參照圖9，其示出了根據本發明又一實施例的該暫態增強電路的方塊圖。在該實施例中，該暫態增強電路10還包括一補償電路16。補償電路16耦接在該第一採樣並保持電路11的輸出端與地之間。由於根據本發明的該COT轉換器1具有反饋路徑，所以如果不仔細設計，該COT轉換器1可能會發生振盪。該補償電路16係設置成向該COT轉換器1提供相位補償，以防止該COT轉換器1產生振盪。9, which shows a block diagram of the transient enhancement circuit according to another embodiment of the present invention. In this embodiment, the transient enhancement circuit 10 further includes a compensation circuit 16. The compensation circuit 16 is coupled between the output terminal of the first sample and hold circuit 11 and the ground. Since the COT converter 1 according to the present invention has a feedback path, if it is not carefully designed, the COT converter 1 may oscillate. The compensation circuit 16 is configured to provide phase compensation to the COT converter 1 to prevent the COT converter 1 from oscillating.

在一個較佳實施例中，如圖10所示，該補償電路16可包括串聯耦接在該第一採樣並保持電路11的輸出端與地之間的一電阻器162和一電容器164。然而，該電阻器162和該電容器164的耦接順序並非本發明的限制條件。在不脫離本發明的精神的情況下，本領域技術人員可以互換地使用任一種設計。In a preferred embodiment, as shown in FIG. 10, the compensation circuit 16 may include a resistor 162 and a capacitor 164 coupled in series between the output terminal of the first sample and hold circuit 11 and the ground. However, the coupling sequence of the resistor 162 and the capacitor 164 is not a limitation of the present invention. Those skilled in the art can interchange any design without departing from the spirit of the present invention.

透過本發明的一些較佳實施例的描述，並且應該理解，較佳實施例僅是說明性的，並不旨在以任何方式限制本發明，並且可以在沒有所描述的實施例的情況下進行改變和修改。在不背離本發明的範圍和精神的前提下，其旨在僅受所附請求項的限制。Through the description of some preferred embodiments of the present invention, it should be understood that the preferred embodiments are only illustrative and are not intended to limit the present invention in any way, and can be carried out without the described embodiments Changes and modifications. Without departing from the scope and spirit of the present invention, it is intended to be limited only by the appended claims.

10:暫態增強電路 11:第一採樣並保持電路 112:第一開關 114:第一電容器 12:零電流檢測電路 13:第二採樣並保持電路 132:第二開關 134:第二電容器 14:箝位電路 15:微分器 16:補償電路 162:電阻器 164:電容器 20:降壓轉換器 30:COT控制器 40:誤差放大器 50:比較器 IOUT:負載電流 S_C1、S_C2、VC:控制訊號 VIN:輸入電壓 VREF:參考電壓 VOUT:輸出電壓 VSW:脈衝序列電壓10: Transient enhancement circuit 11: First sample and hold circuit 112: First switch 114: First capacitor 12: Zero current detection circuit 13: Second sample and hold circuit 132: Second switch 134: Second capacitor 14: Clamp circuit 15: Differentiator 16: Compensation circuit 162: Resistor 164: Capacitor 20: Step-down converter 30: COT controller 40: Error amplifier 50: Comparator I OUT : Load current S_C1, S_C2, VC: Control signal V IN : Input voltage V REF : Reference voltage V OUT : Output voltage V SW : Pulse train voltage

通過參考以下較佳實施例的詳細描述和圖式，可以最好地理解本發明採用的用於實現上述和其他目的的結構和技術手段，其中 ［圖1］是傳統該降壓轉換器的電路結構的方塊圖。 ［圖2］是關於圖1該降壓轉換器的負載電流和輸出電壓的暫態圖。 ［圖3］是本發明的實施例的恆定導通時間（COT）轉換器1的方塊圖。 ［圖4］是本發明實施例的該暫態增強電路的方塊圖。 ［圖5］是本發明實施例的該暫態增強電路的方塊圖。 ［圖6］是本發明另一實施例的該暫態增強電路的方塊圖。 ［圖7］是本發明另一實施例的該暫態增強電路的方塊圖。 ［圖8］是本發明又一實施例的該暫態增強電路的方塊圖。 ［圖9］是本發明又一實施例的該暫態增強電路的方塊圖。 ［圖10］是本發明又一實施例的該暫態增強電路的方塊圖。 By referring to the detailed description and drawings of the following preferred embodiments, one can best understand the structure and technical means adopted by the present invention to achieve the above and other objectives, where [Figure 1] is a block diagram of the circuit structure of the traditional buck converter. [Figure 2] is a transient diagram of the load current and output voltage of the buck converter in Figure 1. [FIG. 3] is a block diagram of the constant on-time (COT) converter 1 of the embodiment of the present invention. [Figure 4] is a block diagram of the transient enhancement circuit of the embodiment of the present invention. [Figure 5] is a block diagram of the transient enhancement circuit of the embodiment of the present invention. [Figure 6] is a block diagram of the transient enhancement circuit according to another embodiment of the present invention. [Figure 7] is a block diagram of the transient enhancement circuit according to another embodiment of the present invention. [Figure 8] is a block diagram of the transient enhancement circuit according to another embodiment of the present invention. [Fig. 9] is a block diagram of the transient enhancement circuit according to another embodiment of the present invention. [Fig. 10] is a block diagram of the transient enhancement circuit according to another embodiment of the present invention.

10:暫態增強電路 10: Transient enhancement circuit

11:第一採樣並保持電路 11: The first sample and hold circuit

12:零電流檢測電路 12: Zero current detection circuit

40:誤差放大器 40: Error amplifier

50:比較器 50: comparator

Claims (20)

一種用於一恆定導通時間轉換器的暫態增強電路，該恆定導通時間轉換器包括一誤差放大器和一比較器，該暫態增強電路包括： 一第一採樣並保持電路，具有一輸入端和一輸出端，其中該第一採樣並保持電路的輸入端耦接該誤差放大器的一輸出端，該第一採樣並保持電路的輸出端耦接到該比較器的一第一輸入端；以及 一零電流檢測電路，耦接到該第一個採樣並保持電路， 其中該零電流檢測電路用來於檢測到流過耦接至該恆定導通時間轉換器的一負載電流為零時，輸出一控制訊號。 A transient enhancement circuit for a constant on-time converter. The constant on-time converter includes an error amplifier and a comparator. The transient enhancement circuit includes: A first sample and hold circuit having an input terminal and an output terminal, wherein the input terminal of the first sample and hold circuit is coupled to an output terminal of the error amplifier, and the output terminal of the first sample and hold circuit is coupled to To a first input terminal of the comparator; and A zero current detection circuit, coupled to the first sample and hold circuit, The zero current detection circuit is used for outputting a control signal when detecting that a load current coupled to the constant on-time converter is zero. 如請求項1所述之該暫態增強電路，更包含： 一第二採樣並保持電路，具有一輸入端和一輸出端，其中該第二採樣並保持電路的輸入端耦接該第一採樣並保持電路的輸出端，該第二採樣並保持電路的輸出端連接到該比較器的第一輸入端；以及 一箝位電路，具有一第一端和一第二端，其中該箝位電路的第一端耦接該第二採樣並保持電路的輸出端，該箝位電路的第二端耦接地， 其中該零電流檢測電路耦接到該第二採樣並保持電路。 The transient enhancement circuit as described in claim 1, further comprising: A second sample and hold circuit having an input terminal and an output terminal, wherein the input terminal of the second sample and hold circuit is coupled to the output terminal of the first sample and hold circuit, and the output of the second sample and hold circuit Terminal is connected to the first input terminal of the comparator; and A clamping circuit having a first terminal and a second terminal, wherein the first terminal of the clamping circuit is coupled to the output terminal of the second sampling and holding circuit, and the second terminal of the clamping circuit is coupled to ground, The zero current detection circuit is coupled to the second sample and hold circuit. 如請求項2所述之該暫態增強電路，更包含： 一補償電路，耦接在該第一採樣並保持電路的輸出端與地之間。 The transient enhancement circuit as described in claim 2 further includes: A compensation circuit is coupled between the output terminal of the first sampling and holding circuit and the ground. 如請求項3項所述之該暫態增強電路，其中該補償電路包含： 一電阻器；以及 一個電容器， 其中該電阻器和該電容器串聯耦接在該第一採樣並保持電路的輸出端和地之間。 The transient enhancement circuit according to claim 3, wherein the compensation circuit includes: A resistor; and A capacitor, The resistor and the capacitor are coupled in series between the output terminal of the first sample and hold circuit and the ground. 如請求項2所述之該暫態增強電路，其中該第二採樣並保持電路包含： 一第二開關，耦接在該第二採樣並保持電路的輸入端和輸出端之間；以及 一第二電容器，耦接在該第二採樣並保持電路的輸入端和地之間， 其中在每個工作循環期間，該第二開關因嚮應該控制訊號而被打開。 The transient enhancement circuit according to claim 2, wherein the second sample and hold circuit includes: A second switch, coupled between the input terminal and the output terminal of the second sample and hold circuit; and A second capacitor, coupled between the input terminal of the second sample and hold circuit and ground, During each working cycle, the second switch is turned on due to the control signal. 如請求項2所述之該暫態增強電路，其中該第二採樣並保持電路被設置為保持從該誤差放大器輸出的一誤差電壓的一採樣電壓位準，然後該箝位電路因響應於該控制訊號而箝位所述採樣電壓位準。The transient enhancement circuit according to claim 2, wherein the second sampling and holding circuit is configured to maintain a sampling voltage level of an error voltage output from the error amplifier, and then the clamping circuit is responsive to the The control signal clamps the sampling voltage level. 如請求項2所述之該暫態增強電路，進一步包括： 具有一輸入端及一輸出端的一微分器，其中該微分器的輸入端耦接到該第二採樣並保持電路的輸出端，該微分器的輸出端耦接到該比較器的第一輸入端。 The transient enhancement circuit as described in claim 2, further comprising: A differentiator having an input terminal and an output terminal, wherein the input terminal of the differentiator is coupled to the output terminal of the second sample and hold circuit, and the output terminal of the differentiator is coupled to the first input terminal of the comparator . 如請求項2所述之該暫態增強電路，其中該箝位電路包括： 多個二極管串聯耦接在該箝位電路的第一端和該箝位電路的第二端之間。 The transient enhancement circuit according to claim 2, wherein the clamping circuit includes: A plurality of diodes are coupled in series between the first end of the clamping circuit and the second end of the clamping circuit. 如請求項1所述之該暫態增強電路，其中該第一採樣並保持電路包括： 一第一開關，連接在該第一採樣並保持電路的輸入端和輸出端之間；以及 一第一電容器，耦接在該第一採樣並保持電路的輸出端和地之間， 其中在每個工作循環期間，該第一開關因響應該控制訊號而被打開。 The transient enhancement circuit according to claim 1, wherein the first sample and hold circuit includes: A first switch connected between the input terminal and the output terminal of the first sample and hold circuit; and A first capacitor, coupled between the output terminal of the first sample and hold circuit and ground, During each working cycle, the first switch is opened in response to the control signal. 如請求項1所述之該暫態增強電路，其中該第一採樣並保持電路被設置為因響應該控制訊號而保持從該誤差放大器輸出的一誤差電壓的一採樣電壓位準。The transient enhancement circuit according to claim 1, wherein the first sampling and holding circuit is configured to maintain a sampling voltage level of an error voltage output from the error amplifier in response to the control signal. 一種恆定導通時間轉換器，包括： 一誤差放大器，具有一第一輸入端，一第二輸入端和一輸出端，其中該第二輸入端耦接一參考電壓； 一比較器，具有一第一輸入端，一第二輸入端及一輸出端； 一降壓轉換器，具有一輸入端和一輸出端，其中該降壓轉換器的輸出端耦接該誤差放大器的第一輸入端、該比較器的第二輸入端以及一負載； 一恆定導通時間控制器，耦接該降壓轉換器的輸入端和該比較器的輸出端之間； 一暫態增強電路，包括： 一第一採樣並保持電路，具有一輸入端和一輸出端，其中該第一採樣並保持電路的輸入端耦接該誤差放大器的輸出端且該第一採樣並保持電路的輸出端耦接到該比較器的第一輸入端；以及 一零電流檢測電路，耦接到該第一採樣並保持電路， 其中該零電流檢測電路用來於檢測到流過耦接至該恆定導通時間轉換器的一負載電流為零時，輸出一控制訊號。 A constant on-time converter includes: An error amplifier having a first input terminal, a second input terminal and an output terminal, wherein the second input terminal is coupled to a reference voltage; A comparator having a first input terminal, a second input terminal and an output terminal; A buck converter having an input terminal and an output terminal, wherein the output terminal of the buck converter is coupled to the first input terminal of the error amplifier, the second input terminal of the comparator and a load; A constant on-time controller, coupled between the input terminal of the buck converter and the output terminal of the comparator; A transient enhancement circuit, including: A first sample and hold circuit having an input terminal and an output terminal, wherein the input terminal of the first sample and hold circuit is coupled to the output terminal of the error amplifier and the output terminal of the first sample and hold circuit is coupled to The first input terminal of the comparator; and A zero current detection circuit, coupled to the first sample and hold circuit, The zero current detection circuit is used for outputting a control signal when detecting that a load current coupled to the constant on-time converter is zero. 如請求項11所述的恆定導通時間轉換器，更包括： 一第二採樣並保持電路，具有一輸入端和一輸出端，其中該第二採樣並保持電路的輸入端耦接該第一採樣並保持電路的輸出端，該第二採樣並保持電路的輸出端耦接到該比較器的該第一輸入端；以及 一箝位電路，耦接在該第二採樣並保持電路的輸出端和地之間， 其中該零電流檢測電路耦接到該第二採樣並保持電路。 The constant on-time converter as described in claim 11 further includes: A second sample and hold circuit having an input terminal and an output terminal, wherein the input terminal of the second sample and hold circuit is coupled to the output terminal of the first sample and hold circuit, and the output of the second sample and hold circuit Terminal is coupled to the first input terminal of the comparator; and A clamping circuit, coupled between the output terminal of the second sample and hold circuit and ground, The zero current detection circuit is coupled to the second sample and hold circuit. 如請求項12所述的恆定導通時間轉換器，其中該箝位電路包括： 多個串聯耦接的二極管。 The constant on-time converter according to claim 12, wherein the clamping circuit includes: A plurality of diodes coupled in series. 如請求項13所述的恆定導通時間轉換器，更包括： 具有一輸入端和一輸出端的一微分器，其中該微分器的輸入端耦接到該第二採樣並保持電路的輸出端，且該微分器的輸出端耦接到該比較器的第一輸入端。 The constant on-time converter as described in claim 13, further comprising: A differentiator having an input terminal and an output terminal, wherein the input terminal of the differentiator is coupled to the output terminal of the second sample and hold circuit, and the output terminal of the differentiator is coupled to the first input of the comparator end. 如請求項12所述的恆定導通時間轉換器，更包括： 一補償電路，耦接在該第一採樣並保持電路的輸出端和地之間。 The constant on-time converter as described in claim 12 further includes: A compensation circuit is coupled between the output terminal of the first sampling and holding circuit and the ground. 如請求項15所述的恆定導通時間轉換器，其中該補償電路包括： 一電阻器；以及 一個電容器， 其中該電阻器和該電容器串聯耦接在該第一採樣並保持電路的輸出端和地之間。 The constant on-time converter according to claim 15, wherein the compensation circuit includes: A resistor; and A capacitor, The resistor and the capacitor are coupled in series between the output terminal of the first sample and hold circuit and the ground. 如請求項12所述的恆定導通時間轉換器，其中該第二採樣並保持電路包括： 一第二開關，耦接在該第二採樣並保持電路的輸入端和輸出端之間；以及 一第二電容器，耦接在該第二採樣並保持電路的輸入端和地之間， 其中在每個工作循環期間，該第二開關因響應該控制訊號而被打開。 The constant on-time converter according to claim 12, wherein the second sample and hold circuit includes: A second switch, coupled between the input terminal and the output terminal of the second sample and hold circuit; and A second capacitor, coupled between the input terminal of the second sample and hold circuit and ground, During each working cycle, the second switch is opened in response to the control signal. 根據請求項12所述的恆定導通時間轉換器，其中該第二採樣並保持電路被設置來保持從所述該誤差放大器輸出的一誤差電壓的一採樣電壓位準，然後該箝位電路因響應於該控制訊號而箝位該採樣電壓位準。The constant on-time converter according to claim 12, wherein the second sampling and holding circuit is configured to maintain a sampling voltage level of an error voltage output from the error amplifier, and then the clamping circuit responds The sampling voltage level is clamped on the control signal. 如請求項11所述的恆定導通時間轉換器，其中所述該第一採樣並保持電路包括： 一第一開關，連接在該第一採樣並保持電路的輸入端和輸出端之間；以及 一第一電容器，耦接在該第一採樣並保持電路的輸出端和地之間， 其中在每個工作循環期間，該第一開關因響應控制訊號而被打開。 The constant on-time converter according to claim 11, wherein the first sample and hold circuit includes: A first switch connected between the input terminal and the output terminal of the first sample and hold circuit; and A first capacitor, coupled between the output terminal of the first sample and hold circuit and ground, During each working cycle, the first switch is opened in response to the control signal. 如請求項11所述的恆定導通時間轉換器，其中所述該第一採樣並保持電路被配置為因響應該控制訊號而保持從所述該誤差放大器輸出的一誤差電壓的一採樣電壓位準。The constant on-time converter according to claim 11, wherein the first sample and hold circuit is configured to maintain a sample voltage level of an error voltage output from the error amplifier in response to the control signal .
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TW200840174A (en) * 2007-03-19 2008-10-01 Semiconductor Components Ind Method of forming a power supply controller and structure therefor
US20120087160A1 (en) * 2010-10-12 2012-04-12 University Of Seoul Industry Cooperation Foundation Power factor correction circuit
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