TWI704547B

TWI704547B - A display driving module and control method and a display driving system

Info

Publication number: TWI704547B
Application number: TW108127434A
Authority: TW
Inventors: 史富洋
Original assignee: 米彩股份有限公司
Priority date: 2019-08-02
Filing date: 2019-08-02
Publication date: 2020-09-11
Also published as: TW202107437A

Abstract

A display driving module and control method is proposed. It comprises: a frequency-adjustable oscillator and a calibration unit; the calibration unit outputs the frequency calibration information to the frequency-adjustable oscillator to make it's output frequency is within the target range; the frequency-adjustable oscillator output is a grayscale clock; a PWM (Pulse-Width-Modulation) module generates a pulse control signal according to the grayscale clock and a driving data; a driving output unit receives the pulse control signal and outputs a driving signal based on the pulse control signal. This invention also proposes a display driving system comprises at least two driving modules. Because the two modules have different oscillators individually, their grayscale clock frequencies are different, and the clock switching timing are not synchronized. Such that the two driving signals' switching noise will not happen simultaneously, and the spectrum will been spread, the EMI spur will been suppressed.

Description

顯示器驅動模組及其控制方法與顯示器驅動系統Display driving module and its control method and display driving system

一種驅動模組、控制方法及驅動系統，尤指一種LED顯示器驅動模組及其控制方法及一種LED顯示器驅動系統。A driving module, a control method and a driving system, especially an LED display driving module and a control method thereof, and an LED display driving system.

LED(Light-Emitting Diode; LED)顯示器係通過一顯示器驅動系統進行驅動產生影像，一LED顯示器包含至少一LED單元及顯示器驅動模組，其驅動模組根據一亮度控制訊號產生一電流訊號，使該電流訊號通過LED單元，而LED單元根據該電流訊號的強度產生相對應強度的光。現有的顯示器驅動模組一般來說是使用脈寬調變機制(Pulse Width Modulation；PWM)控制各該LED單元產生不同亮暗程度。更詳細的說，PWM機制係藉由人眼的視覺暫留特性，也就是在一光源的閃爍頻率大於一臨界值時，人眼便無法感受到光源的閃爍，因此，在大於該臨界頻率的一輸出週期中，根據一亮度控制訊號，調變每一輸出週期中LED單元發光的時間百分比，改變LED單元在該輸出週期中的光源的總輸出量，以提供人眼感受不同的亮度。該發光時間百分比的控制方式是將該輸出週期切割為多個最小單位時間，該LED在該輸出週期中維持發光的最小單位時間的數量則決定了在該輸出週期中的總發光量。該不同位階的發光量被稱為「灰階(Grayscale)」。該輸出週期被切割出的最小單位時間愈小，表示可控制的發光位階愈多，也就是灰階的階層數量愈高，提供人眼感受的明暗變化愈細緻平滑；相反的，當該最小單位時間愈長，表示可控制的發光位階少，灰階的階層數量愈低，人眼感受到的明暗變化則較粗糙，可能感受到較明顯的明暗階段差異。而該輸出週期代表了該LED顯示器的最高「刷新率」。其中，該「最小單位時間」主要係由一灰階時脈訊號(Grayscale Clock; GCLK)產生。該灰階時脈訊號頻率愈大，則該最小單位時間愈短。也就是說，該灰階時脈訊號的頻率與該顯示器的灰階值皆相關。另一方面來說，由於該輸出週期係由複數個相連的最小單位時間組成，在同樣最小單位時間數量的情況下，當該灰階時脈頻率愈大，該輸出週期也愈短，該刷新率也能夠愈高。換句話說，該灰階時脈訊號頻率愈大，該LED顯示器不僅灰階的改變幅度能夠更細緻平滑，且刷新率也能夠提高。請參閱圖10所示，現有技術的LED驅動模組90一般來說包含一驅動輸出模組91及一脈寬調變控制單元92，且具有一控制資訊接收端data、驅動資訊時脈輸入端dclk及一灰階時脈訊號輸入端gclk。該脈寬調變控制單元92通過該控制資訊接收端data接收一脈寬控制資訊，通過該驅動資訊脈輸入端dclk接收一驅動資訊時脈，並通過該灰階時脈訊號輸入端gclk接收一灰階時脈訊號。該驅動資訊時脈係用於觸發輸入控制資訊。該脈寬調變控制單元根據該脈寬控制資訊，及該灰階時脈訊號產生脈寬控制訊號並輸出至該驅動輸出模組91，使得該驅動輸出模組91根據該脈寬控制訊號輸出一驅動訊號。該控制資訊接收端data及該灰階時脈訊號輸入端gclk分別係通過一電路板線路接收該亮度控制資訊及該時脈訊號。然而，基於PCB(Printed circuit board)電路板上流通的訊號頻率過高時，會導致EMI過高，而進一步導致訊號互相干擾而失真，因此PCB電路板對於流通其上的訊號頻率有一定的限制，而該外接灰階時脈訊號的頻率無法超過該限制。一般來說，該電路板上的訊號頻率上限為30Mhz。請參閱圖11所示，在另一現有技術中，該LED驅動模組90僅包含一驅動資訊時脈輸入端dclk及該驅動資訊時脈輸入端dclk，不包含該灰階時脈訊號輸入端gclk。該LED驅動模組90進一步包含一鎖相環單元93(Phase Lock Loop)。該脈寬調變控制單元92係通過該鎖相環單元93電連接到該驅動資訊時脈輸入端dclk，而該鎖相環單元93接收該驅動資訊時脈訊號，對該驅動資訊時脈訊號進行一倍頻，作為一灰階時脈，並輸出該灰階時脈訊號至該脈寬調變單元92。也就是說，經由該鎖相環單元93提高該驅動資訊時脈訊號的頻率，以提供複數個LED驅動模組90的脈寬調變控制單元92一相位同步且頻率相同的灰階時脈訊號。如圖10及圖11所示，當該顯示器系統包含多個LED驅動模組90，且各該LED驅動模組90分別輸出一驅動訊號，由於各該LED驅動模組90接收同一個時脈訊號輸入，例如該灰階時脈訊號或該驅動資訊時脈，也就是該時脈訊號的來源為相同，因此各該LED驅動模組90的驅動訊號為同相，且每一輸出週期中，其訊號上升緣會同步，當一輸出週期中的驅動訊號的佔空比相同，其訊號下降緣也會同步，因此各該驅動訊號在開關時產生的訊號突波的發生時間也會同步，導致電路板上的雜訊(noise)發生疊加效應而過大。此外，同樣基於各該LED驅動模組90接收同一個時脈訊號的緣故，各該LED驅動模組90的灰階時脈訊號頻率相同，使得各該驅動訊號產生的電磁干擾(EMI)頻段過於集中，其EMI頻譜會產生多個突波(spur)，而該EMI的突波容易超出法規對於電子產品的EMI規範，導致產品整體不符規範。綜合以上，現有的LED顯示驅動模組的由外部接收灰階時脈訊號導致灰階及刷新率受到限制，且進一步使得顯示器電路板上的多個驅動訊號生的雜訊過高。若將驅動模組內建鎖相環單元以產生GCLK，仍會有EMI頻譜集中問題，因此容易超出規範。故現有技術的LED顯示器驅動模組勢必須進一步進行改良。 LED (Light-Emitting Diode; LED) displays are driven by a display drive system to generate images. An LED display includes at least one LED unit and a display drive module. The drive module generates a current signal according to a brightness control signal to enable The current signal passes through the LED unit, and the LED unit generates light of corresponding intensity according to the intensity of the current signal. The existing display driving module generally uses a pulse width modulation mechanism (Pulse Width Modulation; PWM) to control each LED unit to produce different brightness and darkness. In more detail, the PWM mechanism is based on the persistence of the human eye, that is, when the flicker frequency of a light source is greater than a critical value, the human eye cannot feel the flicker of the light source. In an output cycle, according to a brightness control signal, the percentage of time that the LED unit emits light in each output cycle is adjusted, and the total output of the light source of the LED unit in the output cycle is changed to provide human eyes with different brightness. The control method of the luminous time percentage is to cut the output period into a plurality of minimum unit times, and the number of the minimum unit time during which the LED keeps emitting light in the output period determines the total amount of light emitted in the output period. The different levels of light emission are called "Grayscale". The smaller the minimum unit time that the output period is cut out, the more controllable luminous levels, that is, the higher the number of gray levels, the more detailed and smooth the light and dark changes that human eyes feel; on the contrary, when the minimum unit The longer the time, the less the controllable luminous level, the lower the number of gray levels, the coarser the light and shade changes perceived by the human eye, and the more obvious difference in light and dark stages may be felt. The output period represents the highest "refresh rate" of the LED display. Among them, the "minimum unit time" is mainly generated by a grayscale clock signal (Grayscale Clock; GCLK). The greater the frequency of the gray-scale clock signal, the shorter the minimum unit time. That is, the frequency of the gray-scale clock signal is related to the gray-scale value of the display. On the other hand, since the output period is composed of a plurality of connected minimum unit times, under the same minimum unit time quantity, when the gray-scale clock frequency is larger, the output period is also shorter, the refresh The rate can also be higher. In other words, the greater the frequency of the gray-scale clock signal, the greater the change range of the gray-scale of the LED display can be more detailed and smooth, and the refresh rate can also be improved. Please refer to FIG. 10, the prior art LED drive module 90 generally includes a drive output module 91 and a pulse width modulation control unit 92, and has a control information receiving terminal data and a drive information clock input terminal dclk and a gray-scale clock signal input terminal gclk. The pulse width modulation control unit 92 receives a pulse width control information through the control information receiving terminal data, a driving information clock through the driving information pulse input terminal dclk, and a gray-scale clock signal input terminal gclk. Grayscale clock signal. The drive information clock is used to trigger input control information. The pulse width modulation control unit generates a pulse width control signal according to the pulse width control information and the gray-scale clock signal and outputs it to the drive output module 91, so that the drive output module 91 outputs according to the pulse width control signal One drive signal. The control information receiving terminal data and the gray-scale clock signal input terminal gclk respectively receive the brightness control information and the clock signal through a circuit board circuit. However, when the frequency of the signal circulating on the PCB (Printed circuit board) is too high, it will cause excessive EMI, which will further cause the signals to interfere with each other and be distorted. Therefore, the PCB circuit board has certain restrictions on the frequency of the signal circulating on it. , And the frequency of the external gray-scale clock signal cannot exceed the limit. Generally speaking, the upper limit of the signal frequency on the circuit board is 30Mhz. Referring to FIG. 11, in another prior art, the LED driving module 90 only includes a driving information clock input terminal dclk and the driving information clock input terminal dclk, but does not include the gray-scale clock signal input terminal gclk. The LED driving module 90 further includes a phase lock loop unit 93 (Phase Lock Loop). The pulse width modulation control unit 92 is electrically connected to the drive information clock input terminal dclk through the phase lock loop unit 93, and the phase lock loop unit 93 receives the drive information clock signal, and the drive information clock signal Perform a frequency doubling as a gray-scale clock, and output the gray-scale clock signal to the pulse width modulation unit 92. That is to say, the frequency of the driving information clock signal is increased by the phase-locked loop unit 93 to provide the pulse width modulation control unit 92 of the plurality of LED driving modules 90 with a phase-synchronized gray-scale clock signal with the same frequency . As shown in FIGS. 10 and 11, when the display system includes a plurality of LED driving modules 90, and each of the LED driving modules 90 respectively outputs a driving signal, since each of the LED driving modules 90 receives the same clock signal Input, such as the gray-scale clock signal or the driving information clock, that is, the source of the clock signal is the same. Therefore, the driving signals of the LED driving modules 90 are in phase, and in each output cycle, the signal The rising edge will be synchronized. When the duty cycle of the driving signal in an output cycle is the same, the falling edge of the signal will also be synchronized. Therefore, the occurrence time of the signal surge generated by each driving signal when switching is also synchronized, resulting in The noise on the surface has a superimposed effect and is too large. In addition, since each LED drive module 90 receives the same clock signal, the gray-scale clock signal frequency of each LED drive module 90 is the same, so that the electromagnetic interference (EMI) frequency band generated by each drive signal is too high. Concentration, its EMI spectrum will generate multiple spurs, and the EMI spurs are likely to exceed the EMI specifications for electronic products in the regulations, resulting in the overall product not complying with the specifications. In summary, the existing LED display driving module receives gray-scale clock signals from the outside, which limits the gray-scale and refresh rate, and further increases the noise generated by the multiple driving signals on the display circuit board. If the drive module is built with a phase-locked loop unit to generate GCLK, there will still be a problem of EMI spectrum concentration, so it is easy to exceed the specification. Therefore, the prior art LED display driving module must be further improved.

有鑑於現有的LED顯示器驅動模組接收外部時脈訊號，導致灰階或刷新率難以提高，且多個LED顯示器驅動模組輸出的驅動訊號升降緣及頻率同步導致顯示系統中電路板上雜訊及EMI集中且過高，本創作提供一種顯示器驅動模組，整合於一積體電路內，該顯示器驅動模組具有一驅動資訊輸入端及一驅動訊號輸出端，並且包含一校正單元、一振盪器、一脈寬調變單元及一驅動輸出單元。該校正單元儲存有一頻率校正資訊，且該校正單元輸出該頻率校正資訊至該振盪器，該振盪器產生一灰階時脈訊號，該頻率校正資訊使得該振盪器產生的灰階時脈訊號在一目標頻率範圍內；該脈寬調變單元電連接該驅動資訊輸入端以接收一驅動資訊，該驅動資訊包含關於一個以上驅動輸出之資訊。該脈寬調變單元電連接該振盪器以接收該灰階時脈訊號，該脈寬調變單元根據該驅動資訊及該灰階時脈訊號輸出一脈寬控制訊號，而該驅動輸出單元電連接該脈寬調變單元以接收該脈寬控制訊號，並且據以輸出一驅動訊號。In view of the fact that the existing LED display driving module receives external clock signals, it is difficult to increase the gray scale or refresh rate, and the rising and falling edges and frequency synchronization of the driving signals output by multiple LED display driving modules cause noise on the circuit board in the display system And EMI is concentrated and too high. This creation provides a display drive module integrated in an integrated circuit. The display drive module has a drive information input terminal and a drive signal output terminal, and includes a calibration unit and an oscillation , A pulse width modulation unit and a drive output unit. The correction unit stores a frequency correction information, and the correction unit outputs the frequency correction information to the oscillator, the oscillator generates a gray-scale clock signal, and the frequency correction information makes the gray-scale clock signal generated by the oscillator in Within a target frequency range; the pulse width modulation unit is electrically connected to the drive information input terminal to receive a drive information, and the drive information includes information about more than one drive output. The pulse width modulation unit is electrically connected to the oscillator to receive the gray-scale clock signal, the pulse-width modulation unit outputs a pulse-width control signal according to the driving information and the gray-scale clock signal, and the drive output unit is electrically connected The pulse width modulation unit is connected to receive the pulse width control signal and output a driving signal accordingly.

本創作還提供一種顯示器驅動控制方法，係由該顯示器驅動模組執行，包含以下步驟：存取一頻率校正資訊；根據該頻率校正資訊控制一振盪器產生一灰階時脈訊號，使該灰階時脈訊號的頻率在一目標頻率範圍內；接收一驅動資訊，根據該驅動資訊及該灰階時脈訊號產生一脈寬控制訊號；根據該脈寬控制訊號產生一驅動訊號。 This creation also provides a display drive control method, which is executed by the display drive module, and includes the following steps: Access a frequency calibration information; Controlling an oscillator to generate a gray-scale clock signal according to the frequency correction information so that the frequency of the gray-scale clock signal is within a target frequency range; Receiving a driving information, and generating a pulse width control signal according to the driving information and the gray-scale clock signal; A driving signal is generated according to the pulse width control signal.

該顯示器驅動模組包含該振盪器，該振盪器用以提供該脈寬調變單元的灰階時脈訊號，並且該校正單元藉由其中儲存的頻率校正資訊校正該振盪器輸出的灰階時脈訊號。由於該振盪器係內建於該顯示器驅動模組內，該振盪器的頻率不受限於一PCB電路板或其他種類之連接電路模組可以接受的頻率上限，因此該脈寬調變單元所接收的該灰階時脈訊號頻率也不受限於該可被接受的頻率上限，而進一步提升該顯示器驅動模組輸出的驅動訊號的灰階或刷新率。該振盪器可以設計為輸出頻率對溫度與電壓的變化不敏感，即在不同溫度與電壓之下輸出頻率變化不大，因此對於輸出週期與刷新率的影響不大。The display driving module includes the oscillator, the oscillator is used to provide the gray-scale clock signal of the pulse width modulation unit, and the correction unit uses the frequency correction information stored therein to correct the gray-scale time output of the oscillator Pulse signal. Since the oscillator is built in the display drive module, the frequency of the oscillator is not limited to the upper limit of the frequency acceptable to a PCB circuit board or other types of connection circuit modules, so the pulse width modulation unit is The received gray-scale clock signal frequency is not limited to the acceptable upper frequency limit, and the gray-scale or refresh rate of the driving signal output by the display driving module is further improved. The oscillator can be designed so that the output frequency is not sensitive to changes in temperature and voltage, that is, the output frequency does not change much under different temperatures and voltages, so it has little effect on the output cycle and refresh rate.

進一步來說，一振盪器係輸出一特定頻率的時脈訊號(clock)，該特定頻率應為振盪器的規格頻率，也就是生產製造時的產品規格。而由於半導體製程必然會在每顆芯片產生不同誤差，每顆芯片的振盪器的實際頻率會有較大誤差。因此，該校正單元儲存一頻率校正資訊，並通過輸出該頻率校正資訊至該振盪器以調整該振盪器輸出的灰階時脈訊號頻率，使該灰階時脈訊號的頻率在該目標頻率範圍內。Furthermore, an oscillator outputs a clock signal (clock) of a specific frequency, and the specific frequency should be the specification frequency of the oscillator, that is, the product specification during manufacturing. Since the semiconductor manufacturing process will inevitably produce different errors in each chip, the actual frequency of the oscillator of each chip will have a large error. Therefore, the correction unit stores a frequency correction information, and adjusts the frequency of the grayscale clock signal output by the oscillator by outputting the frequency correction information to the oscillator, so that the frequency of the grayscale clock signal is within the target frequency range Inside.

一般來說，一LED顯示器包含複數顯示器驅動模組，各該驅動模組輸出的驅動訊號用於驅動至少一顯示單元。由於各該顯示器驅動模組輸出的驅動訊號係基於各該顯示器驅動模組中內建的該振盪器，而各該振盪器產生的灰階時脈訊號的上升緣及下降緣會分散在時間軸上的一段區間，因此即使各該顯示器驅動模組接收相同的驅動資訊，各該脈寬調變單元輸出的脈寬控制訊號具有相同的佔空比，各該脈寬控制訊號的上升緣及下降緣會根據各該灰階時脈訊號而有些微差異，各該驅動輸出單元輸出的驅動訊號的上升緣及下降緣因此也不會同步，進而使得各該驅動訊號的在切換時產生的高頻突波雜訊不會同時出現在電路板上，因此降低了顯示器電路板上的雜訊。Generally speaking, an LED display includes a plurality of display drive modules, and the drive signal output by each drive module is used to drive at least one display unit. Since the drive signal output by each display drive module is based on the built-in oscillator in each display drive module, the rising and falling edges of the gray-scale clock signal generated by each of the oscillators will be scattered on the time axis Therefore, even if each display driving module receives the same driving information, the pulse width control signal output by each pulse width modulation unit has the same duty cycle, and the rising edge and falling edge of each pulse width control signal The edge will be slightly different according to each gray-scale clock signal. Therefore, the rising and falling edges of the driving signal output by each driving output unit will not be synchronized, so that the high frequency of each driving signal generated during switching Surge noise does not appear on the circuit board at the same time, thus reducing the noise on the display circuit board.

更進一步來說，通過各該顯示器驅動模組的頻率校正資訊儲存各該各該振盪器的頻率校正資訊，控制各該振盪器的輸出的灰階時脈訊號頻率在該目標頻率範圍內而不相同，該目標頻率範圍例如是一目標頻率+/-2%的公差範圍內，使得各該顯示器驅動模組根據其灰階時脈訊號所產生的各該驅動訊號間的差異令人眼無法察覺，不影響使用者該顯示器的觀看；而另一方面來說，通過控制各該顯示器驅動模組的灰階時脈訊號不相同，各該灰階時脈訊號的頻率值分散在該目標頻率範圍內，各該驅動訊號在顯示驅動系統中的電路板上形成的EMI的頻譜會被分散，而不會完全單一的集中在該些特定頻率上，因此避免該顯示器電路板上的EMI頻譜在該些特定頻率的突波超出規範。Furthermore, the frequency correction information of each oscillator is stored by the frequency correction information of each display drive module, and the gray-scale clock signal frequency of each oscillator is controlled to be within the target frequency range. Similarly, the target frequency range is, for example, within a tolerance range of +/-2% of a target frequency, so that the difference between the driving signals generated by the display driving modules according to their gray-scale clock signals is unnoticeable. , Does not affect the user’s viewing of the display; on the other hand, by controlling the gray-scale clock signal of each display driving module to be different, the frequency value of each gray-scale clock signal is scattered in the target frequency range Inside, the EMI spectrum formed by each of the driving signals on the circuit board in the display driving system will be dispersed, instead of being completely concentrated on the specific frequencies, so it is avoided that the EMI spectrum on the display circuit board is in the Some specific frequency surges are out of specification.

因此，本創作還提供一種內建灰階時脈訊號的顯示器驅動電路，包含一電路模組、一第一驅動模組及一第二驅動模組，其中該第一驅動模組及該第二驅動模組分別設置於該電路模組上。該第一驅動模組具有一第一驅動資訊輸入端及一第一驅動訊號輸出端，分別電連接該電路模組的線路層。該第一驅動模組包含一第一校正單元、一第一振盪器、一第一脈寬調變單元及一第一驅動輸出單元。該第一振盪器產生一第一灰階時脈訊號，且該第一校正單元儲存有一第一頻率校正資訊並輸出該第一頻率校正資訊至該第一振盪器，使得該第一振盪器根據該第一頻率校正資訊產生的第一灰階時脈訊號在一目標頻率範圍內；該第一脈寬調變單元電連接該第一驅動資訊輸入端以接收一第一驅動資訊，並且電連接該第一振盪器以接收該第一灰階時脈訊號，該第一脈寬調變單元根據該第一驅動資訊及該第一灰階時脈訊號輸出一第一脈寬控制訊號，而該第一驅動輸出單元電連接該第一脈寬調變單元以接收該第一脈寬控制訊號，並且據以產生一第一驅動訊號，由該第一驅動訊號輸出端輸出。Therefore, the present invention also provides a display driving circuit with a built-in gray-scale clock signal, including a circuit module, a first driving module, and a second driving module, wherein the first driving module and the second driving module The driving modules are respectively arranged on the circuit module. The first driving module has a first driving information input terminal and a first driving signal output terminal, which are respectively electrically connected to the circuit layer of the circuit module. The first drive module includes a first correction unit, a first oscillator, a first pulse width modulation unit, and a first drive output unit. The first oscillator generates a first gray-scale clock signal, and the first correction unit stores a first frequency correction information and outputs the first frequency correction information to the first oscillator, so that the first oscillator is based on The first gray-scale clock signal generated by the first frequency correction information is within a target frequency range; the first pulse width modulation unit is electrically connected to the first driving information input terminal to receive a first driving information, and is electrically connected The first oscillator receives the first gray-scale clock signal, the first pulse width modulation unit outputs a first pulse-width control signal according to the first driving information and the first gray-scale clock signal, and the The first drive output unit is electrically connected to the first pulse width modulation unit to receive the first pulse width control signal, and accordingly generate a first drive signal, which is output by the first drive signal output terminal.

類似的，該第二驅動模組具有一第二驅動資訊輸入端及一第二驅動訊號輸出端，分別電連接該電路模組的線路層。該第二驅動模組包含一第二校正單元、一第二振盪器、一第二脈寬調變單元及一第二驅動輸出單元。該第二振盪器產生一第二灰階時脈訊號，且該第二校正單元儲存一第二頻率校正資訊並輸出該第二頻率校正資訊至該第二振盪器，使得該第二振盪器根據該第二頻率校正資訊產生的第二灰階時脈訊號在該目標頻率範圍內；該第二脈寬調變單元電連接該第二驅動資訊輸入端以接收一第二驅動資訊，並且電連接該第二振盪器以接收該第二灰階時脈訊號，該第二脈寬調變單元根據該第二驅動資訊及該第二灰階時脈訊號輸出一第二脈寬控制訊號，而該第二驅動輸出單元電連接該第二脈寬調變單元以接收該第二脈寬控制訊號，並且據以產生一第二驅動訊號，由該第二驅動訊號輸出端輸出。其中，該第一灰階時脈訊號及該第二灰階時脈訊號的頻率不相同。Similarly, the second driving module has a second driving information input terminal and a second driving signal output terminal, which are respectively electrically connected to the circuit layer of the circuit module. The second driving module includes a second calibration unit, a second oscillator, a second pulse width modulation unit, and a second driving output unit. The second oscillator generates a second gray-scale clock signal, and the second correction unit stores a second frequency correction information and outputs the second frequency correction information to the second oscillator, so that the second oscillator is based on The second gray-scale clock signal generated by the second frequency correction information is within the target frequency range; the second pulse width modulation unit is electrically connected to the second driving information input terminal to receive a second driving information, and is electrically connected The second oscillator receives the second gray-scale clock signal, the second pulse-width modulation unit outputs a second pulse-width control signal according to the second driving information and the second gray-scale clock signal, and the The second drive output unit is electrically connected to the second pulse width modulation unit to receive the second pulse width control signal, and accordingly generate a second drive signal, which is output by the second drive signal output terminal. Wherein, the frequencies of the first gray-scale clock signal and the second gray-scale clock signal are different.

該第一驅動模組包含該第一校正單元，其儲存的第一頻率校正資訊係針對該第一振盪器，並校正該第一振盪器的頻率在該目標頻率範圍內；該第二驅動模組包還該第二校正單元，其儲存的第二頻率校正資訊係針對該第二振盪器，並校正該第振盪器的頻率在該目標頻率範圍內。如此一來，該第一振盪器及該第二振盪器的頻分別會落在該目標頻率範圍內，例如是上述的一目標頻率+/-2%的公差範圍內。如此一來，由於該第一驅動模組輸出的該第一驅動訊號係根據該第一灰階時脈訊號產生上升緣及下降緣，該第二驅動模組輸出的第二驅動訊號係根據該第二灰階時脈訊號產生上升緣及下降緣，而該第一灰階時脈訊號及該第二灰階時脈訊號分別來自兩顆分開的振盪器，即使該第一振盪器及該第二振盪器的頻率都落在該目標頻率範圍內，該第一灰階時脈訊號及該第二灰階時脈訊號的每一個方波的上升緣及下降緣也不一定會在同一時間點發生，因此該第一驅動訊號的上升緣及下降緣亦不一定會與該第二驅動訊號的上升緣及下降緣同時發生，使得該第一驅動訊號或該第二驅動訊號的訊號上升緣處或下降緣處產生的高頻突波雜訊不會同時發生，該電路模組上不會同時出現高頻突波雜訊，降低該第一驅動訊號及該第二驅動訊號輸出至該電路模組上後該電路模組上的雜訊干擾。The first driving module includes the first calibration unit, and the stored first frequency calibration information is for the first oscillator, and the frequency of the first oscillator is corrected to be within the target frequency range; the second driving module The second calibration unit is also packaged, and the stored second frequency calibration information is for the second oscillator, and the frequency of the second oscillator is corrected to be within the target frequency range. In this way, the frequencies of the first oscillator and the second oscillator will fall within the target frequency range, for example, within a tolerance range of +/-2% of the aforementioned target frequency. In this way, since the first driving signal output by the first driving module generates rising and falling edges according to the first gray-scale clock signal, the second driving signal output by the second driving module is based on the The second gray-scale clock signal generates rising and falling edges, and the first gray-scale clock signal and the second gray-scale clock signal come from two separate oscillators, even though the first oscillator and the second The frequencies of the two oscillators fall within the target frequency range, and the rising and falling edges of each square wave of the first gray-scale clock signal and the second gray-scale clock signal may not necessarily be at the same time point. Occurs, so the rising edge and falling edge of the first driving signal may not necessarily occur at the same time as the rising edge and falling edge of the second driving signal, so that the signal rising edge of the first driving signal or the second driving signal Or the high-frequency surge noise generated at the falling edge will not occur at the same time, and high-frequency surge noise will not appear on the circuit module at the same time, reducing the output of the first driving signal and the second driving signal to the circuit module Noise interference on the circuit module after grouping.

此外，由於該第一灰階訊號及該第二灰階訊號分別雖然落在該目標頻率範圍內而相近，該第一灰階訊號及該第二灰階訊號的頻率並不相同，該第一驅動訊號及該第二驅動訊號的輸出週期也會因此不同，使得該電路模組上的EMI頻譜被打散，避免EMI在特定頻率超出規範。In addition, since the first gray-scale signal and the second gray-scale signal are close to each other within the target frequency range, the frequencies of the first gray-scale signal and the second gray-scale signal are not the same, and the first gray-scale signal The output period of the driving signal and the second driving signal will also be different, so that the EMI spectrum on the circuit module is broken up, and EMI is prevented from exceeding the specification at a specific frequency.

請參閱圖1所示，本創作提供一種顯示器驅動模組10，具有一驅動資訊輸入端I/P及一驅動訊號輸出端O/P，並且包含一校正單元11、一振盪器12、一脈寬調變單元13及一驅動輸出單元14，該校正單元11儲存一頻率校正資訊，該振盪器12電連接該校正單元11以接收該頻率校正資訊並據以產生一灰階時脈訊號，該灰階時脈訊號的頻率在一目標頻率範圍內；該脈寬調變單元13電連接該驅動資訊輸入端以接收一驅動資訊，並且電連接該振盪器12以接收該灰階時脈訊號，該脈寬調變單元13根據該驅動資訊及該灰階時脈訊號輸出一脈寬控制訊號，而該驅動輸出單元14電連接該脈寬調變單元13以接收該脈寬控制訊號，並且據以輸出一驅動訊號。該驅動訊號通過一電路模組輸出至一顯示單元(圖未示)，例如是一LED發光單元。較佳的，該校正單元包含一非揮發性記憶體(Non-Volatile Memory)。較佳的，該振盪器可以設計為輸出頻率對溫度與電壓的變化不敏感，即在不同溫度與電壓之下輸出頻率變化不大，因此對於輸出週期與刷新率的影響不大。較佳的，該驅動資訊包含至少一驅動輸出之資訊。Please refer to FIG. 1. The present invention provides a display drive module 10, which has a drive information input terminal I/P and a drive signal output terminal O/P, and includes a correction unit 11, an oscillator 12, and a pulse Wide modulation unit 13 and a drive output unit 14. The correction unit 11 stores frequency correction information. The oscillator 12 is electrically connected to the correction unit 11 to receive the frequency correction information and generate a gray-scale clock signal accordingly. The frequency of the gray-scale clock signal is within a target frequency range; the pulse width modulation unit 13 is electrically connected to the driving information input terminal to receive driving information, and is electrically connected to the oscillator 12 to receive the gray-scale clock signal, The pulse width modulation unit 13 outputs a pulse width control signal according to the drive information and the grayscale clock signal, and the drive output unit 14 is electrically connected to the pulse width modulation unit 13 to receive the pulse width control signal, and To output a driving signal. The driving signal is output to a display unit (not shown) through a circuit module, such as an LED light-emitting unit. Preferably, the calibration unit includes a non-volatile memory (Non-Volatile Memory). Preferably, the oscillator can be designed such that the output frequency is not sensitive to changes in temperature and voltage, that is, the output frequency does not change much under different temperatures and voltages, so it has little effect on the output cycle and refresh rate. Preferably, the drive information includes at least one drive output information.

請參閱圖2所示，本創作還提供一種顯示器驅動控制方法，係由該顯示器驅動模組10執行，包含以下步驟：存取一頻率校正資訊（S201）；根據該頻率校正資訊控制一振盪器產生一灰階時脈訊號，使該灰階時脈訊號的頻率在一目標頻率範圍內（S202）；接收一驅動資訊，根據該驅動資訊及該灰階時脈訊號產生一脈寬控制訊號（S203）；根據該脈寬控制訊號產生一驅動訊號（S204）。 Please refer to FIG. 2. This creation also provides a display drive control method, which is executed by the display drive module 10, and includes the following steps: Access a frequency calibration information (S201); Controlling an oscillator to generate a gray-scale clock signal according to the frequency correction information so that the frequency of the gray-scale clock signal is within a target frequency range (S202); Receiving a driving information, and generating a pulse width control signal according to the driving information and the gray-scale clock signal (S203); A driving signal is generated according to the pulse width control signal (S204).

請參閱圖3所示，本創作還提供一種顯示器驅動系統，包含一電路模組40、一第一驅動模組20及一第二驅動模組30，其中該第一驅動模組20及該第二驅動模組30分別設置於該電路模組40上。該第一驅動模組20具有一第一驅動資訊輸入端I/P1及一第一驅動訊號輸出端O/P1，分別電連接該電路模組40的一線路層。該第一驅動模組20包含一第一校正單元21、一第一振盪器22、一第一脈寬調變單元23及一第一驅動輸出單元24。該第一振盪器22產生一第一灰階時脈訊號，且該第一校正單元21儲存有一第一頻率校正資訊並輸出該第一頻率校正資訊至該第一振盪器22，使得該第一振盪器22根據該第一頻率校正資訊產生的第一灰階時脈訊號在一目標頻率範圍內；該第一脈寬調變單元23電連接該第一驅動資訊輸入端I/P1以接收一第一驅動資訊，並且電連接該第一振盪器22以接收該第一灰階時脈訊號，該第一脈寬調變單元23根據該第一驅動資訊及該第一灰階時脈訊號輸出一第一脈寬控制訊號，而該第一驅動輸出單元24電連接該第一脈寬調變單元23以接收該第一脈寬控制訊號，並且據以產生一第一驅動訊號由該第一驅動訊號輸出端輸出。類似的，該第二驅動模組30具有一第二驅動資訊輸入端I/P2及一第二驅動訊號輸出端O/P2，分別電連接該電路模組40的線路層。該第二驅動模組30包含一第二校正單元31、一第二振盪器32、一第二脈寬調變單元33及一第二驅動輸出單元34。該第二振盪器32產生一第二灰階時脈訊號，且該第二校正單元31儲存有一第二頻率校正資訊並輸出該第二頻率校正資訊至該第二振盪器32，使得該第二振盪器32根據該第二頻率校正資訊產生的第二灰階時脈訊號在該目標頻率範圍內；該第二脈寬調變單元33電連接該第二驅動資訊輸入端以接收一第二驅動資訊，並且電連接該第二振盪器32以接收該第二灰階時脈訊號，該第二脈寬調變單元33根據該第二驅動資訊及該第二灰階時脈訊號輸出一第二脈寬控制訊號，而該第二驅動輸出單元34電連接該第二脈寬調變單元33以接收該第二脈寬控制訊號，並且據以產生一第二驅動訊號由該第二驅動訊號輸出端輸出。其中，該第一灰階時脈訊號的頻率大於該第二灰階時脈訊號的頻率。Please refer to FIG. 3, this creation also provides a display driving system, including a circuit module 40, a first driving module 20, and a second driving module 30, wherein the first driving module 20 and the second driving module The two driving modules 30 are respectively arranged on the circuit module 40. The first driving module 20 has a first driving information input terminal I/P1 and a first driving signal output terminal O/P1, which are respectively electrically connected to a circuit layer of the circuit module 40. The first driving module 20 includes a first correction unit 21, a first oscillator 22, a first pulse width modulation unit 23 and a first driving output unit 24. The first oscillator 22 generates a first gray-scale clock signal, and the first correction unit 21 stores a first frequency correction information and outputs the first frequency correction information to the first oscillator 22 so that the first The first gray-scale clock signal generated by the oscillator 22 according to the first frequency correction information is within a target frequency range; the first pulse width modulation unit 23 is electrically connected to the first driving information input terminal I/P1 to receive a First driving information, and electrically connected to the first oscillator 22 to receive the first gray-scale clock signal, and the first pulse width modulation unit 23 outputs according to the first driving information and the first gray-scale clock signal A first pulse width control signal, and the first drive output unit 24 is electrically connected to the first pulse width modulation unit 23 to receive the first pulse width control signal, and accordingly generate a first drive signal from the first Drive signal output terminal output. Similarly, the second driving module 30 has a second driving information input terminal I/P2 and a second driving signal output terminal O/P2, which are respectively electrically connected to the circuit layer of the circuit module 40. The second driving module 30 includes a second calibration unit 31, a second oscillator 32, a second pulse width modulation unit 33 and a second driving output unit 34. The second oscillator 32 generates a second gray-scale clock signal, and the second correction unit 31 stores a second frequency correction information and outputs the second frequency correction information to the second oscillator 32 so that the second The second gray-scale clock signal generated by the oscillator 32 according to the second frequency correction information is within the target frequency range; the second pulse width modulation unit 33 is electrically connected to the second driving information input terminal to receive a second driving Information, and is electrically connected to the second oscillator 32 to receive the second gray-scale clock signal, and the second pulse width modulation unit 33 outputs a second signal according to the second driving information and the second gray-scale clock signal A pulse width control signal, and the second drive output unit 34 is electrically connected to the second pulse width modulation unit 33 to receive the second pulse width control signal, and accordingly generate a second drive signal to be output by the second drive signal端 output. Wherein, the frequency of the first gray-scale clock signal is greater than the frequency of the second gray-scale clock signal.

請參閱圖4所示，圖4係二個顯示器驅動模組10的灰階時脈訊號及輸出的驅動訊號的一波形示意圖，分別是該第一振盪器22產生的第一灰階時脈訊號clk1、該第一驅動輸出模組20輸出的第一驅動訊號Iout1、該第二振盪器32產生的第二灰階時脈訊號clk2，以及該第二驅動輸出模組30輸出的第二驅動訊號Iout2。在本較佳實施中，假設該第一驅動模組20及該第二驅動模組30的第一驅動訊號及該第二驅動訊號的一個輸出週期中包含6個灰階時脈訊號，也就是說，該第一脈寬控制訊號或該第二脈寬控制訊號的佔空比可能為0、16.66%、33%....83.33%或100%。且進一步假設該第一驅動模組20及該第二驅動模組30所接收到的驅動資訊相同，使得該第一脈寬控制訊號及第二脈寬控制訊號的佔空比均為50%，也就是該第一驅動訊號在一個輸出週期中應輸出週期長度為3個第一灰階時脈訊號週期的電流訊號，且該第二驅動訊號應輸出週期長度為3個第二灰階時脈訊號週期的電流訊號。此外，該第一脈寬控制訊號及該第二脈寬控制訊號分別用以控制該第一驅動輸出單元24的一輸出開關及該第二輸出驅動單元的一輸出開關，因此該第一驅動輸出單元24及該第二驅動輸出單元34輸出的驅動訊號理想波形分別與該第一脈寬控制訊號及該第二脈寬控制訊號相同，本圖省略該第一脈寬控制訊號及該第二脈寬控制訊號。Please refer to FIG. 4. FIG. 4 is a schematic diagram of a waveform of the gray-scale clock signal and the output driving signal of the two display driving modules 10, respectively, the first gray-scale clock signal generated by the first oscillator 22 clk1, the first drive signal Iout1 output by the first drive output module 20, the second gray-scale clock signal clk2 generated by the second oscillator 32, and the second drive signal output by the second drive output module 30 Iout2. In this preferred implementation, it is assumed that the first driving signal and the second driving signal of the first driving module 20 and the second driving module 30 include 6 gray-scale clock signals in one output cycle, that is, In other words, the duty cycle of the first pulse width control signal or the second pulse width control signal may be 0, 16.66%, 33%...83.33% or 100%. Furthermore, assuming that the driving information received by the first driving module 20 and the second driving module 30 are the same, so that the duty ratios of the first pulse width control signal and the second pulse width control signal are both 50%, That is, the first driving signal should output a current signal with a period length of 3 first gray-scale clock signal periods in one output period, and the second driving signal should output a current signal with a period length of 3 second gray-scale clock signals. The current signal of the signal cycle. In addition, the first pulse width control signal and the second pulse width control signal are respectively used to control an output switch of the first drive output unit 24 and an output switch of the second output drive unit, so the first drive output The ideal waveforms of the drive signals output by the unit 24 and the second drive output unit 34 are the same as the first pulse width control signal and the second pulse width control signal, respectively. The first pulse width control signal and the second pulse width are omitted in this figure. Wide control signal.

在此必須說明的是，本說明書中為了方便說明而簡化脈寬控制訊號或驅動訊號的組成，實際上，根據該驅動資訊中關於個別一路驅動輸出的位元數N，該脈寬控制訊號會包含2^N個灰階。It must be noted here that the composition of the pulse width control signal or the drive signal is simplified for the convenience of explanation in this manual. In fact, according to the number of bits N of the individual drive output in the drive information, the pulse width control signal will Contains 2^N gray levels.

如圖4所示，由於該第一灰階時脈訊號clk1及該第二灰階時脈訊號clk分別由不同的振盪器，例如第一振盪器22及第二振盪器32，產生的，且該第一振盪器22及該第二振盪器32間並未進行同步。因此，即使在校正到相同的頻率的情況下，該第一灰階時脈訊號clk1及該第二灰階時脈訊號clk2的上升及下降的切換時間點並不會同步，會有一時間差。進一步而言，即使該第一驅動訊號Iout1及該第二驅動訊號Iout2的佔空比相同，均是輸出3個灰階時脈控制訊號週期，由於該第一驅動訊號Iout1及該第二驅動訊號Iout2分別根據該第一灰階時脈訊號clk1及該第二灰階時脈訊號的clk2的上升緣切換輸出電流訊號或關閉輸出電流訊號，該第一驅動訊號Iout1及該第二驅動訊號Iout2的訊號上升緣及下降緣在時間軸上也會錯開，使得在該第一驅動訊號Iout1及該第二驅動訊號Iout2的訊號上升緣處或下降緣處產生的高頻突波雜訊不會同時發生，進而使得在該電路模組40上不會同時出現高頻突波雜訊，因此降低該電路模組40及整體顯示器驅動系統上的雜訊干擾。As shown in FIG. 4, because the first gray-scale clock signal clk1 and the second gray-scale clock signal clk are respectively generated by different oscillators, such as the first oscillator 22 and the second oscillator 32, and The first oscillator 22 and the second oscillator 32 are not synchronized. Therefore, even when the frequency is calibrated to the same frequency, the switching time points of the rising and falling of the first gray-scale clock signal clk1 and the second gray-scale clock signal clk2 will not be synchronized, and there will be a time difference. Furthermore, even if the duty ratios of the first driving signal Iout1 and the second driving signal Iout2 are the same, they both output 3 gray-scale clock control signal periods, because the first driving signal Iout1 and the second driving signal Iout1 Iout2 switches the output current signal or turns off the output current signal according to the rising edge of the first gray-scale clock signal clk1 and the second gray-scale clock signal clk2. The first drive signal Iout1 and the second drive signal Iout2 are The rising and falling edges of the signal are also staggered on the time axis, so that the high-frequency surge noise generated at the rising or falling edges of the first driving signal Iout1 and the second driving signal Iout2 will not occur at the same time Therefore, high-frequency surge noise does not appear on the circuit module 40 at the same time, thereby reducing noise interference on the circuit module 40 and the overall display driving system.

在本創作的一第一較佳實施例中，該脈寬調變單元13接收一第一起始指令或一第二起始指令。該脈寬調變單元13在接收到該驅動資訊後，當進一步接收該第一起始指令，才根據該驅動資訊及該灰階時脈訊號產生一第一數量個輸出週期的脈寬控制訊號，並且暫停輸出，等待該第二起始指令；當接收到該第二起始指令後，該脈寬調變單元13才根據該驅動資訊及該灰階時脈訊號繼續產生一第一數量個輸出週期的脈寬控制訊號。In a first preferred embodiment of the present invention, the pulse width modulation unit 13 receives a first start command or a second start command. After receiving the driving information, the pulse width modulation unit 13 further receives the first start command, and then generates a pulse width control signal of the first number of output cycles according to the driving information and the gray-scale clock signal. And pause output, waiting for the second start instruction; after receiving the second start instruction, the pulse width modulation unit 13 continues to generate a first number of outputs according to the drive information and the gray-scale clock signal Periodic pulse width control signal.

請參閱圖5所示，也就是說，該驅動電路控制方法中，在根據該驅動資訊及該灰階時脈訊號產生一脈寬控制訊號的步驟中（S203），係進一步包括下步驟：接收一第一起始指令（S501）；根據該驅動資訊及該灰階時脈訊號產生並輸出一第一數量個輸出週期的脈寬控制訊號（S502）；等待一第二起始指令（S503）；當接收到該第二起始指令，根據該驅動資訊及該灰階時脈訊號產生該第一數量個輸出週期的脈寬控制訊號（S504）。 Please refer to FIG. 5, that is, in the driving circuit control method, in the step of generating a pulse width control signal according to the driving information and the gray-scale clock signal (S203), the step further includes the following steps: Receive a first start instruction (S501); Generate and output a pulse width control signal of the first number of output cycles according to the driving information and the gray-scale clock signal (S502); Waiting for a second start instruction (S503); When the second start command is received, a pulse width control signal of the first number of output cycles is generated according to the driving information and the gray-scale clock signal (S504).

在本創作中，由於各該驅動模組的振盪器12輸出的灰階時脈訊號的頻率係有差異，因此，各該顯示器驅動模組的脈寬調變單元13係根據起始指令輸出該脈寬控制訊號，而且是一次輸出固定數量個輸出週期的脈寬控制訊號後暫停輸出，並在接收到下一個起始指令時，再開始輸出下一組固定數量個輸出週期的脈寬控制訊號。也就是說，灰階時脈訊號較快的顯示器驅動模組的脈寬調變單元在輸出第一數量個輸出週期的脈寬控制訊號及驅動訊號後，會等待灰階時脈訊號頻率較慢的顯示器驅動模組的脈寬調變單元輸出完第一數量個輸出週期的脈寬控制訊號及驅動訊號，再共同根據該起始指令開始輸出下一個輸出週期的脈寬控制訊號及驅動訊號。In this creation, because the frequency of the gray-scale clock signal output by the oscillator 12 of each drive module is different, the pulse width modulation unit 13 of each display drive module outputs the Pulse width control signal, and after outputting a fixed number of output cycles of pulse width control signal at a time, the output will be suspended, and when the next start command is received, it will start to output the next set of fixed number of output cycles of pulse width control signal . In other words, the pulse width modulation unit of the display driving module with a faster gray-scale clock signal will wait for a slower gray-scale clock signal frequency after outputting the pulse width control signal and driving signal for the first number of output cycles After the pulse width modulation unit of the display driving module of the display unit has outputted the pulse width control signal and driving signal of the first number of output cycles, and then jointly starts outputting the pulse width control signal and driving signal of the next output cycle according to the initial command.

由於各該顯示器驅動模組的振盪器產生的灰階時脈訊號頻率不同，因此各該脈寬調變單元的一個輸出週期的脈寬控制訊號的時間長度也會不同，此控制方法即能夠避免灰階時脈訊號頻率較快的顯示器驅動模組在驅動資訊未更新前經重複輸出後，因總輸出週期不是整數，其總輸出佔空比會較灰階時脈訊號頻率較慢的顯示器驅動模組的總輸出量有明顯差異，導致部份顯示單元亮度不一的問題。Since the frequency of the gray-scale clock signal generated by the oscillator of each display driving module is different, the time length of the pulse width control signal of one output cycle of each pulse width modulation unit will also be different. This control method can avoid Display driver modules with faster gray-scale clock signal frequencies are repeatedly output before the drive information is updated. Since the total output period is not an integer, the total output duty cycle will be slower than the gray-scale clock signal frequency. There is a significant difference in the total output of the modules, which leads to the problem of uneven brightness of some display units.

較佳的，該第一起始指令及該第二起始指令係一輸出更新指令，該輸出更新指令係由一驅動資訊時脈訊號(data clock)及一驅動資訊鎖存訊號(latch)組合產生。舉例來說，該顯示器驅動模組10電連接一控制單元，以接收該控制單元產生的驅動資訊時脈訊號及驅動資訊鎖存訊號。該控制單元通過輸出該驅動資訊時脈訊號及該驅動資訊鎖存訊號控制該顯示器驅動模組10更新至下一筆驅動資訊進行輸出，即產生該輸出更新指令。當該輸出更新指令產生時，該脈寬調變單元13才產生該第一數量個脈寬控制訊號並使得該驅動輸出單元14據以輸出驅動訊號。由於該驅動資訊時脈訊號及該驅動資訊鎖存訊號係由一控制單元統一產生並以並聯的方式同步輸入至各該顯示器驅動模組10，因此各該顯示器驅動模組10會同步接收該輸出更新指令，也就是該第一起始指令及該第二起始指令，而達到本較佳實施例避免灰階時脈訊號頻率較快的顯示器驅動模組重複輸出導致亮度不一的問題的效果。Preferably, the first start command and the second start command are an output update command, and the output update command is generated by a combination of a drive information clock signal (data clock) and a drive information latch signal (latch) . For example, the display driving module 10 is electrically connected to a control unit to receive the driving information clock signal and the driving information latch signal generated by the control unit. The control unit controls the display drive module 10 to update to the next drive information for output by outputting the drive information clock signal and the drive information latch signal, that is, generates the output update command. When the output update command is generated, the pulse width modulation unit 13 generates the first number of pulse width control signals and causes the drive output unit 14 to output drive signals accordingly. Since the driving information clock signal and the driving information latch signal are uniformly generated by a control unit and are synchronously input to each of the display driving modules 10 in parallel, each of the display driving modules 10 will synchronously receive the output The update command, that is, the first start command and the second start command, achieves the effect of avoiding the problem of uneven brightness caused by repeated output of the display driving module with a faster gray-scale clock signal frequency in this preferred embodiment.

也就是說，再請參閱圖3所示，在本較佳實施例的該顯示器驅動系統中，進一步包含一控制單元41，該控制單元41產生該驅動資訊時脈訊號及該驅動資訊鎖存訊號。該第一驅動模組20及該第二驅動模組30分別通過該電路模組40電連接該控制單元41，以接收該驅動資訊時脈訊號及驅動資訊鎖存訊號。該控制單元41通過產生該驅動資訊時脈訊號及該驅動資訊鎖存訊號控制該第一驅動模組20及該第二驅動模組30切換至下一筆驅動資訊進行輸出，即產生該輸出更新指令。由於該第一驅動模組20及該第二驅動模組30係並聯地接收該驅動資訊時脈訊號及該驅動資訊鎖存訊號，該第一驅動模組20及該第二驅動模組30會同步地接收該輸出更新指令，也就是該第一起始指令訊號或該第二起始指令訊號。In other words, please refer to FIG. 3 again. In the display driving system of the preferred embodiment, the display driving system further includes a control unit 41 that generates the driving information clock signal and the driving information latch signal . The first driving module 20 and the second driving module 30 are respectively electrically connected to the control unit 41 through the circuit module 40 to receive the driving information clock signal and the driving information latch signal. The control unit 41 controls the first drive module 20 and the second drive module 30 to switch to the next drive information for output by generating the drive information clock signal and the drive information latch signal, that is, generates the output update command . Since the first drive module 20 and the second drive module 30 receive the drive information clock signal and the drive information latch signal in parallel, the first drive module 20 and the second drive module 30 will Synchronously receive the output update command, that is, the first start command signal or the second start command signal.

請參閱圖6A所示，圖6A是本較佳實施例所述的控制方法的灰階時脈訊號clk1、clk2、驅動訊號Iout1、Iout2及起始指令ctrl波形圖。在本實施例中，設定該第一數量為1，也就是一次輸出一個輸出週期的脈寬控制訊號，以說明本控制方法達成之功效。當該第一數量為複數時，該控制模組、系統及控制方法也能達到相同之功效。由圖中可知，由於該第一灰階時脈訊號clk1的頻率大於該第二灰階時脈訊號clk2的頻率，該第一灰階時脈訊號clk1的週期小於該第二灰階時脈訊號clk2的的週期，在脈寬調變單元的一個輸出週期包含6個灰階時脈的實施例中，該第一驅動訊號Iout1的一個輸出週期T1會小於該第二驅動訊號Iout2的一個輸出週期T2。因此，根據本較佳實施例的控制方法，當該第一驅動訊號Iout1完成一個輸出週期的輸出後，係暫停輸出，並且等待該第二起始指令。Please refer to FIG. 6A. FIG. 6A is a waveform diagram of the gray-scale clock signals clk1, clk2, driving signals Iout1, Iout2, and the initial command ctrl of the control method according to the preferred embodiment. In this embodiment, the first number is set to 1, that is, a pulse width control signal of one output period is output at a time to illustrate the effect achieved by the control method. When the first number is plural, the control module, system and control method can also achieve the same effect. As can be seen from the figure, since the frequency of the first gray-scale clock signal clk1 is greater than the frequency of the second gray-scale clock signal clk2, the period of the first gray-scale clock signal clk1 is smaller than the second gray-scale clock signal The cycle of clk2. In an embodiment where one output cycle of the pulse width modulation unit includes 6 gray-scale clocks, one output cycle T1 of the first driving signal Iout1 is smaller than one output cycle of the second driving signal Iout2 T2. Therefore, according to the control method of the preferred embodiment, when the first driving signal Iout1 completes the output of one output cycle, the output is suspended and the second start command is waited.

較佳的，該控制單元41係根據選用的振盪器的灰階時脈訊號的頻率規格下限，計算得到可能的最長輸出週期，並加上少許寬容時間，而產生該第一起始指令及該第二起始指令，確保每個顯示器驅動模組10都能完整的輸出完該第一數量個輸出週期，才切換至下一驅動資訊進行輸出。Preferably, the control unit 41 calculates the longest possible output period according to the lower limit of the frequency specification of the gray-scale clock signal of the selected oscillator, and adds a little tolerance time to generate the first start command and the first The two initial commands ensure that each display driving module 10 can output the first number of output cycles completely before switching to the next driving information for output.

另外需要說明的是，由於多個振盪器間的製程受於現實狀況限制，因此會有製程上公差，導致各個振盪器的頻率並不會完全一致，即使校正之後，仍會有少許可控的誤差。故本創作通過設置多個不同的振盪器，並利用多個振盪器的製程上公差導致的頻率差異，使得不同振盪器產生的灰階時脈訊號之間具有相位差及頻率差異，進而降低EMI及開關時的突波雜訊。In addition, it should be noted that because the manufacturing process between multiple oscillators is limited by the actual conditions, there will be process tolerances, resulting in that the frequency of each oscillator will not be completely consistent. Even after calibration, there will still be a little controllable error. Therefore, this creation uses multiple different oscillators and uses the frequency differences caused by the tolerances of the multiple oscillators to make the gray-scale clock signals generated by different oscillators have phase differences and frequency differences, thereby reducing EMI And the surge noise when switching.

此外，本較佳實施例的方法雖會使得各該顯示器驅動模組在前後二個起始指令之間的輸出週期數量一致，也就是該第一脈寬調變單元23會在接收到該第一起始指令並輸出第一數量個輸出週期的第一脈寬控制訊號後，仍然必須等待接收到該第二起始指令時，才輸出下一第一數量個輸出週期的第一脈寬控制訊號。同理，該第二脈寬調變單元33會在接收到該第一起始指令並輸出第一數量個輸出週期的第二脈寬控制訊號後，仍然必須等待接收到該第二起始指令時，才輸出下一第一數量個輸出週期的第二脈寬控制訊號。但由於不同振盪器產生的灰階時脈訊號之間具有相位差及頻率差異，因此，如圖6B所示，該第一驅動模組20輸出的第一驅動訊號Iout1與該第二動模組30的第二驅動訊號Iout2上並不會同步切換，即起始時間與結束時間都不會同步，因此能夠達到本創作中各該驅動模組輸出的驅動訊號不同步切換而降低電路模組40上的雜訊的主要功效。In addition, although the method of the preferred embodiment makes the number of output cycles of each display driving module between the two initial commands before and after the same, that is, the first pulse width modulation unit 23 will receive the first pulse width modulation unit 23 After a start command and output the first pulse width control signal of the first number of output cycles, the first pulse width control signal of the next first number of output cycles must be waited until the second start command is received. . Similarly, the second pulse width modulation unit 33 will still have to wait for the second start command after receiving the first start command and output the second pulse width control signal for the first number of output cycles. , The second pulse width control signal of the next first number of output cycles is output. However, due to the phase difference and frequency difference between the gray-scale clock signals generated by different oscillators, as shown in FIG. 6B, the first driving signal Iout1 output by the first driving module 20 and the second driving module 20 The second drive signal Iout2 of 30 does not switch synchronously, that is, neither the start time nor the end time are synchronized. Therefore, it is possible to achieve the asynchronous switching of the drive signals output by the drive modules in this creation and reduce the circuit module 40. The main effect of the noise on.

在本創作的另一較佳實施例中，該脈寬調變單元係以平均分散或隨機分散方式輸出每一輸出週期中的脈寬控制訊號。也就是說，每一輸出週期中的脈寬控制訊號並非以單一方波形式輸出，而是在每一輸出週期中輸出複數個子方波，該些子方波的時間長度總和符合該驅動資訊。該脈寬調變單元可以均等時間間隔方式輸出子方波，或以隨機分散方式輸出該些子方波，使得該脈寬控制訊號平均輸出於各該輸出週期中。如此一來，該脈寬調變單元將每一輸出週期打散，則在任何一輸出週期期間內的時間點中止輸出，也不會顯著影響實際之輸出佔空比，使得顯示單元的實際亮度更加平均且準確。本實施例的脈寬控制訊號輸出方式適合隨時打斷輸出週期，無須計算固定輸出週期後停止輸出，再根據起始指令更新資料。In another preferred embodiment of the present invention, the pulse width modulation unit outputs the pulse width control signal in each output cycle in an evenly dispersed or randomly dispersed manner. That is, the pulse width control signal in each output cycle is not output in the form of a single square wave, but a plurality of sub-square waves are output in each output period, and the sum of the time lengths of the sub-square waves conforms to the driving information. The pulse width modulation unit can output the sub-square waves in an even time interval manner, or output the sub-square waves in a random dispersion manner, so that the pulse width control signal is output on average in each output cycle. In this way, the pulse width modulation unit breaks up each output cycle, and the output is stopped at any point during the output cycle, and the actual output duty cycle is not significantly affected, so that the actual brightness of the display unit More average and accurate. The pulse width control signal output method of this embodiment is suitable for interrupting the output cycle at any time, and it is not necessary to calculate a fixed output cycle and then stop the output, and then update the data according to the initial command.

在本創作的另一較佳實施例中，該顯示器驅動模組10的校正單元11進一步儲存一電流調整資訊，該電流調整資訊係根據該灰階時脈訊號的頻率與一目標頻率的比值產生。該校正單元11將該電流調整資訊輸出至該驅動輸出單元14，使得該驅動輸出單元14根據該電流調整資訊控制該驅動訊號的電流值。In another preferred embodiment of the present invention, the calibration unit 11 of the display driving module 10 further stores a current adjustment information, which is generated based on the ratio of the frequency of the gray-scale clock signal to a target frequency . The correction unit 11 outputs the current adjustment information to the drive output unit 14, so that the drive output unit 14 controls the current value of the drive signal according to the current adjustment information.

請參閱圖7所示，在本較佳實施例中，該顯示器驅動模組係進一步執行以下子步驟：存取一電流調整資訊（S701）；根據該電流調整資訊控制該驅動訊號的電流值（S702）；其中，該電流調整資訊係根據該灰階時脈訊號的頻率與一目標頻率的比值產生。 Please refer to FIG. 7. In this preferred embodiment, the display driving module further executes the following sub-steps: Access a current adjustment information (S701); Control the current value of the driving signal according to the current adjustment information (S702); wherein, The current adjustment information is generated according to the ratio of the frequency of the gray-scale clock signal to a target frequency.

該電流調整資訊用以調整該驅動訊號的電流值，以使得該驅動訊號在每一輸出週期中的總輸出量達到該筆驅動資訊指定的輸出量。舉例來說，假設該第二灰階時脈訊號clk2的頻率為該目標頻率，而該第一灰階時脈訊號clk1的頻率根據該第一頻率校正資訊的校正係該目標頻率的102%。如此一來，在佔空比皆為50%的第一驅動資訊及第二驅動資訊下，該第一驅動輸出單元24在一個輸出週期中輸出3個第一灰階時脈訊號clk2週期的電流訊號，而該第二驅動輸出單元34在一個輸出週期中輸出3個第二灰階時脈訊號clk2週期的電流訊號。那麼在同樣輸出一個輸出週期後，根據其灰階時脈訊號的脈寬乘以電流值可得總輸出量，該第一驅動輸出單24的實際輸出量只有該第二驅動輸出單元34的實際輸出量的98%，而導致些微的總輸出量差異。The current adjustment information is used to adjust the current value of the driving signal so that the total output of the driving signal in each output cycle reaches the output specified by the driving information. For example, suppose that the frequency of the second gray-scale clock signal clk2 is the target frequency, and the frequency of the first gray-scale clock signal clk1 is corrected according to the first frequency correction information to be 102% of the target frequency. In this way, under the first driving information and the second driving information with a duty ratio of 50%, the first driving output unit 24 outputs three currents of the first gray-scale clock signal clk2 period in one output period. The second drive output unit 34 outputs three second gray-scale clock signals clk2 cycles of current signals in one output cycle. Then after the same output cycle, the total output can be obtained by multiplying the pulse width of the gray-scale clock signal by the current value. The actual output of the first drive output unit 24 is only that of the second drive output unit 34. 98% of the output, resulting in a slight difference in total output.

因此，請參閱圖8所示，在本較佳實施中，根據該電流調整資訊，該第一驅動輸出單元24調整該第一驅動訊號Iout1的電流值，使得該第一驅動訊號Iout1的電流訊號的電流值為該第二驅動訊號Iout2的電流訊號的電流值的102%，如此一來，使得該第一驅動訊號Iout1及該第二驅動訊號Iout2在該輸出週期中的總輸出量相等。也就是說，通過該電流調整資訊，使得該第一驅動訊號的脈寬(tw1)與該第一驅動訊號的脈高(H1)的乘積相等於該第二驅動訊號的脈寬(tw2)與該第二驅動訊號的脈高(H2)的乘積，進一步使得該第一驅動訊號Iout1及該第二驅動訊號Iout2在根據第一起始指令及第二起始指令輸出的相同數量的輸出週期中，總輸出量一致，確保顯示器的每一顯示單元對於人眼觀看的亮度精準的一致。Therefore, please refer to FIG. 8. In this preferred embodiment, according to the current adjustment information, the first drive output unit 24 adjusts the current value of the first drive signal Iout1 so that the current signal of the first drive signal Iout1 The current value of is 102% of the current value of the current signal of the second driving signal Iout2, so that the total output of the first driving signal Iout1 and the second driving signal Iout2 in the output period is equal. That is, through the current adjustment information, the product of the pulse width (tw1) of the first driving signal and the pulse height (H1) of the first driving signal is equal to the pulse width (tw2) of the second driving signal and The product of the pulse height (H2) of the second driving signal further makes the first driving signal Iout1 and the second driving signal Iout2 in the same number of output cycles output according to the first start command and the second start command, The total output is consistent to ensure that each display unit of the display is accurately consistent with the brightness of the human eye.

綜上所述，通過本創作第一較佳實施例的驅動模組控制方法，使得各該驅動模組10輸出完一筆驅動資訊，或第一數量個輸出週期的驅動訊號後暫停輸出，再統一開始輸出下一筆驅動資訊，避免灰階時脈頻率較快的驅動模組重複輸出導致亮度不一；進一步的，根據儲存於各該驅動模組10的校正資料儲存單元11中的電流調整資訊，調整各該驅動輸出單元14的驅動訊號的電流值，使得各該驅動模組10在已調整相同的第一數量個輸出週期中，達到與目標輸出量完全一致的總輸出量。To sum up, through the drive module control method of the first preferred embodiment of the present creation, each drive module 10 outputs a single drive information, or the output of the drive signal for the first number of output cycles is suspended, and then unified Start to output the next drive information to avoid repeated output of the drive module with a faster gray-scale clock frequency to cause uneven brightness; further, according to the current adjustment information stored in the calibration data storage unit 11 of each drive module 10, The current value of the drive signal of each drive output unit 14 is adjusted, so that each drive module 10 achieves a total output that is completely consistent with the target output during the first number of output cycles that have been adjusted the same.

由以上敘述可知，本創作不僅藉由在驅動模組10中內建的振盪器15提高驅動模組10接收的的灰階時脈訊號，產生個別切換的灰階時脈訊號，降低顯示驅動系統中電路板上的雜訊，也藉由該校正資料儲存單元11校正各該振盪器產生的灰階時脈訊號使其頻率在目標頻率範圍內，分散電路板上的EMI頻譜避免超出產品規範；還進一步通過控制各該驅動模組10的脈寬調變單元15達到相同第一數量個輸出週期，並且通過調整各該驅動輸出單元14的驅動訊號的電流值，達到精準一致的總輸出量。It can be seen from the above description that this creation not only uses the built-in oscillator 15 in the drive module 10 to increase the gray-scale clock signal received by the drive module 10, but also generates individually switched gray-scale clock signals to reduce the display drive system. The noise on the intermediate circuit board is also corrected by the calibration data storage unit 11 to correct the gray-scale clock signal generated by each oscillator to make its frequency within the target frequency range, and the EMI spectrum on the dispersion circuit board avoids exceeding product specifications; Furthermore, the pulse width modulation unit 15 of each driving module 10 is controlled to achieve the same first number of output cycles, and the current value of the driving signal of each driving output unit 14 is adjusted to achieve a precise and consistent total output.

請參閱圖9所示，在本創作的一第三較佳實施例中，該顯示器驅動模組10進一步包含一倍頻單元15，該脈寬調變單元13係通過該倍頻單元15電連接該振盪器12，而該倍頻單元15接收該灰階時脈訊號，產生一倍頻灰階訊號，並輸出該倍頻灰階脈訊號至該脈寬調變單元13。較佳的，該倍頻單元係一鎖相環(Phase Lock Loop; PLL)電路單元。Please refer to FIG. 9, in a third preferred embodiment of the present invention, the display driving module 10 further includes a frequency multiplication unit 15, and the pulse width modulation unit 13 is electrically connected through the frequency multiplication unit 15. The oscillator 12 and the frequency multiplier unit 15 receive the gray-scale clock signal, generate a multiplied gray-scale signal, and output the multiplied gray-scale signal to the pulse width modulation unit 13. Preferably, the frequency multiplication unit is a phase locked loop (PLL) circuit unit.

通過該倍頻單元15對該振盪器12產生的灰階時脈訊號進行倍頻，產生一數倍於該灰階時脈訊號的倍頻灰階時脈訊號，進一步提高該脈寬調變單元13接收的時脈訊號頻率，因此能進一步提高該驅動模組的灰階或刷新率。The frequency multiplication unit 15 multiplies the frequency of the gray-scale clock signal generated by the oscillator 12 to generate a frequency-multiplied gray-scale clock signal that is several times the gray-scale clock signal, thereby further improving the pulse width modulation unit 13 The received clock signal frequency can therefore further improve the gray scale or refresh rate of the drive module.

以上所述僅是本創作的較佳實施例而已，並非對本創作做任何形式上的限制，雖然本創作已以較佳實施例揭露如上，然而並非用以限定本創作，任何熟悉本專業的技術人員，在不脫離本創作技術方案的範圍內，當可利用上述揭示的技術內容做出些許更動或修飾為等同變化的等效實施例，但凡是未脫離本創作技術方案的內容，依據本創作的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾，均仍屬於本創作技術方案的範圍內。The above is only the preferred embodiment of this creation, and does not limit this creation in any form. Although this creation has been disclosed as above in preferred embodiments, it is not intended to limit this creation. Anyone familiar with the professional technology Personnel, without departing from the scope of this creative technical solution, when the technical content disclosed above can be used to make some changes or modification into equivalent embodiments with equivalent changes, but any content that does not deviate from this creative technical solution is based on this creation Any simple modifications, equivalent changes and modifications made to the above embodiments of the technical essence of the above still fall within the scope of the technical solution of this creation.

10:顯示器驅動模組10: Display driver module

11:校正單元11: Correction unit

12:振盪器12: Oscillator

13:脈寬調變單元13: Pulse width modulation unit

14:驅動輸出單元14: Drive output unit

15:倍頻單元15: Frequency multiplier unit

I/P:驅動資訊輸入端I/P: Drive information input terminal

O/P:驅動訊號輸出端O/P: drive signal output terminal

20:第一顯示器驅動模組20: The first display driver module

21:第一校正單元21: The first correction unit

22:第一振盪器22: The first oscillator

23:第一脈寬調變單元23: The first pulse width modulation unit

24:第一驅動輸出單元24: The first drive output unit

I/P1:第一驅動資訊輸入端I/P1: The first drive information input terminal

O/P1:第一驅動訊號輸出端O/P1: The first drive signal output terminal

30:第二顯示器驅動模組30: The second display driver module

31:第二校正單元31: The second correction unit

32:第二振盪器32: second oscillator

33:第二脈寬調變單元33: The second pulse width modulation unit

34:第二驅動輸出單元34: second drive output unit

I/P2:第二驅動資訊輸入端I/P2: The second drive information input terminal

O/P2:第二驅動訊號輸出端O/P2: The second drive signal output terminal

40:電路模組40: circuit module

41:控制單元41: control unit

90:驅動模組90: drive module

91:驅動輸出單元91: drive output unit

92:脈寬調變單元92: Pulse width modulation unit

data:驅動資訊輸入端data: drive information input terminal

gclk:灰階時脈訊號輸入端gclk: Grayscale clock signal input terminal

Iout:驅動訊號輸出端Iout: drive signal output terminal

圖1係本創作顯示器驅動模組的方塊示意圖。圖2係本創作顯示器驅動模組控制方法的流程圖。圖3係本創作顯示器驅動系統的方塊示意圖。圖4係本創作顯示器驅動模組的訊號波形示意圖。圖5係本創作顯示器驅動模組控制方法第一較佳實施例的流程圖。圖6A及6B係本創作顯示器驅動模組控制方法第一較佳實施例的訊號波形示意圖。圖7係本創作顯示器驅動模組控制方法第二較佳實施例的流程圖。圖8本創作顯示器驅動模組控制方法第二較佳實施例的訊號波形示意圖。圖9本創作顯示器驅動模組第三較佳實施例的方塊示意圖。圖10係現有技術的顯示器驅動模組方塊示意圖。圖11係另一現有技術的顯示器驅動模組方塊示意圖。 Figure 1 is a block diagram of the creative display drive module. Figure 2 is a flowchart of the control method of the creative display drive module. Figure 3 is a block diagram of the creative display drive system. Figure 4 is a schematic diagram of signal waveforms of the creative display drive module. FIG. 5 is a flowchart of the first preferred embodiment of the control method of the creative display driving module. 6A and 6B are schematic diagrams of signal waveforms in the first preferred embodiment of the control method of the creative display driving module. FIG. 7 is a flowchart of the second preferred embodiment of the control method of the creative display driving module. FIG. 8 is a schematic diagram of signal waveforms of the second preferred embodiment of the control method of the creative display driving module. FIG. 9 is a block diagram of the third preferred embodiment of the creative display driving module. FIG. 10 is a block diagram of a display driving module in the prior art. FIG. 11 is a block diagram of another prior art display driving module.

10:顯示器驅動模組 10: Display driver module

11:校正單元 11: Correction unit

12:振盪器 12: Oscillator

13:脈寬調變單元 13: Pulse width modulation unit

14:驅動輸出單元 14: Drive output unit

I/P:驅動資訊輸入端 I/P: Drive information input terminal

O/P:驅動訊號輸出端 O/P: drive signal output terminal

Claims

一種顯示器驅動模組，整合於一積體電路內，具有一驅動資訊輸入端及一驅動訊號輸出端，包含：一校正單元，儲存有一頻率校正資訊，一振盪器，產生一灰階時脈訊號，且該校正單元輸出該頻率校正資訊至該振盪器，使該振盪器產生的該灰階時脈訊號的頻率在一目標頻率範圍內；一脈寬調變單元，電連接該驅動資訊輸入端以接收一驅動資訊，且電連接該振盪器以接收該灰階時脈訊號，並根據該驅動資訊及該灰階時脈訊號輸出一脈寬控制訊號；一驅動輸出單元，電連接該脈寬調變控制單元以接收該脈寬控制訊號，據以產生一驅動訊號並由該驅動訊號輸出端輸出該驅動訊號。 A display driving module, integrated in an integrated circuit, having a driving information input terminal and a driving signal output terminal, comprising: a calibration unit storing a frequency calibration information, an oscillator, and generating a gray-scale clock signal , And the correction unit outputs the frequency correction information to the oscillator, so that the frequency of the gray-scale clock signal generated by the oscillator is within a target frequency range; a pulse width modulation unit is electrically connected to the drive information input terminal To receive a driving information, and electrically connect the oscillator to receive the gray-scale clock signal, and output a pulse width control signal according to the driving information and the gray-scale clock signal; a driving output unit is electrically connected to the pulse width The modulation control unit receives the pulse width control signal, generates a driving signal accordingly, and outputs the driving signal from the driving signal output terminal.

如請求項1所述的顯示器驅動模組，進一步包含：一倍頻單元，其中該脈寬調變單元係通過該倍頻單元電連接該振盪器；該倍頻單元接收該灰階時脈訊號，產生一倍頻灰階訊號，並輸出該倍頻灰階脈訊號至該脈寬調變單元。 The display driving module according to claim 1, further comprising: a frequency multiplication unit, wherein the pulse width modulation unit is electrically connected to the oscillator through the frequency multiplication unit; the frequency multiplication unit receives the gray-scale clock signal , Generate a double frequency gray scale signal, and output the double frequency gray scale pulse signal to the pulse width modulation unit.

如請求項1所述的顯示器驅動模組，其中，當該脈寬調變單元接收一第一起始指令，該脈寬調變單元根據該驅動資訊及該灰階時脈訊號產生第一數量個輸出週期的脈寬控制訊號，並且等待一第二起始指令；當該脈寬調變單元接收一第二起始指令，該脈寬調變單元才根據該驅動資訊及該灰階時脈訊號再產生第一數量個輸出週期的脈寬控制訊號。 The display driving module according to claim 1, wherein when the pulse width modulation unit receives a first start command, the pulse width modulation unit generates a first number of signals according to the driving information and the grayscale clock signal Output the periodic pulse width control signal and wait for a second initial command; when the pulse width modulation unit receives a second initial command, the pulse width modulation unit is based on the driving information and the gray-scale clock signal Then generate the pulse width control signal for the first number of output cycles.

如請求項1或2所述的顯示器驅動模組，其中，該脈寬調變單元係以平均分散方式或隨機分散方式輸出每一輸出週期中的脈寬控制訊號。 The display drive module according to claim 1 or 2, wherein: The pulse width modulation unit outputs the pulse width control signal in each output cycle in an evenly dispersed manner or a randomized manner.

如請求項1至3中任一項所述的顯示器驅動模組，其中，該校正單元進一步儲存一電流調整資訊；該驅動輸出單元接收該校正單元的該電流調整資訊，並根據該電流調整資訊調整該驅動訊號的電流值；其中，該電流調整資訊係根據該灰階時脈訊號的頻率與一目標頻率的比值產生。 The display drive module according to any one of claims 1 to 3, wherein the correction unit further stores a current adjustment information; the drive output unit receives the current adjustment information of the correction unit, and adjusts the information according to the current The current value of the driving signal is adjusted; wherein the current adjustment information is generated according to the ratio of the frequency of the gray-scale clock signal to a target frequency.

一種顯示器驅動模組控制方法，由一顯示器驅動模組執行，包含以下步驟：存取一頻率校正資訊；根據該頻率校正資訊控制一振盪器產生一灰階時脈訊號，使該灰階時脈訊號的頻率在一目標頻率範圍內；接收一驅動資訊，根據該驅動資訊及該灰階時脈訊號產生一脈寬控制訊號；根據該脈寬控制訊號產生一驅動訊號。 A display driving module control method, executed by a display driving module, includes the following steps: accessing frequency correction information; controlling an oscillator to generate a gray-scale clock signal according to the frequency-correcting information to make the gray-scale clock The frequency of the signal is within a target frequency range; receiving a driving information, generating a pulse width control signal according to the driving information and the gray-scale clock signal; generating a driving signal according to the pulse width control signal.

如請求項6所述之顯示器驅動模組控制方法，根據該驅動資訊及該灰階時脈訊號產生一脈寬控制訊號的步驟中，包含以下子步驟：接收一第一起始指令；根據該驅動資訊及該灰階時脈訊號產生並輸出一第一數量個輸出週期的脈寬控制訊號；等待一第二起始指令；當接收該第二起始指令，才根據該驅動資訊及該灰階時脈訊號再產生第一數量個輸出週期的脈寬控制訊號。 According to the display driving module control method of claim 6, the step of generating a pulse width control signal according to the driving information and the gray-scale clock signal includes the following sub-steps: receiving a first initial command; according to the driving Information and the gray-scale clock signal generate and output a pulse width control signal of the first number of output cycles; wait for a second start command; when the second start command is received, the drive information and the gray scale The clock signal generates a pulse width control signal for the first number of output cycles.

如請求項6所述之顯示器驅動模組控制方法，進一步包含以下步驟：存取一電流調整資訊；根據該電流調整資訊控制該驅動訊號的電流值；其中，該電流調整資訊係根據該灰階時脈訊號的頻率與一目標頻率的比值產生。 The display driving module control method of claim 6, further comprising the following steps: accessing a current adjustment information; controlling the current value of the driving signal according to the current adjustment information; wherein the current adjustment information is based on the gray scale The ratio of the frequency of the clock signal to a target frequency is generated.

一種顯示器驅動系統，包含：一電路模組；一第一驅動模組，設置於該電路模組上，具有一第一驅動資訊輸入端及一第一驅動訊號輸出端，包含：一第一振盪器，產生一第一灰階時脈訊號；一第一校正單元，儲存一第一頻率校正資訊，且輸出該第一頻率校正資訊至該第一振盪器，使該第一振盪器產生的第一灰階時脈訊號的頻率在一目標頻率範圍內；一第一脈寬調變單元，電連接該第一驅動資訊輸入端以接收一第一驅動資訊，且電連接該第一振盪器以接收該第一灰階時脈訊號，並據以輸出一第一脈寬控制訊號；一第一驅動輸出單元，電連接該第一脈寬調變單元以接收該第一脈寬控制訊號，並據以輸出一第一驅動訊號；一第二驅動模組，設置於該電路模組上，具有一第二驅動資訊輸入端及一第二驅動訊號輸出端，包含：一第二振盪器，產生一第二灰階時脈訊號；一第二校正單元，儲存一第二頻率校正資訊，且輸出該第二頻率校正資訊至該第二振盪器，使該第二振盪器產生的第二灰階時脈訊號的頻率在該目標頻率範圍內；一第二脈寬調變單元，電連接該第二驅動資訊輸入端以接收一第二驅動資訊，且電連接該第二振盪器以接收該第二灰階時脈訊號，並據以輸出一第二脈寬控制訊號；一第二驅動輸出單元，電連接該第二脈寬調變單元以接收該第二脈寬控制訊號，並據以輸出一第二驅動訊號；其中，該第一灰階時脈訊號的頻率大於該第二灰階時脈訊號的頻率。 A display driving system, comprising: a circuit module; a first driving module, arranged on the circuit module, having a first driving information input terminal and a first driving signal output terminal, including: a first oscillation A device for generating a first gray-scale clock signal; a first correction unit, storing a first frequency correction information, and outputting the first frequency correction information to the first oscillator, so that the first oscillator generated by the first The frequency of a gray-scale clock signal is within a target frequency range; a first pulse width modulation unit is electrically connected to the first driving information input terminal to receive first driving information, and is electrically connected to the first oscillator to Receiving the first gray-scale clock signal and outputting a first pulse width control signal accordingly; a first drive output unit electrically connected to the first pulse width modulation unit to receive the first pulse width control signal, and Accordingly, a first driving signal is output; a second driving module is disposed on the circuit module, having a second driving information input terminal and a second driving signal output terminal, including: a second oscillator, which generates A second gray-scale clock signal; a second correction unit, storing a second frequency correction information, and outputting the second frequency correction information to the second oscillator, so that the second oscillator generates a second gray level The frequency of the clock signal is within the target frequency range; A second pulse width modulation unit, electrically connected to the second driving information input terminal to receive a second driving information, and electrically connected to the second oscillator to receive the second gray-scale clock signal, and output a A second pulse width control signal; a second drive output unit electrically connected to the second pulse width modulation unit to receive the second pulse width control signal, and accordingly output a second drive signal; wherein the first gray The frequency of the second gray-scale clock signal is greater than the frequency of the second gray-scale clock signal.

如請求項9所述的顯示器驅動系統，其中，當該第一驅動模組及該第二驅動模組分別接收一第一起始指令，該第一脈寬調變單元根據該第一驅動資訊及該第一灰階時脈訊號產生並輸出一第一數量個輸出週期的第一脈寬控制訊號，且該第二脈寬調變單元根據該第二驅動資訊及該第二灰階時脈訊號產生並輸出該第一數量個輸出週期的第二脈寬控制訊號，並暫停輸出；當該第一驅動模組及該第二驅動模組分別接收一第二起始指令，該第一脈寬調變單元才根據該第一驅動資訊及該第一灰階時脈訊號再產生並輸出第一數量個輸出週期的第一脈寬控制訊號，且該第二脈寬調變單元才根據該第二驅動資訊及該第二灰階時脈訊號再產生並輸出該第一數量個輸出週期的第二脈寬控制訊號。 The display driving system according to claim 9, wherein when the first driving module and the second driving module respectively receive a first start command, the first pulse width modulation unit is based on the first driving information and The first gray-scale clock signal generates and outputs a first pulse width control signal of a first number of output cycles, and the second pulse-width modulation unit is based on the second driving information and the second gray-scale clock signal Generate and output the first number of output cycles of the second pulse width control signal, and pause the output; when the first drive module and the second drive module each receive a second start command, the first pulse width The modulation unit generates and outputs the first pulse width control signal of the first number of output cycles according to the first driving information and the first gray-scale clock signal, and the second pulse width modulation unit is based on the first pulse width control signal. The second driving information and the second gray-scale clock signal generate and output the second pulse width control signal of the first number of output cycles.

如請求項10所述的顯示器驅動系統，進一步包含：一控制單元，產生一驅動資訊時脈訊號及一驅動資訊鎖存訊號；其中，該第一驅動模組及該第二驅動模組分別電連接該控制單元，以接收該驅動資訊時脈訊號，及接收該驅動資訊鎖存訊號；該第一起始指令及該第二起始指令係根據該驅動資訊時脈訊號及一驅動資訊鎖存訊號組合產生。 The display driving system according to claim 10, further comprising: a control unit that generates a driving information clock signal and a driving information latch signal; wherein, the first driving module and the second driving module are separately electrically connected Connect the control unit to receive the drive information clock signal and receive the drive information latch signal; the first start instruction and the second start instruction are based on the drive information clock signal and a drive information latch signal Combination produces.