TWI702657B - 鰭狀場效電晶體裝置與其形成方法 - Google Patents

鰭狀場效電晶體裝置與其形成方法 Download PDF

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TWI702657B
TWI702657B TW105129953A TW105129953A TWI702657B TW I702657 B TWI702657 B TW I702657B TW 105129953 A TW105129953 A TW 105129953A TW 105129953 A TW105129953 A TW 105129953A TW I702657 B TWI702657 B TW I702657B
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TW201712763A (zh
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林育樟
盧永晏
陳豪育
聶俊峰
張惠政
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台灣積體電路製造股份有限公司
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Abstract

半導體裝置包括：基板；鰭狀結構；以及絕緣層形成於基板上並與鰭狀結構相鄰。半導體裝置包含第一閘極結構形成於至少鰭狀結構與隔離層上。半導體裝置包含具有應變材料的磊晶層，以提供應力至鰭狀結構的通道區。磊晶層具有第一區域與第二區域，第一區域具有第一摻雜劑的第一摻雜濃度，且第二區域具有第二摻雜劑的第二摻雜濃度。第一摻雜濃度大於第二摻雜濃度。磊晶層之掺雜方法為採用磷二聚體的離子佈植。

Description

鰭狀場效電晶體裝置與其形成方法
本揭露關於半導體積體電路，更特別關於具有鰭狀場效電晶體(FinFET)結構的半導體裝置與其製作製程。
為了更高的裝置密度、更高效能、與更低的成本，進入奈米技術製程節點的半導體產業面臨製造和設計的挑戰，導致三維設計如FinFET的發展。FinFET裝置屬於多閘極結構的類型，通常包括高高寬比的半導體鰭狀物，其具有半導體電晶體裝置的通道與源極/汲極區域形成其中。閘極形成於鰭狀物結構上方且沿著鰭狀物結構的側面形成(比如包覆)，可增加通道和源極/汲極區域的表面積，進而產生更快，更可靠、和更易控制的半導體電晶體裝置。舉例來說，FinFET裝置的源極/汲極區域中的應變材料，可採用摻雜磷的含矽磊晶層。
本揭露一實施例提供之鰭狀場效電晶體裝置的形成方法，包括：提供基板，其具有第一鰭狀結構與第二鰭狀結構；形成隔離層於基板上，且隔離層與第一鰭狀結構及第二鰭狀結構相鄰；形成第一閘極結構於至少部份第一鰭狀結構與隔離層上；形成第二閘極結構於至少部份第二鰭狀結構與隔離層上；磊晶成長形成第一應變材料，且第一應變材料提供應力至 第一鰭狀結構的通道區；磊晶成長第二應變材料，且第二應變材料提供應力至第二鰭狀結構的通道區；佈植磷二聚體摻質到第一應變材料其至少第一區域，使第一區域具有磷二聚體摻質的第一摻雜濃度，且第一摻雜濃度大於第一應變材料的第二區域中磷摻質的第二摻雜濃度；以及熱回火至少第一鰭狀結構與第一應變材料，並藉由熱回火使第一鰭狀結構的通道區比第二鰭狀結構的通道區具有更大的通道遷移率。
B-B':剖線
H:高度
T1、T2:厚度
W:寬度
100:FinFET裝置
110:基板110
120:鰭狀結構
120A:井區
120B:通道區
125:源極與汲極區
130:閘極介電層
140:閘極
150:隔離區
150a:第一隔離區
150b:第二隔離區
160:功函數調整層
304a:墊層
304b:遮罩層
306、1202:光阻層
310:溝槽
314:介電材料
317、319、323:上表面
320:閘極堆疊
322:較上部份
324:側壁
326:凹陷部份
328:側壁間隔物材料
330a、330b:應變材料
902:n型FinFET裝置
904:p型FinFET裝置
1204:離子佈植
1210:第一區域
1212:第二區域
1252:區域
1302:熱退火步驟
1402:CESL
1502:ILD層
1802:金屬閘極
1804:高k閘極介電物
第1圖係本揭露的某些實施例中，鰭狀場效應電晶體(FinFET)裝置的透視圖。
第2圖係本揭露某些實施例中，具有鰭狀結構之FinFET裝置其沿著閘極方向的剖視圖。
第3-11、12A-12C、13-19圖係本揭露某些實施例中，FinFET結構的製程其中間階段的剖視圖。
下述內容提供的不同實施例或實例可實施本發明的不同結構。特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本揭露之多種例子中可重複標號，但這些重複僅用以簡化與清楚說明，不代表不同實施例及/或設置之間具有相同標號之單元之間具有相同的對應關係。
此外，空間性的相對用語如「下方」、「其下」、 「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。此外，用語「由...形成」可解釋為「包含」或「由...組成」。
第1圖係本揭露一實施例中，具有鰭狀結構之FinFET(鰭狀場效應電晶體)裝置100的透視圖。第2圖係本揭露一實施例中，具有鰭狀結構之FinFET裝置100其沿著閘極方向的剖視圖。為了簡化說明，上述圖式省略了某些層狀物/結構。
除了其他結構之外，第1圖和第2圖中描述的FinFET裝置100包括基板110、鰭狀結構120、閘極介電層130、與閘極140。在此實施例中，基板110是矽基板。在其他實施例中，基板110可包含另一半導體元素如諸；半導體化合物如IV-IV族半導體化合物(例如SiC與SiGe)或III-V族半導體化合物(例如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP)；或上述之組合。在一實施例中，基板110是SOI(絕緣物上矽)基板的矽層。當採用SOI基板時，鰭狀結構120可自SOI基板的矽層或絕緣層凸起。在後者中，SOI基板的矽層用於形成鰭狀結構120。非晶基板(如非晶Si或非晶SiC)或絕緣材料(如氧化矽)亦可作為基板110。基板110可包含摻有適當雜質(如p-型或n-型導電性)的多種區域。
鰭狀結構120位於基板110上方。鰭狀結構120之組 成可與基板110之組成相同，且可自基板110連續地延伸。在此實施例中，鰭狀結構120之組成為矽。鰭狀結構120的矽層可為本質矽，或適當地摻雜n-型雜質或p-型雜質。
在第1圖中，一個鰭狀結構120位於基板110上方。在第2圖中，三個鰭狀結構120位於基板110上方。然而，鰭狀結構的數量不限於一個或三個，而可為兩個、四個、或更多。此外，一或多個虛置鰭狀結構可與鰭狀結構120的兩側接觸，以改善圖案化製程中的圖案保真度。在某些實施例中，鰭狀結構120的寬度W介於約5nm至約40nm之間。在這些實施例中，鰭狀結構120的寬度W可介於約7nm至約12nm之間。在某些實施例中，鰭狀結構120的高度H介於約10nm至約100nm之間。在其他實施例中，鰭狀結構120的高度H介於約50nm至約100nm之間。
在第2圖中，鰭狀結構120之間的間隔，及/或鰭狀結構120與位於基板110上的另一個元件之間的間隔，填有隔離絕緣層如隔離區150。上述隔離區150包含一或多層的絕緣材料。用於隔離區150的絕緣材料可包括一或多層的氧化矽、氮化矽、氮氧化矽(SiON)、SiOCN、摻雜氟的矽酸鹽玻璃(FSG)、或低k介電材料。
如第2圖所示，位於閘極140下方的鰭狀結構120其較下部份稱作井區120A，且鰭狀結構120的較上部份稱作通道區120B。在閘極140下方，井區120A埋置於隔離區150內，且通道區120B自隔離區150凸起。通道區120B的較下部份亦可埋置於隔離區150內，其深度介於約1nm至約5nm之間。
閘極介電層130覆蓋自隔離區150凸起的通道區120B，且閘極140覆蓋閘極介電層130。閘極140未覆蓋的部分通道區120B作為FinFET裝置100的源極/汲極(見第1圖)。
在這些實施例中，閘極介電層130包括單層或多層結構，其具有一或多種介電材料。舉例來說，閘極介電層130可為單層的氧化矽、氮化矽、高k介電材料、其他合適的介電材料、及/或上述之組合、或上述之多層結構。舉例來說，高k介電材料包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、氧化鈦、二氧化鉿-氧化鋁(HfO2-Al2O3)合金、其他合適的高k介電材料、及/或上述之組合。
閘極140包括諸如一或多層的任何合適材料如多晶矽、鋁、銅、鈦、鉭、鎢、鈷、鉬、氮化鉭、矽化鎳、矽化鈷、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金屬合金、其他合適材料、及/或上述之組合。閘極結構的形成方法可採用閘極後製或置換閘極等方法。
在本揭露的這些實施例中，一或多個功函數調整層160插置於閘極介電層130和閘極140之間。功函數調整層160可包括單層或多層結構，比如具有選擇的功函數以增強裝置效能之金屬層(功函數金屬層)、襯墊層、濕潤層、黏合層、金屬合金、或金屬矽化物的多種組合。功函數調整層160之組成可為一或多種導電材料，比如單層的Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W、Re、Ir、Co、Ni、其他合適的金屬材料、或上述多種材料的多層結構。在某些實施例中，功函數調整層160可包括用於n 型通道之FinFET的第一金屬材料，與用於p型通道之FinFET的第二金屬材料。舉例來說，用於n型通道之FinFET的第一金屬材料，其功函數實質上匹配基板導帶的功函數，或至少實質上匹配通道區120B之導帶的功函數。類似地，用於p型通道之FinFET的第二金屬材料，其功函數實質上匹配基板價帶的功函數，或至少實質上匹配通道區120B之價帶的功函數。在其他實施例中，功函數調整層160可包含多晶矽層。功函數調整層160之形成方法可為ALD、PVD、CVD、電子束蒸鍍、或其他合適製程。此外，可採用不同金屬層分別形成用於n型通道之FinFET與p型通道之FinFET的功函數調整層160。
在閘極140未覆蓋之鰭狀結構120的較上部份形成源極與汲極區125，其形成方法為適當地摻雜雜質於源極與汲極區125。Si或Ge與金屬如Co、Ni、W、Ti或Ta的合金可形成於源極與汲極區125上。在某些實施例中，源極與汲極區125中的應變材料可採用摻雜磷的含矽磊晶層。
離子佈植通常用於形成源極與汲極區125。舉例來說，N型源極/汲極製程包括提供室溫磷離子佈植，以形成摻雜磷的含矽磊晶層。在NMOS FinFET結構(n型源極/汲極區)中，離子佈植後形成的寄生電容不利地影響通道遷移率。一種方法是減少寄生電容，以相對高濃度(比如大於1×1021原子/cm3)的單原子磷進行磷離子佈植。雖然更高濃度的佈植可產生更高摻雜，但磷原子可能局部團簇(比如形成Si3P4化合物)並作為應力源，因此高濃度的離子佈植反而導致更低的摻質活化。為了克服更低的活化，另一個方法採用高溫退火以活化摻質，以解決 離子佈植引起的損傷。然而，用於熱退火的溫度升高，可能導致通道區120B中非預期的應變損失。
本揭露藉由相對較重的淺摻雜於摻雜磷的含矽磊晶層之上表面上，以減少接觸電容並增加NMOS FinFET結構的通道遷移率。特別的是，在磊晶成長步驟後採用磷二聚體(P2 +)離子佈植，在相同的佈植能量下比傳統的磷離子佈植更有效地結合更高的化學磷濃度，並引起更高的非晶程度。磷二聚體離子佈植可為全部或部份地冷佈植，其溫度低於約-20℃以促使更高的非晶程度(或更低的活化能)。
第3至19圖係本揭露某些實施例中，FinFET裝置300的製程其中間階段的剖視圖。值得注意的是，並非所有圖示的構件均為必要，且一或多個實施方式可包含未圖示的額外構件。在未脫離申請專利範圍之範疇的情況下，可改變構件的佈置與類型。另一方面，可採用額外製程、步驟、材料、或構件，不同的構件，或較少的構件。此外，可以改變操作順序。
第3圖係本揭露一實施例中，製程的多種階段之一中具有基板110的FinFET裝置300其剖視圖。在此實施例中，基板110包括晶體矽基板(如晶圓)。依據設計需求，可採用p型基板或n型基板，且基板110可包括多種摻雜區域。在某些實施例中，摻雜區域可以摻雜有p型或n型摻質。舉例來說，摻雜區域可摻雜p型摻質如硼或BF2、n型摻質如磷或砷、及/或上述之組合。摻雜區域可設置以用於n型FinFET或p型FinFET。
在某些其他實施例中，基板110之組成可為某些其他合適的半導體元素如鑽石或鍺；合適的半導體化合物如砷化 鎵、碳化矽、砷化銦、或磷化銦；或合適的半導體合金如碳化矽鍺、磷砷化鎵、或磷化鎵銦。在其他實施例中，基板可包含磊晶層。舉例來說，基板可具有磊晶層位於基體半導體上。此外，基板可為應變材料以增強效能。舉例來說，磊晶層之半導體材料可不同於與基體半導體的半導體材料，比如矽鍺層位於基體矽上，或矽層位於基體矽鍺上。上述應變的基板其形成方法可為選擇性磊晶成長(SEG)。此外，基板可包括SOI基板。在其他實施例中，基板可包括埋置介電層如埋置氧化物(BOX)層，其形成方法可為佈植氧隔離(SIMOX)、晶圓接合、SEG、或其他合適步驟。
在一實施例中，墊層304a和遮罩層304b形成於半導體的基板110上。舉例來說，墊層304a可為具有氧化矽的薄膜，其形成方法可為熱氧化步驟。墊層304a可作為半導體的基板110與遮罩層304b之間的黏合層。墊層304a亦可作為蝕刻遮罩層304b的蝕刻停止層。在至少一實施例中，遮罩層304b之組成為氮化矽，其形成方法可為低壓化學氣相沉積(LPCVD)或電漿增強化學氣相沉積(PECVD)。在後續的圖案化步驟中，遮罩層304b作為硬遮罩。光阻層306形成於遮罩層304b上，之後以光微影圖案化步驟使其圖案化，以形成開口於光阻層306中。在圖案化遮罩層304b與墊層304a後可去除光阻層，之後再進行溝槽蝕刻。
光微影圖案化步驟可包括光阻塗佈(如旋塗)、軟烘烤、對準光罩、曝光、曝光後烘烤、顯影光阻、清洗、乾燥(如硬烘烤)、其他合適步驟、或上述之組合。在其他實施例中，， 光微影圖案化製程可替換為其他合適方法如無光罩光微影、電子束寫入、直寫、及/或離子束寫入。光微影圖案化步驟形成的光阻圖案可作為圖案化遮罩層304b與墊層304a之遮罩。
第4圖係本揭露一實施例中，製程的多種階段之一中FinFET裝置300其剖視圖。蝕刻遮罩層304b和墊層304a以露出下方之半導體的基板110。之後以圖案化的遮罩層304b和墊層304a作為遮罩，蝕刻露出之半導體的基板110以形成溝槽310。
在溝槽蝕刻步驟中，蝕刻基板110的方法可為乾蝕刻、濕蝕刻、或乾蝕刻與濕蝕刻的組合。乾蝕刻步驟可以採用含氟氣體如CF4、SF6、CH2F2、CHF3、及/或C4F8，含氯氣體如Cl2、CHCl3、CCl4、及/或BCl3，含溴氣體如HBr及/或CHBr3，含氧氣體，含碘氣體，其他合適氣體及/或電漿，或上述之組合。
接著可進行濕式清潔步驟以移除半導體的基板110之原生氧化物。清潔步驟可採用稀釋的氫氟酸(DHF)。位於溝槽310之間的部份半導體之基板110，形成半導體的鰭狀結構120。半導體的鰭狀結構120可排列成彼此平行的行列(FinFET裝置300的頂部視角)，且彼此緊密相隔。每一鰭狀結構120具有寬度W和深度D，且與相鄰的鰭狀結構隔有寬度S的溝槽310與鄰近的鰭間隔開。舉例來說，某些實施例之半導體的鰭狀結構120其寬度W可介於約3nm至約30nm之間。
第5圖係本揭露一實施例中，製程的多種階段之一中FinFET裝置300其剖視圖。溝槽310填有一或多層的介電材料 314。介電材料314可包含氧化矽。在一或多個實施中，介電材料314之組成可為二氧化矽，其形成方法可為LPCVD(低壓化學氣相沉積)、電漿CVD、或可流動CVD。在可流動CVD中，沉積可流動介電材料而非氧化矽。顧名思義，可流動介電材料在沉積期間可以“流動”以填入具有高高寬比的間隙或間隔。一般添加多種化學品至含矽前驅物，使沉積的膜可流動。在某些實施例中，添加氮氫鍵。可流動的介電前驅物(特別是可流動氧化矽前驅物)可包括矽酸鹽、矽氧烷、甲基倍半矽氧烷(MSQ)、氫倍半矽氧烷(HSQ)、MSQ/HSQ、全氫矽氮烷(TCPS)、全氫-聚矽氮烷(PSZ)、四乙氧矽烷(TEOS)、或矽烷基胺(如三甲矽烷基胺(TSA))。這些可流動氧化矽材料之形成方法為多重步驟的製程。在沉積可流動膜之後，固化並退火可流動膜以去除不需要的元素，進而形成氧化矽。在去除不需要的元素時，可流動膜將緻密化並收縮。在某些實施例中，採用多重退火步驟。之後，固化和退火可流動膜。
在某些實施例中，可採用其他介電材料如氮化矽、氮氧化矽、摻雜氟的矽酸鹽玻璃(FSG)、或低k介電材料形成介電材料314。在一實施例中，採用矽烷(SiH4)和氧氣(O2)作為反應前驅物，搭配高密度電漿(HDP)CVD步驟形成介電材料314。在其他實施例中，可採用次大氣壓CVD(SACVD)步驟或高高寬比製程(HARP)形成介電材料314，其中製程氣體可包含四乙氧矽烷(TEOS)及/或臭氧(O3)。在又一其他實施例中，可採用旋塗介電物(SOD)製程形成的介電材料如氫倍半矽氧烷(HSQ)或甲基倍半矽氧烷(MSQ)作為介電材料314。在某些實施 例中，凹陷區域(或溝槽310)中可填有多層結構，比如熱氧化物墊層上填有氮化矽或氧化矽。
第6圖係本揭露一實施例中，製程的多種階段之一中FinFET裝置300其剖視圖。在沉積介電材料314後，接著進行化學機械拋光(CMP)及/或回蝕刻步驟，之後移除遮罩層304b和墊層304a。將介電材料314填入溝槽310後，可進行退火步驟。退火步驟可包含快速熱退火(RTA)、雷射退火步驟、或其他合適的退火步驟。
在至少一實施例中，遮罩層304b之組成為氮化矽，因此採用H3PO4的濕蝕刻步驟移除遮罩層304b。若墊層304a之組成為氧化矽，則可採用稀釋的HF酸移除墊層304a。溝槽310中殘留的部份介電材料314在下文中將稱為隔離區150。某些實施例在使隔離區150凹陷後，再移除遮罩層304b和墊層304a。上述凹陷步驟如第7圖所示。
第7圖係本揭露一實施例中，製程的多種階段之一中FinFET裝置300其剖視圖。進行蝕刻步驟，可蝕刻隔離區150以自隔離區150露出半導體的鰭狀結構120其較上部份322。蝕刻步驟可包含乾蝕刻步驟、濕蝕刻步驟、或乾蝕刻步驟與濕蝕刻步驟的組合，以移除部分的隔離區150。可以理解的是，蝕刻步驟可為單一蝕刻步驟或多重蝕刻步驟。
殘留的隔離區150包括上表面317。此外，半導體的鰭狀結構120其較上部份322突出於殘留的隔離區150其上表面317上，可作為FinFET裝置300的主動區(如通道區)。半導體的鰭狀結構120其較上部份222可包括上表面323與側壁324。自 隔離區150其上表面317起算之半導體的鰭狀結構120其較上部份322的高度H，可介於約6nm至約300nm之間。在某些實施例中，較上部份322的高度H大於300nm或小於6nm。為簡化說明，位於相鄰的隔離區150之間的半導體之鰭狀結構120其較上部份322，之後將稱作通道區以說明半導體的鰭狀結構120的每個較上部份，其中隔離區150其上表面317低於半導體的鰭狀結構120其上表面323。
第8圖係本揭露技術的一實施例中，製程的多種階段之一中n型FinFET裝置與p型FinFET裝置其剖視圖。閘極堆疊320形成於半導體的鰭狀結構120其上表面323與側壁324上，且延伸至第一隔離區150a和第二隔離區150b的上表面317。閘極堆疊320包括閘極介電層130，與位於閘極介電層130上的閘極140。
閘極介電層130覆蓋半導體的鰭狀結構120其至少部分通道區的上表面323和側壁324。在某些實施例中，閘極介電層130包括一或多層的氧化矽、氮化矽、氮氧化矽、或高k介電物。高k介電物可包括金屬氧化物如Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu的氧化物，及/或上述的混合物。閘極介電層130之形成方法可為合適步驟如原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、熱氧化、UV-臭氧氧化、或上述之組合。閘極介電層130還可進一步包含介面層(未圖示)以降低閘極介電層130和鰭狀結構120之間的損傷。介面層可包含氧化矽。
接著形成閘極140於閘極介電層130上。在至少一實施例中，閘極140覆蓋了多於一個半導體的鰭狀物120之較上部份322，使n型Fin FET裝置包括多個鰭狀結構。在某些其他實施例中，半導體的鰭狀物120的每個較上部份322均可用於形成分隔的n型Fin FET裝置。閘極140可包含單層或多層結構。閘極140可包括多晶矽。此外，閘極140可為均勻摻雜或非均勻摻雜的多晶矽。在某些其他實施例中，閘極140可包括金屬如Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlN、TaN、NiSi、CoSi、功函數與基板材料相容的其他導電材料、或上述之組合。閘極140的形成方法可為合適步驟如ALD、CVD、PVD、電鍍、或上述之組合。在某些實施例中，用於圖案化多晶矽層的硬遮罩層332係形成於閘極堆疊320上。
在第9至19圖中，顯示具有一或多個p型FinFET結構(如p型FinFET裝置904)與一或多個n型FinFET結構(如n型FinFET裝置902)的半導體裝置。在本揭露中，FinFET裝置300描述為n型Fin FET結構，但可依實施方式配置為另一類型的FinFET結構。為簡化說明，第9至19圖中的主題將以n型FinFET裝置902進行討論，並額外參考p型FinFET裝置904以說明製程的這些結構。
第9圖係本揭露技術的一實施例中，製程的多種階段之一中n型FinFET裝置902與p型FinFET裝置904其透視圖。在第9圖中，提供閘極結構以用於兩個鰭狀結構。在第9圖中，側壁間隔物材料328覆蓋n型Fin FET裝置902，其為沿著閘極堆疊320之垂直側的介電層。在某些實施例中，介電層包括一層或 多層的氧化矽、氮化矽、氮氧化矽、或其他合適材料。介電層可包括單層或多層結構。介電層的毯覆層之形成方法可為CVD、PVD、ALD、或其他合適技術。接著在介電層上進行向異性蝕刻及/或回蝕刻步驟，以形成一對側壁間隔物材料328於閘極堆疊320的兩側上。在形成閘極堆疊320的期間，可進行多種清潔/蝕刻步驟以蝕刻STI區(如第一絕緣區150a與第二絕緣區150b)。
第10圖係本揭露技術的一實施例中，製程的多種階段之一中n型FinFET裝置902與p型FinFET裝置904其透視圖。閘極堆疊320(第8圖)未覆蓋的部份半導體之鰭狀結構120，與形成其上的側壁間隔物材料328(第9圖)，將凹陷以形成半導體的鰭狀結構120之凹陷部份326。凹陷部份326之上表面319低於第一隔離區150a與第二隔離區150b之上表面317。在一實施例中，採用側壁間隔物材料328作為硬遮罩，進行偏置蝕刻步驟使未保護或露出的較上部份322的上表面319凹陷，以形成半導體的鰭狀結構120的凹陷部分326。在一實施例中，可採用HBr及/或Cl2作為蝕刻氣體以進行蝕刻步驟。
第11圖係本揭露技術的一實施例中，製程的多種階段之一中n型FinFET裝置902與p型FinFET裝置904其透視圖。藉由選擇性地成長應變材料(如應變材料330a、330b)於半導體的鰭狀結構120的凹陷部分326上，且並變材料延伸於第一隔離區150a與第二隔離區150b之上表面317上，即可形成第11圖所示的結構。由於應變材料330a與330b的晶格常數不同於半導體的鰭狀結構120之通道區，半導體的鰭狀結構120之通道區 將受到應力以增強裝置的載子遷移率與裝置效能。雖然第11圖中的應變材料330a與330b分別形成以對應每個鰭狀物，但是應變材料330a與330b可連接以形成共同的應變材料結構。
在至少一實施例中，可採用LPCVD步驟磊晶成長應變材料330a如碳化矽(SiC)及/或磷化矽(SiP)，以形成n-型FinFET裝置902的源極與汲極區。在至少一其他實施例中，可採用LPCVD步驟磊晶成長應變材料330b如矽鍺(SiGe)，以形成p型FinFET裝置904的源極與汲極區。
p型FinFET裝置904與n型FinFET裝置902係分別形成。在這方面，可以使用光微影與蝕刻步驟定義n型磊晶區或p型磊晶區。以第10與11圖為例，在形成p型FinFET裝置904的凹陷與源極/汲極時，以氮化矽(SiN)層覆蓋並保護n型FinFET裝置902。在形成用於p型FinFET裝置904的應變材料之後，以SiN層覆蓋保護p型FinFET裝置904，之後在n型FinFET裝置902上進行形成凹陷與應變材料的類似步驟。
第11圖係本揭露一實施例中，製程的多種階段之一中n型FinFET裝置902與p型FinFET裝置904其透視圖。第12B圖顯示本揭露一實施例中，n型Fin FET裝置902其沿著B-B’剖線的剖視圖。第12C圖顯示本揭露一實施例中，深度範圍上的摻雜濃度圖。
如第12A圖所示，當光阻層1202覆蓋p型Fin FET裝置904時，進行磷二聚體的離子佈植1204。如前所述，本揭露提供相對重與淺的摻雜於摻雜磷的磊晶層(如n型FinFET裝置902的n型磊晶區)的上表面，可讓n型Fin FET裝置902的接觸電 容降低與通道遷移率增加。特別地是，磷二聚體(P2 +)的離子佈植1204比習知採用P+的磷離子佈植，更能有效地導入較高化學磷濃度與增加較高非晶等級。
在應變材料330a的上表面上進行磷二聚體離子佈植，可提供較高的磷濃度以降低其與較上層接觸的接觸電阻，並增加沿著通道區的拉伸應變，進而增加n型通道的有效電子遷移率。在這方面，更高的拉伸應變可減少通道區中的基體晶格參數，比如應變材料330a其上表面(自約0.543nm至約0.537nm)的磷濃度增加10%至15%。
在某些實施例中，磷二聚體的離子佈植1204採用約0.1KeV至約500KeV之間的佈植能量佈植摻質種類。在某些實施例中，佈植劑量介於約1×1015原子/cm3至約4×1015原子/cm3之間。在其他實施例中，加速電壓介於約10KeV至約100KeV之間。在這些實施例中，加速電壓介於約1KeV至約10KeV之間。離子束相對於垂直軸1206的傾斜角度可介於約0度至約45度之間。此外，可從兩個方向(如0度和180度，通過旋轉晶圓)或四個方向佈植離子。
在某些實施例中，第一摻雜劑之磷二聚體的離子佈植1204包括：至少冷卻第一鰭狀結構和第一應變材料至低於約-20℃的溫度，因此其為冷佈植。冷佈植的溫度可介於約-10℃至約-100℃之間。舉例來說，某些實施例中包含n型磊晶區(或n-型應變材料)的n型FinFET裝置902可由室溫冷卻至-20℃的溫度，其他實施例則可冷卻至低於-20℃。
由於相對較高的非晶程度(或活化所需的較低的活 化能)，在冷卻溫度下之磷二聚體的離子佈植1204可引發更活化的磷摻質於表面上。如此一來，磷二聚體的離子佈植1204作為冷佈植，可比室溫佈植引發更多橫向散佈。這是因為較冷的溫度導致佈植的磷原子，比應變材料330其上表面的初始穿透點更加橫向移動。用語「橫向變異」指的是離子沿著軸(約正交於初始穿透的表面)的橫向移動。
在一或多個實施方式中，佈植於第一區域1210中的離子(雜質)具有第一橫向變異，且第二區域1212中的雜質具有第二橫向變異。由於磷二聚體的離子佈植1204作為冷佈植步驟操作，因此第一橫向變異大於第二橫向變異。如此一來，由於n型FinFET裝置902的通道長度較短，因此橫向變異的增加導致接觸電阻降低。舉例來說，在磷二聚體的離子佈植後，可移除光阻層1202。此外，接著可進行熱退火步驟(見第13圖)。在某些實施例中，採用磷團簇離子，而非磷二聚體離子。
第1表顯示磷二聚體佈植與退火的兩個不同實例。舉例來說，在室溫下以磷二聚體摻質佈植裝置A，並於冷凍溫度(如約-20℃)下以磷二聚體摻質佈植裝置B。用相同的摻雜劑量(介於約1×1015原子/cm3至約4×1015原子/cm3之間)和相同的退火溫度(介於約950℃至約1250℃之間)佈植與退火裝置A與B。相對於裝置A，裝置B具有更低的總電阻(裝置A的電阻值的0.98倍)、高約3%的閘極至汲極電容效能、與高約2%的閘極至閘極電容效能。在冷凍溫度下佈植造成更高的裝置效能(總電阻較低和電容效能更高)，可增加NMOS FinFET結構的通道遷移率。
Figure 105129953-A0305-02-0020-2
如第12B圖所示，n-型磊晶區可以具有第一區域1210(包括上表面)，其具有介於約0.1nm(奈米)至約8nm之間的第一厚度(T1)。由於磷二聚體的離子佈植1204，第一區域1210比其下之第二區域1212接收更高的磷濃度。在某些實施例中，第二區域1212具有介於約25nm至約60nm之間的第二厚度(T2)，且其摻雜濃度取決於磊晶成長步驟時的磊晶成長磷化矽(或視情況進行的單原子磷佈植)。
第12C圖顯示深度範圍上之摻雜濃度的SIMS(二次離子質譜)圖。如第12C圖所示，此實施例中的磷二聚體摻雜密度峰值(標記為「SiP+P2 I/I+μSSA」)大於約1x1022原子/cm3(如區域1252)，且位於距佈植的矽區域(如第12B圖的第一區域1210)其上表面幾奈米處，以增加表面附近的摻雜濃度。相反地，單原子磷摻雜密度峰值(標記為「SiP」)與具有亞微秒退火的單原子磷摻雜密度峰值(標記為「SiP+μSSA」)均小於磷二聚體摻雜密度峰值。第12C圖顯示在更靠近源極/汲極磊晶區域的 表面的部分，P2 +離子佈植可導入更高量的雜質。
第13圖係本揭露一實施例中，製程的多種階段之一中n型FinFET裝置902與p型FinFET裝置904其透視圖。在磷二聚體的離子佈植1204之後，可在介於約950℃至約1250℃之間的溫度下進行熱退火步驟1302，以活化佈植的磷。如上所述，磷濃度增加(經由磷二聚體離子佈植)會增加施加於n型FinFET裝置902其通道區上的拉伸應變。在這方面，拉伸應變增加可增強通道電子遷移率。
在某些實施例中，熱退火步驟1302可包括加熱半導體裝置(特別是n型FinFET裝置902)至介於約900℃至1000℃之間的溫度。在其他實施例中，上述熱退火步驟1302的溫度介於約1000℃至約1300℃之間。在某些實施例中，熱退火步驟1302的歷時約1秒至約10秒之間。在某些實施例中，熱退火步驟1302均勻地橫跨n型FinFET裝置902與p型FinFET裝置904。熱退火步驟1302可擇自RTA、閃光退火、亞秒退火(SSA)、亞微秒退火(μSSA)、雷射退火、或類似步驟。在某些實施例中，在約950℃至約1250℃之間的溫度下進行約7秒至約10秒之間的RTA。在其他實施例中，在約1050℃至約1150℃之間的溫度下進行約1秒至約6秒的退火步驟。在其他實施例中，在約950℃至約1150℃之間的溫度下進行約10微秒至約500微秒的μSSA。
第14圖係本揭露一實施例中，製程的多種階段之一中n型FinFET裝置902與p型FinFET裝置904其透視圖。在形成源極/汲極區(如應變材料330a、應變材料330b)之後，沉積CESL(接觸蝕刻停止層)1402。在此例中，CESL1402可均勻成層於n 型FinFET裝置902和p型FinFET裝置904上。
第15圖係本揭露一實施例中，製程的多種階段之一中n型FinFET裝置902與p型FinFET裝置904其透視圖。沉積CESL 1402後(見第14圖)後，沉積ILD(層間介電)層1502。ILD層1502的沉積方法可為合適技術如CVD。在此實施例中，ILD層1502均勻成層於於n型FinFET裝置902與p型FinFET裝置904上。ILD層1502包括介電材料如一或多層的氧化矽、氮化矽、低k介電材料、或上述之組合。
第16圖係本揭露一實施例中，製程的多種階段之一中n型FinFET裝置902與p型FinFET裝置904其透視圖。接著以CMP步驟平坦化ILD層1502與硬遮罩，形成第16圖所示的結構。
在本揭露的實施例中，以光微影等步驟圖案化ILD層1502並形成開口露出應變材料330a和330b，以形成源極/汲極(接點)。沉積合適的導電材料如銅、鎢、鎳、鈦、或類似物於開口中。在某些實施例中，在導電材料與源極/汲極的介面處形成金屬矽化物，以改進介面處的導電度。在一例中，以鑲嵌及/或雙鑲嵌步驟形成銅為主的多層內連線結構。在另一實施例中，採用鎢形成鎢插塞於開口中。
在此實施例中，實施方法為STI先製/閘極後製。此實施例中的許多步驟與STI先製/閘極先製的方法相同或類似。這些方法在移除部分STI區域的步驟相同。
為了形成高k介電物/金屬閘極(HK/MG)，可沉積虛置的閘極介電物於鰭狀物露出的末端上、沉積虛置閘極、以及圖案化虛置閘極。在圖案化虛置閘極後，進行與STI先製/閘極 先製的方法相同或類似的步驟，直到對ILD層1502進行CMP之步驟後。
第17圖係本揭露一實施例中，製程的多種階段之一中n型FinFET裝置902與p型FinFET裝置904其剖視圖。在對ILD層1502進行CMP後，亦移除虛置閘極與虛置閘極介電物，且移除方法可為合適的蝕刻步驟。
第19圖係本揭露一實施例中，製程的多種階段之一中n型FinFET裝置902與p型FinFET裝置904其剖視圖。接著沉積金屬閘極1802於高k閘極介電物1804上。依據本揭露的實施例，高k閘極介電物1804可包含一或多層的HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、二氧化鉿-氧化鋁(HfO2-Al2O3)合金、其他合適的高k介電材料、及/或上述之組合。金屬閘極1802之材料可包含一或多層的Ti、TiN、鈦鋁合金、Al、AlN、Ta、TaN、TaC、TaCN、TaSi、或類似物。
第19圖係本揭露一實施例中，製程的多種階段之一中n型FinFET裝置902與p型FinFET裝置904其剖視圖。在形成HK/MG電極結構後，以類似於STI先製/閘極先製的方法圖案化源極/汲極。
在其他實施例中，製造FinFET裝置300的方法採用EPI先製/閘極先製方法，或EPI先製/閘極後製方法。在EPI先製的方法中，形成磊晶層於基板110上，之後圖案化磊晶層以形成鰭狀物(如半導體的鰭狀結構120)。EPI先製之實施例中的許多步驟，與STI先製方法的步驟相同或類似。
依據本揭露實施例的後續製程，亦可形成多種接點/通孔/線路與多層內連線結構(如金屬層和層間介電物)於半導體的基板110上，設置以連接FinFET裝置300的多種結構。舉例來說，多層內連線結構包括垂直內連線如傳統的通孔或接點，與水平內連線如金屬線路。
FinFET裝置300僅用於舉例。FinFET裝置300可用於多種應用如數位電路、影像感測器裝置、異質半導體裝置、動態隨機存取記憶體(DRAM)單元，單電子電晶體(SET)、及/或其他微電子裝置(統稱為微電子裝置)。當然，本揭露的實施例也應用及/或明顯適用於其他類型的電晶體如單閘極電晶體、雙閘極電晶體、與其他多閘極電晶體，且可應用於多種用途如感測器單元、記憶體單元、邏輯單元、與其他單元。
本揭露在磷摻雜的含矽磊晶層其上表面上，提供相對較重和淺的摻雜，使NMOS Fin FET結構的接觸電容減少且通道遷移率增加。特別的是在磊晶成層步驟之後，磷二聚體(P2 +)的離子佈植在相同的佈植劑量下，比傳統磷離子佈植更有效地結合較高的化學磷濃度和非晶等級。磷二聚體離子佈植可為完全或部分的冷佈植(溫度低於-20℃)，以引發更高的非晶準等級(或更低的活化能)。
本揭露一實施例提供之鰭狀場效電晶體裝置的形成方法，包括：提供基板，其具有第一鰭狀結構與第二鰭狀結構；形成隔離層於基板上，且隔離層與第一鰭狀結構及第二鰭狀結構相鄰；形成第一閘極結構於至少部份第一鰭狀結構與隔離層上；形成第二閘極結構於至少部份第二鰭狀結構與隔離層 上；磊晶成長形成第一應變材料，且第一應變材料提供應力至第一鰭狀結構的通道區；磊晶成長第二應變材料，且第二應變材料提供應力至第二鰭狀結構的通道區；佈植磷二聚體摻質到第一應變材料其至少第一區域，使第一區域具有磷二聚體摻質的第一摻雜濃度，且第一摻雜濃度大於第一應變材料的第二區域中磷摻質的第二摻雜濃度；以及熱回火至少第一鰭狀結構與第一應變材料，並藉由熱回火使第一鰭狀結構的通道區比第二鰭狀結構的通道區具有更大的通道遷移率。
在上述方法中，更包括形成光阻層於第二閘極結構與第二應變材料上；以及在佈植磷二聚體摻質後移除光阻層。
在上述方法中，佈植磷二聚體摻質之步驟包括冷卻至少第一鰭狀結構與第一應變材料至低於-20℃，以作為冷佈植步驟的一部份。
在上述方法中，第一區域中的佈植離子具有第一橫向變異，而第二區域中的佈植離子具有第二橫向變異，且冷佈植步驟使第一橫向變異大於第二橫向變異。
在上述方法中，熱回火至少第一鰭狀結構與第一應變材料之步驟，包括將第一鰭狀結構與第一應變材料的溫度加熱到1000℃至1100℃之間。
在上述方法中，熱回火步驟歷時1秒至10秒。
在上述方法中，第一摻雜濃度介於1×1021原子/cm3至1×1022原子/cm3之間。
在上述方法中，磷二聚體摻質的佈植劑量介於 1×1015原子/cm3至4×1015原子/cm3之間。
在上述方法中，更包含形成間隔物於第一閘極結構與第二閘極結構之側壁上；蝕刻第一閘極結構與間隔物未覆蓋之部份的第一鰭狀結構，以形成第一凹陷部份；形成第一應變材料於第一凹陷部份之中與之上；蝕刻第二閘極結構與間隔物未覆蓋之部份的第二鰭狀結構，以形成第二凹陷部份；以及形成第二應變材料於第二凹陷部份之中與之上。
本揭露一實施例提供之鰭狀場效電晶體的形成方法，包括：提供基板，其具有鰭狀結構；形成絕緣層於基板上，且絕緣層與鰭狀結構相鄰；形成閘極結構於至少部份的鰭狀結構與隔離層上；磊晶成長應變材料，且應變材料提供應力至鰭狀結構的通道區；佈植第一型摻質到應變材料其至少第一區域，使第一區域具有第一型摻質的第一摻雜濃度，且第一摻雜濃度大於應變材料的第二區域中第二型磷摻質的第二摻雜濃度；以及熱回火至少鰭狀結構與應變材料，且熱回火步驟使鰭狀結構之通道區比基板上的另一鰭狀結構之通道區具有更大的通道遷移率。
在上述方法中，第一型磷摻質的佈植劑量介於1×1015原子/cm3至4×1015原子/cm3之間，且第一摻雜濃度介於1×1021原子/cm3至1×1022原子/cm3之間。
在上述方法中，佈植第一型磷摻質之步驟包括冷卻至少鰭狀結構與應變材料至低於-20℃。
在上述方法中，熱回火至少鰭狀結構與應變材料之步驟，包括將鰭狀結構與應變材料的溫度加熱到1000℃至 1100℃之間。
在上述方法中，第一型磷摻質為包含磷二聚體(P2 +)的n型摻質，而第二型磷摻質為包含單原子磷(P)的n型摻質。
本揭露一實施例提供之半導體裝置，包括：基板；第一鰭狀結構；第二鰭狀結構；絕緣層形成於基板上並與第一鰭狀結構及第二鰭狀結構相鄰；第一閘極結構形成於至少第一鰭狀結構與隔離層上；第二閘極結構形成於至少第二鰭狀結構與隔離層上；包含第一應變材料的第一磊晶層，提供應力至第一鰭狀結構的通道區；以及包含第二應變材料的第二磊晶層，提供應力至第二鰭狀結構的通道區，第二磊晶層具有第一區域與第二區域，第一區域比第二區域靠近第二磊晶層的上表面，第一區域具有第一摻雜劑的第一摻雜濃度，第二區域具有第二摻雜劑的第二摻雜濃度，且第一摻雜濃度大於第二摻雜濃度。
在上述半導體裝置中，第一摻雜劑係包含磷的n型摻質。
在上述半導體裝置中，第一磊晶層的佈植離子具有第一橫向變異，第二磊晶層的佈植離子具有第二橫向變異，且第二橫向變異大於第一橫向變異。
在上述半導體裝置中，第一區域位於第二區域上，且第一區域之厚度介於0.1nm至8nm之間。
在上述半導體裝置中，第一掺雜劑位於第二磊晶層的上表面上。
在上述半導體裝置中，第一應變材料設置以用於p型FinFET裝置，而第二應變材料設置以用於n型FinFET裝置。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本揭露。本技術領域中具有通常知識者應理解可採用本揭露作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本揭露精神與範疇，並可在未脫離本揭露之精神與範疇的前提下進行改變、替換、或更動。
T1、T2:厚度
110:基板
150:隔離區
902:n型FinFET裝置
1210:第一區域
1212:第二區域
330a:應變材料

Claims (16)

  1. 一種鰭狀場效電晶體裝置的形成方法，包括：提供一基板，其具有一第一鰭狀結構與一第二鰭狀結構；形成一隔離層於該基板上，且該隔離層與該第一鰭狀結構及該第二鰭狀結構相鄰；形成一第一閘極結構於至少部份該第一鰭狀結構與該隔離層上；形成一第二閘極結構於至少部份該第二鰭狀結構與該隔離層上；磊晶成長形成一第一應變材料，且該第一應變材料提供應力至該第一鰭狀結構的通道區；磊晶成長一第二應變材料，且該第二應變材料提供應力至該第二鰭狀結構的通道區；佈植一磷二聚體摻質到該第一應變材料其至少一第一區域，使該第一區域具有該磷二聚體摻質的一第一摻雜濃度，且該第一摻雜濃度大於該第一應變材料的一第二區域中一磷摻質的一第二摻雜濃度；以及熱回火至少該第一鰭狀結構與該第一應變材料，並藉由熱回火使該第一鰭狀結構的通道區比該第二鰭狀結構的通道區具有更大的通道遷移率。
  2. 如申請專利範圍第1項所述之鰭狀場效電晶體裝置的形成方法，更包括：形成一光阻層於該第二閘極結構與該第二應變材料上；以及在佈植該磷二聚體摻質後移除該光阻層。
  3. 一種鰭狀場效電晶體裝置的形成方法，包括：提供一基板，其具有一鰭狀結構；形成一隔離層於該基板上，且該隔離層與該鰭狀結構相鄰；形成一閘極結構於至少部份的該鰭狀結構與該隔離層上；磊晶成長一應變材料，且該應變材料提供應力至該鰭狀結構的一通道區；佈植第一型磷摻質到應變材料其至少一第一區域，使該第一區域具有該第一型磷摻質的第一摻雜濃度，且第一摻雜濃度大於應變材料的一第二區域中的一第二型磷摻質的一第二摻雜濃度；以及熱回火至少該鰭狀結構與該應變材料，且熱回火步驟使該鰭狀結構之該通道區比基板上的另一鰭狀結構之通道區具有更大的通道遷移率。
  4. 如申請專利範圍第3項所述之鰭狀場效電晶體裝置的形成方法，其中該第一型磷摻質為包含磷二聚體(P2 +)的n型摻質，而該第二型磷摻質為包含單原子磷(P)的n型摻質。
  5. 一種鰭狀場效電晶體裝置的形成方法，包括：形成一閘極於一半導體基板上的一第一鰭狀物之至少一第一部份上；形成一應變材料於該第一鰭狀物的一第二部份上，且該應變材料提供應力至該第一鰭狀物的該第一部份中的一通道區；佈植一第一型磷摻質至該應變材料的至少一第一區，該第一區具有該第一型磷摻質的一第一摻雜濃度，且該第一摻 雜濃度大於該應變材料的一第二區中的一第二型磷摻質之一第二摻雜濃度，其中佈植該第一型磷摻質的步驟包括冷卻至少該第一鰭狀物與該應變材料至低於-20℃；以及對至少該第一鰭狀物與該應變材料進行一熱回火步驟，使該第一鰭狀物的該通道區的通道遷移率大於該基板上的一第二鰭狀物的通道區的通道遷移率。
  6. 如申請專利範圍第5項所述之鰭狀場效電晶體裝置的形成方法，其中該第一區中的佈植離子具有一第一橫向變異，該第二區中的佈植離子具有一第二橫向變異，且該第一橫向變異大於該第二橫向變異。
  7. 一種鰭狀場效電晶體裝置，包括：一基板；一第一鰭狀結構；一第二鰭狀結構；一隔離層形成於該基板上並與該第一鰭狀結構及該第二鰭狀結構相鄰；一第一閘極結構形成於至少該第一鰭狀結構與該隔離層上；一第二閘極結構形成於至少該第二鰭狀結構與該隔離層上；包含一第一應變材料的一第一磊晶層，提供應力至該第一鰭狀結構的通道區；以及包含一第二應變材料的一第二磊晶層，提供應力至該第二 鰭狀結構的通道區，該第二磊晶層具有一第一區域與一第二區域，該第一區域比該第二區域靠近該第二磊晶層的上表面，該第一區域具有一第一摻雜劑的一第一摻雜濃度，該第二區域具有一第二摻雜劑的一第二摻雜濃度，且該第一摻雜濃度大於該第二摻雜濃度，其中該第一摻雜劑具有一第一橫向變異，該第二摻雜劑具有一第二橫向變異，且該第一橫向變異大於該第二橫向變異。
  8. 一種鰭狀場效電晶體裝置，包括：一基板；一第一鰭狀結構，具有通道區；一第二鰭狀結構，具有通道區；一第一磊晶層，包括一第一應變材料以提供應力至該第一鰭狀結構的通道區；以及一第二磊晶層，包括一第二應變材料以提供應力至該第二鰭狀結構的通道區，其中該第二磊晶層具有一第一區與一第二區，且該第一區比該第二區靠近該第二磊晶層的表面；該第一區具有一第一摻質的一第一摻雜濃度，而第二區具有一第二摻質的一第二摻雜濃度，以及該第一摻雜濃度大於該第二摻雜濃度，其中該第一摻質具有一第一橫向變異，該第二摻質具有一第二橫向變異，且該第一橫向變異大於該第二橫向變異。
  9. 一種鰭狀場效電晶體裝置，包括： 一基板；一第一鰭狀結構，具有通道區；一第二鰭狀結構，具有通道區；一第一磊晶層，包括一第一應變材料以提供應力至該第一鰭狀結構的通道區；以及一第二磊晶層，包括一第二應變材料以提供應力至該第二鰭狀結構的通道區，其中該第二磊晶層具有一第一區與一第二區，且該第一區比該第二區靠近該第二磊晶層的表面；該第一區具有一第一摻雜濃度的一第一摻質，而第二區具有一第二摻雜濃度的一第二摻質，以及該第一區中的該第一摻質具有第一橫向變異，且該第二區中的該第二摻質具有第二橫向變異，且該第一橫向變異大於該第二橫向變異。
  10. 如申請專利範圍第9項所述之鰭狀場效電晶體裝置，其中該第一區包括該第一摻雜濃度的一磷二聚體摻質，且該第二區包括該第二摻雜濃度的一磷摻質。
  11. 一種鰭狀場效電晶體裝置，包括：一或多個n型鰭狀場效電晶體結構；以及一或多個p型鰭狀場效電晶體結構，其中該或該些n型鰭狀場效電晶體結構包括：一第一閘極結構，形成於一第一鰭狀結構的通道區上；以及多個第一源極/汲極區，形成於該第一閘極結構之兩側上的 該第一鰭狀結構上，其中該些第一源極/汲極區具有一第一區與一第二區，且該第一區比該第二區靠近該些第一源極/汲極區的表面；該第一區具有一第一摻質且該第二區具有一第二摻質，以及該第一區中的該第一摻質具有一第一橫向變異，該第二區中的該第二摻質具有一第二橫向變異，其中該第一橫向變異大於該第二橫向變異。
  12. 如申請專利範圍第11項所述之鰭狀場效電晶體裝置，其中該第一區包括一第一摻雜濃度的一磷二聚體摻質，且該第二區包括一第二摻雜濃度的一磷摻質。
  13. 一種鰭狀場效電晶體裝置，包括：一基板；一第一鰭狀結構；一第二鰭狀結構；一第一閘極結構，形成於該第一鰭狀結構的一部份上；一第二閘極結構，形成於該第二鰭狀結構的一部份上；一第一磊晶層，包括一第一應變材料以提供應力至該第一鰭狀結構的通道區；以及一第二磊晶層，包括一第二應變材料以提供應力至該第二鰭狀結構的通道區，該第二磊晶層具有一第一區與一第二區，該第一區比該第二區靠近該第二磊晶層的表面，該第一區具有一第一摻雜濃度的一第一摻雜劑，該第二區具有一第二摻雜濃度的一第二摻雜劑，且該第一摻雜濃度大於 該第二摻雜濃度，其中該第二鰭狀結構的通道區的通道遷移率大於該第一鰭狀結構的通道區的通道遷移率。
  14. 如申請專利範圍第13項所述之鰭狀場效電晶體裝置，其中該第一區具有該第一摻雜濃度的一磷二聚體摻質，而該第二區具有該第二摻雜濃度的一磷摻質。
  15. 一種鰭狀場效電晶體裝置，包括：一基板；一第一鰭狀結構；一第二鰭狀結構；一第一閘極結構，形成於該第一鰭狀結構的一部份上；一第二閘極結構，形成於該第二鰭狀結構的一部份上；一第一磊晶層，包括一第一應變材料，以提供應力至該第一鰭狀結構的通道區；一第二磊晶層，包括一第二應變材料，以提供應力至該第二鰭狀結構的通道區，該第二磊晶層具有一第一區與一第二區，該第一區比該第二區靠近該第二磊晶層的表面，該第一區具有一第一摻雜濃度的一第一摻雜劑，該第二區具有一第二摻雜濃度的一第二摻雜劑，且該第一摻雜濃度大於該第二摻雜濃度，其中該第一摻雜劑具有一第一橫向變異，該第二摻雜劑具有一第二橫向變異，且該第一橫向變異大於該第二橫向變異，且其中該第一區自該第二磊晶層的表面至該第二區的厚度介於0.1nm至8nm之間。
  16. 如申請專利範圍第15項所述之鰭狀場效電晶體裝置，其中該第一區具有該第一摻雜濃度的一磷二聚體摻質，而該第二區具有該第二摻雜濃度的一磷摻質。
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