TWI701741B - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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TWI701741B
TWI701741B TW107130946A TW107130946A TWI701741B TW I701741 B TWI701741 B TW I701741B TW 107130946 A TW107130946 A TW 107130946A TW 107130946 A TW107130946 A TW 107130946A TW I701741 B TWI701741 B TW I701741B
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metal
region
film
insulating
manufacturing
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TW107130946A
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TW201921508A (zh
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津村一道
東和幸
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日商東芝記憶體股份有限公司
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Abstract

一種製造一半導體裝置之方法包括：在一第一絕緣區域及緊鄰該第一絕緣區域之一第一金屬區域上形成一第一金屬膜，其中該第一金屬膜包含不同於該第一金屬區域之金屬的一金屬；在一第二絕緣區域及緊鄰該第二絕緣區域之一第二金屬區域上形成一第二金屬膜，其中該第二金屬膜包含不同於該第二金屬區域之金屬的一金屬；使該第一金屬膜與該第二金屬膜相互接觸；及熱處理第一基板與第二基板，且由此將該第一金屬區域與該第二金屬區域相互電連接且同時在該第一絕緣區域與該第二絕緣區域之間形成一絕緣界面膜。

Description

半導體裝置之製造方法
本文中所描述之實施例大體係關於一種製造半導體裝置之方法。
已開發了接合複數個半導體晶圓及結合形成於各別半導體晶圓之表面上的電極之技術(晶圓至晶圓(W2W)金屬結合)。在此技術中，半導體晶圓之表面上的電極內埋於絕緣膜中，並且然後在將其接合前暴露。因此，對準複數個半導體晶圓使得各別電極相互結合。
然而，在該半導體晶圓上，鄰近電極可經由結合界面而短路連接，或電極之間的時間相關介電擊穿(TDDB)可惡化。此導致電特性及可靠性之惡化問題。
另外，在即將執行結合之前的半導體晶圓之表面上，暴露多種不同材料，例如，Cu電極及絕緣膜。因此，當執行電漿處理、清潔等以便使絕緣膜之表面至適合於結合之狀態中時，出現藉由清潔而氧化電極表面或藉由電漿處理再濺鍍電極材料的問題。
實施例提供一種半導體裝置之製造方法，其能夠防止在接合複數個半導體晶圓時半導體裝置之電特性及可靠性的惡化，且允許有助 於適用於將裝置接合在一起之對裝置的預處理。
一般而言，根據一個實施例，一種製造半導體裝置之方法包括：在第一絕緣區域及緊鄰該第一絕緣區域之第一金屬區域上形成第一金屬膜，其中該第一金屬膜包含不同於該第一金屬區域之金屬的一金屬；在第二絕緣區域及緊鄰該第二絕緣區域之第二金屬區域上形成第二金屬膜，其中該第二金屬膜包含不同於該第二金屬區域之金屬的金屬；使該第一金屬膜與該第二金屬膜相互接觸，使得第一基板之第一表面面向第二基板之第二表面；以及熱處理第一基板及第二基板，且由此將該第一金屬區域與該第二金屬區域相互電連接並同時在該第一絕緣區域與該第二絕緣區域之間形成絕緣界面膜。
1:第一半導體部件
2:第二半導體部件
10:第一半導體基板
11:絕緣膜
12:佈線部分
13:第一擴散阻止膜
14:第二擴散阻止膜
15:層間絕緣膜
16:佈線連接部分
17:第三擴散阻止膜
18:光阻膜
19:凹槽/開口
20:第二半導體基板
21:絕緣膜
22:佈線段/佈線部分
23:第一擴散阻止膜
24:第二擴散阻止膜
25:層間絕緣膜
26:佈線連接部分
27:第三擴散阻止膜
29:凹槽/開口
31:界面膜
32:界面膜
33:連接部分
100:金屬膜
200:金屬膜
R1:其餘區域/第一區域
R2:形成區域/第二區域
R3:第三區域
R4:第四區域
R10:區域
R20:區域
S311:結合界面
S312:結合界面
S313:結合界面
S321:結合界面
S322:結合界面
S323:結合界面
圖1是說明第一半導體部件之製造製程的橫截面圖。
圖2是說明自圖1繼續之第一半導體部件之製造製程的橫截面圖。
圖3是說明自圖2繼續之第一半導體部件之製造製程的橫截面圖。
圖4是說明自圖3繼續之第一半導體部件之製造製程的橫截面圖。
圖5是說明自圖4繼續之第一半導體部件之製造製程的橫截面圖。
圖6是說明自圖5繼續之第一半導體部件之製造製程的橫截面圖。
圖7是說明自圖6繼續之第一半導體部件之製造製程的橫截面圖。
圖8是說明自圖7繼續之第一半導體部件之製造製程的橫截面圖。
圖9是說明自圖8繼續之第一半導體部件之製造製程的橫截面圖。
圖10是說明第二半導體部件之組態實例的橫截面圖。
圖11是說明接合第一半導體部件與第二半導體部件之製程的橫截面 圖。
圖12是說明自圖11繼續之接合第一半導體部件與第二半導體部件之製程的橫截面圖。
下文，將參看圖式描述本發明之實施例。該實施例不限制本發明。在以下實施例中，半導體基板之垂直方向指示在其上提供半導體元件之表面被視為向上之情況中的相對方向，且可與根據重力加速度之垂直方向不同。圖式是示意性或概念性的，且每一部分之比率未必與在實際情況中之比率相同。在說明書及圖式中，類似於先前參看圖式描述之元件的元件被指派相同附圖標號，且將恰當地省略其詳細描述。
在根據實施例之半導體裝置的製造方法中，例如算術裝置及記憶體裝置之半導體裝置是藉由接合複數個半導體基板來製造。在複數個接合之半導體基板上，包括例如電晶體及用於連接電路元件之佈線部分的電路元件之電子電路提供於單層或堆疊之層上。電子電路相互電連接於複數個接合之半導體基板之間。此是因為當半導體基板相互接合時，一個半導體基板之佈線連接部分與另一半導體基板的佈線連接部分相互結合。佈線連接部分可為金屬佈線或被形成以穿透半導體基板的穿透電極(矽穿孔(TSV))。
將參看圖1至圖12描述根據實施例之半導體裝置的製造方法。圖1至圖9是說明第一半導體部件1之製造製程的橫截面圖。圖10是說明第二半導體部件2之組態實例的橫截面圖。圖11及圖12是說明接合第一半導體部件1與第二半導體部件2之製程的橫截面圖。
首先，將描述形成第一半導體部件1之方法。首先，如圖1 中所說明，絕緣膜11、佈線部分12、第一擴散阻止膜13及第二擴散阻止膜14使用例如化學氣相沈積(CVD)、濺鍍、微影、蝕刻、電鍍、化學機械拋光(CMP)等之半導體裝置製造技術形成於第一半導體基板10上方。在此種情況下，絕緣膜11及佈線部分12之上表面被形成以便大體上相互齊平。
作為絕緣膜11，使用例如SiO2之絕緣體。雖未說明，但電子電路形成於絕緣膜11中。如圖1中所說明，第一半導體基板10安置於絕緣膜11下方。
佈線部分12電連接至形成於絕緣膜11中的電子電路。Cu含於佈線部分12中作為主要組份(整體之50原子%或50原子%以上)。
第一擴散阻止膜13充當阻擋層且防止佈線部分12中含有之Cu擴散至絕緣膜11內。第一擴散阻止膜13由例如Ti、Ta、Ru或其氮化物(TiN、TaN及RuN)之導體形成。
第二擴散阻止膜14充當阻擋層，且防止佈線部分12中含有的Cu擴散至層間絕緣膜15內。第二擴散阻止膜14由例如SiC、SiN或SiCN之絕緣體形成。舉例而言，藉由此樣，有可能防止相互鄰近的複數個佈線部分12之間在圖1之紙表面方向上的短路連接。
接下來，如圖1中所說明，層間絕緣膜15形成於第一半導體基板10之表面上方，即，在第二擴散阻止膜14上。作為第一絕緣膜之層間絕緣膜15是使用CVD等由含有SiO2、SiOC等作為主要組份之氧化膜形成。
接下來，如圖2中所說明，光阻膜18塗佈於層間絕緣膜15上。接下來，如圖3中所說明，藉由微影技術使用於形成佈線連接部分16作為第一佈線膜的圖案形成於光阻膜18中。在此種情況下，在層間絕緣膜 15之其餘區域(第一區域)R1中光阻膜18保留。移除佈線連接部分16之形成區域(第二區域)R2中的光阻膜18。
接下來，如圖4中所說明，使用光阻膜18作為光罩來執行乾式蝕刻。藉由乾式蝕刻處理，處理層間絕緣膜15及第二擴散阻止膜14，且凹槽19(開口)形成於佈線連接部分16之形成區域R2的層間絕緣膜15中。執行乾式蝕刻處理，直至暴露佈線部分12之表面。藉由此樣，移除在第一半導體基板10之表面上的第二區域R2之層間絕緣膜15，且第一區域R1之層間絕緣膜15保留。
接下來，如圖5中所說明，移除留在層間絕緣膜15上之光阻膜18及藉由乾式蝕刻處理產生的殘餘沈積物。舉例而言，執行使用氧電漿之灰化處理或使用溶解光阻之化學溶液的清潔處理。
接下來，如圖6中所說明，第三擴散阻止膜17，其充當阻擋層且形成於層間絕緣膜15之側表面(凹槽19之內壁側)及第二區域R2的佈線部分12上。作為第一阻擋膜之第三擴散阻止膜17是藉由在Ar/N2氣氛中濺鍍Ti、Ta、Ru或其氮化物(TiN、TaN、RuN)等來形成。第三擴散阻止膜17可防止稍後待描述之佈線連接部分16中含有的Cu擴散至層間絕緣膜15內。
接下來，如圖7中所說明，藉由電解電鍍方法將佈線連接部分16沈積於第三擴散阻止膜17上。佈線連接部分16含有(例如)Cu作為主要組份。佈線連接部分16經由第三擴散阻止膜17電連接至佈線部分12。
在形成佈線連接部分16後，可對第一半導體基板10執行例如退火處理的熱處理。藉由此樣，可改善佈線連接部分16之結晶結構且可 改善佈線連接部分16之化學及物理穩定性。
接下來，如圖8中所說明，藉由例如CMP(化學機械拋光)之技術將第三擴散阻止膜17及佈線連接部分16拋光及平坦化，直至暴露層間絕緣膜15。結果，移除層間絕緣膜15上之第三擴散阻止膜17及佈線連接部分16，且佈線連接部分16之表面與層間絕緣膜15的表面大體上齊平。
層間絕緣膜15保持處於第一半導體基板10之表面的第一區域R1中。凹槽19形成於與第一半導體基板10之表面之第一區域R1不同的第二區域R2中，且在凹槽19中形成第三擴散阻止膜17及佈線連接部分16。
佈線連接部分16充當用於電連接分別形成於待相互接合之第一半導體部件1及第二半導體部件2上的電子電路之電極。可任意設計佈線連接部分16之平坦佈局。
接下來，如圖9中所說明，藉由CVD方法使金屬膜100形成於層間絕緣膜15、佈線連接部分16及第三擴散阻止膜17上。作為第一金屬膜之金屬膜100較佳地由比佈線連接部分16更易於氧化的金屬材料形成。舉例而言，在佈線連接部分16為銅之情況下，金屬膜100由選自由Mn、Al、V、Zn、Nb、Zr、Cr、Y、Tc及Re組成之群組之至少一種金屬材料形成。較佳地，金屬膜100之金屬材料是Mn。金屬膜100可為選自以上描述之群組的多種金屬材料之合金。金屬膜100之厚度為(例如)若干奈米。下文，將藉由假定金屬膜100之材料為Mn來進行描述。
在自金屬膜100之形成至第一半導體部件1與第二半導體部件2之接合的時段期間，可使第一半導體部件1及第二半導體部件2暴露於 大氣。氧化物(在佈線連接部分16含有Cu之情況下，CuO)藉由暴露於大氣而形成於佈線連接部分16之表面上。在此種情況下，當金屬膜100之材料比佈線連接部分16的材料更易於氧化時，在佈線連接部分16之表面上的氧化物易於還原。佈線連接部分16之表面上之氧化物被還原，以便使減小佈線連接部分16及26之電阻有可能。
藉由描述之製程，形成第一半導體部件1。
接下來，將描述形成第二半導體部件2之方法。第二半導體部件2可藉由與第一半導體部件1之方法相同的方法來形成。
圖10為說明第二半導體部件2之組態實例的橫截面圖。形成於第二半導體基板20上之絕緣膜21、佈線段22、第一擴散阻止膜23、第二擴散阻止膜24、層間絕緣膜25、佈線連接部分26、第三擴散阻止膜27及金屬膜200分別類似於第一半導體部件1的絕緣膜11、佈線部分12、第一擴散阻止膜13、第二擴散阻止膜14、層間絕緣膜15、佈線連接部分16、第三擴散阻止膜17及金屬膜100來形成。
即，首先，絕緣膜21、佈線部分22、第一擴散阻止膜23及第二擴散阻止膜24形成於第二半導體基板20上。接下來，作為第二絕緣膜之層間絕緣膜25形成第二半導體基板20的表面上方(在第二擴散阻止膜24上)。接下來，藉由使用微影技術及乾式蝕刻技術來處理層間絕緣膜25，且凹槽29(開口)形成於層間絕緣膜25中，使得暴露佈線部分22之表面。在第二半導體基板20之表面的第三區域R3中，保留層間絕緣膜15。凹槽29形成於第二半導體基板20之表面的不同於第三區域R3之第四區域R4中。接下來，作為第二阻擋膜之第三擴散阻止膜27形成於層間絕緣膜25的側表面(凹槽29之內側)上及第四區域R4上方。接下來，將佈線連接部 分26沈積於第三擴散阻止膜27上以形成佈線連接部分26。接下來，將結合界面上的表面平坦化，直至暴露層間絕緣膜25的表面。結果，在第二半導體基板20之表面上，作為第二佈線膜之佈線連接部分26及第三擴散阻止膜27形成於與第三區域R3不同的第四區域R4(凹槽29)中。接下來，作為第二金屬膜之金屬膜200形成於層間絕緣膜25、佈線連接部分26及第三擴散阻止膜27上。藉由此樣，形成第二半導體部件2。
金屬膜200之金屬材料及厚度可與金屬膜100之金屬材料及厚度相同。在膜100及200之總厚度大的情況下，存在金屬膜100及200在熱處理(此將在稍後描述)之後保持未充分地反應且使半導體裝置之電特性惡化的可能性。因此，金屬膜100及200之總厚度較佳地為(例如)10nm或10nm以下。
在自金屬膜200之形成至第一半導體部件1與第二半導體部件2之接合的時段期期間，可使第一半導體部件1及第二半導體部件2暴露於大氣。氧化物藉由暴露於大氣而形成於佈線連接部分26之表面上。舉例而言，在佈線連接部分26含有Cu的情況下，形成之氧化物是CuO。在此種情況下，當金屬膜200之材料比佈線連接部分26的材料更易於氧化時，在佈線連接部分26之表面上的氧化物易於還原。在佈線連接部分26之表面上的氧化物被還原，以便使減小佈線連接部分16及26之電阻有可能。
接下來，對金屬膜100及200執行針對結合之預處理。如上所述，當第一半導體部件1及第二半導體部件2暴露於大氣時，氧化膜形成於金屬膜100及200之表面上。舉例而言，在金屬膜100及200由Mn製造之情況下，MnOx形成於金屬膜100及200之表面上。
舉例而言，在預處理中，對金屬膜100及200執行N2電漿處 理。藉由此樣，在金屬膜100及200之表面上的氧化膜中產生懸鍵，且可使第一半導體部件1與第二半導體部件2之間的結合更強勁。其不限於N2電漿處理，但可在預處理中執行使用另一氣體之電漿處理。另外，可對金屬膜100及200執行水清潔處理。藉由此樣，有可能移除金屬膜100及200之表面上的雜質等。其不限於水清潔處理，而可為使用化學溶液等之清潔處理。
接下來，使第一半導體基板10之表面與第二半導體基板20的表面相互對置，且使佈線連接部分16與佈線連接部分26相互接觸。即，第一半導體部件1(金屬膜100)與第二半導體部件2(金屬膜200)相互對準且接觸，使得佈線連接部分16與佈線連接部分26相互對置(接合)。
圖11及圖12是說明接合第一半導體部件1與第二半導體部件2之製程的橫截面圖。圖11及圖12說明在接合第一半導體部件1與第二半導體部件2時出現位置偏差的狀態。在此種情況下，如圖11中所說明，存在佈線連接部分16與層間絕緣膜25經由***於其間之金屬膜100及200相互對置的區域R20及佈線連接部分26與層間絕緣膜15經由***於其間的金屬膜100及200相互對置之區域R10。在第一半導體部件1及第二半導體部件2在當接合第一半導體部件1與第二半導體部件2時暴露於大氣之情況下，可使用融合結合或表面活化結合(SAB)。
接下來，對接合之第一半導體部件1與第二半導體部件2執行例如退火處理之熱處理。將第一半導體部件1及第二半導體部件2加熱達1小時，例如，在400℃下。在此種情況下，金屬膜100及200在一定程度上擴散至佈線連接部分16及26內，且在佈線連接部分16與佈線連接部分26之間幾乎消失。此外，佈線連接部分16及26擴大。藉由此樣，佈線連 接部分16與26在連接部分33處結合以在圖12中說明之結合界面處電連接在一起。形成於第一半導體部件1中之電子電路電連接至形成於第二半導體部件2中的電子電路。金屬膜100及200可稍微保留於連接部分33處。在金屬膜100及200之材料擴散至佈線連接部分16及26之情況中，佈線連接部分16及26的電阻稍微增大。然而，舉例而言，只要佈線連接部分16及26具有若干歐姆或更小之低電阻，那麼就不存在問題。
藉由以上描述之熱處理，如圖12中所說明，在第一半導體部件1與第二半導體部件2之間的結合界面處，界面膜31形成於佈線連接部分16與層間絕緣膜25之間的結合界面S311處，第三擴散阻止膜17與層間絕緣膜25之間的結合界面S312處，及層間絕緣膜15與層間絕緣膜25之間的結合界面S313處。界面膜32形成於佈線連接部分26與層間絕緣膜15之間的結合界面S321處，第三擴散阻止膜27與層間絕緣膜15之間的結合界面S322處，及層間絕緣膜15與層間絕緣膜25之間的結合界面S323處。
界面膜31具有防止佈線連接部分16中含有之Cu擴散至層間絕緣膜25內的功能。界面膜31為(例如)MnSiOx。界面膜31可處於選自由αxOy、αxSiyOz、αxCyOz及αxFyOz組成之群組之至少一種化合物處。此處，α是金屬膜100之材料，且在實施例中，將藉由將α看作Mn來進行描述。舉例而言，在金屬膜100及200之主要組份是Mn且層間絕緣膜15及25之主要組份是SiO2的情況下，界面膜31是MnSiOx。在佈線連接部分16及26由多種類型之金屬材料製成之情況下，界面膜31可含有多種類型之材料。
界面膜32具有防止佈線連接部分26中含有的Cu擴散至層間絕緣膜15內之功能。類似於界面膜31，界面膜32含有選自由αxOy、 αxSiyOz、αxCyOz及αxFyOz組成之群組的至少一種化合物。舉例而言，在金屬膜100及200之主要組份為Mn且層間絕緣膜15及25的主要組份為SiO2之情況下，界面膜32為MnSiOx。在佈線連接部分16及26由多種類型之金屬材料製成的情況中，界面膜32可含有多種類型之材料。
界面膜31及界面膜32具有電絕緣性質。作為此性質之結果，防止在Cu易於擴散之結合界面處的界面膜31及32之對置側上之佈線與元件之短路連接是有可能的。因此，界面膜31及32防止Cu在結合界面處之擴散。因此，防止鄰近佈線與元件之間的短路連接及佈線與元件之間的TDDB之惡化是有可能的。
作為熱處理之結果，界面膜31以自對準方式形成於佈線連接部分16與層間絕緣膜25之間的結合界面S311處。不與金屬膜100及200在其上形成以在熱處理時形成界面膜(不形成界面膜31)之絕緣層反應的金屬膜100及200之材料在熱處理期間擴散至佈線連接部分16及26內。藉由以上描述之熱處理，亦在第三擴散阻止膜17與層間絕緣膜25之間的界面S312處及在層間絕緣膜15與層間絕緣膜25之間的界面S313處，界面膜31類似地以自對準方式形成。
界面膜32亦類似於界面膜31形成。即，界面膜32以自對準方式形成於佈線連接部分26與層間絕緣膜15之間的界面S321處。此外，在第三擴散阻止膜27與層間絕緣膜15之間的界面S322及層間絕緣膜15與層間絕緣膜25之間的結合界面S323處，界面膜32類似地以自對準方式形成。結果，界面膜32防止佈線連接部分26中之金屬的擴散擴散至層間絕緣膜15內，且界面膜31防止佈線連接部分16中之金屬之擴散擴散至層間絕緣膜25內。
因此，甚至在佈線連接部分16、26之間的位置偏差在接合第一半導體部件1與第二半導體部件2時出現之情況下，界面膜31及32仍可防止Cu自佈線連接部分16及26擴散至層間絕緣膜15及25內。另外，如圖11中所說明，界面膜31及32形成於結合界面處。因此，界面膜31及32不存在於與第三擴散阻止膜17及27相同的平面上。即，當在垂直於半導體基板或半導體部件之表面的方向上查看時，在佈線連接部分16、26之一側處，界面膜31及32不與第三擴散阻止膜17及27重疊。因此，如可自圖12看出，在佈線連接部分16與佈線連接部分26連接之區域中，存在不提供具有比佈線連接部分16及26相對高之電阻的第三擴散阻止膜17及27之區域。有可能保證佈線連接部分16與佈線連接部分26相互連接的較寬區域，使得可進一步防止電阻之增大。金屬膜100及200之材料中之一種可以是Mn並且另一種可以是MnO，或金屬膜100及200之兩種材料可以是MnO。在此種情況下，在熱處理後，MnO形成MnSiOx，作為界面膜31及32，此類似於Mn。
第一半導體基板10及第二半導體基板20可在自金屬膜100及200之形成的真空氣氛中處理，直至第一半導體部件1與第二半導體部件2之間接觸。在此種情況下，很難氧化金屬膜100及200之表面。因此，在熱處理後防止連接部分33之電阻增大是可能的。
在根據實施例之半導體裝置的製造方法中，金屬膜100及200皆形成於第一半導體部件1及第二半導體部件2上。然而，金屬膜100及200中之僅一個可形成於第一半導體部件1及第二半導體部件2上。甚至在此種情況下，可形成界面膜31及32。在此種情況下，在結合之預處理製程中，亦對第一半導體基板10(或第二半導體基板20)之表面執行N2電 漿處理，在基板上無金屬膜100(或200)。在此種情況下，佈線連接部分16(或26)中含有之Cu可再濺鍍至層間絕緣膜15(或25)上。因此，Cu可保留於層間絕緣膜15與層間絕緣膜25之間的界面膜31及32上。在此種情況下，在一些情況下，佈線與元件之間的短路連接或TDDB之惡化有可能發生。因此，雖然可形成金屬膜100及200中之一個，但更佳地，形成金屬膜100及200兩個。
如上所述，根據係根據實施例之半導體裝置之製造方法，金屬膜100(例如Mn)形成於第一半導體部件1中之層間絕緣膜15及佈線連接部分16(例如，Cu)上。金屬膜200(例如，Mn)形成於第二半導體部件2中之上層間絕緣膜25及佈線連接部分26(例如，Cu)上。藉由此樣，當第一半導體部件1與第二半導體部件2相互接合時，使金屬膜100與200相互接觸，且在執行熱處理後形成界面膜31及32(例如，MnSiO2)。結果，可防止Cu自佈線連接部分26至層間絕緣膜15內之擴散，且可防止Cu自佈線連接部分16至層間絕緣膜25內之擴散，同時達成佈線連接部分之低電阻連接。
在不形成金屬膜200之情況中，當佈線連接部分16與26之位置偏離時，使半導體部件中之一個的佈線連接部分16及26之材料(例如，Cu)與另一半導體部件之層間絕緣膜15及25之材料(例如，SiO2)接觸。在此種情況下，Cu可自佈線連接部分16及26擴散至層間絕緣膜15及25內。在層間絕緣膜15與25之結合界面處，歸因於存在微小之瑕疵，Cu易於沿著結合界面擴散。
相比之下，根據實施例之界面膜31及32防止Cu沿著結合界面擴散。藉由此樣，有可能防止鄰近佈線與元件之間的短路連接及TDDB 之惡化，並且有可能改善半導體裝置之電特性及可靠性。
界面膜31及32以自對準方式形成。因此，如與在層間絕緣膜15及25之全部表面上形成SiN等之阻擋膜之情況相比，層間絕緣膜有可能具有低介電常數。使用新絕緣材料來形成層間絕緣膜15及25以用於防止Cu之擴散是無必要的，並且因此，可減少成本。
當在接合至金屬膜100及200前執行預處理時，佈線連接部分16及26之Cu覆蓋有金屬膜100及200。藉由此樣，有可能防止Cu在佈線連接部分16及26中之再濺鍍或氧化，甚至當使用現有N2電漿處理或水清潔處理時。因此，易於執行接合前之預處理。待處理之材料是一種金屬膜100及200，且因此，預處理之最佳化亦變得容易。
雖然已描述某些實施例，但此些實施例僅作為實例而提出，且其並不意欲限制本發明之範圍。實際上，本文中所描述之新穎實施例可以多種其他形式體現；此外，可在不脫離本發明之精神的情況下進行本文中所描述的實施例之形式之各種省略、取代及改變。所附申請專利範圍及其等效物意欲涵蓋將屬於本發明之範圍及精神的此類形式或修改。
相關申請之交叉引用
本申請案是基於且要求來自2017年9月15日提交之日本專利申請案第2017-178257號的優先權，該申請案之全部內容以引用之方式併入本文中。
1‧‧‧第一半導體部件
2‧‧‧第二半導體部件
10‧‧‧第一半導體基板
11‧‧‧絕緣膜
12‧‧‧佈線部分
13‧‧‧第一擴散阻止膜
14‧‧‧第二擴散阻止膜
15‧‧‧層間絕緣膜
16‧‧‧佈線連接部分
17‧‧‧第三擴散阻止膜
20‧‧‧第二半導體基板
21‧‧‧絕緣膜
22‧‧‧佈線段/佈線部分
23‧‧‧第一擴散阻止膜
24‧‧‧第二擴散阻止膜
25‧‧‧層間絕緣膜
26‧‧‧佈線連接部分
27‧‧‧第三擴散阻止膜
31‧‧‧界面膜
32‧‧‧界面膜
33‧‧‧連接部分
S311‧‧‧結合界面
S312‧‧‧結合界面
S313‧‧‧結合界面
S321‧‧‧結合界面
S322‧‧‧結合界面
S323‧‧‧結合界面

Claims (20)

  1. 一種製造一半導體裝置之方法，其包含： 提供包含一第一表面之一第一基板，該第一基板包括一第一絕緣區域及緊鄰該第一絕緣區域之至少一個第一金屬區域； 在該第一絕緣區域及該第一金屬區域上形成一第一金屬膜，其中該第一金屬膜包含不同於該第一金屬區域之金屬的一金屬； 提供包含一第二表面之一第二基板，該第二基板包括一第二絕緣區域及緊鄰該第二絕緣區域之至少一個第二金屬區域； 在該第二絕緣區域及該第二金屬區域上形成一第二金屬膜，其中該第二金屬膜包含不同於該第二金屬區域之金屬的一金屬； 使該第一金屬膜與該第二金屬膜相互接觸，使得該第一基板之該第一表面面向該第二基板之該第二表面；以及 熱處理該第一基板及該第二基板，且由此將該第一金屬區域與該第二金屬區域相互電連接且同時在該第一絕緣區域與該第二絕緣區域之間形成一絕緣界面膜。
  2. 如請求項1之製造該半導體裝置之方法，其中該第一金屬區域之一部分面向該第二絕緣區域。
  3. 如請求項2之製造該半導體裝置之方法，其中一第一阻擋層***於該第一金屬區域與該第一絕緣區域之間，且該第一阻擋層之一部分延伸至在該第一金屬區域之相對側上的該第一基板之該第一表面；以及 該絕緣界面膜跨鄰近面向該第二絕緣區域的該第一金屬區域之該部分的該第一阻擋層之該部分延伸。
  4. 如請求項3之製造該半導體裝置之方法，其中延伸至該第一基板之該第一表面、鄰近不面向該第二絕緣區域的該第一金屬區域之部分的該第一阻擋層之該部分不被該絕緣膜覆蓋。
  5. 如請求項1之製造該半導體裝置之方法，其進一步包含在使該第一金屬膜與該第二金屬膜相互接觸前將第一金屬膜及該第二金屬膜中之至少一者暴露於一電漿。
  6. 如請求項1之製造該半導體裝置之方法，其進一步包含在使該第一金屬膜與該第二金屬膜相互接觸前清潔第一金屬膜及該第二金屬膜中之至少一者或對第一金屬膜及該第二金屬膜中之至少一者執行電漿處理。
  7. 如請求項1之製造該半導體裝置之方法，其中該第一金屬膜由比該第一金屬區域之該金屬更易於氧化的一金屬形成；且 該第二金屬膜由比該第二金屬區域之該金屬更易於氧化之一金屬形成。
  8. 如請求項1之製造該半導體裝置之方法，其中該絕緣界面膜係包含由該第一金屬膜及該第二金屬膜以及該第一絕緣區域及第二絕緣區域之材料形成的一化合物。
  9. 如請求項1之製造半導體裝置之方法，其中該電連接第一金屬區域與該第二金屬區域包括在其中之該第一金屬膜及第二金屬膜之材料。
  10. 如請求項1之製造該半導體裝置之方法，其中該第一金屬膜及第二金屬膜中之至少一者包含一金屬氧化物。
  11. 如請求項1之製造該半導體裝置之方法，其中該第一金屬膜含有選自由Mn、Al、V、Zn、Nb、Zr、Cr、Y、Tc及Re組成之群組的至少一種金屬。
  12. 如請求項1之製造該半導體裝置之方法，其中 該絕緣界面膜包含選自由αx Oy 、αx Siy Oz 、αx Cy Oz 及αx Fy Oz 組成之群組的至少一種化合物，其中該第一金屬膜之一金屬材料由α表示。
  13. 如請求項1之製造該半導體裝置之方法，其中該第一金屬膜及第二金屬膜為Mn，且該界面膜包含MnSiO。
  14. 一種製造一半導體裝置之方法，其包含： 提供包含一第一表面之一第一基板，該第一基板包括一第一絕緣區域及緊鄰該第一絕緣區域之至少一個第一金屬區域； 在該第一絕緣區域及該第一金屬區域上形成一第一金屬膜，其中該第一金屬膜包含不同於該第一金屬區域之金屬的一金屬； 提供包含一第二表面之一第二基板，該第二基板包括一第二絕緣區域及緊鄰該第二絕緣區域之至少一個第二金屬區域； 在該第一絕緣區域及該第一金屬區域上形成一第一金屬膜，其中該第一金屬膜包含不同於該第一金屬區域之金屬的一金屬； 在該第二絕緣區域及該第二金屬區域上形成一第二金屬膜，其中該第二金屬膜包含不同於該第二金屬區域之金屬的一金屬； 使該第一金屬膜與該第二金屬膜相互接觸，使得該第一基板之該第一表面面向該第二基板的該第二表面，且該第一金屬區域之一第一部分面向該第二絕緣區域之一部分，該第二金屬區域之一第一部分面向該第一絕緣區域之一部分，且該第一金屬區域及第二金屬區域中之每一個的一第二部分面向彼此；以及 熱處理該第一基板及該第二基板，且由此將該第一金屬區域與該第二金屬區域之該第二部分相互電連接，且同時在該第一絕緣區域與該第二絕緣區域之間、在該第一金屬區域的該第一部分與該第二絕緣區域之間及在該第二金屬區域之該第一部分與該第一絕緣區域之間形成一絕緣界面膜。
  15. 如請求項14之製造該半導體裝置之方法，其進一步包含： 在該第一金屬區域與該第一絕緣區域之間提供一阻擋層，其中 該絕緣界面膜在該阻擋層之在該第一金屬區域的該第一部分與該第一絕緣區域之間的該部分上延伸，且該絕緣界面膜不在該阻擋層之在該第一金屬區域之該第二部分與該第一絕緣區域之間的該部分上延伸。
  16. 如請求項14之製造該半導體裝置之方法，其中該第一金屬膜及第二金屬膜中之至少一者包含一金屬氧化物。
  17. 如請求項14之製造該半導體裝置之方法，其中該第一金屬膜含有選自由Mn、Al、V、Zn、Nb、Zr、Cr、Y、Tc及Re組成的群組之至少一種金屬。
  18. 如請求項14之製造該半導體裝置之方法，其中該絕緣界面膜包含選自由αx Oy 、αx Siy Oz 、αx Cy Oz 及αx Fy Oz 組成之群組之至少一種化合物，其中該第一金屬膜之一金屬材料由α表示。
  19. 如請求項14之製造該半導體裝置之方法，其中該第一金屬膜及第二金屬膜為Mn，且該界面膜包含MnSiO。
  20. 如請求項14之製造該半導體裝置之方法，其中該電連接第一金屬區域與該第二金屬區域包括在其中之該第一金屬膜及第二金屬膜之該材料。
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