TWI699253B - Residue-free flux and method for producing semiconductor package - Google Patents
Residue-free flux and method for producing semiconductor package Download PDFInfo
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- TWI699253B TWI699253B TW104144430A TW104144430A TWI699253B TW I699253 B TWI699253 B TW I699253B TW 104144430 A TW104144430 A TW 104144430A TW 104144430 A TW104144430 A TW 104144430A TW I699253 B TWI699253 B TW I699253B
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K1/00—Soldering, e.g. brazing, or unsoldering
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K31/00—Processes relevant to this subclass, specially adapted for particular articles or purposes, but not covered by only one of the preceding main groups
- B23K31/02—Processes relevant to this subclass, specially adapted for particular articles or purposes, but not covered by only one of the preceding main groups relating to soldering or welding
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mechanical Engineering (AREA)
- Wire Bonding (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
本發明係關於無殘渣助焊劑及半導體封裝件之製造方法。尤其關於適用於以下焊接工法之無殘渣助焊劑，以及使用該無殘渣助焊劑的半導體封裝件之製造方法中的焊接工法；前述封裝件之製造方法，係將形成於半導體晶片之焊料凸塊與形成於基板之經鍍焊的配線進行焊接後，不冷卻至室溫，而是於100至120℃填充底填料(underfill material)後使之硬化。 The present invention relates to a residue-free flux and a manufacturing method of a semiconductor package. Especially with regard to the residue-free flux suitable for the following soldering methods, and the soldering method in the manufacturing method of semiconductor packages using the residue-free flux; the manufacturing method of the aforementioned package is to combine solder bumps and After soldering, the plated and soldered wiring formed on the substrate is not cooled to room temperature, but is filled with an underfill material at 100 to 120°C and then hardened.
近年來，作為可對應於電子機器的配線等之進一步的高密度化、高頻化之半導體封裝件的構裝方式，係應用倒裝晶片接合(flip chip bonding)。一般而言，倒裝晶片接合中，在將形成於半導體晶片之焊料凸塊與形成於基板之經鍍焊的配線進行焊接後，以稱為底填料之材料來密封半導體晶片與基板之間隙。 In recent years, flip chip bonding has been used as a packaging method of semiconductor packages that can correspond to higher density and higher frequencies of wiring of electronic equipment. Generally speaking, in flip-chip bonding, after soldering solder bumps formed on a semiconductor chip and soldered wiring formed on a substrate, a material called underfill is used to seal the gap between the semiconductor chip and the substrate.
用以對應於配線等之進一步的高密度化、高頻化之次世代的半導體封裝件中，除了焊料凸塊、配線的窄間距化之外，係要求多核化所造成之晶片的大型化。 當於該窄間距化、晶片的大型化時，焊接時所使用之助焊劑的殘渣乃成為問題。 In the next-generation semiconductor packages that correspond to higher density and higher frequencies of wiring, etc., in addition to narrowing the pitch of solder bumps and wiring, it is required to increase the size of the chip caused by multi-core. When the pitch is narrowed and the chip is enlarged, the residue of the flux used in soldering becomes a problem.
於該窄間距化時，由於容易產生洗淨不良，所以容易產生助焊劑殘渣。因而要求無殘渣助焊劑。 When the pitch is narrowed, since cleaning failure is likely to occur, flux residue is likely to occur. Therefore, no residue flux is required.
而且，於現行的製造步驟中，係在將形成於半導體晶片之焊料凸塊與形成於基板之經鍍焊的配線進行焊接後，於冷卻至室溫後，以底填料來密封半導體晶片與基板之間隙。目前，使晶片大型化時，以超音波顯微鏡來觀察焊料凸塊附近時，可看到良好的接合部為灰色，相對於此，係容易產生於接合部看到白色之稱為凸塊斷裂(white bump)的接合不良。 Moreover, in the current manufacturing process, after soldering the solder bumps formed on the semiconductor chip and the plated and soldered wiring formed on the substrate, after cooling to room temperature, the semiconductor chip and the substrate are sealed with an underfill The gap. At present, when the chip is enlarged, when the vicinity of the solder bump is observed with an ultrasonic microscope, it can be seen that the good joint is gray. On the other hand, it is easy to produce the white bump at the joint, which is called bump fracture ( Bad junction of white bump).
此種凸塊斷裂，係產生於焊接後、以底填料密封前，咸認此係因為基板的大型化會促進由半導體晶片與基板之熱膨脹差所造成的應力之故。 This bump fracture occurs after soldering and before sealing with an underfill. It is believed that the increase in the size of the substrate will promote the stress caused by the thermal expansion difference between the semiconductor chip and the substrate.
作為用以抑制此凸塊斷裂的產生之方法，係有探討一種在進行焊接後，不冷卻至室溫，而是在冷卻至100至120℃後，於100至120℃填充底填料，並於130至160℃使底填料硬化之製造方法(以下稱為藉由無殘渣助焊劑之製造方法)(非專利文獻1)。藉由此種藉由無殘渣助焊劑之製造方法，係具有於焊接後可減少因半導體晶片與基板之熱膨脹差所造成的應力，且可縮短製造步驟之優點。另一方面，此種藉由無殘渣助焊劑之製造方法中，因為在焊接後無法洗淨助焊劑殘渣，故要求無殘渣助焊劑。第1圖係顯示說明藉由無殘渣助焊劑之製造方法的一例之 圖。第1圖的A為傳統製程的例子，B為藉由無殘渣助焊劑之製造方法的一例。從第1圖中，可知A與B的較大差異為回焊(第1圖中記載為「Reflow」)後的溫度。如A所示，於回焊後冷卻至室溫時，於冷卻時會變得容易產生凸塊斷裂。相對於此，如B所示，於回焊後不冷卻至室溫，而是於100至120℃(第1圖中為110℃)填充底填料，藉此可抑制凸塊斷裂的產生。 As a method to suppress the occurrence of this bump fracture, it is explored to not cool to room temperature after welding, but after cooling to 100 to 120°C, fill the underfill at 100 to 120°C, and then A manufacturing method for hardening an underfill at 130 to 160°C (hereinafter referred to as a manufacturing method by a residue-free flux) (Non-Patent Document 1). With this manufacturing method using residue-free flux, the stress caused by the difference in thermal expansion between the semiconductor chip and the substrate after soldering can be reduced, and the manufacturing steps can be shortened. On the other hand, in such a manufacturing method using a residue-free flux, since the flux residue cannot be cleaned after soldering, a residue-free flux is required. Fig. 1 shows an example of the manufacturing method by non-residue flux Figure. A in Fig. 1 is an example of a conventional manufacturing process, and B is an example of a manufacturing method using a residue-free flux. From Figure 1, it can be seen that the larger difference between A and B is the temperature after reflow (described as "Reflow" in Figure 1). As shown in A, when it is cooled to room temperature after reflowing, it will become easy to produce bump fracture during cooling. On the other hand, as shown in B, the underfill is filled at 100 to 120°C (110°C in the first figure) instead of cooling to room temperature after reflow, thereby suppressing bump fracture.
作為焊接用的無殘渣助焊劑，係揭示有一種助焊劑組成物(專利文獻1)，其特徵係：含有庚二酸、以及第1及第2有機溶劑，上述第2有機溶劑具有較上述第1溶劑高的沸點，上述庚二酸及上述第2有機溶劑可溶於上述第1有機溶劑。 As a residue-free flux for soldering, a flux composition is disclosed (Patent Document 1), which is characterized by containing pimelic acid, and first and second organic solvents. The second organic solvent has a higher 1 The solvent has a high boiling point, and the pimelic acid and the second organic solvent are soluble in the first organic solvent.
然而，將含有庚二酸之助焊劑組成物使用在藉由無殘渣助焊劑之製造方法時，於焊接後會殘留助焊劑殘渣，而有無法適當地注入底填料之問題。目前，於市面上並未販售可使用在不冷卻至室溫的方法之無殘渣助焊劑。 However, when the flux composition containing pimelic acid is used in a non-residue flux manufacturing method, flux residue will remain after soldering, and there is a problem that the underfill cannot be properly injected. At present, there is no residue-free flux that can be used in a method that does not cool to room temperature.
而且，亦揭示有一種含有特定的羧酸成分、特定的胺成分及特定的溶劑之儲存穩定性的凝膠(專利文獻2)。然而，該凝膠當使用在大小為10mm見方以上之倒裝晶片的焊接時，會有殘留多量的殘渣，羧酸成分未完全溶解於凝膠以及凝膠不平滑之問題。 Furthermore, a storage-stable gel containing a specific carboxylic acid component, a specific amine component, and a specific solvent is also disclosed (Patent Document 2). However, when the gel is used for soldering flip-chips with a size of 10 mm or more, a large amount of residue remains, the carboxylic acid component is not completely dissolved in the gel and the gel is not smooth.
[專利文獻1]日本特開平07-323390號公報 [Patent Document 1] Japanese Patent Application Publication No. 07-323390
[專利文獻2]日本特表2009-514683號公報 [Patent Document 2] JP 2009-514683 A
[非專利文獻1]「No Clean Flux Technology for Large Die Flip Chip Packages」 , Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd, 2013年5月28至31日, 688至693頁 [Non-Patent Document 1] "No Clean Flux Technology for Large Die Flip Chip Packages", Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd, May 28 to 31, 2013, pages 688 to 693
本發明之目的在於提供一種可使用在下述製造方法之無殘渣助焊劑，該製造方法係於焊接後不冷卻至室溫，而是冷卻至100至120℃後，於100至120℃填充底填料後，使底填料硬化。 The purpose of the present invention is to provide a residue-free flux that can be used in the following manufacturing method. The manufacturing method does not cool to room temperature after soldering, but after cooling to 100 to 120°C, fill the underfill at 100 to 120°C After that, the underfill is hardened.
本發明係關於藉由具有以下構成來解決上述課題之無殘渣助焊劑，及半導體封裝件之製造方法。 The present invention relates to a residue-free flux that solves the above-mentioned problems by having the following constitution, and a method of manufacturing a semiconductor package.
[1]一種無殘渣助焊劑，其係使用在下述半導體封裝步驟中：於室溫下，將無殘渣助焊劑塗佈在形成於半導體晶片之焊料凸塊與形成於基板之經鍍焊的配線之間，將形成於半導體晶片之焊料凸塊、與形成於基板之經鍍焊的配線，於240至270℃進行焊接後， 冷卻至100至120℃，保持在100至120℃，將底填料填充於半導體晶片與基板之間，並於130至160℃使底填料硬化；該無殘渣助焊劑含有：(A)乙二醇單苯醚、2-乙基-1,3-己烷二醇、或2-乙基-1,3-己烷二醇：異莰基己醇(重量比)=1：1之混合溶劑，以及(B)草酸、琥珀酸、己二酸、或1,2,4-環己烷三羧酸，惟，排除(A)2-乙基-1,3-己烷二醇與(B)已二酸之組合；並且相對於無殘渣助焊劑100質量份，含有0.3至3.0質量份的(B)成分。 [1] A residue-free flux, which is used in the following semiconductor packaging steps: at room temperature, the residue-free flux is applied to the solder bumps formed on the semiconductor chip and the soldered wiring formed on the substrate In between, the solder bumps formed on the semiconductor chip and the plated and soldered wiring formed on the substrate are soldered at 240 to 270°C, Cool to 100 to 120°C, keep it at 100 to 120°C, fill the underfill between the semiconductor wafer and the substrate, and harden the underfill at 130 to 160°C; the residue-free flux contains: (A) ethylene glycol Monophenyl ether, 2-ethyl-1,3-hexanediol, or 2-ethyl-1,3-hexanediol: isobornylhexanol (weight ratio) = 1:1 mixed solvent, And (B) oxalic acid, succinic acid, adipic acid, or 1,2,4-cyclohexanetricarboxylic acid, but exclude (A) 2-ethyl-1,3-hexanediol and (B) A combination of adipic acid; and contains 0.3 to 3.0 parts by mass of the component (B) relative to 100 parts by mass of the residue-free flux.
[2]如上述[1]所述之無殘渣助焊劑，更含有：(C)於熱重分析中，以升溫速度10℃/分測定時，質量減少至50%之溫度為130至170℃之三級胺。 [2] The residue-free flux as described in [1] above, further containing: (C) In thermogravimetric analysis, when measured at a temperature increase rate of 10°C/min, the temperature at which the mass is reduced to 50% is 130 to 170°C The tertiary amine.
[3]如上述[1]所述之無殘渣助焊劑，其中，(B)成分為脂肪族二羧酸。 [3] The residue-free flux as described in [1] above, wherein the component (B) is an aliphatic dicarboxylic acid.
[4]如上述[1]所述之無殘渣助焊劑，其中，(C)成分為三丁胺。 [4] The residue-free flux as described in [1] above, wherein the component (C) is tributylamine.
[5]如上述[1]所述之無殘渣助焊劑，其中，形成於半導體晶片之焊料凸塊的焊料為錫銀系。 [5] The residue-free flux according to the above [1], wherein the solder of the solder bumps formed on the semiconductor chip is tin-silver-based.
[6]如上述[1]所述之無殘渣助焊劑，其中，形成於基板之經鍍焊的配線的焊料為錫銀銅系。 [6] The residue-free flux according to the above [1], wherein the solder of the plated wiring formed on the substrate is a tin-silver-copper-based solder.
[7]一種半導體封裝件之製造方法，其係依序包含下述步驟： 於室溫下，將上述[1]所述之無殘渣助焊劑塗佈在形成於半導體晶片之焊料凸塊與形成於基板之經鍍焊的配線之間之步驟；將形成於半導體晶片之焊料凸塊與形成於基板之經鍍焊的配線於240至270℃進行焊接之步驟；冷卻至100至120℃之步驟；以及保持在100至120℃，將底填料填充於半導體晶片與基板之間，並於130至160℃使底填料硬化之步驟。 [7] A method of manufacturing a semiconductor package, which sequentially includes the following steps: At room temperature, the step of applying the residue-free flux described in [1] above between the solder bumps formed on the semiconductor chip and the soldered wiring formed on the substrate; the solder formed on the semiconductor chip The bump and the plated and soldered wiring formed on the substrate are soldered at 240 to 270°C; cooled to 100 to 120°C; and kept at 100 to 120°C, and underfill is filled between the semiconductor chip and the substrate , And the step of hardening the underfill at 130 to 160°C.
[8]如上述[7]所述之半導體封裝件之製造方法，包含：將形成於半導體晶片之焊料凸塊與形成於基板之經鍍焊的配線以升溫速度2.5至5.0℃/秒升溫，並於240至270℃進行30至70秒的焊接之步驟。 [8] The method for manufacturing a semiconductor package as described in [7] above, comprising: heating the solder bumps formed on the semiconductor chip and the plated and soldered wiring formed on the substrate at a heating rate of 2.5 to 5.0°C/sec, And at 240 to 270 ℃ for 30 to 70 seconds of welding step.
[9]如上述[7]所述之半導體封裝件之製造方法，在將形成於半導體晶片之焊料凸塊與形成於基板之經鍍焊的配線於240至270℃進行焊接之步驟後，包含以降溫速度1.0至3.0℃/秒冷卻至100至120℃之步驟。 [9] The method for manufacturing a semiconductor package as described in [7] above, after the step of soldering the solder bumps formed on the semiconductor chip and the plated and soldered wiring formed on the substrate at 240 to 270°C, including The step of cooling to 100 to 120°C at a cooling rate of 1.0 to 3.0°C/sec.
[10]一種半導體封裝件，其係藉由上述[7]所述之半導體封裝件之製造方法所製造。 [10] A semiconductor package manufactured by the method of manufacturing a semiconductor package described in [7] above.
根據本發明[1]，可提供一種可使用在下述製造方法之無殘渣助焊劑，該製造方法係於焊接後不冷卻至室溫，而是冷卻至100至120℃後，於100至120℃填充底填料後，使底填料硬化。 According to the present invention [1], it is possible to provide a residue-free flux that can be used in the following manufacturing method. The manufacturing method is not cooled to room temperature after soldering, but after cooling to 100 to 120°C, at 100 to 120°C After filling the underfill, the underfill is hardened.
根據本發明[7]，可簡便地製造出一種半導 體封裝件，其係對應於焊料凸塊、配線的窄間距化和多核化所造成之晶片的大型化者。 According to the present invention [7], a semiconductor The bulk package corresponds to the enlargement of the chip caused by the narrower pitch and multi-core of solder bumps and wiring.
根據本發明[10]，可提供一種半導體封裝件，其係對應於焊料凸塊、配線的窄間距化和多核化所造之晶片的大型化者。 According to the present invention [10], it is possible to provide a semiconductor package which corresponds to the enlargement of the chip produced by the narrower pitch and multi-core of solder bumps and wiring.
第1圖係說明藉由無殘渣助焊劑之製造方法的一例之圖。 Fig. 1 is a diagram illustrating an example of a manufacturing method using residue-free flux.
第2圖係用以說明本發明的半導體封裝件之製造方法之圖。 FIG. 2 is a diagram for explaining the manufacturing method of the semiconductor package of the present invention.
第3圖之上段為殘渣評估後之照片，下段為連接性評估後之照片。 The upper part of Figure 3 is the photo after the residue assessment, and the lower part is the photo after the connectivity assessment.
第4圖係顯示以藉由無殘渣助焊劑之製造方法所製作之比較例4之10mm見方與20mm見方的晶片之超音波顯微鏡(C-SAM)圖像。 Fig. 4 shows the ultrasonic microscope (C-SAM) images of the 10mm square and 20mm square wafers of Comparative Example 4 produced by the manufacturing method without residue flux.
本發明之無殘渣助焊劑，其係使用在下述半導體封裝步驟之無殘渣助焊劑：於室溫下，將無殘渣助焊劑塗佈在形成於半導體晶片之焊料凸塊與形成於基板之經鍍焊的配線之間，在將形成於半導體晶片之焊料凸塊與形成於基板之 經鍍焊的配線於240至270℃進行焊接，之後，冷卻至100至120℃，保持在100至120℃，將底填料填充於半導體晶片與基板之間，並於130至160℃使底填料硬化；其中含有：(A)於熱重分析中，以升溫速度10℃/分測定時，質量減少至50%之溫度(以下稱為T50)為160至210℃之溶劑，以及(B)於熱重分析中，以升溫速度10℃/分測定時，質量減少至50%之溫度為190至320℃之二羧酸或三羧酸；並且相對於無殘渣助焊劑100質量份，含有0.3至3.0質量份的(B)成分。本發明者們為了得到可滿足對於焊料凸塊、經鍍焊的配線之適當的活性力、揮發性，且於回焊後的助焊劑殘渣極少之助焊劑，係對助焊劑組成與回焊條件進行精心探討，而發現適合於藉由無殘渣助焊劑之製造方法的無殘渣助焊劑。在此，所謂對於焊料凸塊、經鍍焊的配線之適當的活性力，意指可去除焊料凸塊或經鍍焊的配線的氧化膜，且不會產生過剩的氣泡，可抑制焊料之空孔(void)的產生者。 The residue-free flux of the present invention is a residue-free flux used in the following semiconductor packaging steps: at room temperature, the residue-free flux is applied to the solder bumps formed on the semiconductor chip and the plated substrate Between the soldered wires, solder bumps formed on the semiconductor chip and plated soldered wires formed on the substrate at 240 to 270°C, then cool to 100 to 120°C and keep at 100 to 120°C, Fill the underfill between the semiconductor wafer and the substrate, and harden the underfill at 130 to 160°C; it contains: (A) In thermogravimetric analysis, the mass is reduced to 50% when measured at a temperature rise rate of 10°C/min. The temperature (hereinafter referred to as T 50 ) is 160 to 210°C for the solvent, and (B) in the thermogravimetric analysis, the temperature at which the mass is reduced to 50% when measured at a heating rate of 10°C/min is 190 to 320°C Dicarboxylic acid or tricarboxylic acid; and containing 0.3 to 3.0 parts by mass of (B) component relative to 100 parts by mass of residue-free flux. In order to obtain a flux that satisfies suitable activity and volatility for solder bumps and soldered wiring, and has very little flux residue after reflow, the composition of the flux and reflow conditions After careful discussion, a residue-free flux suitable for the manufacturing method of residue-free flux was found. Here, the proper activation force for solder bumps and plated and soldered wiring means that the oxide film of solder bumps or plated and soldered wiring can be removed without excessive air bubbles being generated, which can suppress solder voids. The creator of the void.
(A)成分，於無殘渣助焊劑中之主要作用係作為溶劑。(A)成分，係於熱重分析中以升溫速度10℃/分測定時質量減少至50%之溫度為160至210℃之溶劑。(A)成分可列舉出：乙二醇單苯醚(EPH、C6H5OCH2CH2OH、T50： 181℃)、2-乙基-1,3-己烷二醇(T50：189℃)、2-乙基-1,3-己烷二醇：異莰基己醇(Nippon Terpene Chemicals公司製Tersolve MTPH)=1：1之混合溶劑(T50：186℃)等，較佳為乙二醇單苯醚、2-乙基-1,3-己烷二醇、2-乙基-1,3-己烷二醇：異莰基己醇(Nippon Terpene Chemicals公司製Tersolve MTPH)=1：1之混合溶劑。 (A) The main role of component (A) in the residue-free flux is as a solvent. The component (A) is a solvent with a temperature of 160 to 210°C at which the mass is reduced to 50% when measured at a temperature increase rate of 10°C/min in thermogravimetric analysis. (A) Components include: ethylene glycol monophenyl ether (EPH, C 6 H 5 OCH 2 CH 2 OH, T 50 : 181° C.), 2-ethyl-1,3-hexanediol (T 50 ：189℃), 2-ethyl-1,3-hexanediol: isocamylhexanol (Tersolve MTPH manufactured by Nippon Terpene Chemicals) = 1:1 mixed solvent (T 50 : 186℃), etc. Preferably, ethylene glycol monophenyl ether, 2-ethyl-1,3-hexanediol, 2-ethyl-1,3-hexanediol: isobornylhexanol (Tersolve MTPH manufactured by Nippon Terpene Chemicals) ) = 1: 1 mixed solvent.
而且，若從焊料的連接性之觀點來看，(A)成分係以就於熱重分析中以升溫速度10℃/分測定時質量減少至50%之溫度而言，為160至190℃之溶劑與200至240℃之溶劑(例如異莰基己醇(T50：234℃))之混合溶劑為較佳。尤其，當使用20mm見方等級之較大的半導體晶片時，(A)之160至190℃之溶劑與200至240℃之溶劑的混合溶劑之質量比較佳為1：(2以下)，更佳為1：(0.1至2)，又更佳為1：(0.5至2)。又，160至190℃之溶劑與200至240℃之溶劑的混合溶劑之質量比為1：(4至5)時，以升溫速度10℃/分測定時質量減少至50%之溫度容易高於190℃(亦即，容易變成非(A)成分)，而變得容易殘留殘渣。而且，相對於無殘渣助焊劑100質量份，(A)成分較佳為95至99.7質量份，更佳為97至99.5質量份。 Moreover, from the viewpoint of solder connectivity, component (A) is based on the temperature at which the mass decreases to 50% when measured at a temperature increase rate of 10°C/min in thermogravimetric analysis, which is 160 to 190°C A mixed solvent of a solvent and a solvent of 200 to 240°C (for example, isocamylhexanol (T 50 : 234°C)) is preferred. In particular, when using a larger semiconductor wafer of 20mm square grade, the quality of the mixed solvent of (A) 160 to 190°C solvent and 200 to 240°C solvent is preferably 1: (2 or less), more preferably 1: (0.1 to 2), more preferably 1: (0.5 to 2). In addition, when the mass ratio of the mixed solvent of the solvent at 160 to 190°C and the solvent at 200 to 240°C is 1: (4 to 5), the temperature at which the mass decreases to 50% when measured at a heating rate of 10°C/min is easily higher than 190°C (that is, it is easy to become a non-(A) component), and residues tend to remain. Furthermore, with respect to 100 parts by mass of the residue-free flux, the component (A) is preferably from 95 to 99.7 parts by mass, more preferably from 97 to 99.5 parts by mass.
(B)成分，於無殘渣助焊劑中之主要作用係作為活性劑。(B)成分，係於熱重分析中，以升溫速度10℃/分測定時質量減少至50%之溫度為190至320℃之二羧酸或三羧酸。(B)成分主要係作為活性劑發揮作用。(B)成分可列舉出：草酸(HOOCCOOH、T50：195℃)、琥珀酸 (HOOC(CH2)2COOH、T50：230℃)、己二酸(HOOC(CH2)4COOH、T50：268℃)、1,2,4-環己烷三羧酸(H-TMA、T50：310℃)，較佳為草酸、琥珀酸、己二酸、1,2,4-環己烷三羧酸。在此，列舉作為(B)成分之化合物雖為固體，但從於無殘渣助焊劑之均勻分散性之觀點來看，係以可溶解於(A)成分者為較佳。(B)成分係以脂肪族二羧酸為更佳。 (B) The main function of component (B) in the residue-free flux is to act as an active agent. The component (B) is a dicarboxylic acid or tricarboxylic acid whose mass is reduced to 50% at a temperature of 190 to 320°C when measured at a temperature increase rate of 10°C/min in thermogravimetric analysis. The component (B) mainly functions as an active agent. (B) Components include: oxalic acid (HOOCCOOH, T 50 : 195°C), succinic acid (HOOC(CH 2 ) 2 COOH, T 50 : 230°C), adipic acid (HOOC(CH 2 ) 4 COOH, T 50 : 268°C), 1,2,4-cyclohexane tricarboxylic acid (H-TMA, T 50 : 310°C), preferably oxalic acid, succinic acid, adipic acid, 1,2,4-cyclohexane Alkyl tricarboxylic acid. Here, although the compound cited as the component (B) is solid, from the viewpoint of uniform dispersibility of the residue-free flux, it is preferable to be soluble in the component (A). The component (B) is preferably an aliphatic dicarboxylic acid.
相對於無殘渣助焊劑100質量份，係含有(B)成分0.3至3.0質量份，較佳為含有0.5至3.0質量份。未達0.3質量份時，連接性容易變差，超過3.0質量份時，容易殘留殘渣。 It contains 0.3 to 3.0 parts by mass of the component (B), preferably 0.5 to 3.0 parts by mass with respect to 100 parts by mass of the residue-free flux. If it is less than 0.3 parts by mass, the connectivity is likely to deteriorate, and if it exceeds 3.0 parts by mass, residues are likely to remain.
無殘渣助焊劑，從(B)成分的溶解穩定性之觀點來看，較佳為更含有(C)於熱重分析中，以升溫速度10℃/分測定時質量減少至50%之溫度為130至170℃之三級胺者，更佳為更含有三丁胺。當(B)成分不易溶解於(A)成分時，可較佳地使用(C)成分。(C)成分之主要作用係作為活性劑。 Residue-free flux. From the viewpoint of the solubility stability of the component (B), it is better to contain (C) in the thermogravimetric analysis, and the temperature at which the mass decreases to 50% when measured at a temperature rise rate of 10°C/min is The tertiary amine at 130 to 170°C more preferably contains tributylamine. When the component (B) is not easily dissolved in the component (A), the component (C) can be preferably used. The main function of component (C) is to act as an active agent.
相對於(B)成分的質量，(C)成分較佳為10倍以下，更佳為5倍以下，又更佳為2倍以下。(C)成分多於10倍時，則有焊料的連接性變差之疑慮。此外，相對於(B)成分的質量，(C)成分為0.5倍以上時，則容易發揮添加的效果。 With respect to the mass of the (B) component, the (C) component is preferably 10 times or less, more preferably 5 times or less, and still more preferably 2 times or less. (C) When the component is more than 10 times, there is a concern that the solder connectivity will deteriorate. In addition, when the (C) component is 0.5 times or more the mass of the (B) component, the effect of the addition can be easily exhibited.
在不損及本發明的目的之範圍內，無殘渣助焊劑可進一步視所需調配添加劑等。 In the range that does not impair the purpose of the present invention, the residue-free flux can be further equipped with additives and the like as required.
無殘渣助焊劑，係適合形成於半導體晶片之焊料凸塊的焊料為錫銀系之情形。而且，無殘渣助焊劑，係適合於形成於基板之經鍍焊的配線的焊料為錫銀銅系之情形。 The residue-free flux is suitable for the case where the solder of the solder bump formed on the semiconductor chip is tin-silver. In addition, the residue-free flux is suitable for the case where the solder of the plated wiring formed on the substrate is a tin-silver-copper system.
底填料並無特別限定，以下係說明較佳的底填料之環氧樹脂組成物。底填料較佳係至少含有(UA)環氧樹脂以及(UB)硬化劑。 The underfill is not particularly limited, and the epoxy resin composition of the preferable underfill is described below. The underfill preferably contains at least (UA) epoxy resin and (UB) hardener.
(UA)成分，可列舉出雙酚A型環氧樹脂、溴化雙酚A型環氧樹脂、雙酚F型環氧樹脂、萘型環氧樹脂、聯苯型環氧樹脂、酚醛清漆型環氧樹脂、胺基酚系環氧樹脂、脂環型環氧樹脂、醚系或聚醚系環氧樹脂、含環氧乙烷環之環氧樹脂等，從底填料的玻璃轉移點、耐回焊性及耐濕性之觀點來看，較佳為雙酚F型環氧樹脂、胺基酚系環氧樹脂、雙酚A型環氧樹脂、萘型環氧樹脂。 (UA) components include bisphenol A type epoxy resin, brominated bisphenol A type epoxy resin, bisphenol F type epoxy resin, naphthalene type epoxy resin, biphenyl type epoxy resin, novolak type Epoxy resin, aminophenol epoxy resin, alicyclic epoxy resin, ether or polyether epoxy resin, epoxy resin containing ethylene oxide ring, etc., from the glass transition point of the underfill, resistant From the viewpoint of reflow properties and moisture resistance, bisphenol F epoxy resin, aminophenol epoxy resin, bisphenol A epoxy resin, and naphthalene epoxy resin are preferred.
雙酚F型環氧樹脂，較佳係以式(1)所示者：
式中，n表示平均值，較佳為0至6，更佳為0至3。環氧當量較佳為150至900g/eq。 In the formula, n represents an average value, preferably 0-6, more preferably 0-3. The epoxy equivalent is preferably 150 to 900 g/eq.
胺基酚系環氧樹脂，較佳係以式(2)所示者：
更佳為2個官能基係鄰位或對位。 More preferably, the two functional groups are ortho-position or para-position.
雙酚A型環氧樹脂，較佳係以式(3)所示者：
式中，m表示平均值，可列舉出較佳為0至6，特佳為0至3之環氧樹脂。環氧當量較佳為170至1000g/eq。 In the formula, m represents an average value, and epoxy resins preferably from 0 to 6, particularly preferably from 0 to 3 can be cited. The epoxy equivalent is preferably 170 to 1000 g/eq.
(UA)成分可單獨使用或併用2種以上。 The component (UA) can be used alone or in combination of two or more kinds.
(UB)成分，可列舉出胺系硬化劑、酸酐系硬化劑、酚系硬化劑等，從底填料的耐回焊性及耐濕性之觀點來看，較佳為胺系硬化劑。 The (UB) component includes amine hardeners, acid anhydride hardeners, phenol hardeners, and the like. From the viewpoint of reflow resistance and moisture resistance of the underfill, an amine hardener is preferred.
胺系硬化劑，可列舉出脂肪族多胺；芳香族胺；聚胺基醯胺、聚胺基醯亞胺、聚胺基酯及聚胺基脲等改質多胺；三級胺系；咪唑系；醯肼系；二氰醯胺系；三聚氰胺系之化合物等，較佳為芳香族胺系化合物。 Amine hardeners include aliphatic polyamines; aromatic amines; modified polyamines such as polyaminoamides, polyaminoimines, polyurethane esters, and polyaminoureas; tertiary amines; The imidazole series; the hydrazine series; the dicyanamide series; the melamine series compound, etc., preferably an aromatic amine series compound.
芳香族胺系化合物，更佳為包含具有1個芳香族環之芳香族胺化合物及/或具有2個芳香族環之芳香族胺化合物。 The aromatic amine compound more preferably includes an aromatic amine compound having one aromatic ring and/or an aromatic amine compound having two aromatic rings.
具有1個芳香族環之芳香族胺化合物，可列舉出間伸苯二胺等，較佳係以式(4)或式(5)所示者：
具有2個芳香族環之芳香族胺化合物，可列舉出二胺基二苯基甲烷、二胺基二苯基碸等，較佳係以式(6)或式(7)所示者：
(式中，R表示氫、或碳數1至5個的烷基)，更佳為以式(6)或式(7)所示且R碳數為2個的烷基者。 (In the formula, R represents hydrogen or an alkyl group having 1 to 5 carbon atoms), more preferably an alkyl group represented by formula (6) or formula (7) and R having 2 carbon atoms.
(UB)成分可單獨使用或併用2種以上。 The component (UB) can be used alone or in combination of two or more kinds.
從硬化後之底填料的熱膨脹係數之觀點來看，底填料係以更含有(UC)填充材料為佳。(UC)成分，可列舉出氧化矽、氧化鋁、氮化矽、雲母、白碳等，從硬化後之底填料的熱膨脹係數降低及成本之觀點來看，較佳為氧化矽。氧化矽，可使用非晶質氧化矽、結晶性氧化矽、熔融氧化矽、粉碎氧化矽、奈米氧化矽等該領域所使用之各種氧化矽，從硬化後之底填料的熱膨脹係數降低之觀點來看，較佳為非晶質氧化矽。從對於半導體晶片與基板之間隙的填充性之觀點來看，(C)成分的粒徑較佳為0.1至2.0μm，更佳為0.1至1.0μm。在此，平均粒徑係藉由雷射繞射式粒度分布測定裝置所測定。此外，(C)成分的形狀並無特別限定，可列舉出球狀、鱗片狀、非定形等，從密封用液狀樹脂組成物的流動性之觀點來看，較佳為球狀。 From the viewpoint of the thermal expansion coefficient of the underfill after hardening, it is better that the underfill contains (UC) filler. The (UC) component includes silicon oxide, aluminum oxide, silicon nitride, mica, white carbon, etc., and from the viewpoint of the reduction of the thermal expansion coefficient of the underfill after hardening and the cost, silicon oxide is preferred. For silica, various types of silica used in this field, such as amorphous silica, crystalline silica, fused silica, crushed silica, nano-silica, etc., can be used. From the viewpoint of lowering the thermal expansion coefficient of the underfill after curing In view of this, amorphous silicon oxide is preferred. From the viewpoint of filling properties of the gap between the semiconductor wafer and the substrate, the particle size of the component (C) is preferably 0.1 to 2.0 μm, and more preferably 0.1 to 1.0 μm. Here, the average particle size is measured by a laser diffraction particle size distribution measuring device. Moreover, the shape of (C) component is not specifically limited, A spherical shape, a scaly shape, an amorphous shape, etc. are mentioned, From the viewpoint of the fluidity of the liquid resin composition for sealing, a spherical shape is preferable.
(UC)成分可單獨使用或併用2種以上。 (UC) Components can be used alone or in combination of two or more kinds.
從底填料的玻璃轉移點、耐回焊性、及耐濕性之觀點來看，較佳係底填料中相對於成分(UA)100質量份，含有成分(UB)20至100質量份，更佳係含有40至60質量份。 From the viewpoints of the glass transition point, reflow resistance, and moisture resistance of the underfill, it is preferable that the underfill contains 20 to 100 parts by mass of the component (UB) relative to 100 parts by mass of the component (UA), and more The best one contains 40 to 60 parts by mass.
而且，從底填料的流動性、及硬化後之底填料的熱膨脹係數降低之觀點來看，較佳係相對於成分(UA)100質量份，含有成分(UC)160至400質量份，更佳係含有200至350質量份。 Moreover, from the viewpoint of the fluidity of the underfill and the reduction in the thermal expansion coefficient of the underfill after curing, it is preferable to contain 160 to 400 parts by mass of the component (UC) relative to 100 parts by mass of the component (UA), and more preferably It contains 200 to 350 parts by mass.
於底填料中，在不損及本發明的目的之範圍內，可進一步視所需調配碳黑等顏料、染料、矽烷偶合 劑、消泡劑、抗氧化劑、其他添加劑等，以及有機溶劑等。 In the underfill, within the scope that does not impair the purpose of the present invention, pigments such as carbon black, dyes, and silane coupling Agents, defoamers, antioxidants, other additives, etc., and organic solvents.
底填料，例如可藉由同時或分別地將(UA)成分至(UC)成分及其他添加劑等視所需一邊進行加熱處理一邊進行攪拌、熔融、混合、分散而得到。此等混合、攪拌、分散等之裝置並無特別限定，可使用具備攪拌、加熱裝置之擂碎機、三輥磨機、球磨機、行星式混合機、珠磨機等。而且，可適當地組合此等裝置而使用。 The underfill material can be obtained, for example, by simultaneously or separately mixing (UA) component to (UC) component, other additives, etc., while performing heating treatment, and stirring, melting, mixing, and dispersing as necessary. The devices for mixing, stirring, dispersing, etc. are not particularly limited, and crushers, three-roll mills, ball mills, planetary mixers, bead mills, etc. equipped with stirring and heating devices can be used. Moreover, these devices can be combined and used appropriately.
底填料，以於溫度：25℃的黏度係1至100Pa‧s為較佳。在此，黏度係以Brookfield公司製的黏度計(型號：DV-1)來測定。 For the underfill, the viscosity at a temperature of 25°C is preferably from 1 to 100 Pa‧s. Here, the viscosity is measured with a viscometer (model: DV-1) manufactured by Brookfield Corporation.
底填料的硬化，較佳係於130至160℃進行90至150分鐘。 The curing of the underfill is preferably carried out at 130 to 160°C for 90 to 150 minutes.
本發明之半導體封裝件之製造方法，係依序包含下述步驟：於室溫下，將上述無殘渣助焊劑塗佈在形成於半導體晶片之焊料凸塊與形成於基板之經鍍焊的配線之間之步驟；將形成於半導體晶片之焊料凸塊與形成於基板之經鍍焊的配線，於240至270℃進行焊接之步驟；冷卻至100至120℃之步驟；以及保持在100至120℃，將底填料填充於半導體晶片與基板之間，並於130至160℃使底填料硬化之步驟。第2圖係用以說明本發明之半導體封裝件之製造方法之圖。如 第2圖所示，本發明之半導體封裝件之製造方法，係依序包含下述步驟：於室溫下，將上述無殘渣助焊劑塗佈在形成於半導體晶片之焊料凸塊與形成於基板之經鍍焊的配線之間之步驟；將形成於半導體晶片之焊料凸塊與形成於基板之經鍍焊的配線，於240至270℃進行焊接之步驟(第2圖的(1))；冷卻至100至120℃之步驟(第2圖的(1)與(2)之間)；以及保持在100至120℃(第2圖的(2))，將底填料填充於半導體晶片與基板之間，並於130至160℃使底填料硬化之步驟(第2圖的(3))。 The manufacturing method of the semiconductor package of the present invention sequentially includes the following steps: at room temperature, the above-mentioned residue-free flux is applied to the solder bumps formed on the semiconductor chip and the soldered wiring formed on the substrate The steps between; the solder bumps formed on the semiconductor chip and the plated and soldered wiring formed on the substrate are soldered at 240 to 270°C; the step is cooled to 100 to 120°C; and kept at 100 to 120 ℃, filling the underfill between the semiconductor wafer and the substrate, and hardening the underfill at 130 to 160℃. FIG. 2 is a diagram for explaining the manufacturing method of the semiconductor package of the present invention. Such as As shown in Figure 2, the manufacturing method of the semiconductor package of the present invention includes the following steps in sequence: at room temperature, the above-mentioned residue-free flux is applied to the solder bumps formed on the semiconductor chip and formed on the substrate The step between soldering and plating wiring; the step of soldering the solder bumps formed on the semiconductor chip and the soldered wiring formed on the substrate at 240 to 270°C ((1) in Figure 2); The step of cooling to 100 to 120°C (between (1) and (2) in Figure 2); and keeping it at 100 to 120°C ((2) in Figure 2), and filling the underfill material on the semiconductor wafer and substrate In between, the step of hardening the underfill at 130 to 160°C ((3) in Figure 2).
塗佈在形成於半導體晶片之焊料凸塊與形成於基板之經鍍焊的配線之間之上述無殘渣助焊劑的量，較佳為0.02至0.08mg/mm2，最佳為0.04mg/mm2。 The amount of the above-mentioned residue-free flux applied between the solder bumps formed on the semiconductor chip and the soldered wiring formed on the substrate is preferably 0.02 to 0.08 mg/mm 2 , most preferably 0.04 mg/mm 2 .
在將形成於半導體晶片之焊料凸塊與形成於基板之經鍍焊的配線於240至270℃進行焊接之步驟中，無殘渣助焊劑較佳係存在於產生焊料潤濕不久前為止，且在焊料接合後揮發。從無殘渣助焊劑的揮發動作之觀點來看，較佳係以升溫速度2.5至5.0℃/秒升溫，並於240至270℃進行30至70秒的焊接之步驟。 In the step of soldering the solder bumps formed on the semiconductor chip and the plated and soldered wiring formed on the substrate at 240 to 270°C, the residue-free flux is preferably present shortly before the occurrence of solder wetting, and The solder volatilizes after joining. From the viewpoint of the volatilization action of the flux-free flux, it is preferable to perform a step of heating at a heating rate of 2.5 to 5.0°C/sec and performing a soldering process at 240 to 270°C for 30 to 70 seconds.
在將形成於半導體晶片之焊料凸塊與形成於基板之經鍍焊的配線於240至270℃進行焊接之步驟後，冷卻至100至120℃之步驟，降溫速度係以1.0至3.0℃/秒為較佳。降溫速度低於1.0℃/秒時，則生產性變差， 降溫速度高於3.0℃/秒時，則會有良率變差之疑慮。 After the step of soldering the solder bumps formed on the semiconductor chip and the plated and soldered wiring formed on the substrate at 240 to 270°C, the step of cooling to 100 to 120°C, the cooling rate is 1.0 to 3.0°C/sec For better. When the temperature drop rate is less than 1.0°C/sec, the productivity will deteriorate. When the cooling rate is higher than 3.0°C/sec, there is a concern that the yield rate will deteriorate.
基板可列舉出環氧樹脂、玻璃-環氧樹脂、聚醯亞胺樹脂等，惟並不限定於此等。從環境問題來看，形成於基板之經鍍焊的配線的焊料較佳為無鉛焊料合金之錫銀銅系。形成於半導體晶片之焊料凸塊，可使用包含錫、鉛、銅、鉍、銀、鋅、銦等之銲錫合金等，從環境問題來看，較佳為無鉛焊料合金之錫銀系。 Examples of the substrate include epoxy resin, glass-epoxy resin, polyimide resin, etc., but are not limited to these. In view of environmental issues, the solder of the plated wiring formed on the substrate is preferably a lead-free solder alloy of tin, silver, and copper. The solder bumps formed on semiconductor chips can be solder alloys containing tin, lead, copper, bismuth, silver, zinc, indium, etc., and from the viewpoint of environmental issues, lead-free solder alloys of tin-silver are preferred.
以下係藉由實施例來說明本發明，但本發明並不限定於此等。又，以下的實施例中，份、%在未特別言明時，表示重量份、重量%。 The following examples illustrate the present invention, but the present invention is not limited to these. In addition, in the following examples, parts and% indicate parts by weight and% by weight unless otherwise specified.
以第1表至第3表所示之調配比率，使用超音波洗淨機進行混合，調製無殘渣助焊劑。第1表、第3表中，將2-乙基-1,3-己烷二醇記載為「二醇」，將異莰基己醇記載為「MTPH」。而且，係以如下方式調製底填料。使用三輥磨機混合新日鐵住金化學公司製的雙酚F型環氧樹脂(品名：YDF8170)：16.3質量份、三菱化學公司製的胺基酚型環氧樹脂(品名：EP630)：10.9質量份、日本化藥公司製的胺系硬化劑(品名：Kayahard A-A)：12.5質量份、Admatechs公司製的氧化矽填料(品名：SO-E2、平均粒徑：0.5μm)：60.0質量份以及信越化學公司製的矽烷偶合劑(品名：KBM403)，調製底填料。又，比較例3所使用之二羧酸甲 酯混合物(DBE)為CH3OOC(CH2)nCOOCH3(n=2至4)。 Use an ultrasonic cleaner to mix with the mixing ratio shown in Table 1 to Table 3 to prepare a residue-free flux. In Tables 1 and 3, 2-ethyl-1,3-hexanediol is described as "diol" and isobornylhexanol is described as "MTPH". In addition, the underfill was prepared as follows. A three-roll mill was used to mix bisphenol F epoxy resin (product name: YDF8170) manufactured by Nippon Steel & Sumitomo Chemical Corporation: 16.3 parts by mass, and aminophenol epoxy resin manufactured by Mitsubishi Chemical Corporation (product name: EP630): 10.9 Parts by mass, amine hardener manufactured by Nippon Kayaku Corporation (product name: Kayahard AA): 12.5 parts by mass, silica filler manufactured by Admatechs (product name: SO-E2, average particle size: 0.5 μm): 60.0 parts by mass, and The silane coupling agent (product name: KBM403) manufactured by Shin-Etsu Chemical Co., Ltd. was used to prepare an underfill. In addition, the methyl dicarboxylate mixture (DBE) used in Comparative Example 3 is CH 3 OOC(CH 2 ) n COOCH 3 (n=2 to 4).
使用所調製之無殘渣助焊劑、底填料，以下述方式製作半導體封裝件。於10mm見方的半導體晶片，係使用Walts股份有限公司製的晶片(品名：WALTS-TEG FC150JY_LF(PI)□10mm)；於20mm見方的半導體晶片，係使用Walts股份有限公司製的晶片(品名：WALTS-TEG FC150JY_LF(PI)□20mm)；於10mm見方的基板，係使用Walts股份有限公司製的基板(品名：WALTS-KIT 01A150P-10(SAC))；於20mm見方的基板，係使用Walts股份有限公司製的基板(品名：WALTS-KIT FC150-0103JY_2×2(SAC))。 Using the prepared residue-free flux and underfill material, a semiconductor package was produced in the following manner. The semiconductor chip of 10mm square is made by Walts Co., Ltd. (product name: WALTS-TEG FC150JY_LF(PI) □ 10mm); the semiconductor chip of 20mm square is made of Walts Co., Ltd. (product name: WALTS -TEG FC150JY_LF(PI)□20mm); for a 10mm square substrate, use the substrate made by Walts Co., Ltd. (product name: WALTS-KIT 01A150P-10(SAC)); for a 20mm square substrate, use Walts Limited The company's board (product name: WALTS-KIT FC150-0103JY_2×2(SAC)).
首先，於N2氣體環境中，將基板於130℃烘烤2小時。接著，以刷毛將無殘渣助焊劑塗佈於基板的構裝部。半導體晶片，係將構裝部於Ar氣體環境中以400W進行5分鐘的電漿處理。 First, in a N 2 gas environment, the substrate is baked at 130°C for 2 hours. Next, the residue-free flux is applied to the assembly part of the substrate with a brush. The semiconductor wafer is subjected to plasma processing at 400W for 5 minutes in an Ar atmosphere.
將半導體晶片構裝於基板。構裝，係使用Panasonic Factory Solutions股份有限公司製的構裝機(型號：FCB3)，在接頭溫度：25℃、承載台溫度：25℃、負重：36.5N(每1個凸塊為1g)、負重保持時間：5秒之條件下進行。接著，於N2氣體環境中進行回焊。回焊係藉由：以升溫速度4.0℃/秒升溫至260℃，並於260℃進行45秒的焊接之步驟；以及以降溫速度2.2℃/秒冷卻至200℃之步驟來進行。 The semiconductor wafer is assembled on the substrate. The assembly uses the assembly machine (model: FCB3) manufactured by Panasonic Factory Solutions Co., Ltd., at the joint temperature: 25°C, the bearing table temperature: 25°C, the load: 36.5N (1 g per bump), and the load Hold time: under the condition of 5 seconds. Next, reflow is performed in a N 2 gas environment. The reflow is carried out by the steps of heating up to 260°C at a heating rate of 4.0°C/sec, and performing soldering at 260°C for 45 seconds; and cooling to 200°C at a cooling rate of 2.2°C/sec.
於構裝後，剝開半導體晶片與基板，並使用CCD攝影機，以200倍分別觀察半導體晶片側的殘渣與基板側的殘渣。第3圖的上段係顯示殘渣評估後之照片。如第3圖的左側所示，以完全未觀察到殘渣物、滲入者為「◎」，以觀察到非常多的殘渣物、滲入者為「××」，並將「◎」到「××」之間分成「○」、「△」、「×」三個階段。於第1表至第3表係表示結果。此外，第4圖係表示以藉由無殘渣助焊劑之製造方法所製作之比較例4的10mm見方與20mm見方的晶片之超音波顯微鏡(C-SAM)圖像。此時，係以上述條件進行焊接後，冷卻至110℃，並保持在110℃，將底填料填充於半導體晶片與基板之間，於150℃硬化120分鐘。從第4圖中可知，與於10mm見方的晶片者相比，於20mm見方的晶片者係觀察到較多量的殘渣。 After the assembly, peel off the semiconductor wafer and the substrate, and use a CCD camera to observe the residue on the semiconductor wafer side and the residue on the substrate side at 200 times. The upper part of Figure 3 shows the photo after the residue evaluation. As shown on the left side of Fig. 3, the residues are not observed at all, and those who infiltrate are regarded as "◎", and the residues are observed very much, and those who infiltrate are regarded as "××", and set "◎" to "×× "Is divided into three stages: "○", "△" and "×". The results are shown in Table 1 to Table 3. In addition, Fig. 4 shows the ultrasonic microscope (C-SAM) images of the 10mm square and 20mm square wafers of Comparative Example 4 produced by the manufacturing method without residue flux. At this time, after the soldering is performed under the above conditions, it is cooled to 110°C and maintained at 110°C, the underfill is filled between the semiconductor wafer and the substrate, and cured at 150°C for 120 minutes. It can be seen from Fig. 4 that a larger amount of residue was observed for a 20mm square wafer compared to a 10mm square wafer.
構裝後，使用DAGE公司製的X射線檢查裝置(型號：XD7600NT)，觀察半導體晶片的凸塊與基板的焊墊是否連接。第3圖的下段係顯示殘渣評估後之照片。第3圖的左側為連接良好之情形(實施例11)，第3圖的右側為連接不良之情形。連接良好之情形，為焊料熔融而使凸塊與焊墊形成一體。相對於此，連接不良之情形，為凸塊與焊墊未熔融，凸塊與焊墊呈點接觸之狀態。連接性(%)係以[(連接凸塊數)/(全體凸塊數)×100]來計算。結果示於第1表至第3 表。 After the assembly, an X-ray inspection device (model: XD7600NT) manufactured by DAGE was used to observe whether the bumps of the semiconductor wafer were connected to the pads of the substrate. The lower part of Figure 3 shows the photo after the residue evaluation. The left side of Fig. 3 shows a good connection (Example 11), and the right side of Fig. 3 shows a bad connection. When the connection is good, the bumps and the pads are integrated for the solder to melt. In contrast, when the connection is poor, the bump and the pad are not melted, and the bump and the pad are in point contact. Connectivity (%) is calculated by [(Number of connected bumps)/(Number of total bumps)×100]. The results are shown in Table 1 to 3 table.
從第1表至第3表可知，實施例1至14全部均無殘渣，且連接性亦良好。另外，在連續地進行：將形成於半導體晶片之焊料凸塊與形成於基板之經鍍焊的配線，於260℃進行焊接45秒之步驟；冷卻至110℃之步驟；以及保持在110℃，將底填料填充於半導體晶片與基板之間，並於150℃使底填料硬化之步驟，而進行試驗之結果，係可良好地使用底填料。相對於此，(B)成分過多之比較例 1於20mm見方的晶片係觀察到多量的殘渣物、滲入，(B)成分過少之比較例2係連接性差。使用二羧酸甲酯混合物來取代(A)成分之比較例3係連接性差，比較例4係於10mm見方觀察到多量的殘渣物、滲入，於20mm見方觀察到非常多量的殘渣物、滲入。 From Tables 1 to 3, it can be seen that all of Examples 1 to 14 are free of residue and have good connectivity. In addition, it is continuously performed: the solder bumps formed on the semiconductor wafer and the soldered wiring formed on the substrate are soldered at 260°C for 45 seconds; the step is cooled to 110°C; and the temperature is maintained at 110°C, The step of filling the underfill between the semiconductor wafer and the substrate, and hardening the underfill at 150°C, and the result of the test shows that the underfill can be used well. On the other hand, the comparative example with too many components (B) 1. A large amount of residues and infiltration were observed in a wafer system of 20 mm square, and Comparative Example 2 in which the component (B) was too small was poor in connectivity. Comparative Example 3 using a mixture of methyl dicarboxylates instead of component (A) had poor connectivity. Comparative Example 4 observed a large amount of residue and infiltration in a 10 mm square, and a very large amount of residue and infiltration in a 20 mm square.
將含有特定的羧酸成分、特定的胺成分及特定的溶劑之儲存穩定性的凝膠(專利文獻2)的實施例1、3至6，作為本發明的比較試驗來進行(比較例5至9)。此外，不使用記載為鑞等具體的製品名稱不明之原料。其結果係有合計為97質量份之情形。此外，由於上述儲存穩定性凝膠之實施例2的調配與實施例1類似，故不進行。 Examples 1, 3 to 6 of the storage stability gel containing a specific carboxylic acid component, a specific amine component, and a specific solvent (Patent Document 2) were conducted as a comparative test of the present invention (Comparative Examples 5 to 9). In addition, raw materials with unknown product names such as pewter are not used. As a result, it was 97 parts by mass in total. In addition, since the formulation of Example 2 of the storage stable gel is similar to that of Example 1, it is not carried out.
第4表係顯示此等之結果。從第4表中可 知，比較例5至9之含有特定的羧酸成分、特定的胺成分及特定的溶劑之儲存穩定性凝膠，均會殘留殘渣。 Table 4 shows these results. Available from Table 4 It is known that the storage stable gels containing specific carboxylic acid components, specific amine components, and specific solvents of Comparative Examples 5 to 9 all have residues.
用於參考，第5表係顯示於熱重分析中，以升溫速度10℃/分測定實施例、比較例所使用之材料時，質量減少1、50、99%之溫度。第5表中，有將2-乙基-1,3-己烷二醇記載為「二醇」，將異莰基己醇記載為「MTPH」。 For reference, Table 5 shows the temperature at which the mass is reduced by 1, 50, 99% when the materials used in the examples and comparative examples are measured at a heating rate of 10°C/min in the thermogravimetric analysis. In Table 5, 2-ethyl-1,3-hexanediol is described as "diol", and isobornylhexanol is described as "MTPH".
如上所述，本發明之無殘渣助焊劑因為無殘渣，所以可於焊接後不冷卻至室溫，而是冷卻至約110℃後，於同一溫度下填充底填料後，使底填料硬化。 As described above, since the residue-free flux of the present invention has no residue, it can be cooled to about 110°C without cooling to room temperature after soldering, and then filling the underfill at the same temperature to harden the underfill.
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| JP2004025305A (en) * | 2002-04-16 | 2004-01-29 | Tadatomo Suga | Residue-free solder paste |
| US6773958B1 (en) * | 2002-10-17 | 2004-08-10 | Altera Corporation | Integrated assembly-underfill flip chip process |
| TW201106434A (en) * | 2009-08-12 | 2011-02-16 | Renesas Electronics Corp | Method of manufacturing semiconductor device |
| TW201444438A (en) * | 2012-12-28 | 2014-11-16 | Kao Corp | Method for manufacturing circuit board to which electronic component is joined |
Also Published As
| Publication number | Publication date |
|---|---|
| JP6513950B2 (en) | 2019-05-15 |
| WO2016111142A1 (en) | 2016-07-14 |
| TW201634168A (en) | 2016-10-01 |
| JP2016124021A (en) | 2016-07-11 |
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