TWI697906B - Encoder built-in self-test circuit applied in flash memory controller and associated method - Google Patents

Encoder built-in self-test circuit applied in flash memory controller and associated method Download PDF

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TWI697906B
TWI697906B TW108136978A TW108136978A TWI697906B TW I697906 B TWI697906 B TW I697906B TW 108136978 A TW108136978 A TW 108136978A TW 108136978 A TW108136978 A TW 108136978A TW I697906 B TWI697906 B TW I697906B
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encoder
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flash memory
memory controller
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TW202015062A (en
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楊宗杰
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慧榮科技股份有限公司
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Abstract

The present invention provides an encoder BIST circuit applied in a flash memory controller, wherein the encoder BIST circuit includes a control circuit and an encoder. In the operations of the encoder BIST circuit, without accessing any flash memory, the control circuit generates input data to the encoder, and the encoder encodes the input data to generate a parity to the control circuit, wherein the parity is used to determine if functions of the encoder fail or not.

Description

應用於快閃記憶體控制器的編碼器自我測試電路及相關的方法Encoder self-test circuit and related method applied to flash memory controller

本發明係有關於快閃記憶體控制器，尤指一種應用在快閃記憶體控制器中的編碼器自我測試電路。The present invention relates to a flash memory controller, in particular to an encoder self-test circuit used in a flash memory controller.

在快閃記憶體控制器中會設計至少一個編碼器以對輸入資料進行編碼以產生相對應的校驗碼後，再連同輸入資料一併寫入到快閃記憶體晶片中。然而，考慮到編碼器在功能上的正確性，在工廠內的測試階段時，快閃記憶體控制器會與快閃記憶體晶片連結，之後快閃記憶體控制器會被控制以持續地將資料進行編碼後寫入至快閃記憶體晶片中，再將資料從快閃記憶體晶片中讀取出來並進行解碼，以判斷快閃記憶體控制器的編碼及解碼功能是否正常。然而，上述作法至少會遇到以下兩種問題，第一個問題是當判斷快閃記憶體控制器的編碼及解碼功能不正常時，與快閃記憶體控制器相連接的快閃記憶體晶片便浪費了，或是需要另外進行剝離(debonding)製程以使得快閃記憶體晶片可以重複使用；而第二個問題則是當判斷快閃記憶體控制器的編碼及解碼功能不正常時，無法正確迅速地判斷是編碼器的問題還是解碼器的問題，因而造成工程師的困擾。At least one encoder is designed in the flash memory controller to encode the input data to generate a corresponding check code, and then write the input data into the flash memory chip together with the input data. However, considering the functional correctness of the encoder, during the testing phase in the factory, the flash memory controller will be connected to the flash memory chip, and then the flash memory controller will be controlled to continuously The data is encoded and written into the flash memory chip, and then the data is read from the flash memory chip and decoded to determine whether the encoding and decoding functions of the flash memory controller are normal. However, the above approach will encounter at least the following two problems. The first problem is that when the encoding and decoding functions of the flash memory controller are judged to be abnormal, the flash memory chip connected to the flash memory controller It’s wasted, or an additional debonding process is needed to make the flash memory chip reusable; and the second problem is that when the encoding and decoding functions of the flash memory controller are judged to be abnormal, it cannot be Correctly and quickly determine whether the problem is the encoder or the decoder, which causes trouble for engineers.

因此，本發明的目的之一在於提供一種應用於快閃記憶體控制器的編碼器自我測試電路，其可以在不需要快閃記憶體晶片的情形下，單獨地對編碼器進行測試，以解決先前技術中的問題。Therefore, one of the objectives of the present invention is to provide an encoder self-test circuit applied to a flash memory controller, which can test the encoder separately without the need of a flash memory chip to solve Problems in the prior art.

在本發明的一個實施例中，揭露一種應用於快閃記憶體控制器的編碼器自我測試電路，其包含有一控制電路以及一編碼器。在編碼器自我測試電路的操作中，在不對任何快閃記憶體進行存取的情形下，該控制電路產生一輸入資料至該編碼器，該編碼器對該輸入資料進行編碼以產生一校驗碼至該控制電路，以供判斷該編碼器的功能是否正常。In an embodiment of the present invention, an encoder self-test circuit applied to a flash memory controller is disclosed, which includes a control circuit and an encoder. In the operation of the encoder self-test circuit, without accessing any flash memory, the control circuit generates an input data to the encoder, and the encoder encodes the input data to generate a check Code to the control circuit for judging whether the function of the encoder is normal.

在本發明的另一個實施例中，揭露了一種應用於快閃記憶體控制器的編碼器自我測試方法，其包含有以下步驟：在不對任何快閃記憶體進行存取的情形下：產生一輸入資料至一編碼器；使用該編碼器對該輸入資料進行編碼以產生一校驗碼；以及根據該校驗碼以判斷該編碼器的功能是否正常。In another embodiment of the present invention, an encoder self-testing method applied to a flash memory controller is disclosed, which includes the following steps: without accessing any flash memory: generating a Input data to an encoder; use the encoder to encode the input data to generate a check code; and determine whether the function of the encoder is normal according to the check code.

第1圖為依據本發明一實施例之一快閃記憶體控制器110的示意圖，其中快閃記憶體控制器110係用以連接於一主裝置130以及一快閃記憶體模組120之間，且快閃記憶體控制器110用來根據主裝置130的讀取/寫入指令來存取快閃記憶體模組120。在本實施例中，快閃記憶體控制器110包含一微處理器112、一唯讀記憶體（Read Only Memory, ROM）112M、一控制邏輯114、一緩衝記憶體116、與一介面邏輯118。唯讀記憶體112M係用來儲存一程式碼112C，而微處理器112則用來執行程式碼112C以控制對快閃記憶體模組120之存取（Access）。控制邏輯114包含了一編碼器132以及一控制電路134，其中編碼器132用來對寫入到快閃記憶體模組120中的資料進行編碼以產生對應的校驗碼(或稱，錯誤更正碼(Error Correction Code)，ECC)，而控制電路134則是用來對編碼器132進行測試，特別是在快閃記憶體控制器110尚未與快閃記憶體模組120連結時對編碼器132進行測試。Figure 1 is a schematic diagram of a flash memory controller 110 according to an embodiment of the present invention, in which the flash memory controller 110 is used to connect between a main device 130 and a flash memory module 120 And the flash memory controller 110 is used to access the flash memory module 120 according to the read/write command of the host device 130. In this embodiment, the flash memory controller 110 includes a microprocessor 112, a read only memory (Read Only Memory, ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118 . The read-only memory 112M is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control access to the flash memory module 120. The control logic 114 includes an encoder 132 and a control circuit 134. The encoder 132 is used to encode the data written in the flash memory module 120 to generate a corresponding check code (or, error correction). Code (Error Correction Code, ECC), and the control circuit 134 is used to test the encoder 132, especially when the flash memory controller 110 is not connected to the flash memory module 120. carry out testing.

於典型狀況下，快閃記憶體模組120包含了多個快閃記憶體晶片，而每一個快閃記憶體晶片包含複數個區塊（Block），而快閃記憶體控制器110對快閃記憶體模組120進行抹除資料運作係以區塊為單位來進行。另外，一區塊可記錄特定數量的資料頁（Page），其中快閃記憶體控制器110對快閃記憶體模組120進行寫入資料之運作係以資料頁為單位來進行寫入。在本實施例中，快閃記憶體模組120為一立體NAND型快閃記憶體(3D NAND-type flash)模組。In a typical situation, the flash memory module 120 includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks, and the flash memory controller 110 supports the flash memory The data erasing operation of the memory module 120 is performed in units of blocks. In addition, a block can record a specific number of data pages (Pages), in which the flash memory controller 110 writes data to the flash memory module 120 in units of data pages. In this embodiment, the flash memory module 120 is a 3D NAND-type flash (3D NAND-type flash) module.

實作上，透過微處理器112執行程式碼112C之快閃記憶體控制器110可利用其本身內部之元件來進行諸多控制運作，例如：利用控制邏輯114來控制快閃記憶體模組120之存取運作（尤其是對至少一區塊或至少一資料頁之存取運作）、利用緩衝記憶體116進行所需之緩衝處理、以及利用介面邏輯118來與一主裝置（Host Device）130溝通。緩衝記憶體116係以隨機存取記憶體（Random Access Memory，RAM）來實施。例如，緩衝記憶體116可以是靜態隨機存取記憶體（Static RAM，SRAM），但本發明不限於此。In practice, the flash memory controller 110, which executes the program code 112C through the microprocessor 112, can use its own internal components to perform many control operations, for example, using the control logic 114 to control the flash memory module 120 Access operations (especially access operations to at least one block or at least one data page), use the buffer memory 116 to perform the required buffer processing, and use the interface logic 118 to communicate with a host device 130 . The buffer memory 116 is implemented as a random access memory (Random Access Memory, RAM). For example, the buffer memory 116 may be a static random access memory (Static RAM, SRAM), but the invention is not limited thereto.

在一實施例中，快閃記憶體控制器110可以是位於可攜式記憶裝置（例如：符合SD/MMC、CF、MS、XD標準之記憶卡）中，且主裝置130為一可與可攜式記憶裝置連接的電子裝置，例如手機、筆記型電腦、桌上型電腦…等等。而在另一實施例中，快閃記憶體控制器110可以應用在固態硬碟或符合通用快閃記憶體儲存(Universal Flash Storage，UFS)或嵌入式多媒體記憶卡(Embedded Multi Media Card，EMMC)規格之嵌入式儲存裝置，以設置在一電子裝置中，例如設置在手機、筆記型電腦、桌上型電腦之中，而此時主裝置130可以是該電子裝置的一處理器。In one embodiment, the flash memory controller 110 may be located in a portable memory device (for example, a memory card that conforms to SD/MMC, CF, MS, and XD standards), and the main device 130 is a compatible and compatible Electronic devices connected to portable memory devices, such as mobile phones, laptops, desktop computers, etc. In another embodiment, the flash memory controller 110 can be applied to a solid state drive or conform to Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) The embedded storage device of the specification can be installed in an electronic device, such as a mobile phone, a notebook computer, or a desktop computer. In this case, the main device 130 may be a processor of the electronic device.

第2圖為根據本發明一實施例之編碼器132與控制電路134的示意圖。如第2圖所示，控制電路134包含了一隨機資料產生電路210、一多工器220、一種子資料產生電路230以及一輸出電路240。在本實施例中，控制電路134與編碼器132係作為一編碼器自我測試電路，亦即透過控制電路134與編碼器132的運作可以檢測判斷出編碼器132的功能是否正常。此外，控制電路134與編碼器132的自我測試操作係在一晶圓級測試(wafer level test)中的晶片針測(Chip Probe，CP )階段、或是在一封裝後測試(package level test)中的最後測試(Final Test，FT)階段來進行，亦即編碼器132的自我測試操作並不需要對快閃記憶體模組120進行任何的存取操作(此時快閃記憶體控制器110與快閃記憶體模組120也尚未連結)。FIG. 2 is a schematic diagram of the encoder 132 and the control circuit 134 according to an embodiment of the invention. As shown in FIG. 2, the control circuit 134 includes a random data generating circuit 210, a multiplexer 220, a sub-data generating circuit 230, and an output circuit 240. In this embodiment, the control circuit 134 and the encoder 132 are used as an encoder self-test circuit, that is, through the operation of the control circuit 134 and the encoder 132, it can be detected to determine whether the function of the encoder 132 is normal. In addition, the self-test operation of the control circuit 134 and the encoder 132 is performed in a chip probe (CP) stage in a wafer level test, or a package level test. In the final test (Final Test, FT) phase, that is, the self-test operation of the encoder 132 does not require any access operation to the flash memory module 120 (at this time the flash memory controller 110 And the flash memory module 120 is not yet connected).

在第2圖所示之實施例的操作中，首先，在晶圓級測試中的晶片針測階段或是在封裝後測試中的最後測試階段時，工程師會透過快閃記憶體控制器110的一接點(pad)或是一接腳(pin)202以自外部將一自我測試致能訊號BIST_EN輸入，以啟動編碼器132與控制電路134以進行自我測試操作。需注意的是，第2圖繪示了自我測試致能訊號BIST_EN直接輸入到編碼器132與控制電路134，但本發明並不以此為限，在其他的實施例中快閃記憶體控制器110中可包含另一電路以接收自我測試致能訊號BIST_EN後據以啟動編碼器132與控制電路134，這些設計上的變化均隸屬於本發明的範疇。In the operation of the embodiment shown in FIG. 2, first, in the wafer-level test during the chip probing phase or the final test phase in the post-package test, the engineer will use the flash memory controller 110 A pad or pin 202 is used to input a self-test enable signal BIST_EN from the outside to activate the encoder 132 and the control circuit 134 to perform a self-test operation. It should be noted that Figure 2 shows that the self-test enable signal BIST_EN is directly input to the encoder 132 and the control circuit 134, but the present invention is not limited to this. In other embodiments, the flash memory controller Another circuit may be included in 110 to receive the self-test enable signal BIST_EN to activate the encoder 132 and the control circuit 134 accordingly. These design changes belong to the scope of the present invention.

接著，控制電路134會先產生第1筆輸入資料至編碼器132，以供編碼器132進行編碼操作以產生一對應的校驗碼。具體來說，多工器220首先會切換至上方的通道以將一預設輸入資料作為第1筆輸入資料傳送至編碼器132中，而在本實施例中該預設輸入資料係為一全為邏輯值“1”的資料(0xFF)，且大小為2千位元組(KB)，但此並非是本發明的限制。編碼器132接著對該預設輸入資料進行編碼，例如低密度奇偶檢查碼（Low-density parity-check code，LDPC code）的編碼方式，以產生第1筆校驗碼，其中該校驗碼的大小係關連到編碼器132的設計，例如可以是248位元。接著，種子資料產生電路230對第1筆校驗碼進行循環冗餘校驗(Cyclic Redundancy Check，CRC)操作、或是其他任意適合的雜湊(hash)運算操作，以將第1筆校驗碼壓縮為第1筆種子資料(例如，16位元的種子資料)，其中第1筆種子資料係用來提供給隨機資料產生電路210以產生大小為2千位元組的第2筆輸入資料。Then, the control circuit 134 first generates the first input data to the encoder 132 for the encoder 132 to perform an encoding operation to generate a corresponding check code. Specifically, the multiplexer 220 first switches to the upper channel to transmit a preset input data as the first input data to the encoder 132, and in this embodiment, the preset input data is a complete The data is logical value "1" (0xFF), and the size is 2 kilobytes (KB), but this is not a limitation of the present invention. The encoder 132 then encodes the preset input data, such as a low-density parity-check code (LDPC code) encoding method, to generate a first check code, wherein The size is related to the design of the encoder 132, and may be 248 bits, for example. Next, the seed data generation circuit 230 performs a cyclic redundancy check (Cyclic Redundancy Check, CRC) operation on the first check code, or any other suitable hash operation, to convert the first check code Compressed into the first piece of seed data (for example, 16-bit seed data), where the first piece of seed data is provided to the random data generating circuit 210 to generate the second piece of input data with a size of 2 kilobytes.

上述多工器220輸出第1筆輸入資料至編碼器132、編碼器132產生第1筆校驗碼至種子資料產生電路230、以及種子資料產生電路230產生第1筆種子資料至隨機資料產生電路210的操作可以視為第1個循環操作(loop)。The multiplexer 220 outputs the first input data to the encoder 132, the encoder 132 generates the first check code to the seed data generating circuit 230, and the seed data generating circuit 230 generates the first seed data to the random data generating circuit. The operation of 210 can be regarded as the first loop operation (loop).

接著在第2個循環操作中，多工器220會切換至下方的通道以將隨機資料產生電路210所產生的第2筆輸入資料傳送至編碼器132中，編碼器132接著對第2筆輸入資料進行編碼以產生第2筆校驗碼至種子資料產生電路230，種子資料產生電路230接著對將第2筆校驗碼壓縮為第2筆種子資料，其中第2筆種子資料係用來提供給隨機資料產生電路210以產生大小為2千位元組的第3筆輸入資料。Then in the second loop operation, the multiplexer 220 will switch to the lower channel to send the second input data generated by the random data generating circuit 210 to the encoder 132, and the encoder 132 will then input the second input The data is encoded to generate the second check code to the seed data generating circuit 230. The seed data generating circuit 230 then compresses the second check code into the second seed data, where the second seed data is used to provide The random data generating circuit 210 is used to generate the third input data with a size of 2 kilobytes.

在第3個循環操作中，多工器220持續維持在下方的通道以將隨機資料產生電路210所產生的第3筆輸入資料傳送至編碼器132中，編碼器132接著對第3筆輸入資料進行編碼以產生第3筆校驗碼至種子資料產生電路230，種子資料產生電路230接著對將第3筆校驗碼壓縮為第3筆種子資料，其中第3筆種子資料係用來提供給隨機資料產生電路210以產生大小為2千位元組的第4筆輸入資料。In the third loop operation, the multiplexer 220 continues to maintain the lower channel to transmit the third input data generated by the random data generating circuit 210 to the encoder 132, and the encoder 132 then performs the third input data Encode to generate the third check code to the seed data generating circuit 230. The seed data generating circuit 230 then compresses the third check code into the third seed data, where the third seed data is used to provide The random data generating circuit 210 generates the fourth input data with a size of 2 kilobytes.

在經過一定數量的循環操作之後，例如N個循環操作之後，輸出電路240會判斷對種子資料產生電路230所產生的第N筆種子資料的正確性以決定編碼器132的功能是否常，並將判斷結果BIST_OUT透過快閃記憶體控制器110的一接點或是一接腳204將判斷結果BIST_OUT輸出至其他裝置以供工程師參考。具體來說，由於工程師可以先透過模擬得知編碼器132與控制電路134在進行N個循環操作之後所產生的第N筆種子資料的正確數值，而此正確數值可以被預先儲存在控制電路134中或是由工程師另外輸入，因此，輸出電路240可以將N個循環操作之後種子資料產生電路230所產生的第N筆種子資料與此正確數值相比較，若是比較結果相符合則表示編碼器132的功能正常，而若是比較結果不符則表示編碼器132的功能異常。After a certain number of loop operations, such as N loop operations, the output circuit 240 will determine the correctness of the Nth seed data generated by the seed data generation circuit 230 to determine whether the function of the encoder 132 is normal, and The judgment result BIST_OUT outputs the judgment result BIST_OUT to other devices through a contact or a pin 204 of the flash memory controller 110 for reference by the engineer. Specifically, because the engineer can first obtain the correct value of the Nth seed data generated by the encoder 132 and the control circuit 134 after N cycles of operations through simulation, and the correct value can be stored in the control circuit 134 in advance. It may be input by the engineer. Therefore, the output circuit 240 can compare the Nth seed data generated by the seed data generating circuit 230 after N cycles of operations with the correct value. If the comparison result matches, the encoder 132 The function of the encoder 132 is normal, and if the comparison result does not match, the function of the encoder 132 is abnormal.

在本發明的另一個實施例中，輸出電路240可以直接將種子資料產生電路230所產生的第N筆種子資料透過接點或是接腳204傳送至另一電子裝置，以供工程師判斷編碼器132的功能是否正常。In another embodiment of the present invention, the output circuit 240 can directly transmit the Nth seed data generated by the seed data generating circuit 230 to another electronic device through the contact or the pin 204, so that the engineer can judge the encoder Is the function of 132 normal?

在第2圖所示的實施例中，輸出電路240係用來將第N筆種子資料與此正確數值相比較以判斷編碼器132的功能是否正常，然而，在另一實施例中，輸出電路240亦可以將編碼器132所產生的第N筆校驗碼與一正確校驗碼將比較以判斷編碼器132的功能是否正常，這些設計上的變化均應隸屬於本發明的範疇。In the embodiment shown in Figure 2, the output circuit 240 is used to compare the Nth seed data with the correct value to determine whether the function of the encoder 132 is normal. However, in another embodiment, the output circuit 240 can also compare the Nth check code generated by the encoder 132 with a correct check code to determine whether the function of the encoder 132 is normal. These design changes should fall within the scope of the present invention.

如上所述，透過上述的自我測試操作，可以快速有效地判斷出編碼器132的功能是否正常，且在自我測試的過程中不需要存取任何的快閃記憶體模組120，而可以獨立地就快閃記憶體控制器110本身來進行測試，故可以避免先前技術中因為編碼器132的功能異常而導致相連結的快閃記憶體模組120需要另外進行剝離製程的麻煩。此外，由於本實施例中的編碼器自我測試不需要牽涉到解碼操作(不需要使用到位於控制邏輯114中的解碼器)，因此可以避免先前技術中需要另外判斷是編碼器異常或是解碼器異常的問題。As mentioned above, through the above-mentioned self-test operation, it can be quickly and effectively determined whether the function of the encoder 132 is normal, and there is no need to access any flash memory module 120 during the self-test, and can be independently The flash memory controller 110 itself is used for testing, so it can avoid the trouble of a separate stripping process for the connected flash memory module 120 due to the malfunction of the encoder 132 in the prior art. In addition, since the encoder self-test in this embodiment does not need to involve decoding operations (the decoder located in the control logic 114 does not need to be used), it can avoid the need to determine whether the encoder is abnormal or the decoder in the prior art. Unusual problem.

在完成自我測試操作之後，工程師停止將自我測試致能訊號BIST_EN輸入至快閃記憶體控制器110，以使得編碼器132與控制電路134停止操作。After completing the self-test operation, the engineer stops inputting the self-test enable signal BIST_EN to the flash memory controller 110, so that the encoder 132 and the control circuit 134 stop operating.

在以上的實施例中，編碼器132及控制電路134在自我測試操作中所進行的循環操作次數(例如，前述的“N”)可以是任何適合的數值，然而，考慮到編碼器132中有部分的電路可能會因為製程因素而需要較長時間的測試，因此編碼器132及控制電路134需要較高的循環操作次數，例如N大於1000，甚至N可以是10萬或是100萬次，以使得編碼器132中的瑕疵可以在多次循環操作中顯現出來。另一方面，為了讓編碼器132及控制電路134可以進行較完整全面的測試，工程師可以設計這些循環操作中不會產生相同的種子資料，亦即第1筆種子資料到第N筆種子資料中不會有任何兩筆相同的種子資料。In the above embodiment, the number of loop operations performed by the encoder 132 and the control circuit 134 in the self-test operation (for example, the aforementioned "N") can be any suitable value. However, considering that the encoder 132 has Some circuits may require a longer test time due to process factors. Therefore, the encoder 132 and the control circuit 134 require a relatively high number of cycle operations. For example, N is greater than 1,000, and even N can be 100,000 or 1 million times. Therefore, the defects in the encoder 132 can be revealed in multiple cycles of operation. On the other hand, in order to allow the encoder 132 and the control circuit 134 to perform a more complete and comprehensive test, engineers can design that the same seed data will not be generated in these loop operations, that is, the first seed data will be in the Nth seed data. There will be no two identical torrents.

第3圖為根據本發明一實施例之應用於快閃記憶體控制器的編碼器自我測試方法的流程圖。同時參考以上第1、2圖的實施例所述，第3圖的流程如下。FIG. 3 is a flowchart of an encoder self-test method applied to a flash memory controller according to an embodiment of the invention. At the same time, referring to the above embodiments in Figures 1 and 2, the flow in Figure 3 is as follows.

步驟300：流程開始。Step 300: The process starts.

步驟302：透過快閃記憶體控制器的一接點/接腳接收一自我測試致能訊號以開始進行自我測試操作。Step 302: Receive a self-test enable signal through a contact/pin of the flash memory controller to start a self-test operation.

步驟304：使用控制電路及編碼器進行多個循環操作，其中每一個循環操作包含以下步驟304_1~304_3：Step 304: Use the control circuit and the encoder to perform multiple loop operations, and each loop operation includes the following steps 304_1~304_3:

步驟304_1：隨機資料產生電路產生第K筆輸入資料；Step 304_1: The random data generating circuit generates the Kth input data;

步驟304_2：編碼器對該第K筆輸入資料進行編碼以產生第K筆校驗碼；Step 304_2: The encoder encodes the K-th input data to generate the K-th check code;

步驟304_3：種子資料產生電路根據第K筆校驗碼以產生第K筆種子資料至隨機資料產生電路，之後回到步驟304_1以產生第(K+1)筆輸入資料；Step 304_3: The seed data generation circuit generates the Kth seed data to the random data generation circuit according to the Kth check code, and then returns to step 304_1 to generate the (K+1)th input data;

步驟306：判斷第N筆種子資料是否正確，以決定編碼器的功能是否正常。Step 306: Determine whether the Nth seed data is correct to determine whether the function of the encoder is normal.

步驟308：結束自我測試操作。Step 308: End the self-test operation.

簡要歸納本發明，在本發明之應用於快閃記憶體控制器的編碼器自我測試電路，可以在不需要連結到快閃記憶體模組的情形下對快閃記憶體控制器中的編碼器進行功能測試，以準確地判斷出編碼器的功能是否異常。透過本發明可以讓快閃記憶體控制器單獨地進行編碼功能測試，以避免先前技術中需要讓快閃記憶體控制器與快閃記憶體模組相連後才能進行測試，而造成當快閃記憶體控制器有異常時導致相連結的快閃記憶體模組需要另外進行剝離製程的麻煩。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。Briefly summarizing the present invention, the encoder self-test circuit applied to the flash memory controller of the present invention can test the encoder in the flash memory controller without connecting to the flash memory module. Carry out a function test to accurately determine whether the function of the encoder is abnormal. Through the present invention, the flash memory controller can be independently tested for encoding function, so as to avoid the need to connect the flash memory controller to the flash memory module before the test can be performed in the prior art. When the controller has an abnormality, the connected flash memory module requires additional stripping process. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

110:快閃記憶體控制器 112:微處理器 112C:程式碼 112M:唯讀記憶體 114:控制邏輯 116:緩衝記憶體 118:介面邏輯 120:快閃記憶體模組 130:主裝置 132:編碼器 134:控制電路 202、204:接腳 210:隨機資料產生電路 220:多工器 230:種子資料產生電路 240:輸出電路 300~308:步驟 BIST_EN:自我測試致能訊號 BIST_OUT:判斷結果 110: Flash memory controller 112: Microprocessor 112C: Code 112M: Read only memory 114: Control logic 116: buffer memory 118: Interface logic 120: Flash memory module 130: main device 132: Encoder 134: Control Circuit 202, 204: pin 210: Random data generation circuit 220: Multiplexer 230: Seed data generation circuit 240: output circuit 300~308: steps BIST_EN: Self-test enable signal BIST_OUT: judgment result

第1圖為依據本發明一實施例之一快閃記憶體控制器的示意圖。 第2圖為根據本發明一實施例之編碼器與控制電路的示意圖。 第3圖為根據本發明一實施例之應用於快閃記憶體控制器的編碼器自我測試方法的流程圖。FIG. 1 is a schematic diagram of a flash memory controller according to an embodiment of the invention. Figure 2 is a schematic diagram of an encoder and a control circuit according to an embodiment of the invention. FIG. 3 is a flowchart of an encoder self-test method applied to a flash memory controller according to an embodiment of the invention.

110:快閃記憶體控制器 110: Flash memory controller

132:編碼器 132: Encoder

134:控制電路 134: Control Circuit

202、204:接腳 202, 204: pin

210:隨機資料產生電路 210: Random data generation circuit

220:多工器 220: Multiplexer

230:種子資料產生電路 230: Seed data generation circuit

240:輸出電路 240: output circuit

BIST_EN:自我測試致能訊號 BIST_EN: Self-test enable signal

BIST_OUT:判斷結果 BIST_OUT: judgment result

Claims (10)

一種應用於快閃記憶體控制器的編碼器自我測試電路，包含有： 一控制電路；以及 一編碼器； 其中該控制電路產生一輸入資料至該編碼器，該編碼器對該輸入資料進行編碼以產生一校驗碼至該控制電路，以供判斷該編碼器的功能是否正常；以及在判斷該編碼器的功能是否正常的過程中不涉及任何的解碼操作。An encoder self-test circuit applied to flash memory controller, including: A control circuit; and An encoder; The control circuit generates an input data to the encoder, and the encoder encodes the input data to generate a check code to the control circuit for judging whether the encoder is functioning normally; and when judging the encoder The process of whether the function is normal does not involve any decoding operation. 如申請專利範圍第1項所述之編碼器自我測試電路，其中該控制電路係在接收到來自該快閃記憶體控制器外部的一自我測試致能訊號之後才會啟動以產生該輸入資料至該編碼器。For example, the encoder self-test circuit described in item 1 of the scope of patent application, wherein the control circuit is activated after receiving a self-test enable signal from outside the flash memory controller to generate the input data to The encoder. 如申請專利範圍第2項所述之編碼器自我測試電路，其中該自我測試致能訊號係由該快閃記憶體控制器的一接點(pad)或是一接腳(pin)所輸入。For the encoder self-test circuit described in item 2 of the scope of patent application, the self-test enable signal is input by a pad or a pin of the flash memory controller. 如申請專利範圍第3項所述之編碼器自我測試電路，其中該自我測試致能訊號係在一晶圓級測試(wafer level test)中的晶片針測(Chip Probe，CP )階段輸入，或是在一封裝後測試(package level test)中的最後測試(Final Test，FT)階段輸入。The encoder self-test circuit described in item 3 of the scope of patent application, wherein the self-test enable signal is input in the chip probe (CP) stage of a wafer level test, or It is the final test (FT) stage input in a package level test (package level test). 如申請專利範圍第1項所述之編碼器自我測試電路，其中該控制電路判斷該校驗碼或是對該校驗碼進行壓縮所產生的一種子資料是否與一預設資料相符合，以判斷該編碼器的功能是否正常。For example, the encoder self-test circuit described in item 1 of the scope of patent application, wherein the control circuit determines whether the check code or a sub-data generated by compressing the check code is consistent with a preset data, Determine whether the function of the encoder is normal. 一種應用於快閃記憶體控制器的編碼器自我測試方法，包含有： 在不涉及任何解碼操作的情形下： 產生一輸入資料至一編碼器； 使用該編碼器對該輸入資料進行編碼以產生一校驗碼；以及 根據該校驗碼以判斷該編碼器的功能是否正常。An encoder self-test method applied to flash memory controllers, including: Without involving any decoding operations: Generate an input data to an encoder; Use the encoder to encode the input data to generate a check code; and According to the check code to determine whether the function of the encoder is normal. 如申請專利範圍第6項所述之編碼器自我測試方法，其中產生該輸入資料至該編碼器的步驟包含有： 在接收到來自該快閃記憶體控至器外部的一自我測試致能訊號之後才會啟動一控制電路以產生該輸入資料至該編碼器。For example, the encoder self-test method described in item 6 of the scope of patent application, wherein the steps of generating the input data to the encoder include: After receiving a self-test enable signal from the outside of the flash memory controller, a control circuit is activated to generate the input data to the encoder. 如申請專利範圍第7項所述之編碼器自我測試方法，其中該自我測試致能訊號係由該快閃記憶體控制器的一接點(pad)或是一接腳(pin)所輸入。In the encoder self-test method described in item 7 of the patent application, the self-test enable signal is input by a pad or a pin of the flash memory controller. 如申請專利範圍第8項所述之編碼器自我測試方法，其中該自我測試致能訊號係在一晶圓級測試(wafer level test)中的晶片針測(Chip Probe，CP )階段輸入，或是在一封裝後測試(package level test)中的最後測試(Final Test，FT)階段輸入。The encoder self-test method described in item 8 of the scope of patent application, wherein the self-test enabling signal is input in the chip probe (CP) stage of a wafer level test, or It is the final test (FT) stage input in a package level test (package level test). 如申請專利範圍第6項所述之編碼器自我測試方法，其中根據該校驗碼以判斷該編碼器的功能是否正常的步驟包含有： 判斷該校驗碼或是對該校驗碼進行壓縮所產生的一種子資料是否與一預設資料相符合，以判斷該編碼器的功能是否正常。For the encoder self-test method described in item 6 of the scope of patent application, the steps of judging whether the encoder is functioning normally according to the check code include: Determine whether the check code or a kind of sub-data generated by compressing the check code is consistent with a preset data to determine whether the function of the encoder is normal.
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