TWI692819B - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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TWI692819B
TWI692819B TW108103456A TW108103456A TWI692819B TW I692819 B TWI692819 B TW I692819B TW 108103456 A TW108103456 A TW 108103456A TW 108103456 A TW108103456 A TW 108103456A TW I692819 B TWI692819 B TW I692819B
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semiconductor die
active surface
semiconductor
passive element
disposed
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TW108103456A
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TW202010024A (zh
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張簡上煜
徐宏欣
林南君
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力成科技股份有限公司
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Abstract

一種半導體封裝，包括半導體晶粒、絕緣密封體、被動元件例如薄膜電容器以及重佈線路結構。半導體晶粒包括主動表面與位於主動表面的多個導電接墊。絕緣密封體密封半導體晶粒並暴露出半導體晶粒的主動表面。被動元件設置在半導體晶粒的主動表面上。重佈線路結構設置在半導體晶粒的主動表面上，以電性連接至半導體晶粒的導電接墊與被動元件。另提供一種半導體封裝的製造方法。

Description

半導體封裝及其製造方法
本發明提供一種半導體封裝及其製造方法，特別是一種具有嵌入式被動元件的半導體封裝及其製造方法。
隨著科技的進步，電子產品的設計變得更輕、更薄、更短及更小，目標為開發體積更小、重量更輕且整合度更高的產品，以提升市場上的競爭力。然而，隨著這些產品的體積逐漸縮小，電子電路和元件所設置的密度越來越高，並且為了避免電子元件操作而產生的電氣雜訊(electrical noise)可能破壞或損壞半導體晶粒，需對其加以保護。避免這類的破壞和損壞的一種方法是在半導體晶粒附近採用電容器作為高頻雜訊的接地路徑。如此被動元件將會佔據與半導體晶粒相鄰的額外空間，然而，可以最小化這額外空間以進一步地微型化半導體封裝。因此，當持續將半導體封裝微型化的同時，維持半導體封裝件的可靠性與功能性已成為該領域的研究人員的挑戰。
本發明提供一種具有嵌入式被動元件的半導體封裝及其製造方法，可增強半導體封裝的可靠性，並且由於被動元件的嵌入特性，被動元件佔據最小的空間。
本發明提供一種半導體封裝，包括半導體晶粒、絕緣密封體、被動元件(例如薄膜電容器)以及重佈線路結構。半導體晶粒包括主動表面與設置於主動表面上的多個導電接墊。絕緣密封體密封半導體晶粒且暴露出半導體晶粒的主動表面。被動元件設置在半導體晶粒的主動表面上。重佈線路結構設置在半導體晶粒的主動表面上並且電性連接至半導體晶粒的導電接墊與被動元件。
在一實施例中，半導體封裝還包括多個導電端子，設置在相對於半導體晶粒的重佈線路結構上且電性耦接至重佈線路結構。在一實施例中，重佈線路結構的介電層包括多個第一開口，其暴露出半導體晶粒的導電接墊的至少一部份，並且重佈線路結構的第一導電通孔設置在介電層的第一開口中。在一實施例中，重佈線路結構更包括多個第二導電通孔，介電層更包括多個第二開口，其暴露出被動元件的至少一部分，並且第二導電通孔設置在介電層的第二開口中以電性耦接至被動元件。
本發明提供一種半導體封裝的製造方法，至少包括以下步驟。放置被動元件在半導體晶粒的主動表面上，其中半導體晶粒包括設置在主動表面的多個導電接墊。以絕緣密封體密封半導體晶粒，其中絕緣密封體暴露出半導體晶粒的主動表面。形成重佈線 路結構在半導體晶粒的主動表面上，其中重佈線路結構電性連接至半導體晶粒的導電接墊與被動元件。
在一實施例中，半導體封裝的製造方法還包括形成多個導電端子在相對於半導體晶粒的重佈線路結構上，以電性耦接至重佈線路結構。在一實施例中，在形成介電層之後，形成多個第一開口在介電層中，以暴露出半導體晶粒的導電接墊的至少一部份，接著形成第一導電通孔在介電層的第一開口中。在一實施例中，在形成介電層之後，形成多個第二開口在介電層中，以暴露出被動元件的至少一部分，以及形成重佈線路結構更包括形成多個第二導電通孔在第二開口中以電性耦接至被動元件。在一實施例中，半導體封裝的製造方法還包括以絕緣密封體密封半導體晶粒之後，提供第二暫時載板在相對於半導體晶粒的主動表面的絕緣密封體上；以及在形成重佈線路結構之後，移除第二暫時載板。在一實施例中，設置被動元件在半導體晶粒上包括藉由黏著層將被動元件附接在半導體晶粒的主動表面上。在一實施例中，在單體化之前，減少半導體晶圓的厚度。
基於上述，本發明的被動元件嵌入在半導體封裝中。因此，被動元件所佔據的空間小於被動元件未嵌入時所佔據的空間。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
10:半導體封裝
1000:半導體晶圓
100:半導體晶粒
100a:主動表面
100b:後表面
120:導電接墊
400:被動元件
440:黏著層
402:第一電極層
404:薄介電層
406:第二電極層
500:第一暫時載板
510:第一離型層
600:絕緣密封體
700:第二暫時載板
710:第二離型層
800:重佈線路結構
810:介電層
810a:第一開口
810b:第二開口
850:第一導電通孔
860a、860b:第二導電通孔
870:導電圖案
870T:導電圖案
900:導電端子
圖1A至圖1D是本發明一實施例的一種具有被動元件的半導體晶粒的製造方法的示意性剖視圖。
圖2A至圖2I是本發明一實施例的一種半導體封裝的製造方法的示意性剖視圖。
圖3A至圖3D是本發明一實施例的半導體封裝的製造方法的替代步驟的剖視圖。
以下將參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。相同或相似之標號表示相同或相似之元件，以下段落將不再一一贅述。附圖所繪示之各元件的尺寸及空間比例不一定反應反映各元件相對於彼此的實際比例。舉例而言，為了清楚起見，在附圖中放大了被動元件。
圖1A至圖1D是本發明一實施例的一種具有被動元件的半導體晶粒的製造方法的示意性剖視圖。請參照圖1A，提供半導體晶圓1000。半導體晶圓1000可具有主動表面100a與相對於主動表面100a的後表面100b。半導體晶圓1000可包括多個晶粒，並且多個導電接墊120可被設置在半導體晶圓1000的每個晶粒的主動表面100a上。在一些實施例中，導電接墊120可以在晶粒彼此分離之前相應地設置，但本發明不以此為限。半導體晶圓1000可以由矽、聚合物或其他合適的材料製成。
請參照圖1B，至少一個被動元件400設置在半導體晶圓1000的每個晶粒的主動表面100a上。在一些實施例中，被動元件400可以在晶粒彼此分離之前相應地設置，但本發明不以此為限。被動元件400可以設置在主動表面100a上而不覆蓋導電接墊120。舉例來說，可以透過拾取及放置法(pick-and-place method)將每個被動元件400逐一地設置在相鄰的導電接墊120之間的主動表面100a上。舉例來說，在主動表面100a上設置被動元件400的區域配置(或不配置)導電接墊120。被動元件400可以被導電接墊120圍繞。被動元件400可以透過黏著層440附著在半導體晶圓1000的主動表面100a上。舉例來說，黏著層440可以是晶粒貼附膜(die attach film；DAF)或其他合適的黏著材料。被動元件400可以是電容器、電感器、電阻器或其他合適的被動元件。舉例來說，被動元件400可以是薄膜被動元件且可以包括依序堆疊在彼此頂部的第一電極層402、薄介電層404和第二電極層406。在一些實施例中，被動元件400的厚度可小於5μm。
請參照圖1C及圖1D，在設置被動元件400之後，半導體晶圓1000可以被單體化以形成多個半導體晶粒100，如圖1D所示。半導體晶粒100例如是特殊應用積體電路(Application-Specific Integrated Circuit；ASIC)，但本發明不以此為限。其他合適的主動裝置可用以作為半導體晶粒100。在一些實施例中，在進行單體化前，半導體晶圓1000的輪廓可以依設計需求減少至所需厚度。舉例來說，可透過機械研磨製程(mechanical grinding process)、化學機械研磨(chemical mechanical polishing；CMP)製程或其他合適的製程研磨半導體晶圓1000的後表面100b，以減少厚度。作為替代地，被動元件400也可以於單體化後，再設置在半導體晶粒100上，將於稍後的其他實施例詳述。
圖2A至圖2I是本發明另一實施例的一種半導體封裝的製造方法的示意性剖視圖。圖2A至2D是關於半導體晶粒100的密封。請參照圖2A，提供第一暫時載板500。在一些實施例中，可在第一暫時載板500上形成第一離型層510。第一離型層510可以是液態型離型層(liquid-type release layer)、光熱轉換(light-to-heat-conversion；LTHC)層或其他合適的離型層。請參照圖2B，可將半導體晶粒100設置在第一暫時載板500上。半導體晶粒100的主動表面100a可面向第一暫時載板500。在設置半導體晶粒100之後，半導體晶粒100的導電接墊120可被第一離型層510覆蓋。藉著施加於半導體晶粒100的結合力，設置在半導體晶粒100的主動面100a上的被動元件400可以部分地被第一離型層510覆蓋或者嵌入在第一離型層510中。
請參照圖2C，在將半導體晶粒100設置在第一暫時載板500上之後，形成絕緣密封體600在第一暫時載板500上，以密封半導體晶粒100。在一些實施例中，絕緣密封體600的厚度可以大於半導體晶粒100的厚度。絕緣密封體600可以是藉由模塑製程(molding process)形成的環氧樹脂模塑化合物(epoxy molding compound EMC)或是提供防水氣、防氧化、防熱和防衝擊的其他 合適材料。在形成絕緣密封體600之後，選擇地執行減薄製程(thinning process)以減少絕緣密封體600的厚度。減薄製程可以是機械研磨製程、CMP製程或其他合適的製程。減薄製程可有助於降低封裝結構的總高度，並可藉由半導體晶粒100將產生的熱量散發至周圍環境以改善散熱。
請參照圖2D，在密封之後，可選擇性地提供第二暫時載板700在相對於半導體晶粒100的主動表面100a的絕緣密封體600上。在一些實施例中，第二離型層710可設置在第二暫時載板700和絕緣密封體600之間，以增強兩者間的可離型性(releasibility)。在一些實施例中，可移除第一暫時載板500以暴露半導體晶粒100的主動表面100a。舉例來說，可以將如紫外雷射光、可見光或熱量等外部能量施加到第一離型層510，使得第一暫時載板500可以從絕緣密封體600剝離。在移除第一暫時載板500之後，可以暴露出被動元件400和導電接墊120。絕緣密封體600的表面600a與半導體晶粒100的主動表面100a可以是共平面。
圖2E至圖2F示出了在半導體晶粒100的主動表面100a上形成重佈線路結構800的方法。包括多個第一開口810a的介電層810可以形成在絕緣密封體600上。介電層810可形成在絕緣密封體600上以覆蓋半導體晶粒100的主動表面100a。介電層810可具有多個第一開口810a及多個第二開口810b。第一開口810a可暴露出半導體晶粒100的導電接墊120的至少一部份。第二開 口810b可以暴露出第一電極層402的至少一部分和被動元件400的第二電極層406的至少一部分。第一開口810a可以比第二開口810b更深。第一開口810a和第二開口810b的尺寸可以根據設計要求而為相同或不同，並不限於此。
隨後，藉由沉積製程(deposition process)、鍍覆製程(plating process)或其他合適製程，形成導電材料(例如銅、鋁、鎳或其他合適的導電材料)在介電層810上以及在第一開口810a和第二開口810b內。形成在第一開口810a和第二開口810b中的導電材料可分別稱為第一導電通孔850和第二導電通孔860a、860b。每個第一導電通孔850的厚度可以大於每個第二導電通孔860a、860b的厚度。第一導電通孔850嵌入在介電層810中並直接地電性耦接至半導體晶粒100的導電接墊120。第二導電通孔860a、860b嵌入在介電層810中並且直接地電性耦接至被動元件400的第一電極層402和第二電極層406。接下來，可以通過微影和蝕刻製程(photolithography and etching process)圖案化在介電層810上形成的導電材料，以形成導電圖案870。導電圖案870電性連接至第一導電通孔850和第二導電通孔860a、860b。重佈線路結構800可以是扇出型重佈線路結構(fan-out redistribution structure)，其中連接至半導體晶粒100的導電圖案870被重新佈置並且擴展得比半導體晶粒的尺寸更寬。
可將上述步驟重複多次，以獲得電路設計所需的多層的重佈線路結構800。在一些實施例中，最頂部的介電層810可具有 暴露出最頂層的導電圖案870T的至少一部分的開口，用於進一步的電性連接。在一些實施例中，最頂層的導電圖案870T可被稱為是作為後續植球製程(ball mounting process)的凸塊下金屬(under-ball metallurgy；UBM)圖案。
請參照圖2G，在形成重佈線路結構800之後，形成多個導電端子900在相對於絕緣密封體600的重佈線路結構800上。舉例來說，導電端子900可以是藉由植球製程在最頂層的導電圖案870T上所形成的焊球。在一些實施例中，導電端子900可包括通過鍍覆製程或其他合適製程所形成的導電柱、導電凸塊或其組合。然而，本發明不限於此。根據設計所需，可以使用導電端子900的其他可能的形式和形狀。可選擇性地執行焊接製程(soldering process)和回焊製程(reflowing process)以增強導電端子900和重佈線路結構800之間的黏合性。
在一些實施例中，形成導電端子900之後，例如可以藉由將離型層710剝離，以從絕緣密封體600移除第二暫時載板700。第二暫時載板700的移除製程可類似於圖2D所示的第一暫時載板500的移除製程，為了簡潔起見省略詳細描述。在移除第二暫時載板700之後，可選擇性地在絕緣密封體600相對於重佈線路結構800所暴露的表面上設置散熱件(heat sink)。
請參照圖2H及2I，在移除第二暫時載板700之後，可以執行單體化製程(singulation process)，便基本上完成半導體封裝10的製程。由於設置在半導體晶粒100的主動表面100a上的被動 元件400嵌入在重佈線路結構800中並且電性耦接到半導體晶粒100和重佈線路結構800，因此主動裝置和被動裝置的整合性可以在這種小型化的半導體封裝10中實現。此外，重佈線路結構800的第一導電通孔850直接連接到半導體晶粒100的導電接墊120，進而形成不具有焊料凸塊在導電接墊120上的扇出型結構的半導體晶粒100。另外，直接連接至半導體晶粒100和被動元件400的重佈線路結構800可保持短的導電路徑，以改善電氣性能。
圖3A至圖3D是本發明一實施例的半導體封裝的製造方法的替代步驟的截面圖。本實施例的製造方法類似於上述實施例。在所有附圖中，相同或相似的數字表示相同或相似的元件並且不再重複其細節。本實施例與前述實施例之間的區別在於，在移除第一暫時載板500之後，可設置被動元件400在半導體晶粒100的主動面100a上。
舉例來說，請參照圖3A，提供如圖1A所示的半導體晶圓1000，然後進行單體化以形成獨立的多個半導體晶粒100。在單體化後，可將半導體晶粒100設置在第一暫時載板500上，其中半導體晶粒100的主動表面100a面向第一暫時載板500。在一些實施例中，半導體晶粒100的導電接墊120可以被離型層510覆蓋。
請參照圖3B，在設置半導體晶粒100之後，可以在第一暫時載板500上形成絕緣密封體600，以密封半導體晶粒100。絕緣密封體600的形成過程與圖2C所示相似。為簡潔起見，省略了 詳細描述。
請參照圖3C，第二暫時載板700可以提供在絕緣密封體600相對於半導體晶粒100的主動表面100a上。在一些實施例中，第二離型層710可設置在第二暫時載板700和絕緣密封體600之間。所述製程可與圖2D所示製程相似，為簡潔起見省略了詳細描述。在一些實施例中，可以從絕緣密封體600上移除第一暫時載板500，以暴露出半導體晶粒100的主動表面100a。
請參照圖3D，在移除第一暫時載板500之後，將被動元件400設置在半導體晶粒100的主動表面100a上而不覆蓋導電接墊120。半導體封裝的後續製程可類似於圖2F至2I所述過程，為簡潔起見省略了詳細描述。
基於上述，設置在半導體晶粒的主動面上的被動元件嵌入在扇出重佈線路結構中，並電性耦接至半導體晶粒和重佈線路結構，從而在這種緊湊配置的半導體封裝中，實現主動和被動裝置的整合性。此外，直接電性連接到半導體晶粒和被動元件的重佈線路結構可以保持短的導電路徑以改善電氣性能。因此，半導體封裝可以與高端裝置應用兼容。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10：半導體封裝 100：半導體晶粒 400：被動元件 600：絕緣密封體 800：重佈線路結構 900：導電端子

Claims (10)

  1. 一種半導體封裝，包括：一半導體晶粒，包括一主動表面與設置於該主動表面上的多個導電接墊；一絕緣密封體，密封該半導體晶粒且暴露出該半導體晶粒的該主動表面；一被動元件，設置在該半導體晶粒的該主動表面上；以及一重佈線路結構，設置在該半導體晶粒的該主動表面上且電性連接至該半導體晶粒的該些導電接墊與該被動元件，其中該被動元件嵌入在該重佈線路結構中且與該絕緣密封體彼此分離。
  2. 如申請專利範圍第1項所述的半導體封裝，其中該重佈線路結構包括：一介電層，設置在該半導體晶粒的該主動表面上；多個第一導電通孔，嵌入在該介電層中且電性耦接至該半導體晶粒的該些導電接墊；以及一導電圖案，設置在該介電層且電性耦接至該些第一導電通孔。
  3. 如申請專利範圍第2項所述的半導體封裝，其中該被動元件嵌入在該重佈線路結構的該介電層中。
  4. 如申請專利範圍第1項所述的半導體封裝，其中該絕緣密封體的一表面與該半導體晶粒的該主動表面共平面。
  5. 如申請專利範圍第1項所述的半導體封裝，其中該被動元件設置在沒有該些導電接墊的該主動表面的區域中。
  6. 一種半導體封裝的製造方法，包括：放置一被動元件在一半導體晶粒的一主動表面上，其中該半導體晶粒包括設置在該主動表面上的多個導電接墊；以一絕緣密封體密封該半導體晶粒，其中該絕緣密封體暴露出該半導體晶粒的該主動表面；以及形成一重佈線路結構在該半導體晶粒的該主動表面上，其中該重佈線路結構電性連接至該半導體晶粒的該些導電接墊與該被動元件，其中該被動元件嵌入在該重佈線路結構中且與該絕緣密封體彼此分離。
  7. 如申請專利範圍第6項所述的製造方法，其中形成該重佈線路結構包括：形成一介電層在該半導體晶粒的該主動表面上；形成多個第一導電通孔在該介電層中，以連接該半導體晶粒的該些導電接墊；以及形成一導電圖案在該介電層上，以電性耦接至該些第一導電通孔。
  8. 如申請專利範圍第6項所述的製造方法，還包括：形成一離型層在一第一暫時載板上；在設置該被動元件在該半導體晶粒上之後，設置該半導體晶粒在該第一暫時載板上，其中該被動元件嵌入於該離型層中；以及 在該絕緣密封體密封該半導體晶粒之後，移除該第一暫時載板，其中在移除該第一暫時載板之後，該絕緣密封體的一表面與該半導體晶粒的該主動表面共平面。
  9. 如申請專利範圍第6項所述的製造方法，更包括：形成一離型層在一第一暫時載板上；在密封該半導體晶粒之前，設置該半導體晶粒在該第一暫時載板上，其中該半導體晶粒的該主動表面接觸該離型層；以及在密封該半導體晶粒之後，移除該第一暫時載板，以暴露出該半導體晶粒的該主動表面，其中在移除該第一暫時載板之後，該絕緣密封體的一表面與該半導體晶粒的該主動表面共平面，並且該被動元件設置在該半導體晶粒上。
  10. 如申請專利範圍第6項所述的製造方法，更包括：提供一半導體晶圓；設置該被動元件在該半導體晶圓上；以及將該半導體晶圓單體化以形成多個該半導體晶粒。
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Families Citing this family (3)

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Publication number Priority date Publication date Assignee Title
CN113471086B (zh) * 2021-06-29 2024-06-28 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
US20230140738A1 (en) * 2021-10-30 2023-05-04 Raymond Won Bae Microelectronic test and package interface substrates, devices, and methods of manufacture thereof alignment improvement of interconnect on buildup redistribution layers
WO2023201697A1 (en) * 2022-04-22 2023-10-26 Innoscience (suzhou) Semiconductor Co., Ltd. Semiconductor packaged device and method for manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201740443A (zh) * 2016-05-05 2017-11-16 台灣積體電路製造股份有限公司 封裝體及其形成方法
TW201740529A (zh) * 2016-05-05 2017-11-16 台灣積體電路製造股份有限公司 整合扇出型封裝及其製造方法
TW201813041A (zh) * 2016-04-12 2018-04-01 聯發科技股份有限公司 半導體封裝結構
TW201820565A (zh) * 2016-11-29 2018-06-01 新加坡商Ｐｅｐ創新私人有限公司 晶片封裝方法及封裝結構
TW201826418A (zh) * 2016-08-29 2018-07-16 上海兆芯集成電路有限公司 晶片封裝製程

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8164158B2 (en) * 2009-09-11 2012-04-24 Stats Chippac, Ltd. Semiconductor device and method of forming integrated passive device
US9362161B2 (en) * 2014-03-20 2016-06-07 Stats Chippac, Ltd. Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
US9330994B2 (en) * 2014-03-28 2016-05-03 Stats Chippac, Ltd. Semiconductor device and method of forming RDL and vertical interconnect by laser direct structuring
US9040316B1 (en) * 2014-06-12 2015-05-26 Deca Technologies Inc. Semiconductor device and method of adaptive patterning for panelized packaging with dynamic via clipping
US9978700B2 (en) * 2014-06-16 2018-05-22 STATS ChipPAC Pte. Ltd. Method for building up a fan-out RDL structure with fine pitch line-width and line-spacing
US10522440B2 (en) * 2017-11-07 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
US10283377B1 (en) * 2017-11-07 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and manufacturing method thereof
US11328969B2 (en) * 2017-11-16 2022-05-10 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device and manufacturing method thereof
US10734323B2 (en) * 2017-11-22 2020-08-04 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201813041A (zh) * 2016-04-12 2018-04-01 聯發科技股份有限公司 半導體封裝結構
TW201740443A (zh) * 2016-05-05 2017-11-16 台灣積體電路製造股份有限公司 封裝體及其形成方法
TW201740529A (zh) * 2016-05-05 2017-11-16 台灣積體電路製造股份有限公司 整合扇出型封裝及其製造方法
TW201826418A (zh) * 2016-08-29 2018-07-16 上海兆芯集成電路有限公司 晶片封裝製程
TW201820565A (zh) * 2016-11-29 2018-06-01 新加坡商Ｐｅｐ創新私人有限公司 晶片封裝方法及封裝結構

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