TWI692048B - Backside drill embedded die substrate - Google Patents

Backside drill embedded die substrate Download PDF

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Publication number
TWI692048B
TWI692048B TW106108653A TW106108653A TWI692048B TW I692048 B TWI692048 B TW I692048B TW 106108653 A TW106108653 A TW 106108653A TW 106108653 A TW106108653 A TW 106108653A TW I692048 B TWI692048 B TW I692048B
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Taiwan
Prior art keywords
die
layer
substrate
conductive
dielectric layer
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TW106108653A
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Chinese (zh)
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TW201737394A (en
Inventor
金大益
符杰
章韓 尹
金鎮寛
曼紐 阿爾德雷特
左承杰
馬利歐 維雷茲
鐘海 金
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美商高通公司
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Publication of TW201737394A publication Critical patent/TW201737394A/en
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Publication of TWI692048B publication Critical patent/TWI692048B/en

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Abstract

A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.

Description

背側鑽孔嵌入晶粒式基板Drilled back side embeded grain type substrate

本專利申請案主張於2016年3月18日向美國專利商標局提出申請的非臨時申請案第15/074,750的優先權和權益，其全部內容經由援引如同在下文全面闡述一般且出於所有適用目的納入於此。This patent application claims the priority and rights of the non-provisional application No. 15/074,750 filed with the US Patent and Trademark Office on March 18, 2016, the entire contents of which are cited as if fully explained below and for all applicable purposes Included here.

各個特徵大體而言係關於嵌入晶粒式基板，並且尤其係關於其中晶粒在背側鑽孔製程期間被穿透以從該晶粒內暴露傳導焊盤的嵌入晶粒式基板。The various features relate generally to embedded die substrates, and in particular to embedded die substrates in which die are penetrated during the backside drilling process to expose conductive pads from within the die.

對於掌上型和可穿戴電子裝置的需求持續增長。掌上型電子裝置的實例包括行動蜂巢式電話、成像裝置（例如，相機）、音樂裝置（例如，MP3播放機），以及整合了一或多個剛剛提到的裝置的功能性的裝置。可穿戴電子裝置的實例包括可整合成像裝置、視訊顯示器和網際網路存取終端的功能性的眼鏡。可穿戴裝置的附加實例包括可整合監視/記錄/傳送使用者的生理參數（例如，心率、血氧水平、睡眠期間的不寧）及/或地理位置的裝置的功能性的可腕戴式裝置。可腕戴式裝置可附加或替換地將行動蜂巢裝置的功能性與彩色顯示器整合。許多掌上型和可穿戴電子裝置與某種形式的無線通訊整合。使用者期待電子裝置的每次反覆運算所帶來的新特徵、附加記憶體，以及改良的效能。此外，使用者期望其裝置儘管納入新特徵、附加記憶體和改良的效能，但仍將保持相同尺寸或在尺寸上有所減小。The demand for handheld and wearable electronic devices continues to grow. Examples of handheld electronic devices include mobile cellular phones, imaging devices (eg, cameras), music devices (eg, MP3 players), and devices that integrate the functionality of one or more of the devices just mentioned. Examples of wearable electronic devices include functional glasses that can integrate imaging devices, video displays, and Internet access terminals. Additional examples of wearable devices include functional wearable devices that can integrate monitoring/recording/transmission of user's physiological parameters (eg, heart rate, blood oxygen level, restlessness during sleep) and/or geographic location . The wrist-worn device can additionally or alternatively integrate the functionality of the mobile cellular device with the color display. Many handheld and wearable electronic devices are integrated with some form of wireless communication. Users expect new features, additional memory, and improved performance from each iteration of the electronic device. In addition, users expect their devices to retain the same size or be reduced in size despite incorporating new features, additional memory, and improved performance.

為了減小尺寸，裝置可以電晶體密度的增大及/或裝置內納入的晶粒的尺寸的減小的方式來設計。至少出於保護和整合目的，晶粒可被安裝到封裝中。為了減小封裝尺寸，晶粒到封裝中的導線接合可讓步於倒裝晶片接合。封裝形式（諸如，球柵陣列）亦可被用來減小裝置的整體尺寸。In order to reduce the size, the device can be designed in such a way that the density of transistors increases and/or the size of the crystal grains incorporated in the device decreases. At least for protection and integration purposes, the die can be installed into the package. To reduce package size, die-to-package wire bonding can yield to flip chip bonding. Package forms (such as ball grid arrays) can also be used to reduce the overall size of the device.

晶粒/封裝的垂直整合亦可幫助減小電子裝置的整體尺寸。在垂直整合設計中，晶粒/封裝可彼此堆疊。垂直堆疊的晶粒/封裝的實例包括層疊封裝（PoP）結構。PoP結構可包括球柵陣列封裝的垂直堆疊。The vertical integration of the die/package can also help to reduce the overall size of the electronic device. In a vertically integrated design, dies/packages can be stacked on top of each other. Examples of vertically stacked dies/packages include package-on-package (PoP) structures. The PoP structure may include a vertical stack of ball grid array packages.

用於垂直整合的另一結構被稱為嵌入晶粒式基板或嵌入式層壓基板（在本文出於一致性被稱為嵌入晶粒式基板（EDS））。EDS可採用多層式基板。為了減小垂直尺寸，代替將主動晶粒及/或主動/被動組件安裝到該多層式基板頂部的是，該主動晶粒及/或主動/被動組件被安裝在該多層式基板的腔內。Another structure for vertical integration is called an embedded die substrate or embedded laminate substrate (herein referred to as an embedded die substrate (EDS) for consistency). EDS can use multi-layer substrate. In order to reduce the vertical size, instead of mounting the active die and/or active/passive components on top of the multilayer substrate, the active die and/or active/passive components are installed in the cavity of the multilayer substrate.

EDS的使用可減小垂直尺寸，但在實現中仍留下困難。例如，在EDS實現中，從毗鄰於晶粒的相對背側（例如，第二側）的節點接取該晶粒的頂側（例如，第一側）上的焊盤可涉及使用製造昂貴的晶粒。由此期望例如降低在EDS實現中使用的晶粒的成本，但維持從毗鄰於晶粒的背側的節點對該晶粒的頂側上的焊盤的接取。The use of EDS can reduce the vertical size, but it still leaves difficulties in implementation. For example, in an EDS implementation, accessing the pad on the top side (eg, the first side) of the die from a node adjacent to the opposite back side (eg, the second side) of the die may involve the use of expensive manufacturing Grains. It is therefore desirable, for example, to reduce the cost of the die used in EDS implementations, but to maintain access to the pads on the top side of the die from nodes adjacent to the back side of the die.

本文所揭示的各態樣提供了一種裝置以及製造該裝置（諸如嵌入晶粒式基板）的方法。The various aspects disclosed herein provide a device and a method of manufacturing the device (such as an embedded die substrate).

根據一個態樣，一種裝置可包括具有第一側和相對的第二側的基板。該裝置可進一步包括從第一側限定在基板內的腔以及耦合至該腔的基底的晶粒。該晶粒可在晶粒遠離腔的基底的一側上具有傳導焊盤。該裝置可進一步包括延伸穿過基板的第二側、晶粒和傳導焊盤並被限定在其內的孔。該裝置可仍進一步包括在該孔內且在基板的第二側和傳導焊盤之間延伸並穿過基板的該第二側和該傳導焊盤的傳導材料。該傳導材料可形成或被描述為互連。更詳細而言，該傳導材料可形成或被描述為單分段晶粒穿透互連。According to one aspect, a device may include a substrate having a first side and an opposite second side. The device may further include a cavity defined in the substrate from the first side and a die coupled to the base of the cavity. The die may have a conductive pad on the side of the die that is away from the base of the cavity. The device may further include a hole extending through and defined within the second side of the substrate, the die, and the conductive pad. The device may still further include a conductive material that extends within the hole and between the second side of the substrate and the conductive pad and passes through the second side of the substrate and the conductive pad. The conductive material may be formed or described as an interconnect. In more detail, the conductive material may form or be described as a single-segmented grain-penetrating interconnect.

在一些實現中，該基板是核心基板，其包括被夾在該基板的第一側處的第一介電層與該基板的第二側處的第二介電層之間的傳導層。在一些實例中，在該基板為此類核心基板時，腔缺少第一介電層和傳導層，並且腔的基底由腔中暴露的第二介電層限定。In some implementations, the substrate is a core substrate that includes a conductive layer sandwiched between a first dielectric layer at the first side of the substrate and a second dielectric layer at the second side of the substrate. In some examples, when the substrate is such a core substrate, the cavity lacks the first dielectric layer and the conductive layer, and the base of the cavity is defined by the exposed second dielectric layer in the cavity.

在一態樣，該孔是穿過該基板的第二側、晶粒和傳導焊盤連續的。在一態樣，該孔是沿著延伸穿過該基板的第二側、晶粒和傳導焊盤的線性軸成同軸的。在一態樣，該孔是沿該孔的長度的單個線性孔。In one aspect, the hole is continuous through the second side of the substrate, the die, and the conductive pad. In one aspect, the hole is coaxial along a linear axis extending through the second side of the substrate, the die, and the conductive pad. In one aspect, the hole is a single linear hole along the length of the hole.

在一態樣，該傳導材料是單體的單分段。該傳導材料包括僅一層。In one aspect, the conductive material is a single segment of a monomer. The conductive material includes only one layer.

根據另一態樣，一種裝置可包括具有第一側和相對的第二側的基板。該裝置可進一步包括從第一側限定在基板內的腔以及耦合至該腔的基底的晶粒。該晶粒可在晶粒遠離腔的基底的一側上具有傳導焊盤。該裝置仍可進一步包括耦合至基板的第二側的層壓層。在此類態樣，基板的第二側被夾在晶粒與層壓層之間。該裝置可進一步包括延伸穿過層壓層、基板的第二側、晶粒和傳導焊盤並被限定在其內的孔。該裝置可再進一步包括傳導材料，其在該孔內並且在層壓層、基板的第二側、晶粒和傳導焊盤之間延伸並穿過上述各者。該傳導材料可形成或被描述為互連。更詳細而言，傳導材料可形成或被描述為單分段晶粒穿透互連。According to another aspect, a device may include a substrate having a first side and an opposite second side. The device may further include a cavity defined in the substrate from the first side and a die coupled to the base of the cavity. The die may have a conductive pad on the side of the die that is away from the base of the cavity. The device may still further include a laminate layer coupled to the second side of the substrate. In this aspect, the second side of the substrate is sandwiched between the die and the laminate layer. The device may further include a hole extending through and defined within the laminate layer, the second side of the substrate, the die, and the conductive pad. The device may still further include a conductive material that extends within the hole and between the laminate layer, the second side of the substrate, the die and the conductive pad and passes through each of the above. The conductive material may be formed or described as an interconnect. In more detail, the conductive material may form or be described as a single-segmented grain through interconnect.

在一些實現中，該基板是核心基板，其包括被夾在該基板的第一側處的第一介電層與該基板的第二側處的第二介電層之間的傳導層。In some implementations, the substrate is a core substrate that includes a conductive layer sandwiched between a first dielectric layer at the first side of the substrate and a second dielectric layer at the second side of the substrate.

在一態樣，該孔是穿過層壓層、基板的第二側、晶粒和傳導焊盤連續的。在一態樣，該孔是沿著延伸穿過層壓層、基板的第二側、晶粒和傳導焊盤的線性軸成同軸的。在一態樣，該孔是沿該孔的長度的單個線性孔。In one aspect, the hole is continuous through the laminate layer, the second side of the substrate, the die, and the conductive pad. In one aspect, the hole is coaxial along a linear axis that extends through the laminate layer, the second side of the substrate, the die, and the conductive pad. In one aspect, the hole is a single linear hole along the length of the hole.

在一態樣，該傳導材料是單體的單分段。該傳導材料包括僅一層。In one aspect, the conductive material is a single segment of a monomer. The conductive material includes only one layer.

在一態樣，該裝置被納入從包括以下至少一者的群組中選擇的裝置中：行動裝置、掌上型個人通訊系統（PCS）單元、個人數位助理、可攜式資料終端、啟用全球定位系統（GPS）的裝置、導航裝置、機上盒、音樂播放機、視訊播放機、娛樂單元、固定位置終端、通訊裝置、行動電話、智慧型電話、平板電腦、電腦、可穿戴裝置、物聯網路（IoT）裝置、膝上型電腦、伺服器、路由器，以及實現在機動車輛中的電子裝置。In one aspect, the device is included in a device selected from the group consisting of at least one of: a mobile device, a handheld personal communication system (PCS) unit, a personal digital assistant, a portable data terminal, and global positioning enabled System (GPS) devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed-position terminals, communication devices, mobile phones, smart phones, tablets, computers, wearable devices, Internet of Things Internet of Things (IoT) devices, laptops, servers, routers, and electronic devices implemented in motor vehicles.

根據另一態樣，該裝置可包括具有第一側和相對的第二側的基板。該裝置可進一步包括從第一側限定在基板內的腔以及耦合至腔的基底的晶粒。該晶粒可在晶粒遠離腔的基底的一側上具有傳導焊盤。該裝置可進一步包括用於互連穿透基板和晶粒並將傳導焊盤耦合至基板的第二側上的與傳導焊盤相對的節點的構件。根據一個實例，用於互連的構件可包括延伸穿過基板的第二側、晶粒和傳導焊盤並被限定在其內的孔；並且可進一步包括在該孔內且在基板的第二側和傳導焊盤之間延伸並穿過基板的該第二側和該傳導焊盤的傳導材料。根據另一實例，用於互連的構件可以是穿過基板的第二側、晶粒和傳導焊盤連續的。根據又一實例，用於互連的構件可以是沿著延伸穿過基板的第二側、晶粒和傳導焊盤的線性軸成同軸的。在另一實例中，用於互連的構件包括沿孔的長度的單個線性孔。在又一實例中，用於互連的構件包括被形成為從傳導焊盤內耦合至傳導焊盤的單體單分段的傳導材料。According to another aspect, the device may include a substrate having a first side and an opposite second side. The device may further include a cavity defined in the substrate from the first side and a die coupled to the base of the cavity. The die may have a conductive pad on the side of the die that is away from the base of the cavity. The device may further include means for interconnecting the through-substrate and the die and coupling the conductive pad to a node on the second side of the substrate opposite the conductive pad. According to one example, the member for interconnection may include a hole extending through and defined in the second side of the substrate, the die and the conductive pad; and may further include a second in the hole and in the substrate A conductive material extending between the side and the conductive pad and passing through the second side of the substrate and the conductive pad. According to another example, the member for interconnection may be continuous through the second side of the substrate, the die, and the conductive pad. According to yet another example, the member for interconnection may be coaxial along a linear axis extending through the second side of the substrate, the die, and the conductive pad. In another example, the means for interconnecting includes a single linear hole along the length of the hole. In yet another example, the means for interconnecting includes a conductive material formed as a single unit segment coupled from within the conductive pad to the conductive pad.

本文所描述的另一態樣提供了一種製造嵌入晶粒式基板的方法。該方法包括以下步驟：提供具有第一側和相對的第二側的基板。該方法進一步包括以下步驟：形成從第一側限定在基板內的腔。該方法進一步包括以下步驟：將晶粒耦合至該腔的基底，該晶粒在該晶粒遠離該腔的基底的一側上具有傳導焊盤。在一態樣，該方法亦包括以下步驟：鑽孔，該孔延伸穿過基板的第二側、晶粒和傳導焊盤並被限定在其內。該方法仍進一步包括以下步驟：用在基板的第二側、晶粒和傳導焊盤之間延伸並穿過上述各者並且從該孔內耦合至傳導焊盤的傳導材料來鍍敷及/或填充該孔。Another aspect described herein provides a method of manufacturing an embedded die substrate. The method includes the steps of providing a substrate having a first side and an opposing second side. The method further includes the step of forming a cavity defined in the substrate from the first side. The method further includes the step of coupling a die to the substrate of the cavity, the die having a conductive pad on a side of the die away from the substrate of the cavity. In one aspect, the method also includes the step of drilling a hole that extends through and is defined within the second side of the substrate, the die, and the conductive pad. The method still further includes the steps of: plating and/or using a conductive material extending between the second side of the substrate, between the die and the conductive pad and passing through each of the above and coupled from the hole to the conductive pad Fill the hole.

在一些實現中，該晶粒在鑽孔之前被耦合至腔的基底。在一態樣，鑽孔是一次性執行的。因此，該孔在一次製程中被鑽成穿過該基板的第二側、晶粒和傳導焊盤。在一態樣，該孔被形成為是沿著延伸穿過基板的第二側、晶粒和傳導焊盤的線性軸成同軸的。在一態樣，該孔被形成為沿該孔的長度的單個線性孔。In some implementations, the die is coupled to the base of the cavity before drilling. In one aspect, drilling is performed at once. Therefore, the hole is drilled through the second side of the substrate, the die, and the conductive pad in one process. In one aspect, the hole is formed to be coaxial along a linear axis extending through the second side of the substrate, the die, and the conductive pad. In one aspect, the hole is formed as a single linear hole along the length of the hole.

在一態樣，該傳導材料被形成為單體的單分段。在一些實現中，在基板的第二側、晶粒和傳導焊盤之間延伸並穿過上述各者的傳導材料被形成為僅一層。在另一態樣，該方法可進一步包括以下步驟：將層壓層耦合至基板的第二側，其中該孔被進一步鑽成延伸穿過該層壓層並被限定在該層壓層內，並且該傳導材料進一步在該層壓層之間延伸並穿過該層壓層。In one aspect, the conductive material is formed as a single segment of a single body. In some implementations, the conductive material that extends between and passes through the second side of the substrate, the die, and the conductive pad is formed as only one layer. In another aspect, the method may further include the step of coupling the laminate layer to the second side of the substrate, wherein the hole is further drilled to extend through the laminate layer and be defined within the laminate layer, And the conductive material further extends between and through the laminated layer.

本文所描述的另一態樣提供了另一種製造嵌入晶粒式基板的方法。該方法包括以下步驟：提供具有第一側和相對的第二側的基板。該方法進一步包括以下步驟：形成從第一側限定在基板內的腔。該方法仍進一步包括以下步驟：將晶粒耦合至腔的基底，該晶粒在該晶粒遠離腔的基底的一側上具有傳導焊盤。該方法仍進一步包括以下步驟：將層壓層耦合至基板的第二側。在一態樣，該方法亦包括以下步驟：鑽孔，該孔延伸穿過層壓層、基板的第二側、晶粒和傳導焊盤並被限定在其內。該方法仍進一步包括以下步驟：用在層壓層、基板的第二側、晶粒和傳導焊盤之間延伸並穿過上述各者並且從孔內耦合至傳導焊盤的傳導材料來鍍敷及/或填充該孔。Another aspect described herein provides another method of manufacturing an embedded die substrate. The method includes the steps of providing a substrate having a first side and an opposing second side. The method further includes the step of forming a cavity defined in the substrate from the first side. The method still further includes the step of coupling a die to the substrate of the cavity, the die having a conductive pad on a side of the die away from the substrate of the cavity. The method still further includes the step of coupling the laminate layer to the second side of the substrate. In one aspect, the method also includes the step of drilling a hole that extends through and is defined within the laminate layer, the second side of the substrate, the die, and the conductive pad. The method still further includes the steps of: plating with a conductive material that extends between and passes through the laminate layer, the second side of the substrate, the die, and the conductive pad and is coupled from the hole to the conductive pad And/or fill the hole.

在一些實現中，在鑽孔之前，該晶粒被耦合至腔的基底並且該層壓層被耦合至基板的第二側。在一態樣，鑽孔是一次性執行的。在一態樣，孔被形成為是沿著延伸穿過層壓層、基板的第二側、晶粒和傳導焊盤的線性軸成同軸的。在一態樣，孔被形成為沿孔的長度的單個線性孔。In some implementations, prior to drilling, the die is coupled to the base of the cavity and the laminate layer is coupled to the second side of the substrate. In one aspect, drilling is performed at once. In one aspect, the hole is formed to be coaxial along a linear axis that extends through the laminate layer, the second side of the substrate, the die, and the conductive pad. In one aspect, the hole is formed as a single linear hole along the length of the hole.

在一態樣，傳導材料被形成為單體的單分段。在一些實現中，在層壓層、基板的第二側、晶粒和傳導焊盤之間延伸並穿過上述各者的傳導材料被形成為僅一層。在一個實例中，傳導材料在層壓層的遠離基板的第二側的表面與傳導焊盤之間形成互連。In one aspect, the conductive material is formed as a single segment of a single body. In some implementations, the conductive material that extends between and passes through the laminate layer, the second side of the substrate, the die, and the conductive pad is formed as only one layer. In one example, the conductive material forms an interconnection between the surface of the laminate layer on the second side away from the substrate and the conductive pad.

在以下描述中，提供了具體細節以提供對本案的各態樣的透徹理解。然而，一般技術者將理解，沒有本文提供的該等具體細節亦可實踐該等態樣。例如，電路可能用方塊圖圖示以避免使該等態樣湮沒在不必要的細節中。在其他實例中，公知的電路、結構和技術可能不被詳細圖示以免模糊本案的該等態樣。In the following description, specific details are provided to provide a thorough understanding of the various aspects of the case. However, one of ordinary skill will understand that these aspects can be practiced without the specific details provided herein. For example, the circuit may be illustrated with a block diagram to avoid obscuring these features in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail in order not to obscure these aspects of the case.

在一些實現中，晶粒的高度可以沿晶粒的Z方向來定義，該Z方向在本案的附圖中圖示。在一些實現中，晶粒的Z方向可以沿晶粒的第一側（例如，頂側）與相對的第二側（例如，背側）之間的軸來定義。術語頂側（或頂）和背側（或底）可被任意性地指派；然而，作為實例，晶粒的頂側表面可以是包括大部分輸入/輸出焊盤的部分，而晶粒的背側表面可以是被接合、黏附或以其他方式附連到基板的部分。在一些實現中，晶粒的頂側部分可以是晶粒的背側，而晶粒的背側部分可以是晶粒的頂側。頂側部分可以是相對於較低背側部分的較高部分。背側部分可以是相對於較高的頂側部分而言的較低部分。頂側部分和背側部分的進一步實例將在下文進一步描述。晶粒的X-Y方向可代表晶粒的橫向方向及/或覆蓋區。X-Y方向的實例在本案的附圖中圖示及/或在下文進一步描述。在本案的許多附圖中，可跨X-Z橫截面或X-Z平面圖示晶粒以及EDS的各部分。然而，在一些實現中，可跨Y-Z橫截面或Y-Z平面表示晶粒以及EDS的各部分。In some implementations, the height of the grain can be defined along the Z direction of the grain, which is illustrated in the drawings of the present case. In some implementations, the Z direction of the grain may be defined along the axis between the first side (eg, top side) and the opposite second side (eg, back side) of the grain. The terms top side (or top) and back side (or bottom) can be arbitrarily assigned; however, as an example, the top side surface of the die can be the portion that includes most of the input/output pads, while the back side of the die The side surface may be a part that is bonded, adhered, or otherwise attached to the substrate. In some implementations, the top side portion of the die may be the back side of the die, and the back side portion of the die may be the top side of the die. The top side part may be a higher part relative to the lower back side part. The back side portion may be a lower portion relative to the higher top side portion. Further examples of the top side portion and the back side portion will be further described below. The X-Y direction of the crystal grain may represent the lateral direction of the crystal grain and/or the coverage area. Examples of the X-Y direction are illustrated in the drawings of this case and/or described further below. In many drawings in this case, the grains and parts of the EDS can be illustrated across the X-Z cross-section or X-Z plane. However, in some implementations, the grains and portions of the EDS may be represented across the Y-Z cross-section or Y-Z plane.

在一些實現中，互連是晶粒、EDS、裝置或封裝的允許或者促進兩個點、元件及/或組件之間的電及/或熱耦合的元件或組件。在一些實現中，互連可包括跡線，及/或經鍍敷及/或填充的孔（例如，通孔）。在一些實現中，互連可由級聯分段（層）（諸如串聯連接的複數個通孔）形成；此類互連在本文中可被稱為分段式互連。分段式互連可包括分段（例如，層）之間的縫，至少因為分開的分段可在處理期間的分開操作期間被形成。因此，分段式互連（諸如，由通孔的級聯堆疊形成的分段式互連）可在分段之間具有沿分段式互連的長度、貫穿分段式互連的長度的縫。相反，在一些實現中，互連可由僅一個分段（例如，僅一層）形成；此類互連在本文中可被稱為單分段互連（亦即，非分段的互連）。單分段互連可沿該單分段互連的長度、貫穿該單分段互連的長度不具有縫。在一些實現中，互連可以用可被配置成為信號（例如，資料信號、接地信號、功率信號）提供從第一節點到第二節點的電路徑的導電材料來製造。在一些實現中，互連可以用可被配置成提供從第一節點到第二節點的熱路徑的導熱材料來製造。互連可以是導電及/或導熱的。互連可以是電路的一部分。傳導材料實例的非排他性列表包括金、銀和銅。傳導材料可以是傳導糊劑。In some implementations, an interconnect is an element or component of a die, EDS, device, or package that allows or facilitates electrical and/or thermal coupling between two points, elements and/or components. In some implementations, the interconnect may include traces, and/or plated and/or filled holes (eg, vias). In some implementations, interconnects may be formed by cascading segments (layers) (such as a plurality of vias connected in series); such interconnects may be referred to herein as segmented interconnects. The segmented interconnection may include a gap between segments (eg, layers), at least because separate segments may be formed during a separate operation during processing. Therefore, a segmented interconnect (such as a segmented interconnect formed by a cascaded stack of vias) may have between the segments along the length of the segmented interconnect, through the length of the segmented interconnect Seam. In contrast, in some implementations, interconnections may be formed by only one segment (eg, only one layer); such interconnections may be referred to herein as single-segment interconnections (ie, non-segmented interconnections). The single-segment interconnection may have no slits along the length of the single-segment interconnection or through the length of the single-segment interconnection. In some implementations, the interconnect may be fabricated with conductive materials that can be configured to provide electrical paths from the first node to the second node into signals (eg, data signals, ground signals, power signals). In some implementations, the interconnect may be fabricated with a thermally conductive material that can be configured to provide a thermal path from the first node to the second node. The interconnection may be electrically and/or thermally conductive. The interconnection may be part of the circuit. A non-exclusive list of examples of conductive materials includes gold, silver, and copper. The conductive material may be a conductive paste.

如本文所使用的，鑽孔（例如，鑽出孔）可以用包括例如光微影製程、機械製程及/或鐳射鑽孔製程的製程來實現。As used herein, drilling (eg, drilling holes) can be achieved with processes including, for example, photolithography processes, mechanical processes, and/or laser drilling processes.

如本文所使用的，孔可以是實體物體中由在該實體物體中形成的（諸）側壁限定的腔、開口或者空穴。As used herein, a hole may be a cavity, opening, or cavity in a solid object defined by the sidewall(s) formed in the solid object.

在多層裝置中，將最上面的金屬化層標識為第一金屬化層或「M1」層是慣例。每一個較低金屬化層按慣例遞增1。本文提供的示例性EDS被圖示為具有四個金屬化層（M1、M2、M3、M4）。然而，根據本文所描述的各態樣的EDS可以用任何數目的金屬化層來提供。本文完全不意欲限制EDS的金屬化層的數目。概覽 In multilayer devices, it is common practice to identify the topmost metallization layer as the first metallization layer or "M1" layer. Each lower metallization layer is incremented by 1 as usual. The exemplary EDS provided herein is illustrated as having four metallization layers (M1, M2, M3, M4). However, EDS according to various aspects described herein may be provided with any number of metallization layers. This article is by no means intended to limit the number of metallization layers of EDS. Overview

一些特徵係關於嵌入晶粒式基板（EDS），其包括具有被夾在相對的介電層之間的傳導層的基板，基板中的腔，在腔內被安裝到基板的晶粒，以及在基板的該等相對側上被層壓到介電層的預浸層。至少一個單分段互連（例如，用一個連續長度的一種傳導材料鍍敷及/或填充的孔）延伸穿過EDS的背側上的預浸層、基板的介電層並延伸到晶粒。該單分段互連可將晶粒的第一側（例如，頂側）上的傳導焊盤電及/或熱耦合到該預浸層的相對第二側（例如，背側）上的傳導焊盤。該單分段互連（包括在晶粒內的部分）可在EDS的背側鑽孔製程期間、在晶粒在腔內被耦合（例如，安裝）到基板之後被形成。與使用例如在對應於EDS中的預指定位置的位置處具有先前形成的穿基板通孔（TSV）的晶粒相比，在EDS的背側鑽孔製程期間在預指定的位置處形成單分段互連（包括在晶粒內的部分）可導致晶粒成本的降低以及將晶粒整合到EDS中的成本的降低。另外，在EDS的背側鑽孔製程期間在預指定的位置處形成單分段互連（包括在晶粒內的部分）准許該單分段互連沿其整個長度用一種傳導材料來製造，該傳導材料可被選擇以最小化熱耗散接地電阻。示例性嵌入晶粒式基板晶粒類型 Some features pertain to an embedded die substrate (EDS), which includes a substrate with a conductive layer sandwiched between opposing dielectric layers, a cavity in the substrate, a die mounted to the substrate within the cavity, and a A prepreg layer laminated to the dielectric layer on the opposite sides of the substrate. At least one single-segment interconnect (eg, holes plated and/or filled with a continuous length of a conductive material) extends through the prepreg layer on the back side of the EDS, the dielectric layer of the substrate, and extends to the die . The single-segment interconnect may electrically and/or thermally couple the conductive pads on the first side (eg, top side) of the die to the conductive on the opposite second side (eg, back side) of the prepreg layer Pad. The single-segment interconnect (including the portion within the die) may be formed during the backside drilling process of the EDS after the die is coupled (eg, mounted) to the substrate within the cavity. Compared with using, for example, a die having a through-substrate via (TSV) formed previously at a position corresponding to a pre-specified position in EDS, a single point is formed at a pre-specified position during the backside drilling process of EDS Segment interconnection (including the portion within the die) can lead to a reduction in the cost of the die and the cost of integrating the die into the EDS. In addition, the formation of a single-segment interconnection (including the portion within the die) at a pre-specified location during the backside drilling process of EDS permits the single-segment interconnection to be manufactured with a conductive material along its entire length, The conductive material can be selected to minimize heat dissipation ground resistance. Exemplary embedded die substrate die types

EDS通常使用兩種晶粒類型之一。第一類型的晶粒在晶粒的頂側表面上具有輸入/輸出/接地/功率焊盤。EDS中第一類型的晶粒的使用呈現出關於佈線的問題。所有佈線可在晶粒的頂側表面上開始（或結束）。到EDS的在第一類型的晶粒之下的各層的佈線可利用從晶粒向上且在晶粒上方佈線的跡線。從晶粒向上且在晶粒上方對跡線佈線可能在二維和三維空間中皆是困難的。解決佈線問題所涉及的額外時間可提高整體設計的成本。附加跡線可降低可靠性，因為斷路或短路的金屬化的可能性增大。另外，EDS中第一類型的晶粒的使用可不利地影響效能，因為EDS的熱及/或電要求可能至少部分地因跡線的迂回佈線而不被滿足。例如，金屬化的長佈線可使得難以從在EDS內的晶粒中除熱。另外，金屬化的長佈線使得不想要的電磁能量更有可能可耦合到此金屬化中並且由此獲得對晶粒的內部電路系統的接取，從而與晶粒的操作發生干擾。EDS usually uses one of two grain types. The first type of die has input/output/ground/power pads on the top side surface of the die. The use of the first type of die in EDS presents problems regarding wiring. All wiring can start (or end) on the top side surface of the die. The wiring to the layers of the EDS below the first type of die can utilize traces that are routed upward from and above the die. Routing traces from the grain up and above the grain can be difficult in both two-dimensional and three-dimensional spaces. The extra time involved in solving wiring problems can increase the overall design cost. Additional traces can reduce reliability because the possibility of metallization of open or short circuits increases. In addition, the use of the first type of die in EDS can adversely affect performance because the thermal and/or electrical requirements of EDS may not be met at least in part due to the circuitous routing of traces. For example, long metallized wiring can make it difficult to remove heat from the grains within the EDS. In addition, the long metallized wiring makes it more likely that unwanted electromagnetic energy can be coupled into this metallization and thereby gain access to the internal circuitry of the die, thereby interfering with the operation of the die.

第二類型的晶粒可在晶粒的背側表面上具有到至少一些輸入/輸出/接地/功率焊盤的接取。從背側表面接取焊盤是經由使用晶粒中的穿基板通孔（TSV）（亦被稱為穿矽通孔）來實現的。TSV可將頂側焊盤互連到背側焊盤。TSV可被概念化為晶粒中的兩個電節點之間的垂直電連接。在晶粒具有兩個相對的外部表面的情形中，第一節點可以在晶粒的第一（例如，頂側）表面上，而第二節點可以在晶粒的第二（例如，背側）表面上。在此類情形中，TSV可完全穿過晶粒。The second type of die may have access to at least some input/output/ground/power pads on the backside surface of the die. Access to the pads from the backside surface is achieved through the use of through-substrate vias (TSV) in the die (also known as through-silicon vias). TSV can interconnect the top side pad to the back side pad. TSV can be conceptualized as a vertical electrical connection between two electrical nodes in the die. In the case where the die has two opposing outer surfaces, the first node may be on the first (eg, top side) surface of the die, and the second node may be on the second (eg, back side) of the die On the surface. In such cases, the TSV can pass completely through the die.

晶粒的TSV在晶圓廠處的晶粒製造期間形成。如本文所使用的，術語「晶圓廠」代表半導體製造設施或者製造半導體積體電路的場所。在晶圓廠製造晶粒中的TSV至少因增大的晶粒遮罩計數而提高了晶粒的成本，並且增大了用來製造具有TSV的晶粒的操作數目。在晶圓廠將TSV整合到晶粒中亦可涉及與產量相關聯的成本。在晶圓廠生產的一些TSV可能未被正確地製造。例如，在TSV內可能存在斷路，以使得晶粒的第一側上的第一節點將不會被連接到該晶粒的第二側上的第二節點。由於與在晶圓廠製造的TSV相關聯的差錯，產量可能下降並且成本可能上升。The TSV of the die is formed during die manufacturing at the fab. As used herein, the term "fab" refers to a semiconductor manufacturing facility or a place where semiconductor integrated circuits are manufactured. TSVs in fab manufacturing die increase the cost of the die at least due to the increased die mask count and increase the number of operations used to manufacture die with TSVs. The integration of TSVs into dies in fabs can also involve costs associated with output. Some TSVs produced in the fab may not be manufactured correctly. For example, there may be a break in the TSV so that the first node on the first side of the die will not be connected to the second node on the second side of the die. Due to the errors associated with TSVs manufactured at the fab, output may decrease and costs may increase.

在EDS中使用第二類型的晶粒（亦即，具有TSV的晶粒）因在晶粒中納入TSV而導致晶粒的高成本（亦即，製造成有TSV的晶粒比製造成不具有TSV的晶粒成本更高）。涉及附加成本是因為製造成有TSV的晶粒在晶粒的頂側和背側焊盤上皆使用金屬鍍敷，以在EDS整合期間充當鐳射止擋。另外，與由金形成的TSV相結合，與金TSV相關聯的熱傳導並不如由銅提供的熱傳導一般好。因此，使用具有TSV的晶粒的EDS中的熱耗散接地電阻沒有所期望的一般低。示例性嵌入晶粒式基板（ EDS ） The use of the second type of grains in EDS (ie, grains with TSVs) results in the high cost of grains due to the inclusion of TSVs in grains (ie, grains made with TSVs are more expensive than grains made with TSVs TSV's die cost is higher). The additional cost is involved because the die fabricated with TSV uses metal plating on both the top and back side pads of the die to act as a laser stop during EDS integration. In addition, combined with the TSV formed of gold, the heat conduction associated with the gold TSV is not as good as the heat conduction provided by copper. Therefore, the heat dissipation ground resistance in the EDS using the grain with TSV is not as low as expected. Exemplary embedded die substrate ( EDS )

圖1圖示了根據一種辦法的實現第一類型的晶粒124（例如，不具有TSV的晶粒）的嵌入晶粒式基板（EDS）100的實例的橫截面視圖。EDS 100可包括核心基板102，核心基板102包括中央傳導層104、頂側介電層106以及背側介電層108。FIG. 1 illustrates a cross-sectional view of an example of an embedded die substrate (EDS) 100 that implements a first type of die 124 (eg, a die without TSV) according to one approach. The EDS 100 may include a core substrate 102 that includes a central conductive layer 104, a top-side dielectric layer 106, and a back-side dielectric layer 108.

保持晶粒124的腔122可形成在頂側介電層106和中央傳導層104中。腔122的底部可被稱為腔122的「基底」。晶粒124可耦合至腔122的基底（例如，在腔122內耦合至背側介電層108）。腔122可用填充材料138來填充。The cavity 122 holding the die 124 may be formed in the top-side dielectric layer 106 and the central conductive layer 104. The bottom of cavity 122 may be referred to as the "base" of cavity 122. The die 124 may be coupled to the substrate of the cavity 122 (eg, coupled to the backside dielectric layer 108 within the cavity 122). The cavity 122 may be filled with a filling material 138.

晶粒124可包括複數個傳導焊盤128、130、132、134，包括在晶粒124的頂側表面上的第一傳導焊盤128、第二傳導焊盤130、第三傳導焊盤132以及第四傳導焊盤134。圖1的晶粒124不包括TSV（例如，在晶粒製造期間在晶圓廠處形成在晶粒的主體內的通孔）。保護性傳導層136可在該複數個傳導焊盤128、130、132、134中的每一者上提供。The die 124 may include a plurality of conductive pads 128, 130, 132, 134, including a first conductive pad 128, a second conductive pad 130, a third conductive pad 132 on the top side surface of the die 124, and Fourth conductive pad 134. The die 124 of FIG. 1 does not include TSVs (eg, vias formed in the body of the die at the fab during die manufacturing). A protective conductive layer 136 may be provided on each of the plurality of conductive pads 128, 130, 132, 134.

可向頂側介電層106提供頂側層壓層140。可向背側介電層108提供背側層壓層142。The top-side dielectric layer 106 may be provided with a top-side laminate layer 140. The backside dielectric layer 108 may be provided with a backside laminate layer 142.

在圖1的示例性圖示中，在晶粒124的頂側上的該複數個傳導焊盤128、130、132、134之一可連接至EDS 100的處於晶粒124之下的層處的節點（例如，傳導焊盤或跡線）。第二傳導焊盤130與在背側層壓層142的背側上的節點146之間的示例性佈線路徑144（用於電和熱能量）用雙側箭頭來圖示。In the exemplary illustration of FIG. 1, one of the plurality of conductive pads 128, 130, 132, 134 on the top side of die 124 may be connected to the layer of EDS 100 at the level below die 124 Nodes (for example, conductive pads or traces). An exemplary wiring path 144 (for electrical and thermal energy) between the second conductive pad 130 and the node 146 on the back side of the back side laminate layer 142 is illustrated with a double-sided arrow.

頂側鑽孔可被用來到達晶粒124的在該晶粒124頂側上的第二傳導焊盤130。頂側鑽孔可延伸穿過頂側層壓層140和被用來填充腔122的填充材料138。鐳射鑽孔可被用於頂側鑽孔。出於鐳射止擋的目的，保護性傳導層136保護晶粒124的第二傳導焊盤130。鐳射止擋（例如，保護性傳導層136）阻止鐳射鑽孔穿透第二傳導焊盤130到晶粒124中。背側鑽孔可打開從節點146（例如，焊盤或跡線）去往核心基板102的中央傳導層104的路徑。Top-side drilling may be used to reach the second conductive pad 130 of the die 124 on the top side of the die 124. The top-side borehole may extend through the top-side laminate layer 140 and the filler material 138 used to fill the cavity 122. Laser drilling can be used for top side drilling. For the purpose of laser stop, the protective conductive layer 136 protects the second conductive pad 130 of the die 124. A laser stop (eg, protective conductive layer 136) prevents laser drilling from penetrating the second conductive pad 130 into the die 124. Backside drilling may open the path from node 146 (eg, pad or trace) to the central conductive layer 104 of the core substrate 102.

為了達成第二傳導焊盤130與節點146（例如，焊盤或跡線）之間的傳導路徑，可在晶粒124向上和周圍佈線金屬化。金屬化可被向上佈線穿過互連112（穿過頂側層壓層140）。該金屬化可隨後經過晶粒124的邊緣，沿著互連中由傳導跡線148形成的部分被橫向佈線。該金屬化隨後可經過晶粒向下佈線穿過通孔的多個垂直分段（例如，沿Z軸基本對準的分段）和焊盤。例如，金屬化可被佈線穿過第一通孔分段152、第一焊盤154、第二通孔分段156、第三通孔分段158、第二焊盤160和第四通孔分段162，隨後接合背側層壓層142的節點146。任何兩個或兩個以上耦合的通孔分段在本文可被稱為「分段式互連」。剛剛描述的金屬化的迂回佈線可能難以規劃和實現。迂回佈線可向EDS 100的製造添加成本並且可導致EDS 100不能滿足電及/或熱要求。In order to achieve a conductive path between the second conductive pad 130 and the node 146 (eg, pad or trace), metalization may be routed up and around the die 124. The metallization can be routed upward through the interconnect 112 (through the top side laminate layer 140). This metallization may then pass the edge of the die 124 and be routed laterally along the portion of the interconnect formed by the conductive trace 148. This metallization can then be routed down through the die through multiple vertical segments of the via (eg, segments that are substantially aligned along the Z axis) and pads. For example, the metallization may be routed through the first via segment 152, the first pad 154, the second via segment 156, the third via segment 158, the second pad 160, and the fourth via segment Segment 162 then joins node 146 of backside laminate layer 142. Any two or more coupled via segments may be referred to herein as "segmented interconnects." The metalized roundabout wiring just described may be difficult to plan and implement. Circuitous wiring may add cost to the manufacturing of EDS 100 and may cause EDS 100 to fail to meet electrical and/or thermal requirements.

圖2圖示了根據另一種辦法的實現第二類型的晶粒224（例如，具有TSV的晶粒）的EDS 200的實例的橫截面視圖。EDS 200可包括核心基板202，核心基板202包括中央傳導層204、頂側介電層206以及背側介電層208。2 illustrates a cross-sectional view of an example of an EDS 200 that implements a second type of grain 224 (eg, a grain with TSV) according to another approach. The EDS 200 may include a core substrate 202 including a central conductive layer 204, a top-side dielectric layer 206, and a back-side dielectric layer 208.

保持晶粒224的腔222可形成在頂側介電層206和中央傳導層204中。腔222的底部可被稱為腔222的「基底」。晶粒224可耦合至腔222的基底（例如，耦合至腔222內的背側介電層208）。腔222可用填充材料238來填充。The cavity 222 holding the die 224 may be formed in the top-side dielectric layer 206 and the central conductive layer 204. The bottom of cavity 222 may be referred to as the "base" of cavity 222. The die 224 may be coupled to the substrate of the cavity 222 (eg, to the backside dielectric layer 208 within the cavity 222). The cavity 222 may be filled with a filling material 238.

晶粒224可包括複數個傳導焊盤228、230、232、234，包括在晶粒224的頂側表面上的第一傳導焊盤228、第二傳導焊盤230、第三傳導焊盤232以及第四傳導焊盤234。圖2的晶粒224包括第一穿基板通孔（TSV）264和第二TSV 266。第一TSV 264和第二TSV 266可以是在晶粒製造期間在晶圓廠處形成在晶粒224的主體內的通孔。頂側保護性傳導層236可在該複數個傳導焊盤228、230、232、234中的每一者上提供。The die 224 may include a plurality of conductive pads 228, 230, 232, 234, including a first conductive pad 228, a second conductive pad 230, a third conductive pad 232 on the top side surface of the die 224, and Fourth conductive pad 234. The die 224 of FIG. 2 includes a first through-substrate via (TSV) 264 and a second TSV 266. The first TSV 264 and the second TSV 266 may be through holes formed in the body of the die 224 at the fab during die manufacturing. A top-side protective conductive layer 236 may be provided on each of the plurality of conductive pads 228, 230, 232, 234.

可向頂側介電層206提供頂側層壓層240。可向背側介電層208提供背側層壓層242。The top-side dielectric layer 206 may be provided with a top-side laminate layer 240. The backside laminate layer 242 may be provided to the backside dielectric layer 208.

在圖2的示例性圖示中，晶粒224在晶圓廠處製造，其中第一傳導焊盤228耦合至第一TSV 264並且第四傳導焊盤234耦合至第二TSV 266。第一TSV 264和第二TSV 266耦合至背側傳導焊盤268。亦即，晶粒224在晶粒224的主體內包括第一TSV 264和第二TSV 266；第一TSV 264和第二TSV 266在晶圓廠處的晶粒製造期間形成在晶粒224的主體內。在此類配置中，第一傳導焊盤228、第一TSV 264、第四傳導焊盤234、第二TSV 266以及背側傳導焊盤268可由金形成。In the exemplary illustration of FIG. 2, the die 224 is manufactured at the fab, where the first conductive pad 228 is coupled to the first TSV 264 and the fourth conductive pad 234 is coupled to the second TSV 266. The first TSV 264 and the second TSV 266 are coupled to the backside conductive pad 268. That is, the die 224 includes the first TSV 264 and the second TSV 266 in the body of the die 224; the first TSV 264 and the second TSV 266 are formed in the main part of the die 224 during the die manufacturing at the fab in vivo. In such a configuration, the first conductive pad 228, the first TSV 264, the fourth conductive pad 234, the second TSV 266, and the backside conductive pad 268 may be formed of gold.

出於晶粒224的頂側上的鐳射止擋的目的，頂側保護性傳導層236保護該複數個傳導焊盤228、230、232、234。例如，在頂側鑽孔製程期間，鐳射止擋（例如，頂側保護性傳導層236）阻止鐳射鑽孔穿透第二傳導焊盤230並進入到晶粒224中。For the purpose of the laser stop on the top side of the die 224, the top side protective conductive layer 236 protects the plurality of conductive pads 228, 230, 232, 234. For example, during the topside drilling process, a laser stop (eg, topside protective conductive layer 236) prevents the laser drilling from penetrating the second conductive pad 230 and entering the die 224.

出於晶粒224的背側的鐳射止擋的目的，背側保護性傳導層270保護背側傳導焊盤268。向晶粒224添加背側保護性傳導層270向晶粒224添加了成本。背側保護傳導層270充當針對由從EDS 200的背側向核心基板202的中央傳導層204的鐳射鑽孔形成的孔的鐳射止擋。The backside protective conductive layer 270 protects the backside conductive pad 268 for the purpose of a laser stop on the backside of the die 224. Adding the backside protective conductive layer 270 to the die 224 adds cost to the die 224. The backside protective conductive layer 270 serves as a laser stop for the hole formed by the laser drilling from the backside of the EDS 200 to the central conductive layer 204 of the core substrate 202.

可在EDS整合期間在背側鑽孔製程期間形成的互連272、274不延伸進入及/或穿過晶粒224。互連272、274在形成在背側傳導焊盤268上的背側保護性傳導層270（鐳射止擋層）處停止，因為例如在EDS整合期間向晶粒224中鑽孔（例如，延伸進入及/或穿過晶粒的孔、穿透晶粒的孔）可損害晶粒224的顧慮。期望在EDS整合期間不損害晶粒224，例如因為在EDS整合期間替換晶粒224或許是不可能的。受損晶粒的結果可能是EDS 200的完全損耗。The interconnects 272, 274 that may be formed during the backside drilling process during EDS integration do not extend into and/or through the die 224. The interconnects 272, 274 stop at the backside protective conductive layer 270 (laser stop layer) formed on the backside conductive pad 268 because, for example, drilling into the die 224 (eg, extending into And/or holes through the grain, holes through the grain) may damage the concerns of the grain 224. It is desirable not to damage the die 224 during EDS integration, for example because it may not be possible to replace the die 224 during EDS integration. The result of the damaged die may be the complete loss of EDS 200.

對EDS 200的第二種辦法的使用可伴隨著成本。具有TSV的晶粒比不具有TSV的晶粒成本更高。此外，如上文提及的，第一TSV 264和第二TSV 266可由金形成。相反，互連272、274可由銅形成。金的熱傳導率小於銅。相應地，從晶粒224到例如在背側層壓層242的背側上的焊盤或跡線280的熱能量的輸送不是最優的。The use of the second method of EDS 200 can be accompanied by costs. Dies with TSV are more costly than those without TSV. Furthermore, as mentioned above, the first TSV 264 and the second TSV 266 may be formed of gold. In contrast, interconnects 272, 274 may be formed of copper. The thermal conductivity of gold is less than copper. Accordingly, the transfer of thermal energy from the die 224 to, for example, the pad or trace 280 on the back side of the back side laminate layer 242 is not optimal.

與圖1和圖2中圖示的示例性辦法形成對比，經由在EDS整合期間（而非在晶圓廠）向晶粒中進行背側鑽孔而具有形成在晶粒中的至少一個單分段晶粒穿透互連的示例性EDS可經由降低晶圓廠TSV成本而節省成本，可降低用於背側鑽孔的背側銅鍍敷成本，並且可經由使用完全由具有比金好的熱傳導率的導體（諸如銅）形成的單分段晶粒穿透互連而改良效能。改良的示例性嵌入晶粒式基板（ EDS ） In contrast to the exemplary approach illustrated in Figures 1 and 2, there is at least one single point formed in the die via backside drilling into the die during EDS integration (rather than in the fab) Exemplary EDS for segment-through-die interconnects can save costs by reducing fab TSV costs, can reduce the cost of back-side copper plating for back-side drilling, and can be made completely better than gold by using The single-segmented grains formed by thermal conductivity conductors (such as copper) penetrate the interconnect and improve performance. Improved exemplary embedded die substrate ( EDS )

圖3圖示了根據本文所描述的各態樣的包括單分段晶粒穿透第一互連310和單分段晶粒穿透第四互連316的EDS 300的橫截面視圖。FIG. 3 illustrates a cross-sectional view of an EDS 300 including a single-segmented grain through first interconnect 310 and a single-segmented grain through fourth interconnect 316 according to various aspects described herein.

術語「單分段」結構可在本文用來描述單體結構、不可分割結構，及/或未分割結構。如本文所使用的，術語「單分段晶粒穿透互連」可在本文用來描述單體的、不可分割及/或未分割互連，其中該互連的一部分延伸穿過（例如，穿透、刺穿、穿入、穿過、進入）EDS 300的一層（例如，基板層、介電層、層壓層）和EDS 300的晶粒324的至少一部分。單分段晶粒穿透互連的實例可包括柱形結構，其具有帶有所定義非零高度的側壁、經鍍敷的孔及/或由一種傳導材料形成的經填充孔，該經填充孔具有第一端（例如，在第二層壓層342（例如，背側層壓層）或第二介電層308處及/或中的第一端）和遠側的第二端（例如，第一端的終點、EDS 300的晶粒324的第一傳導焊盤328處及/或中，或者在第一傳導焊盤328上提供的保護性傳導層336（例如，鐳射止擋、金屬層、銅層）處及/或中的第二端）。如本文所使用的，單分段晶粒穿透互連（例如，單分段晶粒穿透第一互連310）可例如經由鑽第一孔310H穿過EDS 300的基板302進入EDS 300的晶粒324並且進入晶粒324的傳導焊盤328，並且用從第一孔310H內耦合至傳導焊盤328的第一傳導材料來鍍敷及/或填充第一孔310H來形成。傳導材料可鍍敷第一孔310H的側壁及/或完全地填充第一孔310H。在一些實現中，第一孔310H可具有恆定的直徑或者線性減小的直徑（例如，鑽孔被實現為使得該孔具有恆定直徑或者沿孔的整個長度線性減小的直徑）。The term "single-segment" structure may be used herein to describe a single structure, an indivisible structure, and/or an undivided structure. As used herein, the term "single-segmented grain penetration interconnection" may be used herein to describe a single, indivisible and/or undivided interconnection, where a portion of the interconnection extends through (eg, A layer (eg, substrate layer, dielectric layer, laminate layer) of EDS 300 and at least a portion of die 324 of EDS 300 are penetrated, pierced, penetrated, penetrated, entered. Examples of single-segmented die-penetrating interconnects may include a columnar structure with sidewalls with a defined non-zero height, plated holes, and/or filled holes formed of a conductive material, the filled The hole has a first end (eg, a first end at and/or in the second laminate layer 342 (eg, backside laminate layer) or second dielectric layer 308) and a distal second end (eg , The end point of the first end, and/or in the first conductive pad 328 of the die 324 of the EDS 300, or the protective conductive layer 336 provided on the first conductive pad 328 (eg, laser stop, metal Layer, copper layer) and/or the second end). As used herein, a single-segmented die-penetrating interconnect (eg, a single-segmented die-penetrating first interconnect 310) may enter the EDS 300 through the substrate 302 of the EDS 300, for example, by drilling a first hole 310H The die 324 enters the conductive pad 328 of the die 324 and is formed by plating and/or filling the first hole 310H with the first conductive material coupled into the conductive pad 328 from within the first hole 310H. The conductive material may plate the sidewall of the first hole 310H and/or completely fill the first hole 310H. In some implementations, the first hole 310H may have a constant diameter or a linearly reduced diameter (eg, a drill hole is implemented such that the hole has a constant diameter or a linearly reduced diameter along the entire length of the hole).

在一些實現中，各層的形成（例如，包括複數個分段的導電層）將不在EDS 300中的單分段晶粒穿透互連的橫截面分析或並行搭疊（p搭疊）中被偵測。在一些實現中，根據本文所描述的各態樣的單分段晶粒穿透互連包括僅一個分段（例如，層），此情形與例如複數個接合（例如，抵接）的通孔的堆疊形成對比。In some implementations, the formation of layers (eg, including a plurality of segmented conductive layers) will not be analyzed in cross-sectional analysis or parallel overlap (p-overlap) of the single-segmented grain through interconnect in EDS 300 Detect. In some implementations, the single-segmented die-penetrating interconnection according to various aspects described herein includes only one segment (eg, layer), which is combined with, for example, a plurality of vias (eg, abutting) vias In contrast to the stack.

單分段晶粒穿透第一互連310可沿其整個長度用傳導材料來鍍敷及/或填充。在一些實現中，使用僅一種傳導材料。換言之，在一些實現中，此一種傳導材料沿該單分段晶粒穿透第一互連310的整個長度分佈。此一種傳導材料可形成單體的、不可分割及/或未分割的結構。在一些實現中，該傳導材料可以是銅。在一些實現中，該傳導材料可以是傳導糊劑。單分段晶粒穿透第一互連310可在EDS 300的背側鑽孔製程期間、在晶粒324被耦合（例如，實體安裝）到基板302之後形成。在一些實現中，EDS 300中使用的晶粒324可在晶圓廠處生產為在被預指定用於單分段晶粒穿透第一互連310的位置不具有TSV。The single-segmented die penetration first interconnect 310 may be plated and/or filled with conductive material along its entire length. In some implementations, only one conductive material is used. In other words, in some implementations, this kind of conductive material is distributed along the entire length of the single segmented grain penetrating the first interconnect 310. This conductive material can form a single, indivisible and/or undivided structure. In some implementations, the conductive material may be copper. In some implementations, the conductive material may be a conductive paste. The single-segmented die penetration first interconnect 310 may be formed during the backside drilling process of the EDS 300, after the die 324 is coupled (eg, physically mounted) to the substrate 302. In some implementations, the die 324 used in the EDS 300 may be produced at the fab to have no TSV at a location pre-designated for single-segment die penetration through the first interconnect 310.

EDS 300可包括基板302。基板302可具有第一側301和相對的第二側303。基板302可以是核心基板。基板302可包括被夾在基板302的第一側301處的第一介電層306與基板302的第二側303處的第二介電層308之間的傳導層304。傳導層304可由金屬（諸如銅）形成。傳導層304可以比EDS 300中的其他傳導層（例如，M1層382、M2層384、M3層386、M4層388）厚。傳導層304的厚度可提供剛性及/或對EDS 300的結構支撐。傳導層304可被用作EDS 300的接地平面或者功率平面。The EDS 300 may include the substrate 302. The substrate 302 may have a first side 301 and an opposite second side 303. The substrate 302 may be a core substrate. The substrate 302 may include a conductive layer 304 sandwiched between the first dielectric layer 306 at the first side 301 of the substrate 302 and the second dielectric layer 308 at the second side 303 of the substrate 302. The conductive layer 304 may be formed of metal such as copper. Conductive layer 304 may be thicker than other conductive layers in EDS 300 (eg, M1 layer 382, M2 layer 384, M3 layer 386, M4 layer 388). The thickness of the conductive layer 304 may provide rigidity and/or structural support to the EDS 300. The conductive layer 304 may be used as a ground plane or power plane of the EDS 300.

在替換態樣，基板302可以是核心基板。在替換態樣，構想了基板302可包括被夾在基板302的第一側301處的第一傳導層（未圖示）與基板302的第二側303處的第二傳導層（未圖示）之間的介電層（未圖示）。換言之，在替換態樣，基板302可具有覆在具有傳導層的相對側上的非傳導介電層。可圍繞延伸穿過各層的互連形成合適的絕緣體以防止到介電的任一側上的傳導層的短路。In an alternative aspect, the substrate 302 may be a core substrate. In an alternative aspect, it is contemplated that the substrate 302 may include a first conductive layer (not shown) sandwiched at the first side 301 of the substrate 302 and a second conductive layer (not shown) at the second side 303 of the substrate 302 ) Between the dielectric layers (not shown). In other words, in an alternative aspect, the substrate 302 may have a non-conductive dielectric layer overlying the opposite side with the conductive layer. Appropriate insulators can be formed around the interconnects that extend through the layers to prevent short circuits to the conductive layers on either side of the dielectric .

可在基板302內限定腔322。如本文所描述的，腔322可以是由基板302內的諸側壁限定的開口或空穴。腔322可從基板302的第一側301限定在基板302內。腔322可形成在基板中。腔322可足夠大以保持晶粒324。腔322可藉由包括例如光微影、機械及/或鐳射鑽孔的方法來形成。腔322的底部可被稱為腔322的「基底」。在一些實現中，腔322可缺少第一介電層306和傳導層304，並且腔322的基底可由腔322中暴露的第二介電層308限定。A cavity 322 may be defined within the substrate 302. As described herein, cavity 322 may be an opening or cavity defined by sidewalls within substrate 302. The cavity 322 may be defined within the substrate 302 from the first side 301 of the substrate 302. The cavity 322 may be formed in the substrate. The cavity 322 may be large enough to hold the die 324. The cavity 322 may be formed by methods including, for example, photolithography, mechanical and/or laser drilling. The bottom of cavity 322 may be referred to as the "base" of cavity 322. In some implementations, the cavity 322 may lack the first dielectric layer 306 and the conductive layer 304, and the base of the cavity 322 may be defined by the second dielectric layer 308 exposed in the cavity 322.

晶粒324可包括主動及/或被動電路/組件。晶粒324可使用表面安裝技術（SMT）組件放置系統（常被描述為貼裝機器、晶粒接合機器或射片機）耦合至腔322的基底（例如，在腔322內耦合至第二介電層308）。晶粒324可例如使用黏合劑、焊料或環氧樹脂326耦合至腔322的基底。Die 324 may include active and/or passive circuits/components. The die 324 may be coupled to the substrate of the cavity 322 using surface mount technology (SMT) component placement system (often described as a placement machine, die bonding machine, or film mounter) (eg, coupled to a second medium within the cavity 322 Electrical layer 308). The die 324 may be coupled to the base of the cavity 322 using, for example, an adhesive, solder, or epoxy 326.

晶粒324可包括複數個傳導焊盤328、330、332、334，包括晶粒324在遠離腔322的基底的一側上的第一傳導焊盤328、第二傳導焊盤330、第三傳導焊盤332以及第四傳導焊盤334。圖3中的示例性圖示的晶粒324未圖示在晶粒324的製造期間在晶圓廠處形成在晶粒324內的穿基板通孔（TSV）。在一些實現中，晶粒324可包括在晶粒製造期間在晶圓廠處形成在晶粒324內、但不在被預指定用於單分段晶粒穿透互連（諸如單分段晶粒穿透第一互連310和單分段晶粒穿透第四互連316）的位置上的一或多個TSV。The die 324 may include a plurality of conductive pads 328, 330, 332, 334, including a first conductive pad 328, a second conductive pad 330, a third conductive on the side of the substrate away from the cavity 322 The pad 332 and the fourth conductive pad 334. The exemplary illustrated die 324 in FIG. 3 does not illustrate a through-substrate via (TSV) formed in the die 324 at the fab during the manufacture of the die 324. In some implementations, the die 324 may include formed within the die 324 at the fab during die manufacturing, but is not pre-designated for single-segment die penetration interconnects (such as single-segment die One or more TSVs at locations that penetrate the first interconnect 310 and the single segmented die penetrate the fourth interconnect 316).

該複數個傳導焊盤328、330、332、334可由任何傳導材料（例如，金）形成。保護性傳導層336可在該複數個傳導焊盤328、330、332、334中的每一者上被印刷、沉積、形成或以其他方式提供。在鐳射鑽孔被用於形成單分段晶粒穿透第一互連310、第二互連312、第三互連314及/或單分段晶粒穿透第四互連316的部分的情形中，保護性傳導層336可被用作鐳射止擋。The plurality of conductive pads 328, 330, 332, 334 may be formed of any conductive material (eg, gold). The protective conductive layer 336 may be printed, deposited, formed, or otherwise provided on each of the plurality of conductive pads 328, 330, 332, 334. Laser drilling is used to form a portion of the single-segmented grain through the first interconnect 310, the second interconnect 312, the third interconnect 314 and/or the single-segmented grain through the fourth interconnect 316 In this case, the protective conductive layer 336 may be used as a laser stop.

腔322可用填充材料338來填充以包封、保護及/或固定晶粒324。填充材料338可以是例如包封材料、用來形成第一介電層306的材料，或者預浸材料（諸如被層壓到第一介電層306的頂側表面的預浸材料）。The cavity 322 may be filled with a filling material 338 to encapsulate, protect and/or fix the die 324. The filler material 338 may be, for example, an encapsulating material, a material used to form the first dielectric layer 306, or a prepreg material (such as a prepreg material laminated to the top side surface of the first dielectric layer 306).

可向第一介電層306提供第一層壓層340（例如，頂側層壓層）。可向第二介電層308提供第二層壓層342（例如，背側層壓層）。第一層壓層340和第二層壓層342中的每一者可被稱為預浸（預注入）層。第一層壓層340和第二層壓層342中的每一者可包括一或多個介電和導電層。例如，該等預浸層可經由藉由噴濺向其相應的表面上沉積該等層來提供。向基板302上提供預浸層及/或附加層的其他方式（例如，層壓、接合、附連、黏合、形成）是熟習此項技術者已知的。The first dielectric layer 306 may be provided with a first laminate layer 340 (eg, a top-side laminate layer). The second dielectric layer 308 may be provided with a second laminate layer 342 (eg, a backside laminate layer). Each of the first laminate layer 340 and the second laminate layer 342 may be referred to as a prepreg (pre-injection) layer. Each of the first laminate layer 340 and the second laminate layer 342 may include one or more dielectric and conductive layers. For example, the prepreg layers may be provided by depositing the layers onto their corresponding surfaces by sputtering. Other ways of providing a prepreg layer and/or additional layers on the substrate 302 (eg, lamination, bonding, attachment, bonding, forming) are known to those skilled in the art.

在圖3的示例性圖示中，晶粒324可在晶圓廠處被製造為在被預指定用於單分段晶粒穿透第一互連310和單分段晶粒穿透第四互連316的位置處不具有TSV。其他位置處的TSV是可任選的。減少給定晶粒中的TSV的數目可降低晶粒的成本。代替在晶圓廠處的晶粒製造期間在被預指定用於單分段晶粒穿透第一互連310和單分段晶粒穿透第四互連316的位置處形成TSV的是，單分段晶粒穿透第一互連310和單分段晶粒穿透第四互連316可以在EDS整合期間經由背側鑽孔穿過基板302的至少一部分和晶粒324來形成。In the exemplary illustration of FIG. 3, the die 324 may be fabricated at the fab to be pre-designated for single-segment die penetration first interconnect 310 and single-segment die penetration fourth There is no TSV at the location of interconnect 316. TSVs at other locations are optional. Reducing the number of TSVs in a given die can reduce the cost of the die. Instead of forming TSVs at positions pre-designated for single-segmented die penetration through the first interconnect 310 and single-segmented die penetration through the fourth interconnect 316 during die manufacturing at the fab, The single-segment die-penetration first interconnect 310 and the single-segment die-penetration fourth interconnect 316 may be formed through at least a portion of the substrate 302 and the die 324 via backside drilling during EDS integration.

第一傳導焊盤328和第四傳導焊盤334（其可分別耦合至單分段晶粒穿透第一互連310和單分段晶粒穿透第四互連316）可耦合至晶粒324的主動及/或被動電路。類似地，第二傳導焊盤330和第三傳導焊盤332可耦合至晶粒324的主動及/或被動電路。The first conductive pad 328 and the fourth conductive pad 334 (which may be coupled to the single-segment die penetration first interconnect 310 and the single-segment die penetration fourth interconnect 316, respectively) may be coupled to the die 324 active and/or passive circuits. Similarly, the second conductive pad 330 and the third conductive pad 332 may be coupled to active and/or passive circuits of the die 324.

結合與第二互連312和第三互連314相關聯的頂側鑽孔製程，鐳射止擋（例如，保護性傳導層336）阻止由鐳射鑽孔形成的孔穿透傳導焊盤330、332（其可由金形成）進入晶粒324。第二互連312和第三互連314不延伸進入及/或穿過晶粒324。In conjunction with the top-side drilling process associated with the second interconnect 312 and the third interconnect 314, the laser stop (eg, the protective conductive layer 336) prevents the hole formed by the laser drilling from penetrating the conductive pads 330, 332 (It may be formed of gold) into the grain 324. The second interconnect 312 and the third interconnect 314 do not extend into and/or through the die 324.

結合背側鑽孔製程，單分段晶粒穿透第一互連310和單分段晶粒穿透第四互連316可延伸進入及/或穿過晶粒324。換言之，單分段晶粒穿透第一互連310和單分段晶粒穿透第四互連316可經由鑽孔穿過第二層壓層342（若合適）、第二介電層308（例如，形成在基板302中的腔322的基底）並且進入及/或穿過耦合至腔322的基底的晶粒324來分別被形成在第一孔310H和第四孔316H中。In conjunction with the backside drilling process, the single-segment die penetration first interconnect 310 and the single-segment die penetration fourth interconnect 316 may extend into and/or through the die 324. In other words, the single-segment die-penetrating first interconnect 310 and the single-segment die-penetrating fourth interconnect 316 may pass through the second laminate layer 342 (if appropriate) and the second dielectric layer 308 via drilling (For example, the base of the cavity 322 formed in the substrate 302) and enter and/or pass through the die 324 coupled to the base of the cavity 322 to be formed in the first hole 310H and the fourth hole 316H, respectively.

注意，結合與單分段晶粒穿透第一互連310和單分段晶粒穿透第四互連316相關聯的背側鑽孔製程，不存在處於晶粒324的背側上的鐳射止擋。事實上，鐳射止擋可阻礙在使用鐳射鑽孔實現的背側鑽孔製程期間形成單分段晶粒穿透第一互連310和單分段晶粒穿透第四互連316。至少在被預指定用於形成單分段晶粒穿透互連的位置處消除鐳射止擋可節省成本。Note that in conjunction with the backside drilling process associated with the single-segmented grain penetration first interconnection 310 and the single-segmented grain penetration fourth interconnection 316, there is no laser on the backside of the die 324 Stop. In fact, the laser stop may prevent the formation of single-segmented grain penetration through the first interconnection 310 and the single-segmented grain penetration through the fourth interconnection 316 during the backside drilling process using laser drilling. Eliminating laser stops at least at locations pre-designated for forming single-segmented die-penetrating interconnects can save costs.

在圖3的示例性圖示中，晶粒324的頂側上的第二傳導焊盤330和第三傳導焊盤332中的一者或多者可被連接至在EDS 300處於晶粒324以下的層處的第一節點364和第四節點370（例如，傳導焊盤或跡線）。完成此類連接的佈線路徑的實例在上文結合圖1提供並且為了簡潔將不被重複。In the exemplary illustration of FIG. 3, one or more of the second conductive pad 330 and the third conductive pad 332 on the top side of the die 324 may be connected to where the EDS 300 is below the die 324 The first node 364 and the fourth node 370 at the layer of (eg, conductive pads or traces). Examples of routing paths to complete such connections are provided above in conjunction with FIG. 1 and will not be repeated for brevity.

實現單分段晶粒穿透第一互連310的益處可包括置備經由一種傳導材料（例如，銅）從第一傳導焊盤328（或第一傳導焊盤328上的保護性傳導層336）到第二層壓層342上的M4層388焊盤或跡線366的傳導路徑376。傳導路徑376可穿過晶粒324以及基板302在晶粒324與第二層壓層342之間的部分。由於單分段晶粒穿透第一互連310可由一種傳導材料製成，因此該傳導材料可被選擇為最小化熱耗散接地電阻並最大化熱傳導率。傳導路徑376在圖3中經由雙側箭頭來圖形化地圖示。The benefits of achieving single-segment die penetration through the first interconnect 310 may include provisioning the first conductive pad 328 (or the protective conductive layer 336 on the first conductive pad 328) via a conductive material (eg, copper) Conductive path 376 to the M4 layer 388 pad or trace 366 on the second laminate layer 342. The conductive path 376 may pass through the die 324 and the portion of the substrate 302 between the die 324 and the second laminate layer 342. Since the single-segmented die penetration first interconnect 310 may be made of a conductive material, the conductive material may be selected to minimize heat dissipation ground resistance and maximize thermal conductivity. The conduction path 376 is graphically illustrated in FIG. 3 via double-sided arrows.

實現圖3中圖示的單分段晶粒穿透第四互連316的益處可包括從第四傳導焊盤334（或第四傳導焊盤334上的保護性傳導層336）到第二介電層308上的第三節點368（例如，M3層386第三節點368（例如，焊盤、跡線））的傳導路徑378。傳導路徑378可穿過晶粒324以及基板302在晶粒324與第二層壓層342之間的部分。由於單分段晶粒穿透第四互連316可由一種傳導材料製成，因此該傳導材料可被選擇為最小化熱耗散接地電阻並最大化熱傳導率。傳導路徑378在圖3中經由雙側箭頭來圖形化地圖示。The benefits of achieving the single-segmented die penetration through the fourth interconnect 316 illustrated in FIG. 3 may include from the fourth conductive pad 334 (or the protective conductive layer 336 on the fourth conductive pad 334) to the second dielectric The conductive path 378 of the third node 368 (eg, M3 layer 386 third node 368 (eg, pad, trace)) on the electrical layer 308. The conductive path 378 may pass through the die 324 and the portion of the substrate 302 between the die 324 and the second laminate layer 342. Since the single-segmented die penetration fourth interconnect 316 may be made of a conductive material, the conductive material may be selected to minimize heat dissipation ground resistance and maximize thermal conductivity. The conduction path 378 is graphically illustrated in FIG. 3 via double-sided arrows.

實現本文所描述的結構和方法可導致熱耗散接地電阻的最小化和例如第一傳導焊盤328與背側焊盤或跡線366之間的傳導路徑（例如，傳導路徑376）的熱傳導率的最大化。例如，使用由銅形成的單分段晶粒穿透第一互連310可導致勝過堆疊在銅鍍敷通孔分段上的金TSV通孔分段（例如，如在結合圖2描述的實例中）約30%的熱傳導率改良。Implementing the structures and methods described herein may result in the minimization of heat dissipation ground resistance and the thermal conductivity of the conductive path (eg, conductive path 376) between the first conductive pad 328 and the backside pad or trace 366, for example Maximization. For example, the use of a single-segment die formed of copper to penetrate the first interconnect 310 may result in advantages over the gold TSV via segment stacked on the copper-plated via segment (eg, as described in connection with FIG. 2 In the example) about 30% improvement in thermal conductivity.

概言之，根據一個態樣，裝置（諸如EDS 300）可包括基板302，其具有第一側301和相對的第二側303、從第一側301限定在基板302內的腔322、耦合至腔322的基底的晶粒324，晶粒324在晶粒324遠離腔322的基底的一側上具有傳導焊盤（例如，第四傳導焊盤334）。EDS 300可進一步包括延伸穿過並被限定在基板302的第二側303（例如，第二介電層308內）、晶粒324和傳導焊盤（例如，第四傳導焊盤334）內的孔（例如，第四孔316H）。EDS 300可進一步包括在孔（例如，第四孔316H）內並且在基板302的第二側303（例如，在第二介電層308內）與傳導焊盤（例如，第四傳導焊盤334）之間延伸且穿過第二側303和該傳導焊盤的傳導材料（例如，單分段晶粒穿透第四互連316）。換言之，在圖3的EDS 300的一些實現中，孔（例如，第四孔316H）可以是穿過基板302的第二側303（例如，在第二介電層308內）、晶粒324和傳導焊盤（例如，第四傳導焊盤334）連續的。在一些實現中，孔（例如，第四孔316H）可以是沿著延伸穿過基板302的第二側303（例如，在第二介電層308內）、晶粒324和傳導焊盤（例如，第四傳導焊盤334）的線性軸成同軸的。在一些實現中，孔（例如，第四孔316H）可以是沿著孔（例如，第四孔316H）的長度的單個線性孔。在一些實現中，傳導材料（例如，其形成單分段晶粒穿透第四互連316）可以是單體的單分段。在一些實現中，傳導材料（例如，其形成單分段晶粒穿透第四互連316）可以包括僅一層。換言之，鍍敷及/或填充到孔（例如，第四孔316H）中的傳導材料可被標識為單分段晶粒穿透互連（例如，單分段晶粒穿透第四互連316）。In summary, according to one aspect, a device (such as EDS 300) may include a substrate 302 having a first side 301 and an opposing second side 303, a cavity 322 defined in the substrate 302 from the first side 301, coupled to The die 324 of the base of the cavity 322 has a conductive pad (eg, the fourth conductive pad 334) on the side of the die 324 away from the base of the cavity 322. The EDS 300 may further include a portion extending through and defined within the second side 303 of the substrate 302 (eg, within the second dielectric layer 308), the die 324, and the conductive pad (eg, fourth conductive pad 334) Hole (for example, the fourth hole 316H). The EDS 300 may further include within the hole (eg, the fourth hole 316H) and on the second side 303 of the substrate 302 (eg, within the second dielectric layer 308) and a conductive pad (eg, the fourth conductive pad 334) ) Extending between and through the second side 303 and the conductive material of the conductive pad (for example, a single-segmented grain penetrates the fourth interconnect 316). In other words, in some implementations of EDS 300 of FIG. 3, the hole (eg, fourth hole 316H) may be through second side 303 of substrate 302 (eg, within second dielectric layer 308), die 324, and The conductive pad (for example, the fourth conductive pad 334) is continuous. In some implementations, the hole (eg, the fourth hole 316H) may be along the second side 303 that extends through the substrate 302 (eg, within the second dielectric layer 308), the die 324, and the conductive pad (eg , The linear axis of the fourth conductive pad 334) is coaxial. In some implementations, the hole (eg, fourth hole 316H) may be a single linear hole along the length of the hole (eg, fourth hole 316H). In some implementations, the conductive material (eg, it forms a single segmented grain penetrating fourth interconnect 316) may be a single segment of a single body. In some implementations, the conductive material (eg, it forms a single segmented grain penetrating fourth interconnect 316) may include only one layer. In other words, the conductive material that is plated and/or filled into the hole (eg, the fourth hole 316H) may be identified as a single-segmented grain-penetrating interconnection (eg, a single-segmented grain-penetrating fourth interconnection 316 ).

概言之，根據一個態樣，裝置（諸如EDS 300）可包括基板302，其具有第一側301和相對的第二側303、從第一側301限定在基板302內的腔322、耦合至腔322的基底的晶粒324，晶粒324在晶粒324遠離腔322的基底的一側上具有傳導焊盤（例如，第一傳導焊盤328）。EDS 300可進一步包括耦合至基板302的第二側303（例如，第二介電層308）的層壓層（例如，第二層壓層342），其毗鄰於腔322的基底。在一些態樣，基板302的第二側303（例如，第二介電層308）可被夾在晶粒324與層壓層（例如，第二層壓層342）之間。EDS 300可進一步包括延伸穿過並限定在層壓層（例如，第二層壓層342）、基板302的第二側303（例如，第二介電層308）、晶粒324和傳導焊盤（例如，第一傳導焊盤328）內的孔（例如，第一孔310H）。EDS 300可進一步包括在孔（例如，第一孔310H）內並且在層壓層（例如，第二層壓層342）、基板302的第二側303（例如，第二介電層308）、晶粒324與傳導焊盤（例如，第一傳導焊盤328）之間延伸且穿過上述各者的傳導材料（例如，單分段晶粒穿透第一互連310）。在一些實現中，孔（例如，第一孔310H）可以是穿過層壓層（例如，第二層壓層342）、基板302的第二側303（例如，第二介電層308）、晶粒324和傳導焊盤（例如，第一傳導焊盤328）連續的。在一些實現中，孔（例如，第一孔310H）可以是沿著延伸穿過層壓層（例如，第二層壓層342）、基板302的第二側303（例如，第二介電層308）、晶粒324和傳導焊盤（例如，第一傳導焊盤328）的線性軸成同軸的。在一些實現中，孔（例如，第一孔310H）可以是沿著孔（例如，第一孔310H）的長度的單個線性孔。在一些實現中，傳導材料（例如，其形成單分段晶粒穿透第一互連310）可以是單體的單分段。在一些實現中，傳導材料（例如，其形成單分段晶粒穿透第一互連310）可以僅包括一層。換言之，鍍敷及/或填充到孔（例如，第一孔310H）中的傳導材料可被標識為單分段晶粒穿透互連（例如，單分段晶粒穿透第一互連310）。In summary, according to one aspect, a device (such as EDS 300) may include a substrate 302 having a first side 301 and an opposing second side 303, a cavity 322 defined in the substrate 302 from the first side 301, coupled to The die 324 of the base of the cavity 322 has a conductive pad (eg, the first conductive pad 328) on the side of the die 324 away from the base of the cavity 322. The EDS 300 may further include a laminate layer (eg, second laminate layer 342) coupled to the second side 303 (eg, second dielectric layer 308) of the substrate 302, which is adjacent to the base of the cavity 322. In some aspects, the second side 303 of the substrate 302 (eg, the second dielectric layer 308) may be sandwiched between the die 324 and the laminate layer (eg, the second laminate layer 342). The EDS 300 may further include a laminate layer (eg, the second laminate layer 342), a second side 303 of the substrate 302 (eg, the second dielectric layer 308), a die 324, and a conductive pad extending through and defined The hole (for example, the first hole 310H) in the (for example, the first conductive pad 328). The EDS 300 may further be included within the hole (eg, the first hole 310H) and on the laminate layer (eg, the second laminate layer 342), the second side 303 of the substrate 302 (eg, the second dielectric layer 308), The die 324 extends between the conductive pad (eg, the first conductive pad 328) and passes through the conductive material of each of the above (eg, the single-segmented die penetrates the first interconnect 310). In some implementations, the hole (eg, the first hole 310H) may be through the laminate layer (eg, the second laminate layer 342), the second side 303 of the substrate 302 (eg, the second dielectric layer 308), The die 324 and the conductive pad (for example, the first conductive pad 328) are continuous. In some implementations, the hole (eg, the first hole 310H) may extend along the second side 303 of the substrate 302 (eg, the second dielectric layer) through the laminate layer (eg, the second laminate layer 342) 308), the linear axis of the die 324 and the conductive pad (for example, the first conductive pad 328) are coaxial. In some implementations, the hole (eg, first hole 310H) may be a single linear hole along the length of the hole (eg, first hole 310H). In some implementations, the conductive material (eg, it forms a single segmented grain penetrating the first interconnect 310) may be a single segment of a single body. In some implementations, the conductive material (eg, it forms a single-segmented grain through the first interconnect 310) may include only one layer. In other words, the conductive material that is plated and/or filled into the hole (eg, the first hole 310H) may be identified as a single-segmented die-penetrating interconnect (eg, a single-segmented die-penetrating first interconnect 310 ).

可圍繞延伸穿過各層的互連形成合適的絕緣體以防止例如到傳導層304及/或黏合劑、焊料或環氧樹脂326的短路。Appropriate insulators may be formed around interconnects that extend through the layers to prevent short circuits to conductive layer 304 and/or adhesive, solder, or epoxy 326, for example.

圖4圖示了根據本文所描述的各態樣的包括單分段晶粒穿透第一互連410和單分段晶粒穿透第四互連416的EDS 400的橫截面視圖。圖3的EDS 300與圖4的EDS 400之間的差異在於所有單分段晶粒穿透互連具有在相同層（例如，M4層488）處的第一端411、417。相應地，在圖4的態樣，單分段晶粒穿透互連（410、416）可在單個背側鑽孔製程期間形成。FIG. 4 illustrates a cross-sectional view of an EDS 400 including a single-segmented grain through first interconnect 410 and a single-segmented grain through fourth interconnect 416 according to various aspects described herein. The difference between the EDS 300 of FIG. 3 and the EDS 400 of FIG. 4 is that all single-segmented grain penetration interconnects have first ends 411, 417 at the same layer (eg, M4 layer 488). Correspondingly, in the aspect of FIG. 4, the single-segmented grain penetration interconnects (410, 416) may be formed during a single backside drilling process.

EDS 400可包括基板402。基板402可具有第一側401和相對的第二側403。基板402可以是核心基板。基板402可包括被夾在基板402的第一側401處的第一介電層406與基板402的第二側403處的第二介電層408之間的傳導層404。傳導層404可由金屬（諸如銅）形成。傳導層404可以比EDS 400中的其他傳導層（例如，M1層482、M2層484、M3層486、M4層488）厚。傳導層404的厚度可提供剛性及/或對EDS 400的結構支撐。傳導層404可被用作接地平面或者EDS 400的功率平面。The EDS 400 may include the substrate 402. The substrate 402 may have a first side 401 and an opposite second side 403. The substrate 402 may be a core substrate. The substrate 402 may include a conductive layer 404 sandwiched between the first dielectric layer 406 at the first side 401 of the substrate 402 and the second dielectric layer 408 at the second side 403 of the substrate 402. The conductive layer 404 may be formed of metal such as copper. Conductive layer 404 may be thicker than other conductive layers in EDS 400 (eg, M1 layer 482, M2 layer 484, M3 layer 486, M4 layer 488). The thickness of the conductive layer 404 may provide rigidity and/or structural support for the EDS 400. The conductive layer 404 may be used as a ground plane or a power plane of the EDS 400.

在替換態樣，基板402可以是核心基板。在替換態樣，構想了基板402可包括被夾在基板402的第一側401處的第一傳導層（未圖示）與基板402的第二側403處的第二傳導層（未圖示）之間的介電層（未圖示）。換言之，在替換態樣，基板402可具有覆在具有傳導層的相對側上的非傳導介電層。可圍繞延伸穿過各層的互連形成合適的絕緣體以防止例如到介電的任一側上的傳導層的短路。In an alternative aspect, the substrate 402 may be a core substrate. In an alternative aspect, it is contemplated that the substrate 402 may include a first conductive layer (not shown) sandwiched at the first side 401 of the substrate 402 and a second conductive layer (not shown) at the second side 403 of the substrate 402 ) Between the dielectric layers (not shown). In other words, in an alternative aspect, the substrate 402 may have a non-conductive dielectric layer overlying the opposite side with the conductive layer. Appropriate insulators can be formed around the interconnects that extend through the layers to prevent, for example, short circuits to the conductive layers on either side of the dielectric.

可在基板402內限定腔422。如本文所描述的，腔422可以是由基板402內的諸側壁限定的開口或空穴。腔422可從基板402的第一側401限定在基板402內。腔422可形成在基板中。腔422可足夠大以保持晶粒424。腔422可經由包括例如光微影、機械及/或鐳射鑽孔的方法來形成。腔422的底部可被稱為腔422的「基底」。在一些實現中，腔422可缺少第一介電層406和傳導層404，並且腔422的基底可由腔422中暴露的第二介電層408限定。A cavity 422 may be defined within the substrate 402. As described herein, cavity 422 may be an opening or cavity defined by sidewalls within substrate 402. The cavity 422 may be defined within the substrate 402 from the first side 401 of the substrate 402. The cavity 422 may be formed in the substrate. The cavity 422 may be large enough to hold the die 424. The cavity 422 may be formed by methods including, for example, photolithography, mechanical and/or laser drilling. The bottom of cavity 422 may be referred to as the "base" of cavity 422. In some implementations, the cavity 422 may lack the first dielectric layer 406 and the conductive layer 404, and the base of the cavity 422 may be defined by the second dielectric layer 408 exposed in the cavity 422.

晶粒424可包括主動及/或被動電路/組件。晶粒424可使用表面安裝技術（SMT）組件放置系統（常被描述為貼裝機器、晶粒接合機器或射片機）來被耦合至腔422的基底（例如，在腔422內耦合至第二介電層408）。晶粒424可例如使用黏合劑、焊料或環氧樹脂426耦合至腔422的基底。Die 424 may include active and/or passive circuits/components. The die 424 may be coupled to the substrate of the cavity 422 using surface mount technology (SMT) component placement systems (often described as placement machines, die bonding machines, or film mounters) (eg, within the cavity 422 to the first Two dielectric layers 408). The die 424 may be coupled to the substrate of the cavity 422 using, for example, an adhesive, solder, or epoxy 426.

晶粒424可包括複數個傳導焊盤428、430、432、434，包括晶粒424在遠離腔422的基底的一側上的第一傳導焊盤428、第二傳導焊盤430、第三傳導焊盤432以及第四傳導焊盤434。圖4中的示例性圖示的晶粒424未圖示在晶粒424的製造期間在晶圓廠處形成在晶粒424內的任何穿基板通孔（TSV）。在一些實現中，晶粒424可包括在晶粒製造期間在晶圓廠處形成在晶粒424內、但不在被預指定用於單分段晶粒穿透互連（諸如單分段晶粒穿透第一互連410和單分段晶粒穿透第四互連416）的位置上的一或多個TSV。The die 424 may include a plurality of conductive pads 428, 430, 432, 434, including a first conductive pad 428, a second conductive pad 430, a third conductive on the side of the substrate away from the cavity 422 The pad 432 and the fourth conductive pad 434. The exemplary illustrated die 424 in FIG. 4 does not illustrate any through-substrate vias (TSVs) formed in the die 424 at the fab during the manufacture of the die 424. In some implementations, the die 424 may include formed within the die 424 at the fab during die manufacturing, but is not pre-designated for single-segment die penetration interconnects (such as single-segment die One or more TSVs at locations that penetrate the first interconnect 410 and the single segmented die penetrate the fourth interconnect 416).

該複數個傳導焊盤428、430、432、434可由任何傳導材料（例如，金）形成。保護性傳導層436可在該複數個傳導焊盤428、430、432、434中的每一者上被印刷、沉積、形成或以其他方式提供。在鐳射鑽孔被用於形成單分段晶粒穿透第一互連410、第二互連412、第三互連414及/或單分段晶粒穿透第四互連416的部分的情形中，保護性傳導層436可被用作鐳射止擋。The plurality of conductive pads 428, 430, 432, 434 may be formed of any conductive material (eg, gold). The protective conductive layer 436 may be printed, deposited, formed, or otherwise provided on each of the plurality of conductive pads 428, 430, 432, 434. The laser drilling is used to form a portion of the single-segmented grain through the first interconnect 410, the second interconnect 412, the third interconnect 414 and/or the single-segmented grain through the fourth interconnect 416 In this case, the protective conductive layer 436 may be used as a laser stop.

腔422可以用填充材料438來填充以包封、保護及/或固定晶粒424。填充材料438可以是例如包封材料、用來形成第一介電層406的材料，或者預浸材料（諸如被層壓到第一介電層406的頂側表面的預浸材料）。The cavity 422 may be filled with a filling material 438 to encapsulate, protect and/or fix the die 424. The filling material 438 may be, for example, an encapsulating material, a material used to form the first dielectric layer 406, or a prepreg material (such as a prepreg material laminated to the top side surface of the first dielectric layer 406).

可向第一介電層406提供第一層壓層440（例如，頂側層壓層）。可向第二介電層408提供第二層壓層442（例如，背側層壓層）。第一層壓層440和第二層壓層442中的每一者可被稱為預浸（預注入）層。第一層壓層440和第二層壓層442中的每一者可包括一或多個介電和導電層。例如，該等預浸層可經由藉由噴濺向其相應的表面上沉積該等層來提供。向基板402上提供預浸層及/或附加層的其他方式（例如，層壓、接合、附連、黏合、形成）是熟習此項技術者已知的。The first dielectric layer 406 may be provided with a first laminate layer 440 (eg, a top-side laminate layer). The second dielectric layer 408 may be provided with a second laminate layer 442 (eg, a backside laminate layer). Each of the first laminate layer 440 and the second laminate layer 442 may be referred to as a prepreg (pre-injection) layer. Each of the first laminate layer 440 and the second laminate layer 442 may include one or more dielectric and conductive layers. For example, the prepreg layers may be provided by depositing the layers onto their corresponding surfaces by sputtering. Other ways of providing a prepreg layer and/or additional layers on the substrate 402 (eg, lamination, bonding, attachment, bonding, forming) are known to those skilled in the art.

在圖4的示例性圖示中，晶粒424可在晶圓廠處被製造為在被預指定用於單分段晶粒穿透第一互連410和單分段晶粒穿透第四互連416的位置處不具有TSV。其他位置處的TSV可以是可任選的。減少給定晶粒中的TSV的數目可降低晶粒的成本。代替在晶圓廠處在晶粒製造期間在被預指定用於單分段晶粒穿透第一互連410和單分段晶粒穿透第四互連416的位置處形成TSV的是，單分段晶粒穿透第一互連410和單分段晶粒穿透第四互連416可以在EDS整合期間經由背側鑽孔穿過基板402的至少一部分和晶粒424來形成。In the exemplary illustration of FIG. 4, the die 424 may be manufactured at the fab to be pre-designated for single-segment die penetration through the first interconnect 410 and single-segment die penetration through the fourth There is no TSV at the location of interconnect 416. TSVs at other locations may be optional. Reducing the number of TSVs in a given die can reduce the cost of the die. Instead of forming a TSV at a location in the fab that is pre-designated for single-segment die penetration through the first interconnect 410 and single-segment die penetration through the fourth interconnect 416 during die manufacturing, The single-segment die-penetration first interconnect 410 and the single-segment die-penetration fourth interconnect 416 may be formed through at least a portion of the substrate 402 and the die 424 via backside drilling during EDS integration.

第一傳導焊盤428和第四傳導焊盤434（其可分別耦合至單分段晶粒穿透第一互連410和單分段晶粒穿透第四互連416）可耦合至晶粒424的主動及/或被動電路。類似地，第二傳導焊盤430和第三傳導焊盤432可耦合至晶粒424的主動及/或被動電路。The first conductive pad 428 and the fourth conductive pad 434 (which may be coupled to the single-segment die penetration first interconnect 410 and the single-segment die penetration fourth interconnect 416, respectively) may be coupled to the die The active and/or passive circuit of 424. Similarly, the second conductive pad 430 and the third conductive pad 432 may be coupled to active and/or passive circuits of the die 424.

結合與第二互連412和第三互連414相關聯的頂側鑽孔製程，鐳射止擋（例如，保護性傳導層436）阻擋由鐳射鑽孔形成的孔穿透傳導焊盤430、432（其可由金形成）和晶粒424。第二互連412和第三互連414不延伸進入及/或穿過晶粒424。In conjunction with the top-side drilling process associated with the second interconnect 412 and the third interconnect 414, a laser stop (eg, protective conductive layer 436) blocks the hole formed by the laser drilling from penetrating the conductive pads 430, 432 (It may be formed of gold) and grains 424. The second interconnect 412 and the third interconnect 414 do not extend into and/or through the die 424.

結合背側鑽孔製程，單分段晶粒穿透第一互連410和單分段晶粒穿透第四互連416可延伸進入及/或穿過晶粒424。換言之，單分段晶粒穿透第一互連410和單分段晶粒穿透第四互連416可經由鑽孔穿過第二層壓層442、第二介電層408（例如，形成在基板402中的腔422的基底）並且進入及/或穿過耦合至腔422的基底的晶粒424來從相應的第一孔410H和第四孔416H形成。In conjunction with the backside drilling process, the single-segment die penetration first interconnect 410 and the single-segment die penetration fourth interconnect 416 may extend into and/or through the die 424. In other words, the single-segment die-penetrating first interconnect 410 and the single-segment die-penetrating fourth interconnect 416 may pass through the second laminate layer 442 and the second dielectric layer 408 via drilling (eg, formed The base of the cavity 422 in the substrate 402) and into and/or through the crystal grains 424 coupled to the base of the cavity 422 are formed from the corresponding first holes 410H and fourth holes 416H.

注意，結合與單分段晶粒穿透第一互連410和單分段晶粒穿透第四互連416相關聯的背側鑽孔製程，不存在晶粒424的背側上的鐳射止擋。事實上，鐳射止擋可阻礙在用鐳射鑽孔實現的背側鑽孔製程期間形成單分段晶粒穿透第一互連410和單分段晶粒穿透第四互連416。至少在被預指定用於形成單分段晶粒穿透互連的位置處消除鐳射止擋可節省成本。Note that in conjunction with the backside drilling process associated with the single-segmented die penetration first interconnect 410 and the single-segmented die penetration fourth interconnect 416, there is no laser stop on the backside of the die 424 block. In fact, the laser stop may hinder the formation of single-segment die penetration 410 and single-segment die penetration 416 during the backside drilling process implemented with laser drilling. Eliminating laser stops at least at locations pre-designated for forming single-segmented die-penetrating interconnects can save costs.

實現單分段晶粒穿透第一互連410和單分段晶粒第四互連416的益處可包括經由一種傳導材料（例如，銅）提供傳導路徑476、478。與單分段晶粒穿透第一互連410相關聯的傳導路徑476可從第一傳導焊盤428（或第一傳導焊盤428上的保護性傳導層436）延伸到M4層488焊盤或第二層壓層442上的跡線467。與單分段晶粒穿透第四互連416相關聯的傳導路徑478可從第四傳導焊盤434（或第四傳導焊盤434上的保護性傳導層436）延伸到同一M4層488焊盤或第二層壓層442上的跡線467。傳導路徑476、478可穿過晶粒424、基板402在晶粒424與第二層壓層442之間的部分，以及第二層壓層442。由於單分段晶粒穿透第一互連410和單分段晶粒穿透第四互連416可由一種傳導材料製成，因此該傳導材料可被選擇為最小化熱耗散接地電阻並最大化熱傳導率。傳導路徑476、478在圖4中經由雙側箭頭來圖形化地圖示。The benefits of achieving single-segment die penetration through the first interconnect 410 and the single-segment die fourth interconnect 416 may include providing conductive paths 476, 478 via a conductive material (eg, copper). The conductive path 476 associated with the single-segmented die penetrating the first interconnect 410 may extend from the first conductive pad 428 (or the protective conductive layer 436 on the first conductive pad 428) to the M4 layer 488 pad Or a trace 467 on the second laminate layer 442. The conductive path 478 associated with the single-segmented die penetration through the fourth interconnect 416 may extend from the fourth conductive pad 434 (or the protective conductive layer 436 on the fourth conductive pad 434) to the same M4 layer 488 solder Traces 467 on the disc or second laminate layer 442. The conductive paths 476, 478 may pass through the die 424, the portion of the substrate 402 between the die 424 and the second laminate layer 442, and the second laminate layer 442. Since the single-segment die-penetrating first interconnect 410 and the single-segment die-penetrating fourth interconnect 416 can be made of a conductive material, the conductive material can be selected to minimize heat dissipation ground resistance and maximize Heat conductivity. The conduction paths 476, 478 are graphically illustrated in FIG. 4 via double-sided arrows.

實現本文所描述的結構和方法可導致熱耗散接地電阻的最小化和例如頂側傳導焊盤（例如，第一傳導焊盤428、第四傳導焊盤434）與第二層壓層442上的焊盤或跡線467之間的傳導路徑（例如，傳導路徑476、478）的熱傳導率的最大化。例如，使用由銅形成的單分段晶粒穿透互連（例如，410、416）可導致勝過堆疊在銅鍍敷通孔分段上的金TSV通孔分段（例如，如在結合圖2描述的實例中）約30%的熱傳導率改良。Implementing the structures and methods described herein may result in the minimization of heat dissipation ground resistance and for example on top side conductive pads (eg, first conductive pad 428, fourth conductive pad 434) and second laminate layer 442 The thermal conductivity of the conductive path between the pads or traces 467 (eg, conductive paths 476, 478) is maximized. For example, the use of single-segment die-penetration interconnects formed of copper (eg, 410, 416) may result in advantages over gold TSV via segments stacked on copper-plated via segments (eg, as in bonding In the example depicted in Figure 2) the thermal conductivity improved by about 30%.

可圍繞延伸穿過各層的互連形成合適的絕緣體以防止例如到傳導層404及/或黏合劑、焊料或環氧樹脂426的短路。Appropriate insulators may be formed around interconnects extending through the layers to prevent short circuits to conductive layer 404 and/or adhesive, solder, or epoxy 426, for example.

圖5A圖示了根據本文所描述的各態樣的可被安裝在EDS中的晶粒524的背側平面視圖。例如，晶粒524可被安裝在圖3、圖4、圖6A及/或圖6B的EDS中。晶粒524可具有在晶粒524的邊緣舷內的、填充有主動及/或被動電路系統的區域525。填充有主動及/或被動電路系統的區域525的邊緣在圖5A中由幻影虛線定界。可建立晶粒524的邊緣與填充有主動及/或被動電路系統的區域525的邊緣之間的保護區域527。在一些實現中，即使有亦沒有多少電路系統存在於保護區域527中。5A illustrates a backside plan view of a die 524 that can be installed in EDS according to various aspects described herein. For example, the die 524 may be installed in the EDS of FIGS. 3, 4, 6A, and/or 6B. Die 524 may have an area 525 filled with active and/or passive circuitry within the edge of die 524. The edges of the area 525 filled with active and/or passive circuitry are delimited by phantom dotted lines in FIG. 5A. A protective area 527 may be established between the edge of the die 524 and the edge of the area 525 filled with active and/or passive circuitry. In some implementations, even if there are not many circuitry in the protection area 527.

圖5B圖示了沿線5B-5B取的圖5A的晶粒524的橫截面視圖。圖5B圖形化地圖示了即使有亦沒有多少電路系統存在於保護區域527中。在一些實現中，單分段晶粒穿透互連可位於保護區域527中。然而，單分段晶粒穿透互連可位於晶粒524上的任何地方。FIG. 5B illustrates a cross-sectional view of the grain 524 of FIG. 5A taken along line 5B-5B. FIG. 5B graphically illustrates that even if there are not many circuit systems present in the protection area 527. In some implementations, single-segmented die-penetrating interconnects may be located in the protection area 527. However, single-segment die-penetration interconnects can be located anywhere on die 524.

圖6A圖示了具有被預指定用於單分段晶粒穿透互連的形成的諸第一位置602的第一EDS 600的背側平面視圖。幻影虛線定界了在晶粒624的邊緣舷內的、填充有主動及/或被動電路系統的區域625。圓圈內圍繞的「加」符號圖形化地表徵該等第一位置602中的每一者。第一位置602位於毗鄰於晶粒624的邊界（例如，邊緣）並在其內。在指定的第一位置602處形成的所有單分段晶粒穿透互連可延伸進入及/或穿過晶粒624。圖6A附加地圖示了被預指定用於其他互連的形成的第二位置604，其不延伸進入及/或穿過晶粒624。正方形內圍繞的「加」符號圖形化地表徵第二位置604中的每一者。第二位置604可位於晶粒624的邊界之外或者可位於晶粒624的邊界內。FIG. 6A illustrates a backside plan view of the first EDS 600 with first locations 602 pre-designated for the formation of single-segmented die-penetrating interconnects. The phantom dotted line delimits the area 625 within the edge of the die 624 that is filled with active and/or passive circuitry. The "plus" symbol enclosed within the circle graphically characterizes each of these first positions 602. The first location 602 is located adjacent to and within the boundary (eg, edge) of the die 624. All single-segment die penetration interconnects formed at the designated first location 602 may extend into and/or through die 624. FIG. 6A additionally illustrates a second location 604 that is pre-designated for the formation of other interconnects that does not extend into and/or through die 624. The "plus" symbol surrounded within the square graphically characterizes each of the second positions 604. The second location 604 may be outside the boundary of the die 624 or may be inside the boundary of the die 624.

第一EDS 600的平面視圖在背側鑽孔製程之前的階段提供。圖示了在添加導電層（類似於圖3的M4層388）之前第二層壓層642的背側表面的表示。嵌入在第一EDS 600內的晶粒624的輪廓以幻影虛線表示，因為在所圖示的平面視圖中並且甚至在晶粒624耦合至第一EDS 600的情況下，晶粒624從第一EDS 600的背側將不可見。另外，晶粒624所常駐的腔622（例如，由側壁限定的開口或空穴）的輪廓以幻影虛線呈現，因為腔622將類似地從第一EDS 600的背側不可見。The plan view of the first EDS 600 is provided in the stage before the backside drilling process. A representation of the backside surface of the second laminate layer 642 before adding a conductive layer (similar to the M4 layer 388 of FIG. 3) is illustrated. The outline of the die 624 embedded in the first EDS 600 is indicated by the phantom dotted line because in the illustrated plan view and even in the case where the die 624 is coupled to the first EDS 600, the die 624 is removed from the first EDS 600 The back side of 600 will not be visible. In addition, the outline of the cavity 622 in which the die 624 resides (eg, the opening or cavity defined by the side wall) is represented by a phantom dotted line because the cavity 622 will similarly be invisible from the back side of the first EDS 600.

在一些實現中，在背側鑽孔製程期間，鐳射鑽孔可經由在諸第一位置602中的每一者處鑽孔來形成複數個孔。在諸第一位置602中的每一者處形成的每個孔可延伸進入及/或穿過第二層壓層642、腔622的基底、晶粒624，以及在晶粒624的頂側上的傳導焊盤（未圖示）（並且可進一步暴露與晶粒624的頂側上的傳導焊盤（未圖示）相關聯的鐳射止擋層（未圖示）的下側表面）。In some implementations, during the backside drilling process, laser drilling may form a plurality of holes by drilling at each of the first locations 602. Each hole formed at each of the first locations 602 may extend into and/or through the second laminate layer 642, the base of the cavity 622, the die 624, and on the top side of the die 624 Of the conductive pad (not shown) (and may further expose the lower surface of the laser stop layer (not shown) associated with the conductive pad (not shown) on the top side of the die 624).

在一些實現中，在背側鑽孔製程期間，鐳射鑽孔可經由在第二位置604中的每一者處鑽孔來形成複數個孔。在第二位置604中的每一者處形成的每個孔不延伸進入及/或穿過晶粒624。In some implementations, during the backside drilling process, laser drilling may form a plurality of holes by drilling at each of the second locations 604. Each hole formed at each of the second locations 604 does not extend into and/or through the die 624.

在一些實現中，在諸第一位置602和諸第二位置604中的每一者處鑽孔之後，傳導材料可被用來鍍敷及/或填充該等孔，由此形成該等孔內的互連。傳導材料可鍍敷該等孔的側壁及/或完全地填充該等孔。用傳導材料鍍敷及/或填充該等孔可耦合暴露在該等孔的側壁上（及/或諸第一位置602中的每一者、傳導焊盤（未圖示）及/或晶粒624的頂側上的鐳射止擋（未圖示）處）的金屬化的邊緣以及互連的剩餘部分。用於形成例如M4層的焊盤和跡線的附加金屬化可被添加到第二層壓層642。In some implementations, after drilling at each of the first locations 602 and the second locations 604, conductive material may be used to plate and/or fill the holes, thereby forming inside the holes Interconnection. The conductive material may plate the sidewalls of the holes and/or completely fill the holes. Plating and/or filling the holes with a conductive material may couple the exposed sidewalls of the holes (and/or each of the first locations 602, conductive pads (not shown), and/or die The metalized edge of the laser stop (not shown) on the top side of 624 and the remaining part of the interconnect. Additional metallization for forming pads and traces of, for example, the M4 layer may be added to the second laminate layer 642.

在圖6A中，被預指定用於形成單分段晶粒穿透互連的第一位置602被圖示為朝向晶粒624的外邊緣定位。圍繞晶粒的外邊緣的區域可被稱為保護區域（例如，527，圖5）。該保護區域在晶粒624上或內的主動及/或被動電路系統態樣可具有比晶粒的邊緣舷內的區域625小的密度。在一些實現中，晶粒624可被設計為寬容使用第一位置602的鑽孔（例如，鐳射鑽孔）的失準。在一些實現中，被分派了為單分段晶粒穿透互連鑽出孔的任務的鑽孔可以是鐳射鑽孔，其能夠鑽出直徑在約10與200 μm之間或者在約30與100 μm之間的孔；然而小於或大於所提供的範圍的直徑是可接受且在構想中的。如熟習此項技術者所知的，例如，孔的直徑可取決於晶粒的厚度。在一些實現中，晶粒大小的範圍可以在約1.5x1.5 mm到約10x10 mm的量級上；在一個實現中，晶粒可以為約2x2 mm；然而，晶粒並不限於本文所提供的尺寸並且可取決於例如封裝尺寸更大或更小。In FIG. 6A, the first location 602 pre-designated for forming a single-segmented die-penetrating interconnect is illustrated as being positioned toward the outer edge of the die 624. The area surrounding the outer edge of the die may be referred to as a protection area (eg, 527, FIG. 5). The active and/or passive circuitry of the protection area on or in the die 624 may have a lower density than the area 625 in the edge of the die. In some implementations, the die 624 may be designed to tolerate the misalignment of the drilling (eg, laser drilling) using the first location 602. In some implementations, the drill hole that is assigned the task of drilling a hole for a single-segment grain penetration interconnection may be a laser drill hole, which can drill a diameter between about 10 and 200 μm or between about 30 and Holes between 100 μm; however, diameters smaller or larger than the range provided are acceptable and conceivable. As known to those skilled in the art, for example, the diameter of the hole may depend on the thickness of the grain. In some implementations, the grain size can range on the order of about 1.5x1.5 mm to about 10x10 mm; in one implementation, the grain can be about 2x2 mm; however, the grain is not limited to the ones provided herein The size of the package may depend on, for example, the package size is larger or smaller.

圖6B圖示了具有被預指定用於單分段晶粒穿透互連的形成的諸第一位置602的第二EDS 601的背側平面視圖。幻影虛線定界了在晶粒624的邊緣舷內的、填充有主動及/或被動電路系統的區域625。圖6B的組件的描述與圖6A的組件相同或相似並且將為了簡潔而不被重複。然而，在圖6B中，被預指定用於形成單分段晶粒穿透互連的第一位置602被圖示為位於毗鄰於晶粒624，並且既在晶粒624的外邊緣上（例如，在晶粒的保護區域中）又在晶粒624的邊緣舷內的區域625（例如，具有高密度的主動及/或被動電路系統的區域）內。圖6B的各態樣意在圖示即使晶粒624上或內的主動及/或被動電路系統的密度在晶粒624的邊緣舷內的區域625內可比在毗鄰於晶粒624的邊緣的區域中大，但要設計晶粒624以在晶粒624的邊緣舷內的區域625內容適單分段晶粒穿透互連是有實現可能的。用於製造嵌入晶粒式基板（ EDS ）裝置的示例性序列 FIG. 6B illustrates a back-side plan view of the second EDS 601 with first locations 602 pre-designated for the formation of single-segmented die penetration interconnects. The phantom dotted line delimits the area 625 within the edge of the die 624 that is filled with active and/or passive circuitry. The description of the components of FIG. 6B is the same as or similar to the components of FIG. 6A and will not be repeated for brevity. However, in FIG. 6B, the first location 602 pre-designated for forming a single-segmented die-penetrating interconnect is illustrated as being located adjacent to die 624, and both on the outer edge of die 624 (e.g. , In the protected area of the die) and in the area 625 inboard of the edge of the die 624 (for example, an area with a high density of active and/or passive circuitry). The various aspects of FIG. 6B are intended to illustrate that even if the density of active and/or passive circuitry on or within die 624 is comparable to the area adjacent to the edge of die 624 in the area 625 inboard of the edge of die 624 Zhongda, but it is possible to design the die 624 so that the area 625 in the inboard of the edge of the die 624 is suitable for single-segment die penetration interconnection. Exemplary sequence for manufacturing embedded die substrate ( EDS ) devices

圖7A–圖7C圖示了根據本文所描述的各態樣的用於提供/製造包括單分段晶粒穿透互連的EDS的示例性序列。在一些實現中，提供/製造包括單分段晶粒穿透互連的EDS包括若干製程階段。圖7（包括圖7A–圖7C）圖示了用於提供/製造包括單分段晶粒穿透互連的EDS的階段的示例性序列。在一些實現中，圖7A-圖7C的示例性序列可被用來製造包括圖3、圖4、圖6A及/或圖6B的單分段晶粒穿透互連的EDS。然而，出於簡化目的，圖7A-圖7C將在提供/製造圖3的EDS的上下文中描述。7A-7C illustrate an exemplary sequence for providing/manufacturing an EDS including single-segmented die-penetration interconnects according to various aspects described herein. In some implementations, providing/manufacturing an EDS that includes a single-segment die-penetration interconnection includes several process stages. 7 (including FIGS. 7A-7C) illustrates an exemplary sequence of stages for providing/manufacturing an EDS including single-segment die-penetration interconnects. In some implementations, the exemplary sequence of FIGS. 7A-7C may be used to fabricate EDS including the single-segment die-penetration interconnections of FIGS. 3, 4, 6A, and/or 6B. However, for simplicity purposes, FIGS. 7A-7C will be described in the context of providing/manufacturing the EDS of FIG. 3.

應注意，圖7A-圖7C的序列可以組合一或多個階段以簡化及/或闡明用於提供包括單分段晶粒穿透互連的EDS的序列。在一些實現中，各製程階段的次序可被改變或修改。It should be noted that the sequence of FIGS. 7A-7C may combine one or more stages to simplify and/or clarify the sequence for providing EDS including single-segmented die-penetration interconnections. In some implementations, the order of the various process stages can be changed or modified.

如圖7A所示的階段1圖示了提供基板702之後的狀態。基板702可以是核心基板、核心層。基板702可以是雙側的。基板702可包括可由金屬（諸如銅）形成的傳導層704。傳導層704可以比EDS中的其他傳導層（例如，M1層782、M2層784、M3層786、M4層788）厚。傳導層704的厚度可提供剛性及/或對EDS的結構支撐。傳導層704可被用作接地平面或者EDS的功率平面。基板702可包括在基板702的第一側701處的第一介電層706（例如，頂側介電層）以及基板702的第二側703處的第二介電層708（例如，背側介電層）。第一介電層706和第二介電層708可將傳導層704夾在其間。基板702可由供應商形成或提供。Stage 1 shown in FIG. 7A illustrates the state after the substrate 702 is provided. The substrate 702 may be a core substrate or a core layer. The substrate 702 may be double-sided. The substrate 702 may include a conductive layer 704 that may be formed of metal, such as copper. Conductive layer 704 may be thicker than other conductive layers in EDS (eg, M1 layer 782, M2 layer 784, M3 layer 786, M4 layer 788). The thickness of the conductive layer 704 may provide rigidity and/or structural support for EDS. The conductive layer 704 may be used as a ground plane or a power plane of EDS. The substrate 702 may include a first dielectric layer 706 (eg, a top-side dielectric layer) at the first side 701 of the substrate 702 and a second dielectric layer 708 (eg, a back side) at the second side 703 of the substrate 702 Dielectric layer). The first dielectric layer 706 and the second dielectric layer 708 may sandwich the conductive layer 704 therebetween. The substrate 702 may be formed or provided by a supplier.

階段2圖示了基板702中形成複數個孔711H、713H之後的狀態。該複數個孔711H、713H可由基板702限定。該複數個孔711H、713H可容適分段互連。該複數個孔711H、713H可例如用光微影製程、機械製程及/或鐳射鑽孔製程來形成。Stage 2 illustrates the state after forming a plurality of holes 711H, 713H in the substrate 702. The plurality of holes 711H, 713H may be defined by the substrate 702. The plurality of holes 711H and 713H can accommodate segmented interconnections. The plurality of holes 711H, 713H can be formed by a photolithography process, a mechanical process, and/or a laser drilling process, for example.

階段3圖示了在基板702上及/或中形成M2層784（例如，金屬層）的焊盤或跡線715和M3層786（例如，金屬層）的焊盤或跡線717之後的狀態。在示例性圖示中，M2層784的焊盤或跡線715可形成在第一介電層706上。M3層786的焊盤或跡線717可形成在第二介電層708上及/或中。該複數個孔711H、713H可以用傳導材料填充及/或鍍敷，諸如相同金屬被用於M2層784的焊盤或跡線715和M3層786的焊盤或跡線717。第一分段互連718可藉由傳導材料711和傳導材料713（在該複數個孔711H、713H內）的連接形成在焊盤或跡線715和焊盤或跡線717之間。第一分段互連718被稱為「分段」互連，因為第一分段互連718包括由（分別在）該複數個孔711H、713H中的傳導材料711、713形成的分段（例如，層）。縫705被圖示為在分段之間，此情形指示儘管第一分段互連718在階段3中被示為完整狀態，但孔711H中的傳導材料711的形成可在與孔713H中的傳導材料713的形成不同的階段、不同的時間進行。第一分段互連718由複數個層形成，其中例如每層由不同分段形成。Stage 3 illustrates the state after the pad or trace 715 of the M2 layer 784 (eg, metal layer) and the pad or trace 717 of the M3 layer 786 (eg, metal layer) are formed on and/or in the substrate 702 . In the exemplary illustration, the pad or trace 715 of the M2 layer 784 may be formed on the first dielectric layer 706. Pads or traces 717 of the M3 layer 786 may be formed on and/or in the second dielectric layer 708. The plurality of holes 711H, 713H may be filled with conductive material and/or plated, such as the same metal is used for the pad or trace 715 of the M2 layer 784 and the pad or trace 717 of the M3 layer 786. The first segmented interconnect 718 may be formed between the pad or trace 715 and the pad or trace 717 by the connection of the conductive material 711 and the conductive material 713 (within the plurality of holes 711H, 713H). The first segmented interconnect 718 is called a "segmented" interconnect because the first segmented interconnect 718 includes segments (formed by) the conductive materials 711, 713 in the plurality of holes 711H, 713H ( For example, layer). The slit 705 is illustrated between the segments, which indicates that although the first segment interconnect 718 is shown in a complete state in stage 3, the formation of the conductive material 711 in the hole 711H may be The conductive material 713 is formed at different stages and at different times. The first segment interconnect 718 is formed by a plurality of layers, where for example each layer is formed by a different segment.

階段4圖示了在基板702中形成腔722（例如，由諸側壁限定的開口或空穴）之後的狀態。腔722可經由包括例如光微影、機械製程及/或鐳射鑽孔的方法來形成。腔722可從第一側701限定在基板702內。腔722可經由從第一介電層706和傳導層704移除材料來形成。在一些實現中，腔722可缺少第一介電層706和傳導層704。腔722的寬度和深度可被選擇以提供用於晶粒724的空間，其可被放置在腔722內。在一些實現中，腔722的深度可大於或等於晶粒724的高度加上黏合劑、焊料或環氧樹脂726（其可被用來將晶粒724耦合至腔722的底部（例如，基底））的厚度。相應地，至少取決於晶粒724的高度，可從基板702移除更多或更少材料以形成由基板702限定的腔722。Stage 4 illustrates the state after the cavity 722 (for example, the opening or cavity defined by the side walls) is formed in the substrate 702. The cavity 722 may be formed by methods including, for example, photolithography, mechanical processes, and/or laser drilling. The cavity 722 may be defined within the substrate 702 from the first side 701. The cavity 722 may be formed by removing material from the first dielectric layer 706 and the conductive layer 704. In some implementations, the cavity 722 may lack the first dielectric layer 706 and the conductive layer 704. The width and depth of the cavity 722 may be selected to provide space for the die 724, which may be placed within the cavity 722. In some implementations, the depth of cavity 722 may be greater than or equal to the height of die 724 plus adhesive, solder, or epoxy 726 (which may be used to couple die 724 to the bottom of cavity 722 (eg, substrate) )thickness of. Accordingly, at least depending on the height of the die 724, more or less material may be removed from the substrate 702 to form the cavity 722 defined by the substrate 702.

在一些實現中，傳導層704的某一部分可保持在腔722中；然而，在此類實現中，可實現諸如反焊盤區段及/或絕緣區段之類的措施以確保晶粒的底部上的金屬化及/或穿透腔722的基底的單分段晶粒穿透互連的金屬化不形成與傳導層704的不想要的短路。In some implementations, some portion of the conductive layer 704 may remain in the cavity 722; however, in such implementations, measures such as anti-pad sections and/or insulating sections may be implemented to ensure the bottom of the die The metallization on the top and/or the single-segmented grain penetration metallization through the substrate of cavity 722 does not form an undesirable short circuit with conductive layer 704.

在一些實現中，可在腔722的形成期間移除第二介電層708（例如，背側介電層）的某一部分。在一些實現中，腔722可以經由從基板702中限定腔722的諸側壁以內移除第一介電層706、傳導層704和第二介電層708的全部來形成。在此類實現中，該晶粒可耦合至與第二介電層708毗鄰（例如，在其之下）的層。In some implementations, some portion of the second dielectric layer 708 (eg, backside dielectric layer) may be removed during the formation of the cavity 722. In some implementations, the cavity 722 may be formed by removing all of the first dielectric layer 706, the conductive layer 704, and the second dielectric layer 708 from within the sidewalls of the substrate 702 defining the cavity 722. In such an implementation, the die may be coupled to a layer adjacent (eg, below) the second dielectric layer 708.

階段5圖示了晶粒724已被耦合至腔722的基底（例如，在腔722內耦合至第二介電層708）之後的狀態。晶粒724可以例如使用黏合劑、焊料或環氧樹脂726來耦合。晶粒724可包括複數個傳導焊盤728、730、732、734，包括晶粒724在遠離腔722的基底的一側上的第一傳導焊盤728、第二傳導焊盤730、第三傳導焊盤732以及第四傳導焊盤734。該複數個傳導焊盤728、730、732、734可例如由金形成。該複數個傳導焊盤728、730、732、734中的每一者可具有沉積、鍍敷、添加在該焊盤上的鐳射止擋層736（例如，保護性傳導層）（例如，在該複數個傳導焊盤728、730、732、734中的每一者的頂上的鐳射止擋層736）。鐳射止擋層736可以是例如銅。Stage 5 illustrates the state after the die 724 has been coupled to the substrate of the cavity 722 (eg, coupled to the second dielectric layer 708 within the cavity 722). The die 724 may be coupled using, for example, an adhesive, solder, or epoxy 726. The die 724 may include a plurality of conductive pads 728, 730, 732, 734, including a first conductive pad 728, a second conductive pad 730, a third conductive on the side of the substrate away from the cavity 722 The pad 732 and the fourth conductive pad 734. The plurality of conductive pads 728, 730, 732, 734 may be formed of gold, for example. Each of the plurality of conductive pads 728, 730, 732, 734 may have a laser stop layer 736 (eg, a protective conductive layer) deposited, plated, added on the pad (eg, in the The laser stop layer 736 on top of each of the plurality of conductive pads 728, 730, 732, 734). The laser stop layer 736 may be copper, for example.

階段5進一步圖示了在腔722已接納填充材料738以包封、保護及/或固定晶粒724之後的狀態。填充材料738可至少部分地包封晶粒724。在一些實現中，填充材料738可被施加（例如，形成、提供）以使得填充材料738的表面與第一介電層706的頂側表面基本共面。Stage 5 further illustrates the state after cavity 722 has received filler material 738 to encapsulate, protect, and/or secure die 724. The filler material 738 may at least partially encapsulate the die 724. In some implementations, the filler material 738 may be applied (eg, formed, provided) so that the surface of the filler material 738 is substantially coplanar with the top-side surface of the first dielectric layer 706.

階段6圖示了在單分段晶粒穿透第四互連716在孔716H中形成之後的狀態。孔716H可以例如經由鑽孔穿過第二介電層708（例如，基板702的一部分、基板702中形成的腔722的基底）並進入耦合至腔722的基底的晶粒724中來形成。孔716H可延伸穿過基板702的第二側703（例如，其中基板的第二側可包括第二介電層708）、晶粒724和傳導焊盤734並且可被限定在其內。例如，在示例性圖示中，孔716H延伸穿過基板702的第二介電層708、晶粒724和傳導焊盤734並由其限定。在一些實現中，孔716H可在傳導焊盤734上的鐳射止擋層736處及/或中終止。傳導材料（例如，形成單分段晶粒穿透第四互連716的傳導材料）鍍敷及/或填充孔716H並從孔716H內耦合至傳導焊盤734。傳導材料在第二介電層708的遠離腔的基底的表面與傳導焊盤734之間形成互連（單分段晶粒穿透第四互連716）。焊盤或跡線768可形成在第二介電層708上及/或中。Stage 6 illustrates the state after the single-segmented grain penetrates the fourth interconnect 716 and is formed in the hole 716H. The hole 716H may be formed, for example, by drilling through the second dielectric layer 708 (eg, a portion of the substrate 702, the base of the cavity 722 formed in the substrate 702) and into the die 724 coupled to the base of the cavity 722. The hole 716H may extend through the second side 703 of the substrate 702 (eg, where the second side of the substrate may include the second dielectric layer 708), the die 724, and the conductive pad 734 and may be defined therein. For example, in the exemplary illustration, hole 716H extends through and is defined by second dielectric layer 708, die 724, and conductive pad 734 of substrate 702. In some implementations, the hole 716H may terminate at and/or in the laser stop layer 736 on the conductive pad 734. A conductive material (eg, a conductive material forming a single segmented grain penetrating the fourth interconnect 716) plated and/or filled the hole 716H and coupled to the conductive pad 734 from within the hole 716H. The conductive material forms an interconnection between the surface of the second dielectric layer 708 away from the cavity's substrate and the conductive pad 734 (single-segmented grains penetrate the fourth interconnection 716). Pads or traces 768 may be formed on and/or in the second dielectric layer 708.

單分段晶粒穿透第四互連716可與其右邊的第一分段互連718形成對比。單分段晶粒穿透第四互連716可被描述為單體的單分段、單體結構、不可分割結構，及/或未分割結構。單分段晶粒穿透第四互連716可被描述為延伸穿過基板702、晶粒724和傳導焊盤734並被限定在其內的結構。相反，第一分段互連718由第一傳導材料分段711和第二傳導材料分段713的堆疊集合形成並且不延伸進入及/或穿過晶粒724及/或晶粒724的頂側上的任何傳導焊盤。The single segmented grain penetration fourth interconnect 716 can be contrasted with the first segmented interconnect 718 to the right. The single-segmented die penetration fourth interconnect 716 may be described as a single-segmented single-segment, single-element structure, indivisible structure, and/or undivided structure. The single-segmented die penetration fourth interconnect 716 may be described as a structure extending through and defined within the substrate 702, die 724, and conductive pad 734. In contrast, the first segmented interconnect 718 is formed by the stacked set of the first conductive material segment 711 and the second conductive material segment 713 and does not extend into and/or through the die 724 and/or the top side of the die 724 On any conductive pad.

階段7圖示了在向第一介電層706提供第一層壓層740（例如，頂側層壓層）並向第二介電層708提供第二層壓層742之後的狀態。第一層壓層740和第二層壓層742中的每一者可被稱為預浸（預注入）層。第一層壓層740和第二層壓層742中的每一層可包括一或多個介電和導電層。例如，該等預浸層可經由藉由噴濺向其相應的表面上沉積該等層來提供。向基板702上提供預浸層及/或附加層的其他方式（例如，層壓、接合、附連、黏合、形成）是熟習此項技術者已知的。Stage 7 illustrates the state after the first dielectric layer 706 is provided with the first laminate layer 740 (for example, the top-side laminate layer) and the second dielectric layer 708 is provided with the second laminate layer 742. Each of the first laminate layer 740 and the second laminate layer 742 may be referred to as a prepreg (pre-injection) layer. Each of the first laminate layer 740 and the second laminate layer 742 may include one or more dielectric and conductive layers. For example, the prepreg layers may be provided by depositing the layers onto their corresponding surfaces by sputtering. Other ways of providing a prepreg layer and/or additional layers on the substrate 702 (eg, lamination, bonding, attachment, bonding, forming) are known to those skilled in the art.

階段8圖示了在經由在第一層壓層740（例如，第一預浸層）上開始在預指定位置鑽孔形成包括第一頂側舷外孔752H、第一頂側舷內孔712H、第二頂側舷內孔714H和第二頂側舷外孔746H的第一複數個孔之後的狀態。該第一複數個孔可在頂側鑽孔製程期間形成。包括第一舷外孔762H、第二舷外孔756H和舷內孔710H的第二複數個孔可經由在第二層壓層742（例如，第二預浸層）處開始在預指定位置鑽孔來形成。該第二複數個孔可在背側鑽孔製程期間形成。Stage 8 illustrates the formation of the first top-side outboard hole 752H and the first top-side inboard hole 712H by drilling on the first laminate layer 740 (eg, the first prepreg layer) at a predetermined location. , The state after the first plurality of holes of the second top side inboard hole 714H and the second top side outboard hole 746H. The first plurality of holes may be formed during the top-side drilling process. The second plurality of holes including the first outboard hole 762H, the second outboard hole 756H, and the inboard hole 710H may be drilled at a pre-designated location via the second laminate layer 742 (eg, the second prepreg layer) Holes to form. The second plurality of holes may be formed during the backside drilling process.

在頂側鑽孔製程期間，第一頂側舷內孔712H和第二頂側舷內孔714H延伸穿過第一層壓層740以及腔722內的填充材料738的一部分。第一頂側舷內孔712H和第二頂側舷內孔714H在鐳射止擋層736處終止。第一頂側舷內孔712H和第二頂側舷內孔714H不延伸進入及/或穿過晶粒724（及/或不延伸進入及/或穿過晶粒724處的傳導焊盤730、732）。第一頂側舷外孔752H和第二頂側舷外孔746H亦延伸穿過第一層壓層740。第一頂側舷外孔752H在第一介電層706上的焊盤或跡線754上終止。第二頂側舷外孔746H在第一介電層706上的焊盤或跡線715上終止。During the topside drilling process, the first topside inboard hole 712H and the second topside inboard hole 714H extend through the first laminate layer 740 and a portion of the filler material 738 in the cavity 722. The first top side inboard hole 712H and the second top side inboard hole 714H terminate at the laser stop layer 736. The first top side inboard hole 712H and the second top side inboard hole 714H do not extend into and/or through the die 724 (and/or do not extend into and/or through the conductive pad 730 at the die 724, 732). The first top side outboard hole 752H and the second top side outboard hole 746H also extend through the first laminate layer 740. The first top side outboard hole 752H terminates on a pad or trace 754 on the first dielectric layer 706. The second top side outboard hole 746H terminates on a pad or trace 715 on the first dielectric layer 706.

在背側鑽孔製程期間，第一舷外孔762H延伸穿過第二層壓層742並由其限定，並且在第二介電層708上的M3層786的焊盤或跡線760處終止。第二舷外孔756H延伸穿過第二層壓層742並由其限定，並且在第二介電層708上的M3層786的焊盤或跡線717處終止。在背側鑽孔製程期間，舷內孔710H（其可使用傳導材料鍍敷及/或填充以形成單分段晶粒穿透第一互連710）延伸穿過第二層壓層742、基板702（例如，第二介電層708、基板702的位於晶粒724與第二層壓層742之間的部分（例如，腔722的基底））、晶粒724和傳導焊盤728並由其限定。例如，在示例性圖示中，舷內孔710H延伸穿過第二層壓層742、基板702的第二介電層708、晶粒724和傳導焊盤728並由其限定。舷內孔710H可在傳導焊盤728上的鐳射止擋層736處或中終止。During the backside drilling process, the first outboard hole 762H extends through and is defined by the second laminate layer 742 and terminates at the pad or trace 760 of the M3 layer 786 on the second dielectric layer 708 . The second outboard hole 756H extends through and is defined by the second laminate layer 742 and terminates at the pad or trace 717 of the M3 layer 786 on the second dielectric layer 708. During the backside drilling process, the inboard hole 710H (which can be plated and/or filled with conductive material to form a single-segmented die to penetrate the first interconnect 710) extends through the second laminate layer 742, the substrate 702 (eg, second dielectric layer 708, portion of substrate 702 between die 724 and second laminate layer 742 (eg, base of cavity 722)), die 724, and conductive pad 728 limited. For example, in the exemplary illustration, inboard hole 710H extends through and is defined by second laminate layer 742, second dielectric layer 708 of substrate 702, die 724, and conductive pad 728. The inboard hole 710H may terminate at or in the laser stop layer 736 on the conductive pad 728.

該第一複數個孔（包括第一頂側舷外孔752H、第一頂側舷內孔712H、第二頂側舷內孔714H和第二頂側舷外孔746H）和該第二複數個孔（包括第一舷外孔762H、第二舷外孔756H和舷內孔710H）可經由包括例如光微影、機械及/或鐳射鑽孔的方法來形成。The first plurality of holes (including the first top side outboard hole 752H, the first top side inboard hole 712H, the second top side inboard hole 714H, and the second top side outboard hole 746H) and the second plurality of holes The holes (including the first outboard hole 762H, the second outboard hole 756H, and the inboard hole 710H) may be formed by methods including, for example, photolithography, mechanical, and/or laser drilling.

階段9圖示了在傳導材料被用來形成舷內孔710H中的單分段晶粒穿透第一互連710之後的狀態。傳導材料在第二層壓層742的遠離基板702的第二側703（例如，其中基板的第二側可包括第二介電層708）的表面與傳導焊盤734之間形成互連（單分段晶粒穿透第一互連710）。另外，階段9圖示了第一頂側舷外孔752H中的傳導材料752、第一頂側舷內孔712H中的傳導材料712、第二頂側舷內孔714H中的傳導材料714、第二頂側舷外孔746H中的傳導材料746、第一舷外孔762H中的傳導材料762、第二舷外孔756H中的傳導材料756。階段9進一步圖示了形成在第一層壓層740上及/或中的M1層782以及形成在第二層壓層742上及/或中的M4層788。M1層782可包括第一水平跡線790和第二水平跡線792。M4層788可包括第一節點764、第二節點766和第四節點770（例如，其中節點可以是傳導焊盤或跡線）。Stage 9 illustrates the state after the conductive material is used to form a single segmented grain in the inboard hole 710H penetrating the first interconnect 710. The conductive material forms an interconnection between the surface of the second laminate layer 742 away from the second side 703 of the substrate 702 (eg, where the second side of the substrate may include the second dielectric layer 708) and the conductive pad 734 (single The segmented die penetrates the first interconnect 710). In addition, stage 9 illustrates the conductive material 752 in the first top side outboard hole 752H, the conductive material 712 in the first top side inboard hole 712H, the conductive material 714 in the second top side inboard hole 714H, the first Conductive material 746 in the two top side outboard holes 746H, conductive material 762 in the first outboard hole 762H, and conductive material 756 in the second outboard hole 756H. Stage 9 further illustrates the M1 layer 782 formed on and/or in the first laminate layer 740 and the M4 layer 788 formed on and/or in the second laminate layer 742. The M1 layer 782 may include a first horizontal trace 790 and a second horizontal trace 792. The M4 layer 788 may include a first node 764, a second node 766, and a fourth node 770 (eg, where the node may be a conductive pad or trace).

可實現沒有用於將晶粒724耦合至基板702的黏合劑、焊料或環氧樹脂726的保護區域（未圖示）（諸如，反焊盤區段及/或絕緣區段），其可圍繞單分段晶粒穿透第一互連710和單分段晶粒穿透第四互連716提供以排除例如在黏合劑、焊料或環氧樹脂726導電的情況下到黏合劑、焊料或環氧樹脂726的短路。A protected area (not shown) without adhesive, solder, or epoxy 726 for coupling the die 724 to the substrate 702 may be realized (such as a counter pad section and/or an insulating section), which may surround The single-segment die-penetration first interconnection 710 and the single-segment die-penetration fourth interconnection 716 are provided to exclude, for example, the adhesive, solder, or epoxy from the adhesive, solder, or epoxy 726 being conductive Short circuit of the oxygen resin 726.

在一些實現中，可在核心基板上併發地製造若干EDS，並且可執行切單製程以將核心基板切割成個體EDS。用於製造嵌入晶粒式基板（ EDS ）的示例性方法 In some implementations, several EDSs can be manufactured concurrently on the core substrate, and a singulation process can be performed to cut the core substrate into individual EDSs. Exemplary method for manufacturing embedded die substrate ( EDS )

圖8圖示了用於製造包括單分段晶粒穿透互連的EDS的示例性方法的流程圖800。在一些實現中，圖8的示例性方法可被用來製造包括圖3、圖4、圖6A及/或圖6B的單分段晶粒穿透互連的EDS。然而，出於簡化目的，圖8將在提供/製造圖3的EDS的上下文中描述。FIG. 8 illustrates a flowchart 800 of an exemplary method for manufacturing an EDS including single-segment die-penetration interconnects. In some implementations, the exemplary method of FIG. 8 can be used to fabricate EDS including the single-segment die-penetrating interconnections of FIGS. 3, 4, 6, 6A, and/or 6B. However, for simplicity purposes, FIG. 8 will be described in the context of providing/manufacturing the EDS of FIG. 3.

應注意，圖8提供的方塊的序列可以組合一或多個操作以簡化及/或闡明用於製造包括單分段晶粒穿透互連的EDS的方法。在一些實現中，各方塊的次序可被改變或修改。It should be noted that the sequence of blocks provided in FIG. 8 may combine one or more operations to simplify and/or clarify the method for manufacturing EDS including single-segment die-penetration interconnects. In some implementations, the order of the various blocks can be changed or modified.

可提供基板（802）。基板可具有第一側和相對的第二側。基板可以是雙側的。基板可以是核心基板（例如，核心層）。基板可包括可由金屬（諸如銅）形成的傳導層。基板可包括在基板的第一側上的第一介電層（例如，頂側介電層）並且可包括在基板的第二側上的第二介電層（例如，背側介電層）。第一介電層和第二介電層可將該傳導層夾在其間。A substrate (802) can be provided. The substrate may have a first side and an opposite second side. The substrate may be double-sided. The substrate may be a core substrate (for example, a core layer). The substrate may include a conductive layer that may be formed of metal, such as copper. The substrate may include a first dielectric layer (eg, top-side dielectric layer) on the first side of the substrate and may include a second dielectric layer (eg, back-side dielectric layer) on the second side of the substrate . The first dielectric layer and the second dielectric layer may sandwich the conductive layer therebetween.

可在基板中形成複數個孔以容適複數個互連（804）。例如，光微影製程、機械製程及/或鐳射鑽孔製程可被用來形成該複數個孔。在一些實現中，該複數個孔可使用鐳射鑽孔來形成。A plurality of holes may be formed in the substrate to accommodate a plurality of interconnections (804). For example, a photolithography process, a mechanical process, and/or a laser drilling process can be used to form the plurality of holes. In some implementations, the plurality of holes may be formed using laser drilling.

金屬化（例如，傳導材料）可被提供（806）給該複數個孔以形成互連並且可被圖案化在第一介電層和第二介電層上以形成焊盤及/或跡線。Metallization (eg, conductive material) may be provided (806) to the plurality of holes to form interconnections and may be patterned on the first dielectric layer and the second dielectric layer to form pads and/or traces .

可在基板中形成腔（808）。該腔可被限定在基板內。如本文所描述的，腔可以是由基板內的諸側壁限定的開口或空穴。腔可以從基板的第一側形成並被限定在基板內。腔可經由從第一介電層和傳導層移除材料來形成。腔的寬度和深度可被選擇以提供用於晶粒的空間，晶粒可被放置在腔內。在一些實現中，腔的深度可大於或等於晶粒的高度加上黏合劑、焊料或環氧樹脂（其將晶粒耦合至腔的底部（或基底））的厚度。A cavity (808) may be formed in the substrate. The cavity may be defined within the substrate. As described herein, the cavity may be an opening or cavity defined by sidewalls within the substrate. The cavity may be formed from the first side of the substrate and defined within the substrate. The cavity may be formed by removing material from the first dielectric layer and the conductive layer. The width and depth of the cavity can be selected to provide space for the die, which can be placed within the cavity. In some implementations, the depth of the cavity may be greater than or equal to the height of the die plus the thickness of the adhesive, solder, or epoxy (which couples the die to the bottom (or substrate) of the cavity).

可將晶粒耦合至腔的基底（例如，耦合至腔內暴露的第二介電層）（810）。該晶粒可具有耦合至腔的基底的第一側以及遠離腔的基底的相對第二側。晶粒可例如使用黏合劑、焊料或環氧樹脂來耦合。晶粒可包括複數個傳導焊盤。該複數個傳導焊盤可例如由金形成。該晶粒可具有在晶粒遠離腔的基底的一側（晶粒的相對第二側）上的至少一個傳導焊盤。該複數個傳導焊盤可各自具有沉積、鍍敷、添加在焊盤的頂部上的鐳射止擋層。鐳射止擋層可以是金屬（諸如銅）的覆蓋層。鐳射止擋層的金屬可以不同於底下的傳導焊盤的金屬。The die may be coupled to the substrate of the cavity (eg, coupled to the exposed second dielectric layer in the cavity) (810). The die may have a first side coupled to the base of the cavity and an opposite second side of the base away from the cavity. The die can be coupled using, for example, an adhesive, solder, or epoxy. The die may include a plurality of conductive pads. The plurality of conductive pads may be formed of gold, for example. The die may have at least one conductive pad on the side of the die away from the base of the cavity (the opposite second side of the die). The plurality of conductive pads may each have a laser stop layer deposited, plated, and added on top of the pad. The laser stop layer may be a cover layer of metal (such as copper). The metal of the laser stop layer may be different from the metal of the underlying conductive pad.

腔可接納填充材料來包封、保護及/或固定晶粒（812）。填充材料可至少部分地包封晶粒。在一些實現中，填充材料可被施加（例如，形成、提供）以使得填充材料的表面與第一介電層的表面基本共面。The cavity may receive a filler material to encapsulate, protect and/or fix the die (812). The filler material may at least partially encapsulate the die. In some implementations, the filler material may be applied (eg, formed, provided) such that the surface of the filler material is substantially coplanar with the surface of the first dielectric layer.

可經由鑽孔以延伸穿過基板、晶粒和傳導焊盤來形成（814）（例如，提供）孔。例如，該孔可延伸穿過基板的第二側（例如，基板中晶粒所耦合至的層、基板中具有被描述為腔的基底的表面的層、基板的包括第二介電層的層）並被限定在其內，延伸進入及/或穿過耦合至腔的基底的晶粒，並且延伸進入及/或穿過晶粒的遠離腔的基底的一側上的傳導焊盤。在一些實現中，該孔可延伸進入及/或穿過晶粒並且在晶粒上的傳導焊盤的表面處終止或暴露該表面。傳導焊盤的該表面可以是傳導焊盤的下表面。傳導焊盤的下表面可以在位於基本沿晶粒的頂部與傳導焊盤的底部之間的介面的平面上。The hole may be formed (814) (eg, provided) via drilling to extend through the substrate, die, and conductive pad. For example, the hole may extend through the second side of the substrate (eg, the layer in the substrate to which the die is coupled, the layer in the substrate having the surface of the base described as a cavity, the layer of the substrate including the second dielectric layer ) And is defined therein, extending into and/or through the die coupled to the substrate of the cavity, and extending into and/or through the conductive pad on the side of the substrate away from the cavity of the substrate. In some implementations, the hole may extend into and/or through the die and terminate or expose the surface at the surface of the conductive pad on the die. The surface of the conductive pad may be the lower surface of the conductive pad. The lower surface of the conductive pad may be on a plane that lies substantially along the interface between the top of the die and the bottom of the conductive pad.

傳導材料可被提供以鍍敷及/或填充孔並且從孔內耦合至傳導焊盤（816）。傳導材料可鍍敷該孔的側壁及/或完全地填充該孔。延伸穿過基板的第二介電層、晶粒且被限定在其內並且進入及/或穿過傳導焊盤的孔可一次性形成，或者換言之在一次製程期間或在一個動作中形成。可從EDS的第二介電層延伸穿過晶粒並且進入及/或穿過遠離晶粒耦合至腔的基底的彼側的晶粒側上的傳導焊盤的傳導材料可以是單體的、不可分割及/或未分割的結構。相應地，由於傳導材料延伸穿過基板、晶粒和傳導焊盤，並且可被形成為單體的、不可分割及/或未分割的分段（例如，一個結構、一個分段、單個分段），因此該傳導材料可被稱為單分段晶粒穿透互連。另外，該孔在EDS整合期間（例如，在EDS整合期間在背側鑽孔製程（例如，操作、動作）期間）形成。如先前所提及的，實體厭惡在EDS整合期間鑽孔進入晶粒，因為害怕損害晶粒。然而，已經發現本文所描述的各態樣可經由從晶粒中消除至少一些TSV（由此降低晶粒遮罩計數以及在製造晶粒中使用的操作數目）來降低晶粒的成本。另外，由於根據本文所描述的各態樣形成的單分段晶粒穿透互連可從一種傳導材料形成為單分段，因此其可從具有比用於在晶粒中製造TSV的材料（諸如，金）好的熱傳導率的傳導材料形成。例如，在一些實現中，可被用於形成單分段晶粒穿透互連的傳導材料可以是銅。銅單分段晶粒穿透互連的熱傳導率已被發現具有比用於砷化鎵（GaAs）晶粒的金好30%並且比用於體矽/絕緣體上覆矽（SOI）CMOS（SOI CMOS）的鎢（W）好100%的熱傳導率。Conductive material may be provided to plate and/or fill the hole and couple to the conductive pad from within the hole (816). The conductive material may plate the sidewall of the hole and/or completely fill the hole. The second dielectric layer extending through the substrate, the die, and the holes defined therein and entering and/or passing through the conductive pads may be formed at once, or in other words formed during one process or in one action. The conductive material that may extend from the second dielectric layer of the EDS through the die and into and/or through the conductive pad on the die side on the side of the substrate away from the die coupling to the cavity may be monolithic, Indivisible and/or undivided structure. Accordingly, since the conductive material extends through the substrate, die, and conductive pad, and can be formed as a single, indivisible and/or undivided segment (eg, a structure, a segment, a single segment ), so this conductive material can be referred to as a single-segmented grain-through interconnect. In addition, the hole is formed during the EDS integration (eg, during the EDS integration during the backside drilling process (eg, operation, action)). As mentioned previously, the entity hates drilling holes into the grain during EDS integration because of fear of damage to the grain. However, it has been found that the various aspects described herein can reduce the cost of the die by eliminating at least some TSVs from the die (thereby reducing the die mask count and the number of operations used in manufacturing the die). In addition, since the single-segmented grain-penetrating interconnects formed according to various aspects described herein can be formed from a conductive material into a single-segmented material, it can be made from a material having a higher TSV than that used to manufacture TSVs in the grains ( Conductive materials with good thermal conductivity, such as gold. For example, in some implementations, the conductive material that can be used to form the single-segmented grain-through interconnect can be copper. The thermal conductivity of copper single-segment grain penetration interconnects has been found to be 30% better than gold used for gallium arsenide (GaAs) grains and for bulk silicon/silicon on insulator (SOI) CMOS (SOI) CMOS) tungsten (W) has a good thermal conductivity of 100%.

可向第一介電層提供第一層壓層並且可向第二介電層提供第二層壓層（818）。A first laminate layer may be provided to the first dielectric layer and a second laminate layer may be provided to the second dielectric layer (818).

可在合適的情況下執行頂側鑽孔製程（820）。The top side drilling process (820) can be performed under appropriate circumstances.

可在合適的情況下執行附加背側鑽孔（822），其中背側鑽孔可包括在合適的情況下形成用於附加單分段晶粒穿透互連的附加孔。由於附加層（第二層壓層）被添加到整體EDS結構，因此在背側鑽孔製程期間，被指定為單分段晶粒穿透互連的孔可延伸穿過第二層壓層、基板在晶粒與第二層壓層（例如，腔的基底）之間的（諸）層、晶粒和在晶粒的頂側上的傳導焊盤並且被限定在其內。在一些實現中，孔可在傳導焊盤上的鐳射止擋層處終止。Additional backside drilling (822) may be performed where appropriate, where the backside drilling may include forming additional holes for additional single-segmented die-penetrating interconnects where appropriate. Since an additional layer (second laminate layer) is added to the overall EDS structure, during the backside drilling process, the hole designated as a single-segmented grain penetration interconnection can extend through the second laminate layer, The substrate layer(s) between the die and the second laminate layer (eg, the base of the cavity), the die, and the conductive pad on the top side of the die and are defined therein. In some implementations, the hole may terminate at the laser stop layer on the conductive pad.

可在第一層壓層上及/或中形成M1層（例如，傳導材料/導電層/金屬化層），並且可在第二層壓層上及/或中形成M4層以圖案化焊盤及/或跡線（824）。An M1 layer (eg, conductive material/conductive layer/metallization layer) may be formed on and/or in the first laminate layer, and an M4 layer may be formed on and/or in the second laminate layer to pattern the pad And/or traces (824).

圖9圖示了用於製造包括單分段晶粒穿透互連的EDS的示例性方法的另一流程圖900。在一些實現中，圖9的示例性方法可被用來製造包括圖3、圖4、圖6A及/或圖6B的單分段晶粒穿透互連的EDS。然而，出於簡化目的，圖9將在提供/製造圖3的EDS的上下文中描述。9 illustrates another flowchart 900 of an exemplary method for manufacturing an EDS including single-segment die-penetration interconnects. In some implementations, the exemplary method of FIG. 9 can be used to fabricate EDS including the single-segment die-penetrating interconnections of FIGS. 3, 4, 6, 6A, and/or 6B. However, for simplicity purposes, FIG. 9 will be described in the context of providing/manufacturing the EDS of FIG. 3.

應注意，圖9提供的方塊的序列可以組合一或多個操作以簡化及/或闡明用於製造包括單分段晶粒穿透互連的EDS的方法。在一些實現中，各方塊的次序可被改變或修改。It should be noted that the sequence of blocks provided in FIG. 9 may combine one or more operations to simplify and/or clarify a method for manufacturing EDS including single-segment die-penetration interconnects. In some implementations, the order of the various blocks can be changed or modified.

可提供（902）具有第一側和相對的第二側的基板。限定在基板內的腔（例如，由基板內的諸側壁限定的開口或空穴）可在基板內形成（904）。限定在基板內的腔可以從基板的第一側形成。晶粒可被耦合至腔的基底（906），該晶粒在晶粒遠離腔的基底的一側上具有傳導焊盤。可任選地，可向腔添加（908）填充材料。填充材料可例如用於包封、保護及/或固定晶粒。A substrate having a first side and an opposing second side may be provided (902). Cavities defined in the substrate (eg, openings or voids defined by the sidewalls in the substrate) may be formed in the substrate (904). The cavity defined in the substrate may be formed from the first side of the substrate. A die may be coupled to the base of the cavity (906), the die having a conductive pad on the side of the die away from the base of the cavity. Optionally, a filler material may be added (908) to the cavity. The filler material can be used, for example, to encapsulate, protect and/or fix the die.

可進行鑽孔的製程，該孔延伸穿過基板、晶粒和傳導焊盤並被限定在其內（910）。該孔可暴露傳導焊盤的表面（例如，傳導焊盤的表面從孔內接取/可見）。可使用傳導材料鍍敷及/或填充（912）孔，該傳導材料從孔內耦合至傳導焊盤。在一些實現中，該晶粒可在鑽孔之前被耦合至腔的基底。在一些實現中，鑽孔可一次性執行。換言之，孔的完整長度可在一個製程（例如，背側鑽孔製程）期間形成。在一些實現中，該孔可被形成為是沿著延伸穿過基板的第二側、晶粒和傳導焊盤的線性軸成同軸的。在一些實現中，該孔可被形成為沿著孔的長度的單個線性孔。在一些實現中，鍍敷及/或填充該孔的傳導材料可被形成為單體的單分段。在一些實現中，傳導材料可在基板的第二側、晶粒和傳導焊盤之間延伸並穿過上述各者，並且可被形成為僅一個層（例如，一種傳導材料的僅一個分段、一種傳導材料的僅一個層）。在一些實現中，傳導材料可在基板的遠離腔的基底的第二側的表面與傳導焊盤之間形成互連。在一些實現中，傳導材料可在基板的背側表面上的孔的開口與傳導焊盤之間形成互連。在一些實現中，互連可被形成為單個分段（例如，單分段晶粒穿透互連）。在一些實現中，該互連是單體的、不可分割及/或未分割的結構。A process of drilling may be performed, the hole extending through the substrate, the die, and the conductive pad and defined within (910). The hole may expose the surface of the conductive pad (eg, the surface of the conductive pad is taken/visible from the hole). The hole may be plated and/or filled (912) with a conductive material that couples from the hole to the conductive pad. In some implementations, the die may be coupled to the base of the cavity before drilling. In some implementations, drilling can be performed all at once. In other words, the full length of the hole can be formed during one process (eg, backside drilling process). In some implementations, the hole may be formed to be coaxial along a linear axis extending through the second side of the substrate, the die, and the conductive pad. In some implementations, the hole may be formed as a single linear hole along the length of the hole. In some implementations, the conductive material that plated and/or filled the hole may be formed as a single, single segment. In some implementations, the conductive material may extend between and through the second side of the substrate, the die, and the conductive pad, and may be formed as only one layer (eg, only one segment of a conductive material , Only one layer of a conductive material). In some implementations, the conductive material may form an interconnection between the surface of the second side of the substrate remote from the base of the cavity and the conductive pad. In some implementations, the conductive material may form an interconnection between the opening of the hole on the backside surface of the substrate and the conductive pad. In some implementations, the interconnect may be formed as a single segment (eg, a single-segment die-penetrating interconnect). In some implementations, the interconnect is a monolithic, indivisible and/or undivided structure.

圖10圖示了用於製造包括單分段晶粒穿透互連的EDS的示例性方法的另一流程圖1000。在一些實現中，圖10的示例性方法可被用來製造包括圖3、圖4、圖6A及/或圖6B的單分段晶粒穿透互連的EDS。然而，出於簡化目的，圖10將在提供/製造圖4的EDS的上下文中描述。FIG. 10 illustrates another flowchart 1000 of an exemplary method for manufacturing an EDS including single-segment die-penetration interconnects. In some implementations, the exemplary method of FIG. 10 can be used to fabricate EDS including the single-segment die-penetrating interconnections of FIGS. 3, 4, 6, 6A, and/or 6B. However, for simplicity purposes, FIG. 10 will be described in the context of providing/manufacturing the EDS of FIG. 4.

應注意，圖10提供的方塊的序列可以組合一或多個操作以簡化及/或闡明用於製造包括單分段晶粒穿透互連的EDS的方法。在一些實現中，各方塊的次序可被改變或修改。It should be noted that the sequence of blocks provided in FIG. 10 may combine one or more operations to simplify and/or clarify the method for manufacturing EDS including single-segment die-penetration interconnects. In some implementations, the order of the various blocks can be changed or modified.

可提供（1002）具有第一側和相對的第二側的基板。限定在基板內的腔（例如，由基板內的諸側壁限定的開口或空穴）可在基板中形成（1004）。限定在基板內的腔可以從基板的第一側形成。該晶粒可耦合至腔的基底（1006），該晶粒在晶粒遠離腔的基底的一側上具有傳導焊盤。可任選地，可向腔添加（1008）填充材料。填充材料可例如用於包封、保護及/或固定晶粒。A substrate having a first side and an opposite second side may be provided (1002). Cavities defined within the substrate (eg, openings or voids defined by the sidewalls within the substrate) may be formed in the substrate (1004). The cavity defined in the substrate may be formed from the first side of the substrate. The die may be coupled to the base of the cavity (1006), the die having a conductive pad on the side of the die away from the base of the cavity. Optionally, filler material can be added (1008) to the cavity. The filler material can be used, for example, to encapsulate, protect and/or fix the die.

可向基板的第二側（例如，基板的背側）耦合（1010）層壓層（例如，第二層壓層）。可任選地，可向基板的第一側（例如，基板的頂側）耦合（1012）第一層壓層。A laminate layer (eg, a second laminate layer) may be coupled (1010) to a second side of the substrate (eg, the back side of the substrate). Optionally, the first laminate layer may be coupled (1012) to the first side of the substrate (eg, the top side of the substrate).

可進行鑽孔的製程，該孔延伸穿過第二層壓層、基板、晶粒和傳導焊盤並被限定在其內（1014）。該孔可暴露傳導焊盤的表面（例如，傳導焊盤的表面從孔內接取/可見）。可使用傳導材料鍍敷及/或填充（1016）孔，該傳導材料從孔內耦合至傳導焊盤。A process of drilling may be performed, the hole extending through the second laminate layer, the substrate, the die, and the conductive pad and being defined therein (1014). The hole may expose the surface of the conductive pad (eg, the surface of the conductive pad is taken/visible from the hole). The hole may be plated and/or filled (1016) with a conductive material that couples from the hole to the conductive pad.

在一些實現中，在鑽孔之前，該晶粒可耦合至腔的基底並且層壓層可耦合至基板的第二側。在一些實現中，鑽孔可一次性執行。換言之，孔的完整長度可在一個製程（例如，背側鑽孔製程）期間形成。在一些實現中，該孔可被形成為是沿著延伸穿過層壓層、基板的第二側、晶粒和傳導焊盤的線性軸成同軸的。在一些實現中，孔可被形成為沿著孔的長度的單個線性孔。在一些實現中，鍍敷及/或填充該孔的傳導材料可被形成為單體的單分段。在一些實現中，傳導材料可在層壓層、基板的第二側、晶粒和傳導焊盤之間延伸並穿過上述各者，並且可被形成為僅一個層（例如，一種傳導材料的僅一個分段、一種傳導材料的僅一個層）。在一些實現中，傳導材料可在層壓層的遠離腔的基底的表面與傳導焊盤之間形成互連。在一些實現中，傳導材料可在第二層壓層的背側表面上的孔的開口與傳導焊盤之間形成互連。在一些實現中，該互連可被形成為單個分段（例如，單分段晶粒穿透互連）。在一些實現中，該互連是單體的、不可分割及/或未分割的結構。示例性電子裝置 In some implementations, before drilling, the die may be coupled to the base of the cavity and the laminate layer may be coupled to the second side of the substrate. In some implementations, drilling can be performed all at once. In other words, the full length of the hole can be formed during one process (eg, backside drilling process). In some implementations, the hole may be formed to be coaxial along a linear axis extending through the laminate layer, the second side of the substrate, the die, and the conductive pad. In some implementations, the hole may be formed as a single linear hole along the length of the hole. In some implementations, the conductive material that plated and/or filled the hole may be formed as a single, single segment. In some implementations, the conductive material may extend between and through the laminate layer, the second side of the substrate, the die, and the conductive pad, and may be formed as only one layer (eg, a conductive material) Only one segment, only one layer of a conductive material). In some implementations, the conductive material may form an interconnection between the surface of the laminate layer's substrate remote from the cavity and the conductive pad. In some implementations, the conductive material may form an interconnection between the opening of the hole on the backside surface of the second laminate layer and the conductive pad. In some implementations, the interconnect may be formed as a single segment (eg, a single-segment die-penetrating interconnect). In some implementations, the interconnect is a monolithic, indivisible and/or undivided structure. Exemplary electronic device

圖11圖示了可與任何前述的包括單分段晶粒穿透互連的EDS整合的各種電子裝置。例如，電子裝置（諸如，行動電話裝置1102、膝上型電腦裝置1104、固定位置終端裝置1106、可穿戴裝置1108）可包括如本文所述的包括單分段晶粒穿透互連1100的EDS。圖11中所圖示的電子裝置是示例性的。例如，如本文所述的包括單分段晶粒穿透互連1100的EDS可被納入其他電子裝置中，包括但不限於包括以下各項的裝置群組：行動裝置、掌上型個人通訊系統（PCS）單元、個人數位助理、可攜式資料終端、啟用全球定位系統（GPS）的裝置、導航裝置、機上盒、音樂播放機、視訊播放機、娛樂單元、固定位置終端（例如，計量讀數裝備）、通訊裝置、行動電話、智慧型電話、平板電腦、電腦、可穿戴裝置（例如，手錶、眼鏡）、物聯網路（IoT）裝置、膝上型電腦、伺服器、路由器、在機動車輛（例如，包括自主機動車輛）中實現的電子裝置，或者儲存或取得資料或電腦指令的任何其他裝置，或其任何組合。FIG. 11 illustrates various electronic devices that can be integrated with any of the foregoing EDS including single-segment die penetration interconnects. For example, an electronic device (such as a mobile phone device 1102, a laptop computer device 1104, a fixed location terminal device 1106, a wearable device 1108) may include an EDS including a single-segment die-penetrating interconnect 1100 as described herein . The electronic device illustrated in FIG. 11 is exemplary. For example, the EDS including the single-segment die-penetrating interconnect 1100 as described herein can be incorporated into other electronic devices, including but not limited to device groups including: mobile devices, handheld personal communication systems ( PCS) unit, personal digital assistant, portable data terminal, GPS-enabled device, navigation device, set-top box, music player, video player, entertainment unit, fixed-position terminal (eg, meter reading Equipment), communication devices, mobile phones, smart phones, tablets, computers, wearable devices (eg, watches, glasses), Internet of Things (IoT) devices, laptops, servers, routers, in motor vehicles (For example, including autonomous motor vehicles) Electronic devices implemented, or any other devices that store or retrieve data or computer instructions, or any combination thereof.

圖3、圖4、圖5A、圖5B、圖6A、圖6B、圖7A-圖7C、圖8、圖9及/或圖10中圖示的組件、製程、特徵及/或功能中的一或多個可被重新安排及/或組合成單個組件、製程、特徵或功能，或可在若干組件、製程，或功能中實施。亦可添加附加的元件、組件、製程，及/或功能而不會脫離本案。亦應當注意，本案中的圖3、圖4、圖5A、圖5B、圖6A、圖6B、圖7A-圖7C、圖8、圖9及/或圖10及其相應描述不限於晶粒及/或IC。在一些實現中，圖3、圖4、圖5A、圖5B、圖6A、圖6B、圖7A-圖7C、圖8、圖9及/或圖10及其相應描述可被用於製造、建立、提供，及/或生產整合裝置。在一些實現中，裝置可包括晶粒、整合裝置、晶粒封裝、積體電路（IC）、裝置封裝、積體電路（IC）封裝、晶圓、半導體裝置、層疊封裝（PoP）裝置、嵌入晶粒式基板及/或仲介體。One of the components, processes, features, and/or functions illustrated in FIGS. 3, 4, 5, 5A, 5B, 6A, 6B, 7A-7C, 8, 9, and/or 10 Or multiple ones may be rearranged and/or combined into a single component, process, feature, or function, or may be implemented in several components, processes, or functions. Additional components, assemblies, processes, and/or functions can also be added without departing from this case. It should also be noted that Figure 3, Figure 4, Figure 5A, Figure 5B, Figure 6A, Figure 6B, Figure 7A-Figure 7C, Figure 8, Figure 9, and/or Figure 10 and their corresponding descriptions in this case are not limited to grains and /Or IC. In some implementations, FIGS. 3, 4, 5A, 5B, 6A, 6B, 7A-7C, 8, 9, and/or 10 and their corresponding descriptions can be used for manufacturing , Provide, and/or produce integrated devices. In some implementations, the device may include a die, integrated device, die package, integrated circuit (IC), device package, integrated circuit (IC) package, wafer, semiconductor device, package-on-package (PoP) device, embedded Die-type substrates and/or intermediaries.

措辭「示例性」在本文中用於表示「用作示例、實例或說明」。本文中描述為「示例性」的任何實現或態樣不必被解釋為優於或勝過本案的其他態樣。同樣，術語「態樣」不要求本案的所有態樣皆包括所論述的特徵、優點或操作模式。術語「耦合」在本文中被用於指兩個物件之間的直接或間接耦合。例如，若物件A實體地接觸物件B，且物件B接觸物件C，則物件A和C可仍被認為是彼此耦合的——即便物件A和C並非彼此直接實體接觸。The word "exemplary" is used herein to mean "used as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" need not be interpreted as superior or superior to other aspects of the case. Similarly, the term "appearance" does not require that all aspects of the case include the discussed feature, advantage or mode of operation. The term "coupling" is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically contacts object B, and object B contacts object C, then objects A and C may still be considered to be coupled to each other—even if objects A and C are not directly in physical contact with each other.

另外，注意到，本文包含的各種揭示可能是作為被圖示為流程圖、流程圖、結構圖或方塊圖的程序來描述的。儘管流程圖可能會把諸操作描述為順序程序，但是該等操作中有許多操作能夠並行或併發地執行。另外，該等操作的次序可被重新安排。程序在其操作完成時終止。In addition, note that the various disclosures contained herein may be described as programs illustrated as flowcharts, flowcharts, structural diagrams, or block diagrams. Although the flowchart may describe operations as sequential programs, many of these operations can be performed in parallel or concurrently. In addition, the order of such operations can be rearranged. The program terminates when its operation is completed.

本文中所描述的本案的各種特徵可實現於不同系統中而不會脫離本案。應注意，本案的以上各態樣僅是實例，且不應被解釋成限定本案。對本案的各態樣的描述意欲是說明性的，而非限定所附請求項的範疇。由此，本發明的教示可以現成地應用於其他類型的裝置，並且許多替換、修改和變形對於熟習此項技術者將是顯而易見的。The various features of the case described in this article can be implemented in different systems without departing from the case. It should be noted that the above aspects of this case are only examples and should not be construed as limiting this case. The description of the various aspects of the case is intended to be illustrative, not to limit the scope of the appended claims. Thus, the teachings of the present invention can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

100‧‧‧嵌入晶粒式基板（EDS）102‧‧‧核心基板104‧‧‧中央傳導層106‧‧‧頂側介電層108‧‧‧背側介電層112‧‧‧穿過互連122‧‧‧腔124‧‧‧晶粒128‧‧‧第一傳導焊盤130‧‧‧第二傳導焊盤132‧‧‧第三傳導焊盤134‧‧‧第四傳導焊盤136‧‧‧保護性傳導層138‧‧‧填充材料140‧‧‧頂側層壓層142‧‧‧背側層壓層144‧‧‧佈線路徑146‧‧‧節點148‧‧‧傳導跡線152‧‧‧第一通孔分段154‧‧‧第一焊盤156‧‧‧第二通孔分段158‧‧‧第三通孔分段160‧‧‧第二焊盤162‧‧‧第四通孔分段200‧‧‧EDS202‧‧‧核心基板204‧‧‧中央傳導層206‧‧‧頂側介電層208‧‧‧背側介電層222‧‧‧腔224‧‧‧晶粒228‧‧‧第一傳導焊盤230‧‧‧第二傳導焊盤232‧‧‧第三傳導焊盤234‧‧‧第四傳導焊盤236‧‧‧頂側保護性傳導層240‧‧‧頂側層壓層242‧‧‧背側層壓層264‧‧‧第一TSV266‧‧‧第二TSV268‧‧‧背側傳導焊盤270‧‧‧背側保護性傳導層272‧‧‧互連274‧‧‧互連280‧‧‧焊盤/跡線300‧‧‧EDS301‧‧‧第一側302‧‧‧基板303‧‧‧第二側304‧‧‧傳導層306‧‧‧第一介電層308‧‧‧第二介電層310‧‧‧單分段晶粒穿透第一互連310H‧‧‧第一孔312‧‧‧第二互連314‧‧‧第三互連316‧‧‧單分段晶粒穿透第四互連316H‧‧‧第四孔322‧‧‧腔324‧‧‧晶粒326‧‧‧黏合劑/焊料/環氧樹脂328‧‧‧第一傳導焊盤330‧‧‧第二傳導焊盤332‧‧‧第三傳導焊盤334‧‧‧第四傳導焊盤336‧‧‧保護性傳導層340‧‧‧第一層壓層342‧‧‧第二層壓層364‧‧‧第一節點366‧‧‧焊盤/跡線368‧‧‧第三節點370‧‧‧第四節點376‧‧‧傳導路徑378‧‧‧傳導路徑382‧‧‧M1層384‧‧‧M2層386‧‧‧M3層388‧‧‧M4層400‧‧‧EDS401‧‧‧第一側402‧‧‧基板403‧‧‧第二側404‧‧‧傳導層406‧‧‧第一介電層408‧‧‧第二介電層410‧‧‧單分段晶粒穿透第一互連410H‧‧‧第一孔411‧‧‧第一端412‧‧‧第二互連414‧‧‧第三互連416‧‧‧單分段晶粒穿透第四互連416H‧‧‧第四孔417‧‧‧第一端422‧‧‧腔424‧‧‧晶粒426‧‧‧黏合劑/焊料/環氧樹脂428‧‧‧第一傳導焊盤430‧‧‧第二傳導焊盤432‧‧‧第三傳導焊盤434‧‧‧第四傳導焊盤436‧‧‧保護性傳導層438‧‧‧填充材料440‧‧‧第一層壓層442‧‧‧第二層壓層467‧‧‧跡線476‧‧‧傳導路徑478‧‧‧傳導路徑482‧‧‧M1層484‧‧‧M2層486‧‧‧M3層488‧‧‧M4層524‧‧‧晶粒525‧‧‧區域527‧‧‧保護區域600‧‧‧第一EDS601‧‧‧第二EDS602‧‧‧第一位置604‧‧‧第二位置622‧‧‧腔624‧‧‧晶粒625‧‧‧區域642‧‧‧第二層壓層701‧‧‧第一側702‧‧‧基板703‧‧‧第二側704‧‧‧傳導層705‧‧‧縫706‧‧‧第一介電層708‧‧‧第二介電層710‧‧‧單分段晶粒穿透第一互連710H‧‧‧舷內孔711‧‧‧第一傳導材料分段711H‧‧‧孔712‧‧‧傳導材料712H‧‧‧第一頂側內側孔713‧‧‧第二傳導材料分段713H‧‧‧孔714‧‧‧傳導材料714H‧‧‧第二頂側舷內孔715‧‧‧焊盤/跡線716‧‧‧單分段晶粒穿透第四互連716H‧‧‧孔717‧‧‧焊盤/跡線718‧‧‧第一分段互連722‧‧‧腔724‧‧‧晶粒726‧‧‧黏合劑/焊料/環氧樹脂728‧‧‧第一傳導焊盤730‧‧‧第二傳導焊盤732‧‧‧第三傳導焊盤734‧‧‧第四傳導焊盤736‧‧‧鐳射止擋層738‧‧‧填充材料740‧‧‧第一層壓層742‧‧‧第二層壓層746‧‧‧傳導材料746H‧‧‧第二頂側舷外孔752‧‧‧傳導材料752H‧‧‧第一頂側舷外孔754‧‧‧焊盤/跡線756‧‧‧傳導材料756H‧‧‧第二舷外孔760‧‧‧焊盤/跡線762‧‧‧傳導材料762H‧‧‧第一舷外孔764‧‧‧第一節點766‧‧‧第二節點768‧‧‧焊盤/跡線770‧‧‧第四節點782‧‧‧M1層784‧‧‧M2層786‧‧‧M3層788‧‧‧M4層790‧‧‧第一水平跡線792‧‧‧第二水平跡線800‧‧‧流程圖802‧‧‧方塊804‧‧‧方塊806‧‧‧方塊808‧‧‧方塊810‧‧‧方塊812‧‧‧方塊814‧‧‧方塊816‧‧‧方塊818‧‧‧方塊820‧‧‧方塊822‧‧‧方塊824‧‧‧方塊900‧‧‧流程圖902‧‧‧方塊904‧‧‧方塊906‧‧‧方塊908‧‧‧方塊910‧‧‧方塊912‧‧‧方塊1000‧‧‧流程圖1002‧‧‧方塊1004‧‧‧方塊1006‧‧‧方塊1008‧‧‧方塊1010‧‧‧方塊1012‧‧‧方塊1014‧‧‧方塊1016‧‧‧方塊1100‧‧‧單分段晶粒穿透互連1102‧‧‧行動電話裝置1104‧‧‧膝上型電腦裝置1106‧‧‧固定位置終端裝置1108‧‧‧可穿戴裝置100‧‧‧Embedded die substrate (EDS) 102‧‧‧Core substrate 104‧‧‧Central conductive layer 106‧‧‧Top-side dielectric layer 108‧‧‧Back-side dielectric layer 112‧‧‧ Even 122‧‧‧ Cavity 124‧‧‧ Die 128‧‧‧ First conductive pad 130‧‧‧ Second conductive pad 132‧‧‧ Third conductive pad 134‧‧‧ Fourth conductive pad 136‧ ‧‧Protective conductive layer 138‧‧‧‧Fill material 140‧‧‧Top side laminate layer 142‧‧‧Back side laminate layer 144‧‧‧Wiring path 146‧‧‧Node 148‧‧‧ Conductive trace 152‧ ‧‧First through-hole segment 154‧‧‧First pad 156‧‧‧Second through-hole segment 158‧‧‧ Third through-hole segment 160‧‧‧Second pad 162‧‧‧Fourth Through-hole segment 200‧‧‧EDS202‧‧‧core substrate 204‧‧‧central conductive layer 206‧‧‧top-side dielectric layer 208‧‧‧back-side dielectric layer 222‧‧‧cavity 224‧‧‧ die 228‧‧‧ First conductive pad 230‧‧‧ Second conductive pad 232‧‧‧ Third conductive pad 234‧‧‧ Fourth conductive pad 236‧‧‧ Top side conductive conductive layer 240‧‧‧ Top side laminated layer 242‧‧‧Back side laminated layer 264‧‧‧ First TSV266‧‧‧Second TSV268‧‧‧ Backside conductive pad 270‧‧‧Backside protective conductive layer 272‧‧‧ Mutual 274‧‧‧Interconnect 280‧‧‧Pad/trace 300‧‧‧EDS301‧‧‧First side 302‧‧‧Substrate 303‧‧‧Second side 304‧‧‧Conducting layer 306‧‧‧ A dielectric layer 308‧‧‧Second dielectric layer 310‧‧‧Single-segmented grain through the first interconnect 310H‧‧‧First hole 312‧‧‧Second interconnect 314‧‧‧Inter 316‧‧‧Single-segment die through fourth interconnect 316H‧‧‧Four hole 322‧‧‧Cavity 324‧‧‧ Die 326‧‧‧ Adhesive/Solder/Epoxy resin 328‧‧‧ First conductive pad 330 ‧‧‧ Second conductive pad 332 ‧‧‧ Third conductive pad 334 ‧‧‧ Fourth conductive pad 336 ‧‧‧ Protective conductive layer 340 ‧‧‧‧Laminate layer 342 ‧‧‧ Second laminate layer 364‧‧‧ First node 366‧‧‧Pad/trace 368‧‧‧ Third node 370‧‧‧ Fourth node 376‧‧‧Conduct path 378‧‧‧Conduct path 382‧‧‧M1 layer 384‧‧‧M2 layer 386‧‧‧M3 layer 388‧‧‧M4 layer 400‧‧‧‧EDS401‧‧‧first side 402‧‧‧substrate 403‧‧‧second side 404‧‧ ‧Conducting layer 406‧‧‧First dielectric layer 408‧‧‧Second dielectric layer 410‧‧‧Single-segmented grain through the first interconnect 410H‧First hole 411‧‧‧First end 412‧‧‧Second interconnection 414‧‧‧ Third interconnection 416‧‧‧Single-segment grain through fourth interconnection 416H 417‧‧‧ First end 422‧‧‧ Cavity 424‧‧‧ Die 426‧‧‧ Adhesive/Solder/Epoxy resin 428‧‧‧ First conductive pad 430‧‧‧Second conductive pad 432‧ ‧‧ Third conductive pad 434‧‧‧ Fourth conductive pad 436‧‧‧Protective conductive layer 438‧‧‧Filling material 440‧‧‧First laminated layer 442‧‧‧Second laminated layer 467‧ ‧ Trace 476‧‧‧ Conduction path 478‧‧‧ Conduction path 482‧‧‧M1 layer 484‧‧‧M2 layer 486‧‧‧M3 layer 488‧‧‧M4 layer 524‧‧‧grain 525‧‧‧ Area 527‧‧‧Protection area 600‧‧‧First EDS601‧‧‧Second EDS602‧‧‧First position 604‧‧‧‧Second position 622‧‧‧Cavity 624‧‧‧Grain 625 ‧‧‧Second laminated layer 701‧‧‧First side 702‧‧‧Substrate 703‧‧‧Second side 704‧‧‧Conducting layer 705‧‧‧Slit 706‧‧‧First dielectric layer 708‧‧ ‧Second dielectric layer 710‧‧‧Single-segmented die penetrating the first interconnect 710H ‧‧‧Inboard hole 711‧‧‧First conductive material segment 711H ‧‧‧ First top side inner hole 713‧‧‧Second conductive material segment 713H‧‧‧‧Hole 714‧‧‧ Conductive material 714H‧‧‧Second top side inboard hole 715‧‧‧Pad/trace 716‧‧‧Single-segment die through fourth interconnect 716H‧‧‧ Hole 717‧‧‧Pad/trace 718‧‧‧First-segment interconnect 722‧‧‧Cavity 724‧‧‧ die 726‧‧‧ Adhesive/Solder/Epoxy resin 728‧‧‧ First conductive pad 730‧‧‧ Second conductive pad 732‧‧‧ Third conductive pad 734‧‧‧ Fourth conductive pad 736‧ ‧‧Laser stop layer 738‧‧‧‧filling material 740‧‧‧first laminated layer 742‧‧‧second laminated layer 746‧‧‧conducting material 746H‧‧‧second top side outboard hole 752‧‧ ‧Conducting material 752H‧‧‧First top side outboard hole 754‧‧‧Pad/trace 756‧‧‧Conducting material 756H‧‧‧Second outboard hole 760‧‧‧Pad/trace 762‧‧ ‧Conducting material 762H‧‧‧First outboard hole 764‧‧‧First node 766‧‧‧Second node 768‧‧‧Pad/trace 770‧‧‧Fourth node 782‧‧‧M1 layer 784‧ ‧‧M2 layer 786‧‧‧M3 layer 788‧‧‧M4 layer 790‧‧‧first horizontal trace 792‧‧‧second horizontal trace 800‧‧‧flow chart 802‧‧‧block 804‧‧‧block 806‧‧‧block 808‧‧‧block 810‧‧‧block 812‧‧‧block 814‧‧‧block 816‧‧‧block 818‧‧‧block 820‧‧‧block 822‧‧‧block 824‧‧‧block 900‧‧‧ Flowchart 902‧‧‧ Party Block 904‧‧‧ Block 906‧‧‧ Block 908‧‧‧ Block 910‧‧‧ Block 912‧‧‧ Block 1000‧‧‧ Flowchart 1002‧‧‧ Block 1004‧‧‧ Block 1006‧‧‧ Block 1008‧‧ ‧Block 1010‧‧‧Block 1012‧‧‧Block 1014‧‧‧Block 1016‧‧‧Block 1100‧‧‧Single-segment through-die interconnect 1102‧‧‧Mobile phone device 1104‧‧‧Laptop Device 1106‧‧‧ Fixed position terminal device 1108‧‧‧ Wearable device

在結合附圖理解下文闡述的詳細描述時，各種特徵、本質和優點會變得明顯，在附圖中，相像的元件符號貫穿始終作相應標識。When the detailed description set forth below is understood in conjunction with the accompanying drawings, various features, essences, and advantages will become apparent. In the drawings, like element symbols are marked throughout.

圖1圖示了根據一種辦法的實現第一類型的晶粒的嵌入晶粒式基板（EDS）的實例的橫截面視圖。FIG. 1 illustrates a cross-sectional view of an example of an embedded die substrate (EDS) implementing a first type of die according to one approach.

圖2圖示了根據另一種辦法的實現第二類型的晶粒的EDS的實例的橫截面視圖。Figure 2 illustrates a cross-sectional view of an example of an EDS implementing a second type of grain according to another approach.

圖3圖示了根據本文所描述的各態樣的包括單分段晶粒穿透第一互連和單分段晶粒穿透第二互連的EDS的橫截面視圖。FIG. 3 illustrates a cross-sectional view of an EDS including single-segment grain penetration first interconnect and single-segment grain penetration second interconnect according to various aspects described herein.

圖4圖示了根據本文所描述的各態樣的包括單分段晶粒穿透第一互連和單分段晶粒穿透第二互連的另一EDS的橫截面視圖。4 illustrates a cross-sectional view of another EDS including single-segmented grain penetration through a first interconnection and single-segmented grain penetration through a second interconnection according to various aspects described herein.

圖5A圖示了根據本文所描述的各態樣的可被安裝在EDS中的晶粒的背側平面視圖。5A illustrates a backside plan view of a die that can be installed in EDS according to various aspects described herein.

圖5B圖示了沿線5B-5B取的圖5A的晶粒的橫截面視圖。5B illustrates a cross-sectional view of the grain of FIG. 5A taken along line 5B-5B.

圖6A圖示了根據本文所描述的各態樣的具有被預指定用於單分段晶粒穿透互連的形成的諸第一位置的第一EDS的背側平面視圖。6A illustrates a back-side plan view of a first EDS having first locations pre-designated for the formation of single-segmented grain penetration interconnects according to various aspects described herein.

圖6B圖示了根據本文所描述的各態樣的具有被預指定用於單分段晶粒穿透互連的形成的諸第一位置的第二EDS的背側平面視圖。6B illustrates a back-side plan view of a second EDS having first locations pre-designated for the formation of single-segmented grain-through interconnects according to various aspects described herein.

圖7（包括圖7A–7C）圖示了根據本文所描述的各態樣的用於提供/製造包括單分段晶粒穿透互連的EDS的各階段的示例性序列。7 (including FIGS. 7A-7C) illustrates an exemplary sequence of stages for providing/manufacturing EDS including single-segmented grain-penetrating interconnections according to various aspects described herein.

圖8圖示了根據本文所描述的各態樣的用於製造包括單分段晶粒穿透互連的EDS的示例性方法的流程圖。FIG. 8 illustrates a flowchart of an exemplary method for manufacturing an EDS including single-segmented die-penetrating interconnects according to various aspects described herein.

圖9圖示了根據本文所描述的各態樣的用於製造包括單分段晶粒穿透互連的EDS的示例性方法的另一流程圖。9 illustrates another flowchart of an exemplary method for manufacturing an EDS including a single-segmented die-penetrating interconnection according to various aspects described herein.

圖10圖示了根據本文所描述的各態樣的用於製造包括單分段晶粒穿透互連的EDS的示例性方法的另一流程圖。FIG. 10 illustrates another flowchart of an exemplary method for manufacturing an EDS including a single-segmented die-penetrating interconnection according to various aspects described herein.

圖11圖示了可與任何前述包括單分段晶粒穿透互連的EDS整合的各種電子裝置。FIG. 11 illustrates various electronic devices that can be integrated with any of the foregoing EDS including single-segment die penetration interconnects.

國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無Domestic storage information (please note in order of storage institution, date, number) No

國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無Overseas hosting information (please note in order of hosting country, institution, date, number) No

702‧‧‧基板 702‧‧‧ substrate

704‧‧‧傳導層 704‧‧‧Conducting layer

706‧‧‧第一介電層 706‧‧‧First dielectric layer

708‧‧‧第二介電層 708‧‧‧Second dielectric layer

710‧‧‧單分段晶粒穿透第一互連 710‧‧‧Single-segment die penetration first interconnect

710H‧‧‧舷內孔 710H‧‧‧Inboard hole

711‧‧‧第一傳導材料分段 711‧‧‧The first conductive material segment

712‧‧‧傳導材料 712‧‧‧Conducting material

712H‧‧‧第一頂側內側孔 712H‧‧‧Inner hole of the first top side

713‧‧‧第二傳導材料分段 713‧‧‧Second conductive material segment

714‧‧‧傳導材料 714‧‧‧Conducting materials

714H‧‧‧第二頂側舷內孔 714H‧‧‧Second top side inner hole

715‧‧‧焊盤/跡線 715‧‧‧Pad/trace

716‧‧‧單分段晶粒穿透第四互連 716‧‧‧Single-segment die penetration fourth interconnect

716H‧‧‧孔 716H‧‧‧hole

717‧‧‧焊盤/跡線 717‧‧‧Pad/trace

722‧‧‧腔 722‧‧‧ cavity

724‧‧‧晶粒 724‧‧‧grain

726‧‧‧黏合劑/焊料/環氧樹脂 726‧‧‧Adhesive/Solder/Epoxy resin

728‧‧‧第一傳導焊盤 728‧‧‧The first conductive pad

730‧‧‧第二傳導焊盤 730‧‧‧Second conductive pad

732‧‧‧第三傳導焊盤 732‧‧‧The third conductive pad

734‧‧‧第四傳導焊盤 734‧‧‧ fourth conductive pad

736‧‧‧鐳射止擋層 736‧‧‧Laser stop layer

738‧‧‧填充材料 738‧‧‧Filling material

740‧‧‧第一層壓層 740‧‧‧Layer 1

742‧‧‧第二層壓層 742‧‧‧Layer 2

746‧‧‧傳導材料 746‧‧‧Conducting materials

746H‧‧‧第二頂側舷外孔 746H‧‧‧Second top outboard hole

752‧‧‧傳導材料 752‧‧‧Conducting materials

752H‧‧‧第一頂側舷外孔 752H‧‧‧First top outboard hole

754‧‧‧焊盤/跡線 754‧‧‧Pad/trace

756‧‧‧傳導材料 756‧‧‧Conducting material

756H‧‧‧第二舷外孔 756H‧‧‧Second outboard hole

760‧‧‧焊盤/跡線 760‧‧‧Pad/trace

762‧‧‧傳導材料 762‧‧‧Conducting materials

762H‧‧‧第一舷外孔 762H‧‧‧First outboard hole

764‧‧‧第一節點 764‧‧‧First node

766‧‧‧第二節點 766‧‧‧The second node

768‧‧‧焊盤/跡線 768‧‧‧Pad/trace

770‧‧‧第四節點 770‧‧‧The fourth node

782‧‧‧M1層 782‧‧‧M1 floor

784‧‧‧M2層 784‧‧‧M2 floor

786‧‧‧M3層 786‧‧‧M3 floor

788‧‧‧M4層 788‧‧‧M4 floor

790‧‧‧第一水平跡線 790‧‧‧The first horizontal trace

792‧‧‧第二水平跡線 792‧‧‧The second horizontal trace

Claims (28)

一種用於製造一嵌入晶粒式基板的裝置，包括：具有一第一側和相對的一第二側的一基板；其中該基板是一核心基板，該核心基板包括：一傳導層、一第一介電層，該第一介電層耦合至該傳導層的一第一表面，及一第二介電層，該第二介電層耦合至該傳導層的相對的一第二表面；一腔，該腔限定在該基板內，其中：該腔缺少該第一介電層和該傳導層；及該腔的一基底由該第二介電層來限定，其中該腔的側壁是由該第一介電層和該傳導層的共面的平面限定；耦合至該腔的該基底的一晶粒，該晶粒在該晶粒遠離該腔的該基底的一側上具有一傳導焊盤；一孔，該孔延伸穿過該第二介電層、該晶粒和該傳導焊盤並被限定在該第二介電層、該晶粒和該傳導焊盤內；及一傳導材料，該傳導材料在該孔內且在該第二介電層、該晶粒，及該傳導焊盤之間延伸並穿過該第二介電層、該晶粒，及該傳導焊盤。 An apparatus for manufacturing an embedded die substrate includes: a substrate having a first side and an opposite second side; wherein the substrate is a core substrate, the core substrate includes: a conductive layer, a first A dielectric layer, the first dielectric layer is coupled to a first surface of the conductive layer, and a second dielectric layer, the second dielectric layer is coupled to an opposite second surface of the conductive layer; a A cavity defined in the substrate, wherein: the cavity lacks the first dielectric layer and the conductive layer; and a base of the cavity is defined by the second dielectric layer, wherein the sidewall of the cavity is defined by the A coplanar plane definition of the first dielectric layer and the conductive layer; a die coupled to the substrate of the cavity, the die having a conductive pad on a side of the die away from the substrate of the cavity A hole that extends through the second dielectric layer, the die and the conductive pad and is defined within the second dielectric layer, the die and the conductive pad; and a conductive material, The conductive material extends within the hole and between the second dielectric layer, the die, and the conductive pad and passes through the second dielectric layer, the die, and the conductive pad. 如請求項1之裝置，其中該孔是穿過該第二介電層、該晶粒和該傳導焊盤連續的。 The device of claim 1, wherein the hole is continuous through the second dielectric layer, the die, and the conductive pad. 如請求項1之裝置，其中該孔是沿著延伸穿過該第二介電層、該晶粒和該傳導焊盤的一線性軸成同軸的。 The device of claim 1, wherein the hole is coaxial along a linear axis extending through the second dielectric layer, the die, and the conductive pad. 如請求項1之裝置，其中該孔是沿該孔的一長度的一單個線性孔。 The device of claim 1, wherein the hole is a single linear hole along a length of the hole. 如請求項1之裝置，其中該傳導材料是一單體的單分段。 The device of claim 1, wherein the conductive material is a single, single segment. 如請求項1之裝置，其中該傳導材料包括僅一層。 The device of claim 1, wherein the conductive material includes only one layer. 如請求項1之裝置，其中該傳導材料從該傳導焊盤內耦合至該傳導焊盤，且在該傳導焊盤遠離該腔的該基底的一側處終止。 The device of claim 1, wherein the conductive material is coupled from the conductive pad to the conductive pad, and terminates at a side of the substrate of the conductive pad away from the cavity. 一種用於製造一嵌入晶粒式基板的裝置，包括：具有一第一側和相對的一第二側的一基板，其中該基板是一核心基板，該核心基板包括：一傳導層、一第一介電層，該第一介電層耦合至該傳導層的一第一表面，及一第二介電層，該第二介電層耦合至該傳導層的相對的一第二表面； 一腔，該腔限定在該基板內，其中：該腔缺少該第一介電層和該傳導層；及該腔的一基底由該第二介電層來限定，其中該腔的側壁是由該第一介電層和該傳導層的共面的平面限定；耦合至該腔的該基底的一晶粒，該晶粒在該晶粒遠離該腔的該基底的一側上具有一傳導焊盤；一層壓層，其耦合至該基板的該第二側，該第二介電層被夾在該晶粒與該層壓層之間；一孔，其延伸穿過該層壓層、該第二介電層、該晶粒，及該傳導焊盤且被限定在該層壓層、該第二介電層、該晶粒，及該傳導焊盤內；及一傳導材料，其在該孔內並且在該層壓層、該第二介電層、該晶粒，及該傳導焊盤之間延伸並穿過該層壓層、該第二介電層、該晶粒，及該傳導焊盤。 An apparatus for manufacturing an embedded die substrate includes: a substrate having a first side and an opposite second side, wherein the substrate is a core substrate, the core substrate includes: a conductive layer, a first A dielectric layer, the first dielectric layer is coupled to a first surface of the conductive layer, and a second dielectric layer, the second dielectric layer is coupled to an opposite second surface of the conductive layer; A cavity defined in the substrate, wherein: the cavity lacks the first dielectric layer and the conductive layer; and a base of the cavity is defined by the second dielectric layer, wherein the sidewall of the cavity is defined by The coplanar plane of the first dielectric layer and the conductive layer defines; a die of the substrate coupled to the cavity, the die having a conductive weld on the side of the die away from the substrate of the cavity A laminated layer, which is coupled to the second side of the substrate, the second dielectric layer is sandwiched between the die and the laminated layer; a hole, which extends through the laminated layer, the The second dielectric layer, the die, and the conductive pad are defined within the laminate layer, the second dielectric layer, the die, and the conductive pad; and a conductive material, which is located in the Within the hole and between the laminate layer, the second dielectric layer, the die, and the conductive pad and extending through the laminate layer, the second dielectric layer, the die, and the conduction Pad. 如請求項8之裝置，其中該孔是穿過該層壓層、該第二介電層、該晶粒和該傳導焊盤連續的。 The device of claim 8, wherein the hole is continuous through the laminate layer, the second dielectric layer, the die, and the conductive pad. 如請求項8之裝置，其中該孔是沿著延伸穿過該層壓層、該第二介電層、該晶粒和該傳導焊盤的一線性軸成同軸的。 The device of claim 8, wherein the hole is coaxial along a linear axis extending through the laminate layer, the second dielectric layer, the die, and the conductive pad. 如請求項8之裝置，其中該孔是沿該孔的一長度的一單個線性孔。 The device of claim 8, wherein the hole is a single linear hole along a length of the hole. 如請求項8之裝置，其中該傳導材料是一單體的單分段。 The device of claim 8, wherein the conductive material is a single, single segment. 如請求項8之裝置，其中該傳導材料包括僅一層。 The device of claim 8, wherein the conductive material includes only one layer. 如請求項8之裝置，其中該裝置被納入從包括以下至少一者的一群組中選擇的一裝置中：一行動裝置、一掌上型個人通訊系統(PCS)單元、一個人數位助理、一可攜式資料終端、一啟用全球定位系統(GPS)的裝置、一導航裝置、一機上盒、一音樂播放機、一視訊播放機、一娛樂單元、一固定位置終端、一通訊裝置、一行動電話、一智慧型電話、一平板電腦、一電腦、一可穿戴裝置、一物聯網路(IoT)裝置、一膝上型電腦、一伺服器、一路由器，以及實現在一機動車輛中的一電子裝置。 The device of claim 8, wherein the device is included in a device selected from a group including at least one of: a mobile device, a palm-sized personal communication system (PCS) unit, a digital assistant, a Portable data terminal, a global positioning system (GPS) enabled device, a navigation device, a set-top box, a music player, a video player, an entertainment unit, a fixed location terminal, a communication device, a mobile A phone, a smart phone, a tablet, a computer, a wearable device, an Internet of Things (IoT) device, a laptop, a server, a router, and a device implemented in a motor vehicle Electronic device. 一種用於製造一嵌入晶粒式基板的裝置，包括：具有一第一側和相對的一第二側的一基板，其中該基板是一核心基板，該核心基板包括：一傳導層、一第一介電層，該第一介電層耦合至該傳導層的一第一表面，及一第二介電層，該第二介電層耦合至該傳導層的相對的一第二表面；一腔，該腔限定在該基板內，其中： 該腔缺少該第一介電層和該傳導層；及該腔的一基底由該第二介電層來限定，其中該腔的側壁是由該第一介電層和該傳導層的共面的平面限定；耦合至該腔的該基底的一晶粒，該晶粒在該晶粒遠離該腔的該基底的一側上具有一傳導焊盤；及用於一互連穿透該基板和該晶粒並將該傳導焊盤耦合至該基板的該第二側上的與該傳導焊盤相對的一節點的構件。 An apparatus for manufacturing an embedded die substrate includes: a substrate having a first side and an opposite second side, wherein the substrate is a core substrate, the core substrate includes: a conductive layer, a first A dielectric layer, the first dielectric layer is coupled to a first surface of the conductive layer, and a second dielectric layer, the second dielectric layer is coupled to an opposite second surface of the conductive layer; a A cavity defined within the substrate, wherein: The cavity lacks the first dielectric layer and the conductive layer; and a substrate of the cavity is defined by the second dielectric layer, wherein the sidewall of the cavity is coplanar with the first dielectric layer and the conductive layer A plane defined by; a die coupled to the substrate of the cavity, the die having a conductive pad on a side of the die away from the cavity of the substrate; and for an interconnect to penetrate the substrate and The die and the conductive pad are coupled to a member of a node on the second side of the substrate opposite the conductive pad. 如請求項15之裝置，其中該用於該互連的構件包括：一孔，其延伸穿過該第二介電層、該晶粒，及該傳導焊盤並被限定在該第二介電層、該晶粒，及該傳導焊盤內；及在該孔內且在該第二介電層、該晶粒，及該傳導焊盤之間延伸並穿過該第二介電層、該晶粒，及該傳導焊盤的一傳導材料。 The device of claim 15, wherein the member for the interconnect includes: a hole that extends through the second dielectric layer, the die, and the conductive pad and is defined in the second dielectric Layer, the die, and the conductive pad; and within the hole and between the second dielectric layer, the die, and the conductive pad and extending through the second dielectric layer, the The die, and a conductive material of the conductive pad. 如請求項15之裝置，其中該用於該互連的構件是穿過該第二介電層、該晶粒和該傳導焊盤連續的。 The device of claim 15, wherein the member for the interconnection is continuous through the second dielectric layer, the die, and the conductive pad. 如請求項15之裝置，其中該用於該互連的構件是沿著延伸穿過該第二介電層、該晶粒和該傳 導焊盤的一線性軸成同軸的。 The device of claim 15, wherein the member for the interconnect extends along the second dielectric layer, the die, and the transfer A linear axis of the guide pad is coaxial. 如請求項15之裝置，其中該用於該互連的構件包括沿該孔的一長度的一單個線性孔。 The device of claim 15, wherein the member for the interconnection includes a single linear hole along a length of the hole. 如請求項15之裝置，其中該用於該互連的構件包括：被形成為從該傳導焊盤內耦合至該傳導焊盤，且在該傳導焊盤遠離該腔的該基底的一側處終止的一單體的單分段的一傳導材料。 The device of claim 15, wherein the member for the interconnect includes: formed to couple from within the conductive pad to the conductive pad, and at a side of the substrate of the conductive pad away from the cavity A single piece of conductive material terminated by a single cell. 一種製造一嵌入晶粒式基板的方法，包括以下步驟：提供具有一第一側和相對的一第二側的一基板，其中該基板是一核心基板，該核心基板包括：一傳導層、一第一介電層，該第一介電層耦合至該傳導層的一第一表面，及一第二介電層，該第二介電層耦合至該傳導層的相對的一第二表面；形成限定在該基板內的一腔，其中：該腔缺少該第一介電層和該傳導層；及該腔的一基底由該第二介電層來限定，其中該腔的側壁是由該第一介電層和該傳導層的共面的平面限定；將一晶粒耦合至該腔的該基底，該晶粒在該晶粒遠離該腔的該基底的一側上具有一傳導焊盤；鑽一孔，該孔延伸穿過該第二介電層、該晶粒，及 該傳導焊盤並被限定在該第二介電層、該晶粒、及該傳導焊盤內；及利用在該第二介電層、該晶粒和該傳導焊盤之間延伸並穿過上述各者，並從該孔內耦合至該傳導焊盤的一傳導材料來鍍敷及/或填充該孔。 A method for manufacturing an embedded die substrate includes the following steps: providing a substrate having a first side and an opposite second side, wherein the substrate is a core substrate, the core substrate includes: a conductive layer, a A first dielectric layer, the first dielectric layer is coupled to a first surface of the conductive layer, and a second dielectric layer, the second dielectric layer is coupled to an opposite second surface of the conductive layer; Forming a cavity defined in the substrate, wherein: the cavity lacks the first dielectric layer and the conductive layer; and a base of the cavity is defined by the second dielectric layer, wherein the sidewall of the cavity is formed by the The coplanar plane of the first dielectric layer and the conductive layer defines; a substrate coupling a die to the cavity, the die having a conductive pad on the side of the die away from the substrate of the cavity Drilling a hole that extends through the second dielectric layer, the die, and The conductive pad is defined within the second dielectric layer, the die, and the conductive pad; and extends between and through the second dielectric layer, the die, and the conductive pad Each of the above, and a conductive material coupled to the conductive pad from the hole to plate and/or fill the hole. 如請求項21之方法，其中該晶粒在鑽該孔之前被耦合至該腔的該基底。 The method of claim 21, wherein the die is coupled to the substrate of the cavity before drilling the hole. 如請求項21之方法，其中鑽該孔是一次性執行的。 The method of claim 21, wherein drilling the hole is performed at once. 如請求項21之方法，其中該孔被形成為是沿著延伸穿過該第二介電層、該晶粒和該傳導焊盤的一線性軸成同軸的。 The method of claim 21, wherein the hole is formed to be coaxial along a linear axis extending through the second dielectric layer, the die, and the conductive pad. 如請求項21之方法，其中該孔被形成為沿該孔的一長度的一單個線性孔。 The method of claim 21, wherein the hole is formed as a single linear hole along a length of the hole. 如請求項21之方法，其中該傳導材料被形成為一單體的單分段。 The method of claim 21, wherein the conductive material is formed as a single, single segment. 如請求項21之方法，其中在該第二介電層、該晶粒和該傳導焊盤之間延伸並穿過上述各者的該傳導材料被形成為僅一層。 The method of claim 21, wherein the conductive material extending between the second dielectric layer, the die, and the conductive pad and passing through each of the above is formed as only one layer. 如請求項21之方法，進一步包括以下步驟：將一層壓層耦合至該基板的該第二側， 其中該孔被進一步鑽成延伸穿過該層壓層並被限定在該層壓層內，並且該傳導材料進一步在該層壓層之間延伸並穿過該層壓層。 The method of claim 21, further comprising the steps of: coupling a laminate layer to the second side of the substrate, Where the hole is further drilled to extend through the laminate layer and be defined within the laminate layer, and the conductive material further extends between the laminate layers and through the laminate layer.
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