TWI685919B - A manufacturing method of a trench isolation structure and high voltage semiconductor device - Google Patents

A manufacturing method of a trench isolation structure and high voltage semiconductor device Download PDF

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TWI685919B
TWI685919B TW108102158A TW108102158A TWI685919B TW I685919 B TWI685919 B TW I685919B TW 108102158 A TW108102158 A TW 108102158A TW 108102158 A TW108102158 A TW 108102158A TW I685919 B TWI685919 B TW I685919B
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isolation structure
conductivity type
trench
substrate
angle
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TW108102158A
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TW202029407A (en
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黃振明
邱淳靖
吳偉豪
丁鉦翰
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力晶積成電子製造股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A manufacturing method of a trench isolation structure includes forming a mask layer on a substrate, and patterning the mask layer to form a first opening which corresponds to a predetermined formation location of the trench isolation structure. Then, a plurality of spacers is formed on a plurality of sidewalls of the first opening, wherein a first angle is between a side surface of each of the spacers and a surface of the substrate. The exposed spacers and the substrate are removed by using the mask layer as an etching mask to form a first trench in the substrate, and a first bevel is formed at the bottom of each sidewall of the first trench, wherein the position of the first bevel corresponds to the first angle. An insulating material is then formed in the first trench.

Description

溝渠式隔離結構的製造方法及高壓半導體元件Method for manufacturing trench isolation structure and high-voltage semiconductor element

本發明是有關於一種隔離結構的製造方法以及半導體元件，且特別是有關於一種溝渠式隔離結構的製造方法及高壓半導體元件。The invention relates to a method for manufacturing an isolation structure and a semiconductor element, and in particular to a method for manufacturing a trench isolation structure and a high-voltage semiconductor element.

在微小線寬及高積極度的要求下，元件間干擾越來越明顯，因而被用來作為元件之間絕緣的淺溝槽隔離（Shallow Trench Isolation, STI）結構也就變得越來越重要。Under the requirements of small line width and high enthusiasm, the interference between components is becoming more and more obvious, so the shallow trench isolation (STI) structure used as insulation between components becomes more and more important. .

然而，目前所採用的STI結構多呈現其側壁底部與水平面之間具有一尖角的輪廓，因此易於所述尖角處產生熱載子崩潰（hot carrier breakdown）現象，進而影響高壓半導體元件（例如橫向擴散金氧半導體（LDMOS）電晶體）的特定導通電阻（specific on-resistance，Rsp）、崩潰電壓（breakdown voltage，BVDSS）、安全工作區域（Safe Operating Area，SOA）及熱載子壽命（hot carrier lifetimes，HCL）等性質。However, the currently used STI structures often have a sharp corner profile between the bottom of the side wall and the horizontal plane, so it is prone to hot carrier breakdown at the sharp corner, thereby affecting high-voltage semiconductor devices (such as Specific On-resistance (Rsp), Breakdown Voltage (BVDSS), Safe Operating Area (SOA) and Hot Carrier Lifetime (LDMOS Transistor) carrier lifetimes, HCL) and other properties.

因此，如何在滿足微小線寬及高積極度的需求的同時，還能夠防止熱載子崩潰現象的產生，已成為本領域研究人員的一大挑戰。Therefore, how to meet the needs of small line width and high enthusiasm while preventing the collapse of hot carriers has become a major challenge for researchers in this field.

本發明提供一種隔離結構的製造方法，能製作出有效防止熱載子崩潰現象產生的隔離結構，而提升使用其作為絕緣結構的元件之性能。The invention provides a method for manufacturing an isolation structure, which can produce an isolation structure that effectively prevents the occurrence of the collapse of hot carriers, and improves the performance of components using it as an insulating structure.

本發明另提供一種高壓半導體元件，藉由隔離結構，而有效防止熱載子崩潰現象產生。The invention also provides a high-voltage semiconductor device, which effectively prevents the collapse of the hot carrier through the isolation structure.

本發明的溝渠式隔離結構的製造方法，包括以下步驟。於基底上形成罩幕層。圖案化罩幕層，以形成第一開口，其對應於溝渠式隔離結構的預定形成位置。然後，在第一開口的多個側壁形成多個間隙壁，其中每個間隙壁的側面與基底的表面之間具有第一夾角。以罩幕層作為蝕刻罩幕，去除露出的多個間隙壁與基底，以於基底中形成第一溝渠，在第一溝渠的每一側壁底部形成有第一倒角，其中第一倒角的位置對應於第一夾角。接著，於第一溝渠中形成絕緣材料。The manufacturing method of the trench isolation structure of the present invention includes the following steps. A mask layer is formed on the substrate. The mask layer is patterned to form a first opening, which corresponds to a predetermined formation position of the trench isolation structure. Then, a plurality of partition walls are formed on the plurality of side walls of the first opening, wherein the side surface of each partition wall has a first included angle with the surface of the substrate. The mask layer is used as an etching mask to remove the exposed plurality of spacers and the substrate to form a first trench in the substrate. A first chamfer is formed at the bottom of each side wall of the first trench. The position corresponds to the first included angle. Next, an insulating material is formed in the first trench.

在本發明的一實施例中，形成上述多個間隙壁的步驟包括於基底上共形地形成氧化層，以於第一開口的底部形成多個第二倒角。並且，回蝕刻氧化層，直到露出基底的表面，其中多個間隙壁的位置對應於第二倒角。In an embodiment of the invention, the step of forming the plurality of spacers includes conformally forming an oxide layer on the substrate to form a plurality of second chamfers at the bottom of the first opening. Furthermore, the oxide layer is etched back until the surface of the substrate is exposed, where the positions of the plurality of spacers correspond to the second chamfer.

在本發明的一實施例中，在形成上述多個間隙壁之後以及在形成第一溝渠之前，還可包括在罩幕層上形成圖案化光阻層，圖案化光阻層具有對應於第一開口的第二開口。In an embodiment of the present invention, after forming the plurality of spacers and before forming the first trench, it may further include forming a patterned photoresist layer on the mask layer, the patterned photoresist layer having a layer corresponding to the first The second opening of the opening.

在本發明的一實施例中，上述圖案化光阻層還可具有第三開口，並露出部分罩幕層，且在形成第一溝渠期間，以圖案化光阻層作為蝕刻罩幕，去除第三開口露出的罩幕層與基底，以同時形成第一溝渠與第二溝渠。In an embodiment of the present invention, the patterned photoresist layer may further have a third opening and expose a portion of the mask layer, and during the formation of the first trench, the patterned photoresist layer is used as an etching mask to remove the first The mask layer and the substrate exposed by the three openings form the first trench and the second trench at the same time.

在本發明的一實施例中，上述多個間隙壁與基底之間的蝕刻選擇比介於0.9~1.1。In an embodiment of the invention, the etching selection ratio between the plurality of spacers and the substrate is between 0.9 and 1.1.

在本發明的一實施例中，上述第一溝渠的每一側壁包括第一壁與連接於第一壁上方的第二壁，第一壁與基底的底面之間具有第二夾角，且第二夾角為銳角，第二壁與基底的底面之間具有第三夾角，第三夾角大於第二夾角，且第三夾角為銳角或直角。In an embodiment of the invention, each side wall of the first trench includes a first wall and a second wall connected above the first wall, a second angle between the first wall and the bottom surface of the substrate, and the second The included angle is an acute angle, and there is a third included angle between the second wall and the bottom surface of the base, the third included angle is greater than the second included angle, and the third included angle is an acute angle or a right angle.

在本發明的一實施例中，上述第二夾角介於20度～60度，上述第三夾角介於75度～90度。In an embodiment of the invention, the second included angle is between 20 degrees and 60 degrees, and the third included angle is between 75 degrees and 90 degrees.

本發明的一種高壓半導體元件，包括基底、第一導電型埋入層（buried layer）、第一導電型磊晶層、閘極、閘極絕緣層、第二導電型基體（body）、第一導電型漂移區（drift）、源極、溝渠式隔離結構以及汲極。第一導電型埋入層形成於基底上。第一導電型磊晶層形成於第一導電型埋入層上。閘極形成於第一導電型磊晶層上。閘極絕緣層介於閘極與第一導電型埋入層之間。第二導電型基體形成於閘極的第一側的第一導電型磊晶層中，且第二導電型基體部分重疊於閘極。第一導電型漂移區形成於閘極的第二側的第一導電型磊晶層中，且第一導電型漂移區部分重疊於閘極。源極位於閘極的第一側的第二導電型基體中。溝渠式隔離結構位於閘極的第二側的第一導電型漂移區中，其中溝渠式隔離結構的每一側壁底部形成有一倒角。汲極位於溝渠式隔離結構遠離閘極的一側的第一導電型漂移區中。A high-voltage semiconductor device of the present invention includes a substrate, a first conductivity type buried layer, a first conductivity type epitaxial layer, a gate electrode, a gate insulating layer, a second conductivity type body, and a first Conductive drift, source, trench isolation structure and drain. The first conductive type buried layer is formed on the substrate. The first conductivity type epitaxial layer is formed on the first conductivity type buried layer. The gate electrode is formed on the first conductivity type epitaxial layer. The gate insulating layer is interposed between the gate electrode and the first conductive type buried layer. The second conductive type substrate is formed in the first conductive type epitaxial layer on the first side of the gate, and the second conductive type substrate partially overlaps the gate. The first conductivity type drift region is formed in the first conductivity type epitaxial layer on the second side of the gate, and the first conductivity type drift region partially overlaps the gate. The source electrode is located in the second conductivity type substrate on the first side of the gate electrode. The trench isolation structure is located in the drift region of the first conductivity type on the second side of the gate, wherein the bottom of each sidewall of the trench isolation structure is formed with a chamfer. The drain is located in the drift region of the first conductivity type on the side of the trench isolation structure away from the gate.

在本發明的另一實施例中，上述溝渠式隔離結構的每一側壁包括第一壁與連接於第一壁上方的第二壁，第一壁與基底的底面之間具有第一夾角，且第一夾角為銳角，第二壁與基底的底面之間具有第二夾角，第二夾角大於第一夾角，且第二夾角為銳角或直角。In another embodiment of the present invention, each side wall of the trench isolation structure includes a first wall and a second wall connected above the first wall, and a first angle is formed between the first wall and the bottom surface of the substrate, and The first included angle is an acute angle, and the second included angle between the second wall and the bottom surface of the base is greater than the first included angle, and the second included angle is an acute angle or a right angle.

在本發明的另一實施例中，上述第一夾角介於20度～60度，上述第二夾角介於75度～90度。In another embodiment of the present invention, the first included angle is between 20 degrees and 60 degrees, and the second included angle is between 75 degrees and 90 degrees.

在本發明的另一實施例中，在上述基底中具有至少一元件隔離結構，元件隔離結構包圍第二導電型基體與第一導電型漂移區。In another embodiment of the present invention, there is at least one element isolation structure in the above substrate, and the element isolation structure surrounds the second conductivity type substrate and the first conductivity type drift region.

在本發明的另一實施例中，上述高壓半導體元件還可包括摻雜區。摻雜區位於源極遠離閘極的一側的第二導電型基體中，且摻雜區與源極為不同導電型。In another embodiment of the present invention, the above-mentioned high-voltage semiconductor element may further include a doped region. The doped region is located in the second conductivity type matrix on the side of the source away from the gate, and the doped region and the source are of different conductivity types.

在本發明的另一實施例中，上述第一導電型為N型，上述第二導電型為P型；反之亦然。In another embodiment of the present invention, the first conductivity type is N-type, and the second conductivity type is P-type; vice versa.

在本發明的另一實施例中，上述高壓半導體元件為LDMOS。In another embodiment of the present invention, the high-voltage semiconductor device is LDMOS.

基於上述，本發明於溝渠式隔離結構的製造方法中，藉由在第一開口的多個側壁形成多個間隙壁，並去除露出的多個間隙壁與基底，以形成具有第一倒角的第一溝渠，因此能有效防止熱載子崩潰現象產生，藉以提升半導體元件的性能及可靠度。另外，本發明的高壓元件中使用具有倒角的溝渠式隔離結構，可改善高壓半導體元件的特定導通電阻、崩潰電壓、安全工作區域及熱載子壽命等性質，進而提升高壓半導體元件的性能及可靠度。Based on the above, in the manufacturing method of the trench isolation structure of the present invention, a plurality of spacers are formed on the plurality of sidewalls of the first opening, and the plurality of exposed spacers and the substrate are removed to form the first chamfered The first trench can therefore effectively prevent the occurrence of hot carrier collapse, thereby improving the performance and reliability of the semiconductor device. In addition, the use of chamfered trench isolation structure in the high-voltage device of the present invention can improve the properties such as specific on-resistance, breakdown voltage, safe working area and hot carrier lifetime of the high-voltage semiconductor device, thereby improving the performance and performance of the high-voltage semiconductor device Reliability.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

下文列舉一些實施例並配合所附圖式來進行詳細地說明，但所提供的實施例並非用以限制本發明所涵蓋的範圍。此外，圖式僅以說明為目的，並未依照原尺寸作圖。為了方便理解，下述說明中相同的元件將以相同之符號標示來說明。另外，關於文中所使用「包括」、「具有」等等用語，均為開放性的用語；也就是指包含但不限於。而且，文中所提到的方向性用語，例如：「上」、「下」等，僅是用以參考圖式的方向。因此，使用的方向性用語是用來說明，而並非用來限制本發明。The following lists some embodiments and details in conjunction with the accompanying drawings, but the provided embodiments are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only, and are not drawn according to the original dimensions. For ease of understanding, the same elements in the following description will be described with the same symbols. In addition, the terms "including" and "having" used in the text are all open terms; that is, they include but are not limited to. Moreover, the directional terms mentioned in the text, such as "upper" and "lower", are only used to refer to the directions of the drawings. Therefore, the directional terms used are for illustration, not for limiting the present invention.

圖1A～圖1E是依照本發明的一實施例的一種溝渠式隔離結構的製造流程剖面示意圖。1A to 1E are schematic cross-sectional views of a manufacturing process of a trench isolation structure according to an embodiment of the invention.

請參照圖1A，於基底100上形成罩幕層102，並圖案化罩幕層102，以形成第一開口104，且第一開口104對應於溝渠式隔離結構的預定形成位置。在本實施例中，在形成罩幕層102之前，還可先形成氧化層106，以提升罩幕層102與基底100之間的貼附。另外，圖案化罩幕層102的方法例如在罩幕層102上形成具有對應於第一開口104的開口的圖案化光阻層（未繪示），並以所述圖案化光阻層作為蝕刻罩幕，去除部份的罩幕層102，以形成第一開口104。在本實施例中，基底100例如為矽基底或絕緣體上覆矽（silicon on insulator，SOI）基底。罩幕層102的材料例如氮化矽，然而本發明不以此為限。Referring to FIG. 1A, a mask layer 102 is formed on a substrate 100, and the mask layer 102 is patterned to form a first opening 104, and the first opening 104 corresponds to a predetermined formation position of the trench isolation structure. In this embodiment, before the mask layer 102 is formed, an oxide layer 106 may be formed to enhance the adhesion between the mask layer 102 and the substrate 100. In addition, a method of patterning the mask layer 102 is, for example, to form a patterned photoresist layer (not shown) having an opening corresponding to the first opening 104 on the mask layer 102, and use the patterned photoresist layer as an etch In the mask, a part of the mask layer 102 is removed to form the first opening 104. In this embodiment, the substrate 100 is, for example, a silicon substrate or a silicon on insulator (SOI) substrate. The material of the mask layer 102 is, for example, silicon nitride, but the invention is not limited thereto.

請參照圖1B，於基底100上共形地形成氧化層110，以於第一開口104的底部104a形成多個倒角112。在本實施例中，倒角112例如為一斜面。在其他實施例中，倒角112也可以是圓弧面，只要能夠於後續形成所需的間隙壁即可，則本發明不以此為限。形成氧化層110的方式例如是化學氣相沉積法。Referring to FIG. 1B, an oxide layer 110 is conformally formed on the substrate 100 to form a plurality of chamfers 112 at the bottom 104a of the first opening 104. In this embodiment, the chamfer 112 is, for example, a slope. In other embodiments, the chamfer 112 may also be a circular arc surface, as long as the required partition wall can be formed later, the present invention is not limited thereto. The method of forming the oxide layer 110 is, for example, a chemical vapor deposition method.

請參照圖1C，回蝕刻氧化層110，直到露出基底100的表面100a。然後，在第一開口104的多個側壁104b形成多個間隙壁120，其中多個間隙壁120的位置對應於倒角112。在本實施例中，回蝕刻氧化層110的方法例如是以罩幕層102為罩幕進行回蝕刻。在其他實施例中，也可以將設計所需而形成的圖案化光阻層（未繪示）作為蝕刻罩幕進行回蝕刻，但本發明不以此為限。Referring to FIG. 1C, the oxide layer 110 is etched back until the surface 100a of the substrate 100 is exposed. Then, a plurality of partition walls 120 are formed on the plurality of side walls 104b of the first opening 104, wherein the positions of the plurality of partition walls 120 correspond to the chamfers 112. In the present embodiment, the method of etching back the oxide layer 110 is, for example, etching back using the mask layer 102 as a mask. In other embodiments, the patterned photoresist layer (not shown) formed as required by the design may also be used as an etching mask for etching back, but the invention is not limited thereto.

在本實施例中，間隙壁120的側面120a與基底100的表面100a之間具有第一夾角θ1。在本實施例中，第一夾角θ1例如鈍角。舉例來說，第一夾角θ1介於120度～160度，其中可藉由組合非等向性蝕刻及等向性蝕刻來調整第一夾角θ1，但本發明不以此為限。In this embodiment, a first angle θ1 is formed between the side 120 a of the spacer 120 and the surface 100 a of the substrate 100. In this embodiment, the first included angle θ1 is, for example, an obtuse angle. For example, the first included angle θ1 is between 120 degrees and 160 degrees. The first included angle θ1 can be adjusted by combining anisotropic etching and isotropic etching, but the present invention is not limited thereto.

請參照圖1D，在罩幕層102上形成圖案化光阻層130，圖案化光阻層130具有對應於第一開口104的第二開口132。在本實施例中，第二開口132例如露出間隙壁120與基底100的表面100a。另外，圖案化光阻層130還可具有第三開口134，並且第三開口134露出部份的罩幕層102。1D, a patterned photoresist layer 130 is formed on the mask layer 102, and the patterned photoresist layer 130 has a second opening 132 corresponding to the first opening 104. In this embodiment, the second opening 132 exposes the partition wall 120 and the surface 100 a of the substrate 100, for example. In addition, the patterned photoresist layer 130 may also have a third opening 134, and the third opening 134 exposes a portion of the mask layer 102.

請參照圖1E，以圖案化光阻層130作為蝕刻罩幕，去除露出的間隙壁120與基底100，以於基底100中形成第一溝渠140。在本實施例中，去除露出的間隙壁120與基底100的同時，也可以去除圖1D中的第三開口134露出的罩幕層102及底下的氧化層106與基底100，以同時形成第一溝渠140與第二溝渠150，其中第二溝渠150對應第四開口136。多個間隙壁120與罩幕層102與基底100三者間的蝕刻選擇比例如介於0.9~1.1。接著，去除圖案化光阻層130。在本實施例中，第一溝渠140的深度例如大於第二溝渠150的深度，第一溝渠140的寬度例如略大於第二溝渠150的寬度。在其他實施例中，若第一溝渠140的深度小於第二溝渠150的深度，則第一溝渠140的寬度將更大於第二溝渠150的寬度，然而本發明並不以此為限。舉例來說，第一溝渠140的深寬比例如介於0.2～1.0，但本發明並不以此為限。Referring to FIG. 1E, the patterned photoresist layer 130 is used as an etching mask to remove the exposed spacer 120 and the substrate 100 to form a first trench 140 in the substrate 100. In this embodiment, while removing the exposed spacer 120 and the substrate 100, the mask layer 102 and the underlying oxide layer 106 and the substrate 100 exposed by the third opening 134 in FIG. 1D can also be removed to form the first The trench 140 and the second trench 150, wherein the second trench 150 corresponds to the fourth opening 136. The etching selection ratio between the plurality of spacers 120 and the mask layer 102 and the substrate 100 is, for example, 0.9 to 1.1. Next, the patterned photoresist layer 130 is removed. In this embodiment, the depth of the first trench 140 is, for example, greater than the depth of the second trench 150, and the width of the first trench 140 is, for example, slightly greater than the width of the second trench 150. In other embodiments, if the depth of the first trench 140 is smaller than the depth of the second trench 150, the width of the first trench 140 will be greater than the width of the second trench 150, however, the invention is not limited thereto. For example, the aspect ratio of the first trench 140 is, for example, 0.2-1.0, but the invention is not limited thereto.

在本實施例中，多個間隙壁120與基底100之間的蝕刻選擇比介於0.9~1.1。舉例來說，多個間隙壁120與基底100之間的蝕刻選擇比介於規定的範圍，則可使間隙壁120與基底100的蝕刻速率相似，以同時去除露出的間隙壁120與基底100。藉此，可在第一溝渠140的側壁140a的底部形成有倒角142，其中倒角142的位置對應於間隙壁120。換句話說，倒角142的位置對應於第一夾角θ1。In this embodiment, the etching selection ratio between the plurality of spacers 120 and the substrate 100 ranges from 0.9 to 1.1. For example, if the etching selection ratio between the plurality of spacers 120 and the substrate 100 is within a predetermined range, the etching rate of the spacers 120 and the substrate 100 may be similar, so that the exposed spacers 120 and the substrate 100 are simultaneously removed. Thereby, a chamfer 142 may be formed at the bottom of the side wall 140a of the first trench 140, wherein the position of the chamfer 142 corresponds to the spacer 120. In other words, the position of the chamfer 142 corresponds to the first included angle θ1.

在本實施例中，第一溝渠140的側壁140a包括第一壁140b與連接於第一壁140b上方的第二壁140c。第一壁140b與基底100的底面100b之間具有第二夾角θ2，第二壁140c與基底100的底面之間具有第三夾角θ3。在本實施例中，第二夾角θ2例如為銳角，第三夾角θ3例如為銳角或直角，其中第三夾角θ3大於第二夾角θ2。舉例來說，第二夾角θ2介於20度～60度，第三夾角θ3介於75度～90度。In this embodiment, the side wall 140a of the first trench 140 includes a first wall 140b and a second wall 140c connected above the first wall 140b. The first wall 140b and the bottom surface 100b of the substrate 100 have a second included angle θ2, and the second wall 140c and the bottom surface of the substrate 100 have a third included angle θ3. In this embodiment, the second included angle θ2 is, for example, an acute angle, and the third included angle θ3 is, for example, an acute angle or a right angle, where the third included angle θ3 is greater than the second included angle θ2. For example, the second included angle θ2 is between 20 degrees and 60 degrees, and the third included angle θ3 is between 75 degrees and 90 degrees.

在其他實施例中，也可依據製程設計需求，直接以罩幕層102作為蝕刻罩幕，去除露出的間隙壁120與基底100，以於基底100中形成第一溝渠140，而可選擇性地進行上述圖1D至圖1E所示的製程，然而本發明不以此為限。In other embodiments, the mask layer 102 may be used as an etching mask directly to remove the exposed spacers 120 and the substrate 100 according to the design requirements of the process, so as to form the first trench 140 in the substrate 100, which may be selectively The processes shown in FIG. 1D to FIG. 1E are performed, but the invention is not limited thereto.

接著，於第一溝渠140與第二溝渠150中形成絕緣材料。至此，已大致上完成溝渠式隔離結構160的製作，且第一溝渠140中的溝渠式隔離結構160可作為高壓半導體元件的汲極側隔離結構，而第二溝渠150中的溝渠式隔離結構160可作為一般半導體主動區之間的隔離結構，但本發明並不限於此。Next, an insulating material is formed in the first trench 140 and the second trench 150. So far, the fabrication of the trench isolation structure 160 has been substantially completed, and the trench isolation structure 160 in the first trench 140 can be used as the drain-side isolation structure of the high-voltage semiconductor device, and the trench isolation structure 160 in the second trench 150 It can be used as an isolation structure between general semiconductor active regions, but the invention is not limited thereto.

以下，將說明上述製造流程所形成的實施例進一步應用於高壓半導體元件的實施例，但本發明並不限定於以下的實施形態。Hereinafter, the embodiment formed by the above-mentioned manufacturing process will be described as an embodiment in which the high-voltage semiconductor element is further applied, but the present invention is not limited to the following embodiments.

圖2是依照本發明的另一實施例的一種高壓半導體元件的剖面示意圖。2 is a schematic cross-sectional view of a high-voltage semiconductor device according to another embodiment of the invention.

請參考圖2，高壓半導體元件20包括基底200、第一導電型埋入層202、第一導電型磊晶層204、閘極206、閘極絕緣層208、第二導電型基體210、第一導電型漂移區212、源極214、溝渠式隔離結構216以及汲極218。在本實施例中的高壓半導體元件20是以LDMOS電晶體為例。然而，本發明並不限於此；在其他實施例中，高壓半導體元件20也可以是其他有相同問題的高壓半導體元件。基底200例如為矽基底或絕緣體上覆矽基底。Referring to FIG. 2, the high-voltage semiconductor device 20 includes a substrate 200, a first conductive type buried layer 202, a first conductive type epitaxial layer 204, a gate 206, a gate insulating layer 208, a second conductive type base 210, a first The conductive drift region 212, the source electrode 214, the trench isolation structure 216, and the drain electrode 218. The high-voltage semiconductor element 20 in this embodiment uses an LDMOS transistor as an example. However, the present invention is not limited to this; in other embodiments, the high-voltage semiconductor element 20 may also be other high-voltage semiconductor elements having the same problem. The substrate 200 is, for example, a silicon substrate or a silicon-on-insulator substrate.

在本實施例中，第一導電型埋入層202形成於基底200上。第一導電型磊晶層204形成於第一導電型埋入層202上。閘極206形成於第一導電型磊晶層204上。閘極絕緣層208介於閘極206與第一導電型埋入層202之間。第二導電型基體210形成於閘極206的第一側206a的第一導電型磊晶層204中，且第二導電型基體210部分重疊於閘極206。第一導電型漂移區212形成於閘極206的第二側206b的第一導電型磊晶層204中，且第一導電型漂移區212部分重疊於閘極206。在本實施例中，第一導電型例如N型，第二導電型例如P型。在其他實施例中，第一導電型例如P型，第二導電型例如N型，然而本發明不以此為限。In this embodiment, the first conductive type buried layer 202 is formed on the substrate 200. The first conductive type epitaxial layer 204 is formed on the first conductive type buried layer 202. The gate electrode 206 is formed on the first conductive type epitaxial layer 204. The gate insulating layer 208 is interposed between the gate 206 and the first conductive type buried layer 202. The second conductive type substrate 210 is formed in the first conductive type epitaxial layer 204 on the first side 206 a of the gate 206, and the second conductive type substrate 210 partially overlaps the gate 206. The first conductivity type drift region 212 is formed in the first conductivity type epitaxial layer 204 on the second side 206 b of the gate 206, and the first conductivity type drift region 212 partially overlaps the gate 206. In this embodiment, the first conductivity type is, for example, N type, and the second conductivity type is, for example, P type. In other embodiments, the first conductivity type is, for example, P type, and the second conductivity type is, for example, N type, however, the invention is not limited thereto.

在本實施例中，源極214位於閘極206的第一側206a的第二導電型基體210中。溝渠式隔離結構216位於閘極206的第二側206b的第一導電型漂移區212中，其中溝渠式隔離結構216的側壁216a的底部形成有倒角220。汲極218位於溝渠式隔離結構216遠離閘極206的一側的第一導電型漂移區212中。In the present embodiment, the source electrode 214 is located in the second conductive type substrate 210 on the first side 206 a of the gate electrode 206. The trench isolation structure 216 is located in the first conductivity type drift region 212 on the second side 206b of the gate electrode 206, wherein the bottom of the sidewall 216a of the trench isolation structure 216 is formed with a chamfer 220. The drain 218 is located in the first conductivity type drift region 212 on the side of the trench isolation structure 216 away from the gate 206.

在本實施例中，溝渠式隔離結構216例如為淺溝槽隔離結構。在其他實施例中，溝渠式隔離結構216也可以是場氧化（field oxide）結構或矽局部氧化（local oxidation of silicon，LOCOS）結構，只要溝渠式隔離結構216具有倒角220而可改善高壓半導體元件20的性能及可靠度即可，則本發明不以此為限。In this embodiment, the trench isolation structure 216 is, for example, a shallow trench isolation structure. In other embodiments, the trench isolation structure 216 may also be a field oxide structure or a local oxidation of silicon (LOCOS) structure, as long as the trench isolation structure 216 has a chamfer 220 to improve the high voltage semiconductor The performance and reliability of the element 20 may be sufficient, and the invention is not limited thereto.

在本實施例中，溝渠式隔離結構216的側壁216a包括第一壁216b與連接於第一壁216b上方的第二壁216c。第一壁216b與基底200的底面200a（即水平面）之間具有第一夾角θ4，第二壁216c與基底200的底面200a之間具有第二夾角θ5。在本實施例中，第一夾角θ4為銳角，第二夾角θ5為銳角或直角，且第二夾角θ5大於第一夾角θ4。舉例來說，第一夾角θ4介於20度～60度，第二夾角θ5介於75度～90度。In this embodiment, the side wall 216a of the trench isolation structure 216 includes a first wall 216b and a second wall 216c connected above the first wall 216b. The first wall 216b has a first angle θ4 between the bottom surface 200a (ie, horizontal plane) of the base 200, and the second wall 216c has a second angle θ5 between the bottom surface 200a of the base 200. In this embodiment, the first included angle θ4 is an acute angle, the second included angle θ5 is an acute angle or a right angle, and the second included angle θ5 is greater than the first included angle θ4. For example, the first included angle θ4 is between 20 degrees and 60 degrees, and the second included angle θ5 is between 75 degrees and 90 degrees.

在本實施例中，在基底200中具有至少一元件隔離結構222。元件隔離結構222包圍第二導電型基體210與第一導電型漂移區212。In this embodiment, there is at least one element isolation structure 222 in the substrate 200. The element isolation structure 222 surrounds the second conductive type base 210 and the first conductive type drift region 212.

在本實施例中，高壓半導體元件20還可包括摻雜區224。摻雜區224位於源極214遠離閘極206的一側的第二導電型基體210中，且摻雜區224與源極214為不同導電型。In this embodiment, the high-voltage semiconductor element 20 may further include a doped region 224. The doped region 224 is located in the second conductivity type base 210 on the side of the source electrode 214 away from the gate electrode 206, and the doped region 224 and the source electrode 214 are of different conductivity types.

以下，將比較高壓半導體元件採用具有倒角的溝渠式隔離結構與傳統的溝渠式隔離結構之間的電性模擬實驗。In the following, we will compare the electrical simulation experiment between the trench isolation structure with chamfered and the traditional trench isolation structure of the high voltage semiconductor device.

〈對照例1～3〉<Comparative Examples 1 to 3>

對圖3的溝渠式隔離結構進行模擬電性測試。將對照例1～3的尺寸列於下表1中，並將模擬結果列於下表2中。Carry out simulated electrical test on the trench isolation structure of FIG. 3. The dimensions of Comparative Examples 1 to 3 are listed in Table 1 below, and the simulation results are listed in Table 2 below.

〈實驗例1～6〉<Experimental examples 1 to 6>

對圖4的溝渠式隔離結構進行模擬電性測試。將實驗例1～實驗例6的尺寸列於下表1中，並將模擬結果列於下表2中。圖4所示的角度45°例如對應於圖1E所示的第二夾角，角度80°例如對應於圖1E所示的第三夾角。Simulate electrical test on the trench isolation structure of Figure 4. The dimensions of Experimental Example 1 to Experimental Example 6 are listed in Table 1 below, and the simulation results are listed in Table 2 below. The angle 45° shown in FIG. 4 corresponds to the second included angle shown in FIG. 1E, for example, and the angle 80° corresponds to the third included angle shown in FIG. 1E, for example.

[表1]   X1(Å) X2(Å) X3(Å) X4(Å) D1(Å) D2(Å) D3(Å) 對照例1 670 2760 4100 - 3800 - - 對照例2 670 2260 3600 - 3800 - - 對照例3 670 1760 3100 - 3800 - - 實驗例1 300 2260 4100 620 3800 3500 300 實驗例2 300 1760 3600 620 3800 3500 300 實驗例3 300 1260 3100 620 3800 3500 300 實驗例4 200 2430 4100 635 3800 3600 200 實驗例5 200 1930 3600 635 3800 3600 200 實驗例6 200 1430 3100 635 3800 3600 200 [Table 1] X1(Å) X2(Å) X3(Å) X4(Å) D1(Å) D2(Å) D3(Å) Comparative Example 1 670 2760 4100 - 3800 - - Comparative Example 2 670 2260 3600 - 3800 - - Comparative Example 3 670 1760 3100 - 3800 - - Experimental Example 1 300 2260 4100 620 3800 3500 300 Experimental Example 2 300 1760 3600 620 3800 3500 300 Experimental Example 3 300 1260 3100 620 3800 3500 300 Experimental Example 4 200 2430 4100 635 3800 3600 200 Experimental Example 5 200 1930 3600 635 3800 3600 200 Experimental Example 6 200 1430 3100 635 3800 3600 200

[表2]   Vtgm(V) Ron(Ω) BVDSS(V) 改善Ron的程度 犧牲BVDSS的程度 對照例1 1.128 24132 25.91 - - 對照例2 1.094 16619 25.93 - - 對照例3 1.106 13052 25.94 - - 實驗例1 1.117 21716 25.87 -10.0% -0.15% 實驗例2 1.105 15509 25.90 -6.7% -0.12% 實驗例3 1.070 12149 25.74 -6.9% -0.77% 實驗例4 1.050 22127 25.86 -8.3% -0.19% 實驗例5 1.122 15954 25.87 -4.0% -0.23% 實驗例6 1.094 12418 25.87 -4.9% -0.27% [Table 2] Vtgm(V) Ron(Ω) BVDSS(V) Improve the degree of Ron Sacrificing BVDSS Comparative Example 1 1.128 24132 25.91 - - Comparative Example 2 1.094 16619 25.93 - - Comparative Example 3 1.106 13052 25.94 - - Experimental Example 1 1.117 21716 25.87 -10.0% -0.15% Experimental Example 2 1.105 15509 25.90 -6.7% -0.12% Experimental Example 3 1.070 12149 25.74 -6.9% -0.77% Experimental Example 4 1.050 22127 25.86 -8.3% -0.19% Experimental Example 5 1.122 15954 25.87 -4.0% -0.23% Experimental Example 6 1.094 12418 25.87 -4.9% -0.27%

表1中，X1～X4為寬度，D1～D3為深度。表2中，Vtgm為臨界電壓，Ron為導通電阻，BVDSS為崩潰電壓。由表2可知，相較於僅在側壁與基底底面之間具有80度夾角的對照例1～3而言，具有倒角的實驗例1～6的Ron明顯降低，且不會影響崩潰電壓。舉例來說，實驗例1～6可降低約4%～10%的導通電阻，但僅犧牲BVDSS的程度約0.12%～0.77%。In Table 1, X1 to X4 are the width, and D1 to D3 are the depth. In Table 2, Vtgm is the critical voltage, Ron is the on-resistance, and BVDSS is the breakdown voltage. It can be seen from Table 2 that Ron of Experimental Examples 1 to 6 with chamfering is significantly lower than that of Comparative Examples 1 to 3 which only have an angle of 80 degrees between the side wall and the bottom surface of the substrate, and does not affect the breakdown voltage. For example, Experimental Examples 1 to 6 can reduce the on-resistance by about 4% to 10%, but only the degree of sacrificing BVDSS is about 0.12% to 0.77%.

也就是說，藉由如實驗例1～6般的溝渠式隔離結構具有倒角，而可有效降低導通電阻，且能夠有效防止熱載子崩潰現象產生，進而提升半導體元件的性能及可靠度。That is to say, the trench isolation structure as in Experimental Examples 1 to 6 has a chamfer, which can effectively reduce the on-resistance, and can effectively prevent the occurrence of hot carrier collapse, thereby improving the performance and reliability of the semiconductor device.

綜上所述，本發明於溝渠式隔離結構的製造方法中，藉由在第一開口的側壁形成間隙壁，且間隙壁的材料選用蝕刻率與基底材料相近者，因此在形成溝渠時，可同時去除露出的間隙壁與基底，並形成具有倒角的溝渠，因此這種溝渠式隔離結構作為高壓半導體元件（如LDMOS）的汲極側隔離結構，能有效防止熱載子崩潰現象產生，藉以改善高壓半導體元件的特定導通電阻、崩潰電壓、安全工作區域及熱載子壽命等性質，進而提升高壓半導體元件的性能及可靠度。In summary, in the manufacturing method of the trench isolation structure of the present invention, the spacer is formed on the side wall of the first opening, and the material of the spacer is selected to have an etching rate similar to that of the base material. Therefore, when forming the trench, At the same time, the exposed gap walls and the substrate are removed, and a trench with a chamfer is formed. Therefore, this trench isolation structure, as a drain-side isolation structure of a high-voltage semiconductor device (such as LDMOS), can effectively prevent the occurrence of hot carrier collapse. Improve the specific on-resistance, breakdown voltage, safe working area and hot carrier life of high-voltage semiconductor components, and then improve the performance and reliability of high-voltage semiconductor components.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

20‧‧‧高壓半導體元件 100、200‧‧‧基底 100a‧‧‧表面 100b、200a‧‧‧底面 102‧‧‧罩幕層 104‧‧‧第一開口 104a‧‧‧底部 104b、140a、216a‧‧‧側壁 106、110‧‧‧氧化層 112、142、220‧‧‧倒角 120‧‧‧間隙壁 130‧‧‧圖案化光阻層 132‧‧‧第二開口 134‧‧‧第三開口 136‧‧‧第四開口 140‧‧‧第一溝渠 140b、216b‧‧‧第一壁 140c、216c‧‧‧第二壁 150‧‧‧第二溝渠 160、216‧‧‧溝渠式隔離結構 θ1、θ4‧‧‧第一夾角 θ2、θ5‧‧‧第二夾角 θ3‧‧‧第三夾角 202‧‧‧第一導電型埋入層 204‧‧‧第一導電型磊晶層 206‧‧‧閘極 206a‧‧‧第一側 206b‧‧‧第二側 208‧‧‧閘極絕緣層 210‧‧‧第二導電型基體 212‧‧‧第一導電型漂移區 214‧‧‧源極 218‧‧‧汲極 222‧‧‧元件隔離結構 224‧‧‧摻雜區 D1、D2、D3‧‧‧深度 X1、X2、X3、X4‧‧‧寬度20‧‧‧High voltage semiconductor components 100, 200‧‧‧ base 100a‧‧‧Surface 100b, 200a‧‧‧Bottom 102‧‧‧Cover 104‧‧‧First opening 104a‧‧‧Bottom 104b, 140a, 216a 106, 110‧‧‧ oxide layer 112,142,220‧‧‧Chamfer 120‧‧‧Gap 130‧‧‧patterned photoresist layer 132‧‧‧Second opening 134‧‧‧ Third opening 136‧‧‧ Fourth opening 140‧‧‧The first ditch 140b, 216b ‧‧‧ first wall 140c, 216c ‧‧‧ second wall 150‧‧‧Second Ditch 160、216‧‧‧Trench isolation structure θ1, θ4‧‧‧First angle θ2, θ5 ‧‧‧Second included angle θ3‧‧‧The third angle 202‧‧‧The first conductivity type buried layer 204‧‧‧ First conductive epitaxial layer 206‧‧‧Gate 206a‧‧‧First side 206b‧‧‧Second side 208‧‧‧Gate insulation 210‧‧‧second conductive substrate 212‧‧‧The first conductivity type drift zone 214‧‧‧Source 218‧‧‧ Jiji 222‧‧‧Component isolation structure 224‧‧‧Doped area D1, D2, D3 ‧‧‧ depth X1, X2, X3, X4‧‧‧Width

圖1A～圖1E是依照本發明的一實施例的一種溝渠式隔離結構的製造流程剖面示意圖。 圖2是依照本發明的另一實施例的一種高壓半導體元件的剖面示意圖。 圖3是對照例1～3的溝渠式隔離結構的剖面示意圖。 圖4是實驗例1～6的溝渠式隔離結構的剖面示意圖。 1A to 1E are schematic cross-sectional views of a manufacturing process of a trench isolation structure according to an embodiment of the invention. 2 is a schematic cross-sectional view of a high-voltage semiconductor device according to another embodiment of the invention. 3 is a schematic cross-sectional view of the trench isolation structure of Comparative Examples 1 to 3. FIG. 4 is a schematic cross-sectional view of the trench isolation structure of Experimental Examples 1 to 6. FIG.

100‧‧‧基底 100‧‧‧ base

100b‧‧‧底面 100b‧‧‧Bottom

102‧‧‧罩幕層 102‧‧‧Cover

104‧‧‧第一開口 104‧‧‧First opening

106‧‧‧氧化層 106‧‧‧Oxide layer

136‧‧‧第四開口 136‧‧‧ Fourth opening

140‧‧‧第一溝渠 140‧‧‧The first ditch

140a‧‧‧側壁 140a‧‧‧side wall

140b‧‧‧第一壁 140b‧‧‧The first wall

140c‧‧‧第二壁 140c‧‧‧Second Wall

142‧‧‧倒角 142‧‧‧Chamfer

150‧‧‧第二溝渠 150‧‧‧Second Ditch

160‧‧‧溝渠式隔離結構 160‧‧‧Trench isolation structure

θ2‧‧‧第二夾角 θ2‧‧‧Second included angle

θ3‧‧‧第三夾角 θ3‧‧‧The third angle

Claims (14)

一種溝渠式隔離結構的製造方法，包括： 於一基底上形成一罩幕層； 圖案化所述罩幕層，以形成一第一開口，其對應於一溝渠式隔離結構的一預定形成位置； 在所述第一開口的多數個側壁形成多數個間隙壁，其中每個所述間隙壁的一側面與所述基底的一表面之間具有第一夾角； 以所述罩幕層作為蝕刻罩幕，去除露出的所述多數個間隙壁與所述基底，以於所述基底中形成一第一溝渠，在所述第一溝渠的每一側壁底部形成有一第一倒角，其中所述第一倒角的位置對應於所述第一夾角；以及 於所述第一溝渠中形成一絕緣材料。 A method for manufacturing a trench isolation structure includes: Forming a mask layer on a substrate; Patterning the mask layer to form a first opening corresponding to a predetermined formation position of a trench isolation structure; A plurality of partition walls are formed on the plurality of side walls of the first opening, wherein a first included angle is formed between a side surface of each of the partition walls and a surface of the base; Using the mask layer as an etching mask, the exposed plurality of spacers and the substrate are removed to form a first trench in the substrate, and a bottom of each side wall of the first trench is formed A first chamfer, wherein the position of the first chamfer corresponds to the first included angle; and An insulating material is formed in the first trench. 如申請專利範圍第1項所述的溝渠式隔離結構的製造方法，其中形成所述多數個間隙壁的步驟包括： 於所述基底上共形地形成一氧化層，以於所述第一開口的一底部形成多數個第二倒角；以及 回蝕刻所述氧化層，直到露出所述基底的一表面，其中所述多數個間隙壁的位置對應於所述第二倒角。 The method for manufacturing a trench isolation structure as described in item 1 of the patent application scope, wherein the step of forming the plurality of spacers includes: Forming an oxide layer conformally on the substrate to form a plurality of second chamfers on a bottom of the first opening; and The oxide layer is etched back until a surface of the substrate is exposed, wherein the positions of the plurality of spacers correspond to the second chamfer. 如申請專利範圍第1項所述的溝渠式隔離結構的製造方法，其中在形成所述多數個間隙壁之後以及在形成所述第一溝渠之前，更包括： 在所述罩幕層上形成一圖案化光阻層，所述圖案化光阻層具有對應於所述第一開口的一第二開口。 The method for manufacturing a trench isolation structure as described in item 1 of the patent application scope, wherein after forming the plurality of spacers and before forming the first trench, the method further includes: A patterned photoresist layer is formed on the mask layer, and the patterned photoresist layer has a second opening corresponding to the first opening. 如申請專利範圍第3項所述的溝渠式隔離結構的製造方法，其中所述圖案化光阻層更具有一第三開口，並露出部分所述罩幕層，且在形成所述第一溝渠期間，以所述圖案化光阻層作為蝕刻罩幕，去除所述第三開口露出的所述罩幕層與所述基底，以同時形成所述第一溝渠與一第二溝渠。The method for manufacturing a trench isolation structure as described in item 3 of the patent application, wherein the patterned photoresist layer further has a third opening, and exposes a portion of the mask layer, and the first trench is formed In the meantime, the patterned photoresist layer is used as an etching mask to remove the mask layer and the substrate exposed by the third opening to form the first trench and a second trench at the same time. 如申請專利範圍第1項所述的溝渠式隔離結構的製造方法，其中所述多數個間隙壁與所述基底之間的蝕刻選擇比介於0.9~1.1。The method for manufacturing a trench isolation structure as described in item 1 of the patent application range, wherein the etching selection ratio between the plurality of spacers and the substrate is between 0.9 and 1.1. 如申請專利範圍第1項所述的溝渠式隔離結構的製造方法，其中所述第一溝渠的每一所述側壁包括一第一壁與連接於所述第一壁上方的一第二壁，所述第一壁與所述基底的一底面之間具有一第二夾角，且所述第二夾角為銳角，所述第二壁與所述基底的所述底面之間具有一第三夾角，所述第三夾角大於所述第二夾角，且所述第三夾角為銳角或直角。The method for manufacturing a trench isolation structure as described in item 1 of the patent application, wherein each side wall of the first trench includes a first wall and a second wall connected above the first wall, There is a second angle between the first wall and a bottom surface of the base, and the second angle is an acute angle, and there is a third angle between the second wall and the bottom surface of the base, The third included angle is greater than the second included angle, and the third included angle is an acute angle or a right angle. 如申請專利範圍第6項所述的溝渠式隔離結構的製造方法，其中所述第二夾角介於20度～60度，所述第三夾角介於75度～90度。The method for manufacturing a trench isolation structure as described in item 6 of the patent application, wherein the second included angle is between 20 degrees and 60 degrees, and the third included angle is between 75 degrees and 90 degrees. 一種高壓半導體元件，包括： 一基底； 一第一導電型埋入層（buried layer），形成於所述基底上； 一第一導電型磊晶層，形成於所述第一導電型埋入層上； 一閘極，形成於所述第一導電型磊晶層上； 一閘極絕緣層，介於所述閘極與所述第一導電型埋入層之間； 一第二導電型基體（body），形成於所述閘極的一第一側的所述第一導電型磊晶層中，且所述第二導電型基體部分重疊於所述閘極； 一第一導電型漂移區（drift），形成於所述閘極的一第二側的所述第一導電型磊晶層中，且所述第一導電型漂移區部分重疊於所述閘極； 一源極，位於所述閘極的所述第一側的所述第二導電型基體中； 一溝渠式隔離結構，位於所述閘極的所述第二側的所述第一導電型漂移區中，其中所述溝渠式隔離結構的每一側壁底部形成有一倒角；以及 一汲極，位於所述溝渠式隔離結構遠離所述閘極的一側的所述第一導電型漂移區中。 A high-voltage semiconductor component, including: A base A first conductivity type buried layer (buried layer) formed on the substrate; A first conductivity type epitaxial layer formed on the first conductivity type buried layer; A gate electrode formed on the first conductive epitaxial layer; A gate insulating layer between the gate electrode and the first conductive type buried layer; A second conductivity type body is formed in the first conductivity type epitaxial layer on a first side of the gate, and the second conductivity type body partially overlaps the gate; A first conductivity type drift region (drift) is formed in the first conductivity type epitaxial layer on a second side of the gate electrode, and the first conductivity type drift region partially overlaps the gate electrode ; A source electrode, located in the second conductivity type substrate on the first side of the gate electrode; A trench isolation structure located in the drift region of the first conductivity type on the second side of the gate electrode, wherein the bottom of each sidewall of the trench isolation structure is formed with a chamfer; and A drain is located in the drift region of the first conductivity type on a side of the trench isolation structure away from the gate. 如申請專利範圍第8項所述的高壓半導體元件，其中所述溝渠式隔離結構的每一所述側壁包括一第一壁與連接於所述第一壁上方的一第二壁，所述第一壁與所述基底的一底面之間具有一第一夾角，且所述第一夾角為銳角，所述第二壁與所述基底的所述底面之間具有一第二夾角，所述第二夾角大於所述第一夾角，且所述第二夾角為銳角或直角。The high-voltage semiconductor device according to item 8 of the patent application scope, wherein each of the side walls of the trench isolation structure includes a first wall and a second wall connected above the first wall, the first There is a first angle between a wall and a bottom surface of the base, and the first angle is an acute angle, and a second angle between the second wall and the bottom surface of the base, the first The second included angle is greater than the first included angle, and the second included angle is an acute angle or a right angle. 如申請專利範圍第9項所述的高壓半導體元件，其中所述第一夾角介於20度～60度，所述第二夾角介於75度～90度。The high-voltage semiconductor device according to item 9 of the patent application range, wherein the first included angle is between 20 degrees and 60 degrees, and the second included angle is between 75 degrees and 90 degrees. 如申請專利範圍第8項所述的高壓半導體元件，其中在所述基底中具有至少一元件隔離結構，所述元件隔離結構包圍所述第二導電型基體與所述第一導電型漂移區。The high-voltage semiconductor element according to item 8 of the patent application range, wherein at least one element isolation structure is provided in the substrate, and the element isolation structure surrounds the second conductivity type base body and the first conductivity type drift region. 如申請專利範圍第8項所述的高壓半導體元件，更包括：摻雜區，位於所述源極遠離所述閘極的一側的所述第二導電型基體中，且所述摻雜區與所述源極為不同導電型。The high-voltage semiconductor device according to item 8 of the scope of the patent application further includes: a doped region located in the second conductivity type substrate on the side of the source away from the gate electrode, and the doped region Very different conductivity type from the source. 如申請專利範圍第8項所述的高壓半導體元件，其中所述第一導電型為N型，所述第二導電型為P型；反之亦然。The high-voltage semiconductor element as described in item 8 of the patent application range, wherein the first conductivity type is N type and the second conductivity type is P type; vice versa. 如申請專利範圍第8項所述的高壓半導體元件，其中所述高壓半導體元件為LDMOS。The high-voltage semiconductor element as described in item 8 of the patent application range, wherein the high-voltage semiconductor element is LDMOS.
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