TWI685840B - Controller and control method for dynamic random access memory - Google Patents

Controller and control method for dynamic random access memory Download PDF

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TWI685840B
TWI685840B TW106140707A TW106140707A TWI685840B TW I685840 B TWI685840 B TW I685840B TW 106140707 A TW106140707 A TW 106140707A TW 106140707 A TW106140707 A TW 106140707A TW I685840 B TWI685840 B TW I685840B
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level
time
stack
time point
recharge
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TW201832235A (en
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陳忱
沈鵬
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中國商上海兆芯集成電路有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

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Abstract

Scheduling for refreshing a dynamic random access memory (DRAM). Operation commands of a DRAM are queued in a command queue. Based on the content queued in the command queue, a microcontroller allocates a refresh monitoring interval to provide a plurality of first per-bank refresh time points and a plurality of second per-bank refresh time points in an interleaving way.

Description

動態隨機存取記憶體控制器以及動態隨機存取記憶體控制方法 Dynamic random access memory controller and dynamic random access memory control method

本案係有關於動態隨機存取記憶體(DRAM)之再充電(refresh)排程。 This case is about the refresh schedule of dynamic random access memory (DRAM).

動態隨機存取記憶體(Dynamic Random Access Memory，DRAM)是一種半導體記憶體，是利用電容內儲存電荷的多寡來代表一個二進位位元(bit)是1還是0。由於電容會有漏電的現象，因此動態隨機存取記憶體(DRAM)有再充電(refresh)需求，以維護所儲存的數據可靠度。 Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory that uses the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. Due to the leakage of capacitors, dynamic random access memory (DRAM) needs to be recharged to maintain the reliability of the stored data.

本案有關於動態隨機存取記憶體(DRAM)之再充電(refresh)排程。 This case relates to the refresh schedule of dynamic random access memory (DRAM).

根據本案一種實施方式實現的一種動態隨機存取記憶體控制器包括一指令佇列(command queue)以及一微控制器。該指令佇列使要發送至一動態隨機存取記憶體的操作指令於其中排隊。該微控制器視該指令佇列的內容，於一監控時間單位內複數個第一階層單堆再充電時間點對該動態隨機存取記憶體的一第一階層(rank)的複數個記憶單元堆逐堆進行再充電(per-bank refreshing)。該微控制器更視該指令佇列的內容， 於該監控時間單位內複數個第二階層單堆再充電時間點對該動態隨機存取記憶體的一第二階層的複數個記憶單元堆逐堆進行再充電。該等第二階層單堆再充電時間點與該等第一階層單堆再充電時間點一對一交錯。如此設計使得動態隨機存取記憶體控制器之運算資源得以不過度集中在再充電上。 A dynamic random access memory controller implemented according to an embodiment of the present application includes a command queue and a microcontroller. The command queue queues the operation commands to be sent to a dynamic random access memory. According to the content of the command queue, the microcontroller controls a plurality of first-rank (rank) memory cells of the dynamic random access memory in a plurality of first-tier single-stack recharge time points within a monitoring time unit Recharge (per-bank refreshing) stack by stack. The microcontroller also looks at the content of the command queue, and stacks a plurality of second-level single-stack multiple-level memory cells of the dynamic random-access memory within the monitoring time unit at a recharge time point The stack is recharged. The recharging time points of the second layer single stack and the recharging time points of the first layer single stack are interleaved one-to-one. Such a design allows the computing resources of the dynamic random access memory controller not to be excessively concentrated on recharging.

本案概念更可實現為動態隨機存取記憶體控制方法，包括以下步驟：提供一指令佇列，使要發送至一動態隨機存取記憶體的操作指令於其中排隊；視該指令佇列的內容，於一監控時間單位內複數個第一階層單堆再充電時間點對該動態隨機存取記憶體的一第一階層的複數個記憶單元堆逐堆進行再充電；以及視該指令佇列的內容，於該監控時間單位內複數個第二階層單堆再充電時間點對該動態隨機存取記憶體的一第二階層的複數個記憶單元堆逐堆進行再充電。該等第二階層單堆再充電時間點與該等第一階層單堆再充電時間點一對一交錯。 The concept of this case can also be implemented as a dynamic random access memory control method, including the following steps: providing a command queue to queue operation commands to be sent to a dynamic random access memory; depending on the content of the command queue , Recharging the multiple first-level single-stack multiple-memory unit stacks of the dynamic random-access memory one by one within a monitoring time unit; and depending on the command queue In the monitoring time unit, a plurality of second-level single stack recharge time points in the monitoring time unit recharge the plurality of second-level multiple memory cell stacks of the dynamic random access memory one by one. The recharging time points of the second layer single stack and the recharging time points of the first layer single stack are interleaved one-to-one.

本案所揭露之前述動態隨機存取記憶體控制器以及控制方法為多個階層提供階層交錯的逐堆再充電，使得系統資源不會長時間被再充電需求獨佔。動態隨機存取記憶體的操作指令因而得以順暢執行。 The aforementioned dynamic random access memory controller and control method disclosed in this case provide hierarchical staggered stack-by-stack recharging for multiple hierarchies, so that system resources will not be monopolized by recharging requirements for a long time. The operation instructions of the dynamic random access memory can be smoothly executed.

下文特舉實施例，並配合所附圖示，詳細說明本發明內容。 The following describes the embodiments in detail and the accompanying drawings to explain the content of the present invention in detail.

100‧‧‧動態隨機存取記憶體 100‧‧‧Dynamic Random Access Memory

102‧‧‧動態隨機存取記憶體控制器 102‧‧‧Dynamic Random Access Memory Controller

104‧‧‧指令佇列 104‧‧‧Command queue

106‧‧‧微控制器 106‧‧‧Microcontroller

108‧‧‧晶片組 108‧‧‧ Chipset

bank11…bank18、bank21…bank28‧‧‧記憶體單元堆 bank11…bank18, bank21…bank28‧‧‧Memory cell stack

rank1、rank2‧‧‧階層(儲存空間) rank1, rank2‧‧‧ hierarchy (storage space)

t11…t18、t21…t28‧‧‧第一、第二階層單堆再充電時間點 t11...t18, t21...t28

T1_1、T1_2、T2_1、T2_2‧‧‧時間點 T1_1, T1_2, T2_1, T2_2 ‧‧‧

tREFI‧‧‧監控時間單位 tREFI‧‧‧Monitoring time unit

tRFCpr‧‧‧時限 tRFCpr‧‧‧ time limit

S302‧‧‧步驟，計數器Cnt1減1 S302‧‧‧Step, counter Cnt1 decrements by 1

S304‧‧‧步驟，有對應於階層rank1之存取指令等待於指令佇列？ In step S304‧‧‧, there is an access command corresponding to level rank1 waiting for the command queue?

S306‧‧‧步驟，計數器Cnt1>=8？ S306‧‧‧Step, counter Cnt1>=8?

S308‧‧‧步驟，此輪監控時間單位tREFI不再對階層rank1做再充電 Step S308‧‧‧, this round of monitoring time unit tREFI no longer recharges rank1

S310‧‧‧步驟，對階層rank1一次性再充電(計數器Cnt1加1) Step S310‧‧‧recharge the rank1 once (counter Cnt1 plus 1)

S312‧‧‧步驟，計時tRFCpr S312‧‧‧step, time tRFCpr

S314‧‧‧步驟，有對應於階層rank1之存取指令等待於指令佇列？ In step S314‧‧‧, there is an access command corresponding to rank rank1 waiting for the command queue?

S316‧‧‧步驟，計數器Cnt1>=8？ Step S316‧‧‧, counter Cnt1>=8?

S318‧‧‧步驟，對階層rank1一次性再充電(計數器Cnt1加1) Step S318‧‧‧recharge the rank1 once (counter Cnt1 plus 1)

S320‧‧‧此輪監控時間單位tREFI不再對階層rank1做再充電 S320‧‧‧This time monitoring unit tREFI no longer recharges rank rank1

S322‧‧‧計數器Cnt1>=1？ S322‧‧‧Counter Cnt1>=1?

S324‧‧‧步驟，對階層rank1之複數個記憶單元堆bank11~bank18逐堆再充電(計數器Cnt1加1) S324‧‧‧Step, recharge each of the multiple memory cell stacks bank11~bank18 of rank rank1 (counter Cnt1 plus 1)

S402‧‧‧步驟，階層rank1一次性再充電送出？ S402‧‧‧Step, rank1 is recharged and sent out at one time?

S404‧‧‧步驟，已滿足時限tRFCpr？ Step S404‧‧‧ Has the time limit tRFCpr been met?

S406‧‧‧步驟，調降該指令佇列中對應於階層rank1的存取指令之優先權 Step S406‧‧‧ Decrease the priority of the access command corresponding to rank rank1 in the command queue

S408‧‧‧步驟，復原該指令佇列中對應於階層rank1之存取指令之優先權 Step S408‧‧‧ restore the priority of the access command corresponding to the rank rank1 in the command queue

S410‧‧‧步驟，監控階層rank1之記憶單元堆bank11~bank18個別的再充電請求 Step S410‧‧‧ monitor the individual recharge requests of bank11~bank18 of the memory cell stack of rank1

S412‧‧‧步驟，調升該指令佇列中對應於階層rank1除記憶單元堆bank1i外的其他記憶單元堆的存取指令之優先權 Step S412‧‧‧ increase the priority of the access command of the memory unit stack corresponding to the rank rank1 except the memory unit stack bank1i in the command queue

S414‧‧‧步驟，已滿足時限tRFCpb？ Step S414‧‧‧ Has the time limit tRFCpb been met?

S416‧‧‧步驟，調降該指令佇列中對應於記憶單元堆bank1i的存取指令之優先權 Step S416‧‧‧Decrease the priority of the access command corresponding to the memory cell bank bank1i in the command queue

S418‧‧‧步驟，復原該指令佇列中對應於階層rank1之存取指令之優先權Step S418‧‧‧ restore the priority of the access command corresponding to rank rank1 in the command queue

第1圖為方塊圖，根據本案一種實施方式圖解一動態隨機存 取記憶體100以及相關之動態隨機存取記憶體控制器102；第2圖為時序圖，根據本案一種實施方式劃分一個監控時間單位tREFI；第3A、3B圖為流程圖，圖解微控制器106所實施之階層rank1之再充電指令排程，每監控時間單位tREFI實施一次；以及第4A、4B圖為流程圖，圖解微控制器106所實施之階層rank1存取指令排程。 Figure 1 is a block diagram illustrating a dynamic random access memory 100 and related dynamic random access memory controller 102 according to an embodiment of the case; Figure 2 is a timing diagram, dividing a monitoring time according to an embodiment of the case Unit tREFI; Figures 3A and 3B are flow charts illustrating the recharge command scheduling of the rank 1 implemented by the microcontroller 106, which is implemented once per monitoring time unit tREFI; and Figures 4A and 4B are flow charts illustrating the micro control The hierarchical rank1 access command schedule implemented by the processor 106.

以下敘述列舉本發明的多種實施例。以下敘述介紹本發明的基本概念，且並非意圖限制本發明內容。實際發明範圍應依照申請專利範圍界定之。 The following description lists various embodiments of the present invention. The following description introduces the basic concept of the present invention and is not intended to limit the content of the present invention. The actual scope of invention shall be defined in accordance with the scope of patent application.

第1圖為方塊圖，根據本案一種實施方式圖解一動態隨機存取記憶體100以及相關之動態隨機存取記憶體控制器102。動態隨機存取記憶體控制器102包括一指令佇列104以及一微控制器106。指令佇列104使要發送至該動態隨機存取記憶體102的操作指令於其中排隊。在微控制器106的運作下，動態隨機存取記憶體100將以最佳化方式再充電，避免阻礙該指令佇列104中操作指令之執行。微控制器106可包括運算電路以及運算程式碼。第1圖實施例是將動態隨機存取記憶體控制器102實現在晶片組108，值得注意的是，在晶片組108與中央處理單元(未繪示)集成在同一片上系統(System on a Chip，SoC)的實施方式中，動態隨機存取記憶體控制器102實現於該片上系統晶片上；在傳統南北橋分立的晶片組108的實施方式中，動態隨機存取記憶體控制器102，更具體而言，係實現於晶片組108 的北橋上，但並不意圖限定之。 FIG. 1 is a block diagram illustrating a dynamic random access memory 100 and related dynamic random access memory controller 102 according to an embodiment of the present invention. The dynamic random access memory controller 102 includes a command queue 104 and a microcontroller 106. The command queue 104 queues the operation commands to be sent to the dynamic random access memory 102. Under the operation of the microcontroller 106, the dynamic random access memory 100 will be recharged in an optimized manner to avoid hindering the execution of the operation commands in the command queue 104. The microcontroller 106 may include an arithmetic circuit and arithmetic code. The embodiment in FIG. 1 implements the dynamic random access memory controller 102 on the chipset 108. It is worth noting that the chipset 108 and the central processing unit (not shown) are integrated on the same system-on-a-chip (System on a Chip , SoC) implementation, the dynamic random access memory controller 102 is implemented on the system-on-chip chip; in the conventional implementation of the discrete chipset 108 of the north-south bridge, the dynamic random access memory controller 102, more Specifically, it is implemented on the north bridge of the wafer set 108, but it is not intended to be limited.

動態隨機存取記憶體100的記憶單元可由兩條通道(channels)讀取，每條通道又包括多組記憶體模組(Memory Module，例如Dual In-line Memory Module,DIMM)，每個記憶體模組又包括多組記憶體顆粒(chip)，連結至同一個片選(Chip Select,CS)信號的一組記憶體顆粒稱之為一階層(rank)。舉例而言，如第1圖所示，一個記憶體模組的儲存空間劃分為階層rank1以及階層rank2。同一階層的儲存空間(rank)又可劃分為多個記憶單元堆(banks)。各記憶單元堆(bank)由一組字線以及位線控制。如圖所示，階層rank1的儲存空間包括八個記憶單元堆bank11…bank18，階層rank2的儲存空間包括八個記憶單元堆bank21…bank28。 The memory unit of the dynamic random access memory 100 can be read by two channels, and each channel includes multiple groups of memory modules (Memory Module, such as Dual In-line Memory Module, DIMM), each memory The module also includes multiple sets of memory chips, and a set of memory particles connected to the same Chip Select (CS) signal is called a rank. For example, as shown in Figure 1, the storage space of a memory module is divided into rank rank1 and rank rank2. The storage rank of the same hierarchy can be divided into multiple memory cell banks. Each bank of memory cells is controlled by a set of word lines and bit lines. As shown in the figure, the storage space of the rank rank1 includes eight memory unit stacks bank11...bank18, and the storage space of the rank rank2 includes eight memory unit stacks bank21...bank28.

動態隨機存取記憶體100之再充電可以「階層(rank)」為單位，也可以「記憶單元堆(bank)」為單位。一階層可被一次性再充電(per-rank refreshing)，也可被逐堆再充電(per-bank refreshing)。以下標號一次性再充電(per-rank refreshing)的耗時為tRFCpr，將使得該階層在時限tRFCpr都被佔用無法存取。以下標號單堆再充電(per-bank refreshing)的耗時為tRFCpb，佔用對象是單個記憶單元堆(bank)。時限tRFCpr通常遠長於時限tRFCpb。一種實施方式中，時限tRFCpr長達210ns，而時限tRFCpb僅90ns。動態隨機存取記憶體100的再充電是依監控時間單位(以下標號tREFI)排程。一階層之完全再充電(可能採一次性再充電per-rank refreshing或是一系列的逐堆再充電per-bank refreshing)通常被設計成每個監控時間單位 tREFI中發生一回。但在本發明中，一次性再充電(per-rank refreshing)可集中反覆發生後、在後續數個監控時間單位tREFI省略：例如，一階層甚至可在一監控時間單位tREFI反覆一次性再充電達8回，而後續8個監控時間單位tREFI則不發生再充電。在本發明中，一次性再充電(per-rank refreshing)更可被推遲，至後續監控時間單位tREFI集中反覆發生：例如，一階層甚至可在前8個監控時間單位tREFI均不發生再充電，而在最後一監控時間單位tREFI反覆一次性再充電8回。一種實施方式中，監控時間單位tREFI長達7.8us或者3.9us，遠長於上述時限tRFCpr及時限tRFCpb。 The recharging of the dynamic random access memory 100 may be in units of "rank" or "bank". A level can be recharged once (per-rank refreshing) or recharged one by one (per-bank refreshing). The time-consuming per-rank refreshing of the following label is tRFCpr, which will cause the class to be occupied and inaccessible within the time limit tRFCpr. The following label single-stack refreshing (per-bank refreshing) takes tRFCpb, and the occupied object is a single memory cell bank (bank). The time limit tRFCpr is usually much longer than the time limit tRFCpb. In one embodiment, the time limit tRFCpr is as long as 210 ns, while the time limit tRFCpb is only 90 ns. The recharge of the dynamic random access memory 100 is scheduled according to a monitoring time unit (hereinafter referred to as tREFI). One level of full recharge (perhaps one-time recharge per-rank refreshing or a series of stack-by-stack recharge per-bank refreshing) is usually designed to occur once per monitoring time unit tREFI. However, in the present invention, one-time recharge (per-rank refreshing) can be omitted after repeated occurrences in subsequent monitoring time units tREFI: for example, a class can even repeat one-time recharging up to one monitoring time unit tREFI 8 times, and the subsequent 8 monitoring time units tREFI will not recharge. In the present invention, one-time recharge (per-rank refreshing) can be postponed until the subsequent monitoring time unit tREFI occurs repeatedly: for example, a level can not even recharge in the first 8 monitoring time units tREFI, In the last monitoring time unit tREFI, it recharges 8 times at a time. In one embodiment, the monitoring time unit tREFI is as long as 7.8us or 3.9us, which is much longer than the above time limit tRFCpr and time limit tRFCpb.

第2圖為時序圖，根據本案一種實施方式劃分一個監控時間單位tREFI。如圖所示，各監控時間單位tREFI可提供第一階層單堆再充電時間點t11…t18以及第二階層單堆再充電時間點t21…t28，彼此一對一交錯一即順序為t11→t21→t12→t22→t13→t23→t14→t24→t15→t25→t16→t26→t17→t27→t18→t28。第一階層單堆再充電時間點t11…t18對應階層rank1的記憶單元堆bank11…bank18。第二階層單堆再充電時間點t21…t28對應階層rank2的記憶單元堆bank21…bank28。微控制器106可根據指令佇列104的內容，於一監控時間單位tREFI內的該等第一階層單堆再充電時間點t11…t18對記憶單元堆bank11…bank18逐堆進行再充電，以實現完全再充電該階層rank1。微控制器106可根據指令佇列104的內容，於一監控時間單位tREFI內的該等第二階層單堆再充電時間點t21…t28對記憶單元堆bank21…bank28逐堆進行再充電，以實現完全再 充電該階層rank2。以上所述概念是以階層穿插方式而分配監控時間單位tREFI給所有記憶單元堆。同樣概念也可施行於4階層、甚至未來更多階層之記憶體架構上。 Figure 2 is a timing diagram, according to one embodiment of this case, a monitoring time unit tREFI is divided. As shown in the figure, each monitoring time unit tREFI can provide the first layer single stack recharging time t11...t18 and the second layer single stack recharging time t21...t28, interleaved one by one with the sequence of t11→t21 →t12→t22→t13→t23→t14→t24→t15→t25→t16→t26→t17→t27→t18→t28. The recharging time points t11...t18 of the first level single stack correspond to the memory cell stacks bank11...bank18 of the rank rank1. The recharge time points t21...t28 of the second hierarchical single stack correspond to the memory cell banks bank21...bank28 of hierarchical rank2. According to the content of the command queue 104, the microcontroller 106 can recharge the memory cell banks bank11...bank18 one by one at the recharge time points t11...t18 of the first-level single-stack within a monitoring time unit tREFI to achieve Fully recharge this rank rank1. According to the content of the command queue 104, the microcontroller 106 can recharge the memory cell banks bank21...bank28 one by one at the recharging time points t21...t28 of the second hierarchical single stack within a monitoring time unit tREFI to achieve Fully recharge this rank rank2. The concept described above allocates the monitoring time unit tREFI to all memory cell stacks in a hierarchical interleaving manner. The same concept can be applied to the memory architecture of 4 levels, and even more levels in the future.

此外，該等第一階層單堆再充電時間點t11…t18可如圖等距相距(相距一第一時間間隔)，甚至該等第二階層單堆再充電時間點t21…t28也可如圖等距相距(相距一第二時間間隔)。第一階層單堆再充電時間點t11可如圖重疊監控時間單位tREFI的起始點。第一階層單堆再充電時間點t18可與下一監控時間單位中的第一階層單堆再充電時間點t11同樣相距該第一時間間隔。第二階層單堆再充電時間點t28可與下一監控時間單位中的第二階層單堆再充電時間點t21同樣相距該第二時間間隔。圖例中，第一時間間隔等同第二時間間隔。第一階層單堆再充電時間點t11與第二階層單堆再充電時間點t21的時間間隔可等同上述第二階層單堆再充電時間點t21與第一階層單堆再充電時間點t12的時間間隔。此段所述概念係均時劃分監控時間單位tREFI給所有記憶單元堆。同樣概念也可施行於4階層、甚至未來更多階層之記憶體架構上。 In addition, the recharging time points t11...t18 of the first-level single stacks can be equidistant as shown (a first time interval apart), and even the recharging time points t21...t28 of the second-level single stacks can also be shown as Equidistant (a second time interval apart). The recharging time point t11 of the first layer single stack may overlap the starting point of the monitoring time unit tREFI as shown in FIG. The recharge time point t18 of the first hierarchical single stack may be the same as the first time interval from the recharge time point t11 of the first hierarchical single stack in the next monitoring time unit. The second layer single stack recharging time t28 may be the same as the second time interval from the second layer single stack recharging time t21 in the next monitoring time unit. In the legend, the first time interval is equal to the second time interval. The time interval between the first layer single stack recharge time t11 and the second layer single stack recharge time t21 can be equal to the time between the second layer single stack recharge time t21 and the first layer single stack recharge time t12 interval. The concept described in this paragraph is to divide the monitoring time unit tREFI equally to all memory unit stacks. The same concept can be applied to the memory architecture of 4 levels, and even more levels in the future.

至於對階層一次性再充電(per-rank refreshing)的操作，一種實施方式是於某一監控時間單位tREFI內對應之階層rank1或者rank2閒置(在一實施例中，“閒置”即是在該指令佇列104中無對應於階層rank1或者rank2的存取指令待處理)的區間，以閒置的運算資源反覆進行，使後續數個監控時間單位(如，Nx(tREFI))無須耗費資源於該階層的再充電。如第2圖所示，階層rank1之一次性再充電可發生在時間點T1_1、滿足時 限時tRFCpr後的時間點T1_2…以下類推。另有一種實施方式是令一監控時間單位tREFI內的一次性再充電(per-rank refreshing)起始處對齊逐堆再充電(per-bank refreshing)起始處。如第2圖所示，階層rank2之一次性再充電可起始發生在時間點T2_1、更在滿足時限時tRFCpr後再發生在時間點T2_2…以下類推。時間點T2_1對齊第二階層單堆再充電時間點t21。 As for the per-rank refreshing operation, one implementation method is to idle the corresponding rank rank1 or rank2 within a certain monitoring time unit tREFI (in one embodiment, “idle” is in the command There is no interval in the queue 104 corresponding to the level of rank1 or rank2 access commands to be processed), which is repeated with idle computing resources, so that subsequent monitoring time units (eg, Nx(tREFI)) do not need to consume resources at that level Recharge. As shown in Figure 2, a one-time recharge of rank rank1 can occur at time point T1_1, time point T1_2 after the time limit tRFCpr is met, and so on. Another embodiment is to align the starting point of per-rank refreshing within a monitoring time unit tREFI with the starting point of per-bank refreshing. As shown in Figure 2, a one-time recharge of rank rank2 can start at time point T2_1, and even after meeting the time limit tRFCpr and then at time point T2_2... and so on. The time point T2_1 is aligned with the second layer single stack recharge time point t21.

以下方便說明，專對階層rank1討論再充電排程之細項。 The following is convenient for explanation, and discusses the details of the recharging schedule for class rank1.

第3A、3B圖為流程圖，圖解微控制器106所實施之階層rank1之再充電指令排程，每監控時間單位tREFI實施一次。微控制器106以一計數器(以下標號Cnt1)計數對階層rank1進行再充電(無論採一次性再充電per-rank refreshing或是採多次逐堆再充電per-bank refreshing以實現對階層rank1完全再充電)的次數。步驟S302於每回合監控時間單位tREFI之始，將計數器Cnt1遞減1。步驟S304判斷有無對應於階層rank1之存取指令等待於該指令佇列104。階層rank1無存取指令等待於該指令佇列104時，步驟S306更檢查計數器Cnt1之計數是否達一上限(此例設定為8，等同階層rank1之記憶單元堆bank11…bank18的數量)。若計數器Cnt1之計數未達8，步驟S310對階層rank1執行一次性再充電(per-rank charging)，計數器Cnt1隨之遞增1。步驟S312計時達時限tRFCpr，確認一次性再充電(per-rank charging)單次實施完畢後，可以步驟S314以及步驟S316確認指令佇列104以及計數器Cnt1的狀況。倘若還是無對應於階層rank1的存取指令等待於該指令佇列104、且該計數器Cnt1之計 數還是未達8，則步驟S318再次對階層rank1執行一次性再充電(per-rank charging)，計數器Cnt1隨之遞增1。如此根據指令佇列104以及計數器Cnt1之狀況而進行的階層rank1一次性再充電(per-rank charging)會連續地重覆施行直至步驟S316判斷出計數器Cnt1之計數達8。根據步驟S320，此回合監控時間單位tREFI將不再對階層rank1進行再充電。步驟S308也是同樣的設計概念。 FIGS. 3A and 3B are flowcharts illustrating the scheduling of the recharging command of the rank 1 implemented by the microcontroller 106, which is implemented once per monitoring time unit tREFI. The microcontroller 106 counts a counter (hereinafter referred to as Cnt1) to recharge the rank 1 (whether to use one-time recharge per-rank refreshing or multiple stack-by-stack recharge per-bank refreshing to achieve complete re-ranking of rank 1 Charge) times. Step S302 decrements the counter Cnt1 by 1 at the beginning of each round of monitoring time unit tREFI. Step S304 determines whether there is an access command corresponding to rank rank1 waiting for the command queue 104. When the rank1 no access command is waiting for the command queue 104, step S306 further checks whether the count of the counter Cnt1 reaches an upper limit (in this example, it is set to 8, which is equal to the number of bank11...bank18 of the memory cell stack of rank1). If the count of the counter Cnt1 does not reach 8, step S310 performs per-rank charging on the rank rank1, and the counter Cnt1 is incremented accordingly. In step S312, the time limit tRFCpr is counted, and after confirming that the single-time recharging (per-rank charging) has been implemented once, the status of the command queue 104 and the counter Cnt1 can be confirmed in steps S314 and S316. If there is still no access command corresponding to the rank rank1 waiting for the command queue 104, and the count of the counter Cnt1 still does not reach 8, step S318 performs per-rank charging on the rank1 rank again, the counter Cnt1 is incremented by 1. Thus, the rank-rank one-time per-rank charging performed according to the status of the command queue 104 and the counter Cnt1 is continuously repeated until step S316 determines that the count of the counter Cnt1 reaches 8. According to step S320, this round of monitoring time unit tREFI will no longer recharge rank rank1. Step S308 has the same design concept.

若步驟S304判定有對應於該階層rank1之存取指令等待於該指令佇列104，步驟S322會檢查計數器Cnt1是否為0，以判斷此回合監控時間單位tREFI是否急迫需要再充電。若計數器Cnt1大於零，此回合監控時間單位tREF1非急迫需要再充電，流程進入步驟S312提供緩衝時間(此例為時限tRFCpr，也可為其他時間長度)以執行該指令佇列104中對應於該階層rank1之存取指令。如此一來，指令佇列104中對應於該階層rank1之存取指令優先於該階層rank1之再充電。待步驟S314確認已無對應於階層rank1的存取指令等待於該指令佇列104，閒置的運算資源同樣可用於重覆施行階層rank1之一次性再充電(per-rank charging)，直至步驟S316判斷出計數器Cnt1之計數達8。 If it is determined in step S304 that there is an access command corresponding to rank1 waiting for the command queue 104, step S322 will check whether the counter Cnt1 is 0 to determine whether the monitoring time unit tREFI of this round urgently needs recharging. If the counter Cnt1 is greater than zero, the round monitoring time unit tREF1 does not need to be recharged urgently, and the flow proceeds to step S312 to provide a buffer time (in this case, the time limit tRFCpr, or other time lengths) to execute the instruction queue 104 corresponding to the Access command for rank rank1. In this way, the access command corresponding to the rank rank1 in the command queue 104 has priority over the recharge of the rankrank1. After step S314 confirms that there is no access command corresponding to the rank rank1 waiting for the command queue 104, the idle computing resources can also be used to repeat the per-rank charging of the rank rank1 until the judgment in step S316 The count of the out counter Cnt1 reaches 8.

若步驟S322判斷計數器Cnt1為0，此回合監控時間單位tREFI急迫需要再充電，步驟S324對該階層rank1之複數個記憶單元堆bank11~bank18逐堆再充電(per-bank refreshing)以實現對階層rank1完全再充電，計數器Cnt1隨階層rank1之完全再充電遞增1。如此一來，未輪到再充電的記憶單元堆得以被 存取。階層rank1等待於該指令佇列104的存取指令不會被過度延滯。在一實施方式中，步驟S322可依照第2圖所示第一階層單堆再充電時間點t11…t18對該階層rank1之複數個記憶單元堆bank11~bank18逐堆再充電(per-bank refreshing)。 If step S322 determines that the counter Cnt1 is 0, this round of monitoring time unit tREFI urgently needs to be recharged, and step S324 recharges (per-bank refreshing) the plurality of memory cell stacks bank11~bank18 of the rank rank1 one by one (per-bank refreshing) With full recharge, the counter Cnt1 is incremented by 1 with the complete recharge of rank1. In this way, the memory cell stack that has not been recharged is accessed. The access command of the rank rank1 waiting for the command queue 104 is not excessively delayed. In one embodiment, step S322 may recharge the plurality of memory cell stacks bank11~bank18 of rank1 of rank1 per-bank refreshing (per-bank refreshing) according to the recharging time points t11...t18 of the first hierarchy single stack shown in FIG. 2 .

第3A、3B圖可施行於動態隨機存取記憶體的其他階層上。例如，微控制器106可為階層rank2提供另一計數器(標號為Cnt2)進行第3A、3B圖程序。計數器Cnt2可在第2圖所示之第二階層單堆再充電時間點t21減一，以維護之。 Figures 3A and 3B can be implemented on other levels of dynamic random access memory. For example, the microcontroller 106 may provide another counter (labeled Cnt2) for the rank rank2 to perform the procedures of FIGS. 3A and 3B. The counter Cnt2 can be decremented by one at the recharge time t21 of the second layer single stack shown in FIG. 2 to maintain it.

第4A、4B圖為流程圖，圖解微控制器106所實施之階層rank1存取指令排程。第4A、4B圖係基於第3A、3B圖之再充電排程而設計，每監控時間單位tREFI實施一次。步驟S402於每回合監控時間單位tREFI之始檢查階層rank1一次性再充電(per-rank charging)請求的發送狀況。該回合監控時間單位tREFI有作階層rank1的一次性再充電(per-rank charging)時，步驟S404檢查是否滿足時限tRFCpr。若是一次性再充電(per-rank charging)反覆施行的例子，則步驟S404所檢查的會是時限tRFCpr的倍數。未達時限時，為了避免階層rank1存取指令搶到運算資源、卻因階層rank1再充電而拖延，微控制器106以步驟S406調降該指令佇列104中對應於該階層rank1的存取指令之優先權。如此一來，非存取該階層rank1的指令可優先使用運算資源且不被延滯。階層的一次性再充電(per-rank charging)結束、步驟S404判斷時限滿足時，微控制器106執行步驟S408，復原該指令佇列104中對應於該階層rank1之存取指令之優先權。 4A and 4B are flowcharts illustrating the scheduling of the hierarchical rank1 access commands implemented by the microcontroller 106. Figures 4A and 4B are designed based on the recharging schedule of Figures 3A and 3B, and are implemented once per monitoring time unit tREFI. Step S402 checks the sending status of the per-rank charging request of the rank rank1 at the beginning of each round of the monitoring time unit tREFI. When there is a one-time recharge (per-rank charging) for the rank rank1 in the monitoring time unit tREFI of this round, step S404 checks whether the time limit tRFCpr is satisfied. If it is an example in which per-rank charging is repeatedly performed, the multiple of the time limit tRFCpr will be checked in step S404. When the time limit is not reached, in order to avoid the hierarchical rank1 access command grabbing the computing resources but being delayed due to the hierarchical rank1 recharge, the microcontroller 106 reduces the access command corresponding to the hierarchical rank1 in the command queue 104 in step S406 Priority. In this way, instructions that do not access rank 1 of the hierarchy can preferentially use computing resources without being delayed. When the per-rank charging of the hierarchy ends and it is determined in step S404 that the time limit is satisfied, the microcontroller 106 executes step S408 to restore the priority of the access command in the command queue 104 corresponding to rank 1 of the hierarchy.

若步驟S402判定該回合監控時間單位tREFI不對階層rank1做一次性再充電(per-rank charging)，步驟S410監控階層rank1之記憶單元堆bank11~bank18個別的再充電請求(per-bank refreshing)。對於單一記憶單元堆bank1i之再充電，步驟S412調升該指令佇列104中對應於該階層rank1除該單一記憶單元堆bank1i外的其他記憶單元堆的存取指令之優先權。步驟S414檢查是否滿足時限tRFCpb。未達時限tRFCpb時，為了避免記憶單元堆bank1i存取指令無謂搶到運算資源，微控制器106以步驟S416調降該指令佇列104中對應於該記憶單元堆bank1i的存取指令之優先權。如此一來，非存取該記憶單元堆bank1i的指令可優先使用運算資源且不被延滯。單一記憶單元堆bank1i的再充電結束、步驟S414判斷時限tRFCpb滿足時，微控制器106執行步驟S418，復原該指令佇列104中對應於該階層rank1之所有記憶單元堆(無論之前對應的存取指令之優先權係被調升或調降的記憶單元堆)的存取指令之優先權。步驟S410對記憶單元堆bank11~bank18個別的再充電請求監控及時(例如，達時間點t18，或達監控時間單位tREFI)，則流程結束。 If it is determined in step S402 that the round monitoring time unit tREFI does not perform per-rank charging for the rank rank1, step S410 monitors the individual recharge requests (per-bank refreshing) of the memory banks bank11 to bank18 of the rank rank1. For recharging the single memory cell stack bank1i, step S412 increases the priority of the access commands in the command queue 104 corresponding to the rank1 other memory cell stacks than the single memory cell stack bank1i. Step S414 checks whether the time limit tRFCpb is satisfied. When the time limit tRFCpb is not reached, in order to prevent the memory cell bank bank1i access command from unnecessarily grabbing computing resources, the microcontroller 106 reduces the priority of the access command in the instruction queue 104 corresponding to the memory cell stack bank1i in step S416 . In this way, instructions that do not access the memory cell bank bank1i can preferentially use computing resources without being delayed. When the recharge of the single memory cell bank bank1i is completed, and step S414 determines that the time limit tRFCpb is satisfied, the microcontroller 106 executes step S418 to restore all the memory cell stacks in the command queue 104 corresponding to the rank rank1 (regardless of the previous corresponding access The priority of the instruction is the priority of the access instruction of the memory unit stack that is raised or lowered. In step S410, the individual recharge requests of the memory cell banks bank11~bank18 are monitored in time (for example, at the time point t18, or at the monitoring time unit tREFI), and the process ends.

本案更揭露動態隨機存取記憶體控制方法。任何依循以上概念施作於一動態隨機存取記憶體上的控制方法，皆屬於本案所欲保護範圍。本案所揭露之前述動態隨機存取記憶體控制器以及控制方法係根據階層rank1或者rank2的閒置狀況，來動態排程對階層rank1或者rank2的再充電操作，具體而言，係於某一監控時間單位tREFI內對應之階層閒置的區間，連續反覆對該階層進行一次性再充電操作，而不必固定地每隔 一監控時間單位才進行一次性再充電操作，使後續數個監控時間單位(如，Nx(tREFI))無須耗費資源於該階層的再充電，從而提高對應於該階層的存取指令的執行效率。本發明另一方面係於對某一階層的某一記憶單元堆進行再充電操作時，動態調整對應於該階層各個記憶單元堆所對應存取指令的優先級，使得未輪到再充電的記憶單元堆對應的存取指令得以被執行，使得該階層等待於該指令佇列的存取指令不會被過度延滯。 This case also discloses a dynamic random access memory control method. Any control method applied to a dynamic random access memory according to the above concept belongs to the protection scope of this case. The aforementioned dynamic random access memory controller and control method disclosed in this case are based on the idle status of rank1 or rank2 to dynamically schedule the recharging operation of rank1 or rank2, specifically, during a certain monitoring time In the interval where the corresponding stratum in the unit tREFI is idle, a one-time recharge operation is continuously performed on the stratum repeatedly, without having to perform a one-time recharge operation every fixed monitoring time unit, so that subsequent monitoring time units (eg, Nx(tREFI)) does not need to consume resources to recharge the hierarchy, thereby improving the execution efficiency of access commands corresponding to the hierarchy. Another aspect of the present invention is to dynamically adjust the priority of the access command corresponding to each memory cell stack of a hierarchy when recharging a memory cell stack of a hierarchy, so that it is not the turn to recharge the memory The access instruction corresponding to the unit stack is executed, so that the access instruction waiting for the instruction queue of the hierarchy will not be excessively delayed.

動態隨機存取記憶體更有其他變形。除了支援逐堆再充電(per-bank refreshing)的LPDDR3以及LPDDR4規格，也有不支援逐堆再充電、僅採一次性再充電(per-rank refreshing)的DDR3以及DDR4。關於DDR3以及DDR4規格，步驟S324所執行的操作是對階層rank1作一次性再充電，掌握優先於該階層rank1之存取指令、對該階層rank1再充電的原則，即在此種情形下，儘管有該階層rank1之存取指令待處理，在計數器Cnt1為0時，對該階層rank1的再充電需求更為迫切，優先級更高。此外，DDR3以及DDR4無關第4B圖之單堆再充電監控。 Dynamic random access memory has other variants. In addition to the LPDDR3 and LPDDR4 specifications that support per-bank refreshing (per-bank refreshing), there are also DDR3 and DDR4 that do not support per-bank refreshing and only use per-rank refreshing. Regarding the DDR3 and DDR4 specifications, the operation performed in step S324 is to recharge the rank1 at a time, and to grasp the principle of accessing the priority rank1 and recharging the rank1, that is, in this case, although There is an access command of this rank rank1 to be processed. When the counter Cnt1 is 0, the demand for recharging rank1 is more urgent and the priority is higher. In addition, DDR3 and DDR4 have nothing to do with the single stack recharge monitoring in Figure 4B.

雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟悉此項技藝者，在不脫離本發明之精神和範圍內，當可做些許更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone who is familiar with this skill can do some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be as defined in the scope of the attached patent application.

t11…t18、t21…t28‧‧‧第一、第二階層單堆再充電時間點 t11...t18, t21...t28

T1_1、T1_2、T2_1、T2_2‧‧‧時間點 T1_1, T1_2, T2_1, T2_2 ‧‧‧

tREFI‧‧‧監控時間單位 tREFI‧‧‧Monitoring time unit

tRFCpr‧‧‧時限 tRFCpr‧‧‧ time limit

Claims (18)

一種記憶體控制器，包括：一指令佇列，使要發送至一動態隨機存取記憶體的操作指令於其中排隊；以及一微控制器，其中：該微控制器視該指令佇列的內容，於一監控時間單位內複數個第一階層單堆再充電時間點對該動態隨機存取記憶體的一第一階層的複數個記憶單元堆逐堆進行再充電；該微控制器視該指令佇列的內容，於該監控時間單位內複數個第二階層單堆再充電時間點對該動態隨機存取記憶體的一第二階層的複數個記憶單元堆逐堆進行再充電；該等第二階層單堆再充電時間點與該等第一階層單堆再充電時間點一對一交錯；該微控制器更以一第一計數器計數對該第一階層完全再充電的次數；該微控制器計時每逢一第一首時間點，即令該第一計數器減一，其中，該等第一階層單堆再充電時間點中對應該第一階層之該等記憶單元堆中一首記憶單元堆者為該第一首時間點；且該微控制器是在該第一計數器為零但有對應於該第一階層之存取指令等待於該指令佇列時，於上述第一階層單堆再充電時間點對該第一階層的該等記憶單元堆逐堆進行再充電，使該第一階層未輪到再充電的記憶單元堆得以被存取。 A memory controller includes: a command queue for queuing operation commands to be sent to a dynamic random access memory; and a microcontroller, wherein: the microcontroller depends on the content of the command queue , Recharge the multiple first-level single-stack multiple-memory unit stacks of the dynamic random access memory one by one within a monitoring time unit; the microcontroller sees the command The content of the queue recharges the plurality of second-level single-stack memory cells of the dynamic random access memory one by one in the monitoring time unit at a plurality of second-level single-stack recharge time points; The second-level single-stack recharge time point and the first-level single-stack recharge time point are interleaved one-to-one; the microcontroller also counts the number of times the first level is fully recharged by a first counter; the micro-controller Every time the first time point of the timer is counted, the first counter is decremented by one. Among them, the first level of single-stack recharge time points corresponding to the first level of the memory cell stacks The first time point; and the microcontroller is in the first level single stack again when the first counter is zero but there is an access command corresponding to the first level waiting for the command queue At the charging time point, the memory cell stacks of the first hierarchy are recharged one by one, so that the memory cell stacks of the first hierarchy that have not been recharged can be accessed. 如申請專利範圍第1項所述之記憶體控制器，其中：該等第一階層單堆再充電時間點等距相距一第一時間間隔。 The memory controller as described in item 1 of the patent application scope, wherein: the recharging time points of the first-level single stacks are equally spaced apart by a first time interval. 如申請專利範圍第1項所述之記憶體控制器，其中：該等第二階層單堆再充電時間點等距相距一第二時間間隔。 The memory controller as described in item 1 of the patent application scope, wherein: the recharging time points of the second-level single stacks are equally spaced apart by a second time interval. 如申請專利範圍第1項所述之記憶體控制器，其中：該第一首時間點重疊上述監控時間單位的起始點。 The memory controller as described in item 1 of the patent application scope, wherein: the first time point overlaps the starting point of the monitoring time unit. 如申請專利範圍第4項所述之記憶體控制器，其中：該等第一階層單堆再充電時間點中對應該第一階層之該等記憶單元堆中一末記憶單元堆者為一第一末時間點；且該監控時間單位中的上述第一末時間點與一下一監控時間單位中的上述第一首時間點相距一第一時間間隔，其中該等第一階層單堆再充電時間點等距相距該第一時間間隔。 The memory controller as described in item 4 of the patent application scope, wherein: among the first-level single-stack recharge time points, one of the first-level memory cell stacks corresponding to the last memory cell stack is the first A last time point; and the first last time point in the monitoring time unit is separated from the first first time point in the next monitoring time unit by a first time interval, wherein the recharge time of the first-level single stack The points are equidistant from the first time interval. 如申請專利範圍第4項所述之記憶體控制器，其中：該等第二階層單堆再充電時間點中對應該第二階層之該等記憶單元堆中一首記憶單元堆者為一第二首時間點。 The memory controller as described in item 4 of the patent application scope, wherein: among the second-level single-stack recharge time points, one of the first-level memory unit stacks corresponding to the second-level single-stack memory stack is the first Two points in time. 如申請專利範圍第6項所述之記憶體控制器，其中：該等第一階層單堆再充電時間點中對應該第一階層之該等記憶單元堆中一次記憶單元堆者為一第一次時間點；且上述第一首時間點與第二首時間點的時間間隔等同上述第二首時間點與第一次時間點的時間間隔。 The memory controller as described in item 6 of the patent application scope, wherein: among the first-level single stack recharge time points, the first one of the first-level memory cell stacks is the first one The second time point; and the time interval between the first time point and the second time point is equal to the time interval between the second time point and the first time point. 如申請專利範圍第1項所述之記憶體控制器，其中： 該微控制器更以一第二計數器計數對該第二階層完全再充電的次數；該微控制器計時每逢一第二首時間點，即令該第二計數器減一，其中，該等第二階層單堆再充電時間點中對應該第二階層之該等記憶單元堆中一首記憶單元堆者為該第二首時間點；且該微控制器是在該第二計數器為零但有對應於該第二階層之存取指令等待於該指令佇列時，於上述第二階層單堆再充電時間點對該第二階層的該等記憶單元堆逐堆進行再充電，使該第二階層未輪到再充電的記憶單元堆得以被存取。 The memory controller as described in item 1 of the patent application scope, in which: The microcontroller also counts the number of times the second level is fully recharged with a second counter; the microcontroller decrements the second counter by one every second time point, wherein the second Among the recharge time points of the hierarchical single stack, one of the memory cell stacks corresponding to the second hierarchical stack is the second first time point; and the microcontroller is in the second counter is zero but there is a correspondence When the access command of the second hierarchy is waiting for the command queue, the memory cells of the second hierarchy are recharged one by one at the time of recharging the single stack of the second hierarchy to make the second hierarchy The memory cell stack that has not been recharged is accessed. 如申請專利範圍第8項所述之記憶體控制器，其中：該微控制器在該第一計數器之計數尚未達一第一上限、且無對應於該第一階層之存取指令等待於該指令佇列時，連續對該第一階層執行一次性再充電；且該微控制器在該第二計數器之計數尚未達一第二上限、且無對應於該第二階層之存取指令等待於該指令佇列時，連續對該第二階層執行一次性再充電。 The memory controller as described in item 8 of the patent application range, wherein: the count of the first counter in the microcontroller has not reached a first upper limit, and no access command corresponding to the first level is waiting for the When the command is queued, it continuously performs a one-time recharge of the first level; and the count of the second counter of the microcontroller has not reached a second upper limit, and no access command corresponding to the second level is waiting for When the command is queued, a one-time recharge is continuously performed on the second level. 一種動態隨機存取記憶體控制方法，包括：提供一指令佇列，使要發送至一動態隨機存取記憶體的操作指令於其中排隊；視該指令佇列的內容，於一監控時間單位內複數個第一階層單堆再充電時間點對該動態隨機存取記憶體的一第一階層的複數個記憶單元堆逐堆進行再充電；以及 視該指令佇列的內容，於該監控時間單位內複數個第二階層單堆再充電時間點對該動態隨機存取記憶體的一第二階層的複數個記憶單元堆逐堆進行再充電，其中：該等第二階層單堆再充電時間點與該等第一階層單堆再充電時間點一對一交錯；以一第一計數器計數對該第一階層完全再充電的次數；計時每逢一第一首時間點，即令該第一計數器減一，其中，該等第一階層單堆再充電時間點中對應該第一階層之該等記憶單元堆中一首記憶單元堆者為該第一首時間點；且在該第一計數器為零但有對應於該第一階層之存取指令等待於該指令佇列時，於上述第一階層單堆再充電時間點對該第一階層的該等記憶單元堆逐堆進行再充電，使該第一階層未輪到再充電的記憶單元堆得以被存取。 A dynamic random access memory control method includes: providing a command queue to queue operation commands to be sent to a dynamic random access memory; depending on the content of the command queue, within a monitoring time unit A plurality of first-level single-stack recharge time points for recharging the first-level multiple-level memory cell stacks of the dynamic random access memory one by one; and Depending on the content of the command queue, the multiple second-level single-stack recharge time points of the dynamic random-access memory are recharged one by one within the monitoring time unit. Among them: the recharging time points of the second layer single stack and the recharging time points of the first layer single stack are interleaved one by one; a first counter is used to count the number of times the first layer is completely recharged; At a first time point, the first counter is decremented by one, wherein the first memory cell stack in the memory cell stacks corresponding to the first hierarchy in the first layer single stack recharge time point is the first counter A first time point; and when the first counter is zero but there is an access command corresponding to the first level waiting for the command queue, the first level is recharged at the first level single stack recharge time point The memory cell stacks are recharged one by one, so that the first level of memory cell stacks that are not recharged can be accessed. 如申請專利範圍第10項所述之動態隨機存取記憶體控制方法，其中：該等第一階層單堆再充電時間點等距相距一第一時間間隔。 The dynamic random access memory control method as described in item 10 of the patent application scope, wherein: the recharging time points of the first-level single stacks are equally spaced apart by a first time interval. 如申請專利範圍第10項所述之動態隨機存取記憶體控制方法，其中：該等第二階層單堆再充電時間點等距相距一第二時間間隔。 The dynamic random access memory control method as described in item 10 of the patent application scope, wherein the recharging time points of the second-level single stacks are equally spaced apart by a second time interval. 如申請專利範圍第10項所述之動態隨機存取記憶體控制方法，其中： 該第一首時間點重疊上述監控時間單位的起始點。 The dynamic random access memory control method as described in item 10 of the patent application scope, in which: The first time point overlaps the starting point of the monitoring time unit. 如申請專利範圍第13項所述之動態隨機存取記憶體控制方法，其中：該等第一階層單堆再充電時間點中對應該第一階層之該等記憶單元堆中一末記憶單元堆者為一第一末時間點；且該監控時間單位中的上述第一末時間點與一下一監控時間單位中的上述第一首時間點相距一第一時間間隔，其中該等第一階層單堆再充電時間點等距相距該第一時間間隔。 The dynamic random access memory control method as described in item 13 of the patent application scope, wherein: the first-level single-stack recharge time point corresponds to the last-level memory cell stack among the first-level memory stacks It is a first last time point; and the first last time point in the monitoring time unit is separated from the first first time point in the next monitoring time unit by a first time interval, wherein the first-level The stack recharge time points are equidistant from the first time interval. 如申請專利範圍第13項所述之動態隨機存取記憶體控制方法，其中：該等第二階層單堆再充電時間點中對應該第二階層之該等記憶單元堆中一首記憶單元堆者為一第二首時間點。 The dynamic random access memory control method as described in item 13 of the patent application scope, wherein: the second-level single-stack recharge time point corresponds to one of the second-level memory cell stacks It is a second time point. 如申請專利範圍第15項所述之動態隨機存取記憶體控制方法，其中：該等第一階層單堆再充電時間點中對應該第一階層之該等記憶單元堆中一次記憶單元堆者為一第一次時間點；且上述第一首時間點與第二首時間點的時間間隔等同上述第二首時間點與第一次時間點的時間間隔。 The dynamic random access memory control method as described in item 15 of the patent application scope, wherein: the first-level single-stack recharge time point corresponds to one of the first-level memory cell stacks It is a first time point; and the time interval between the first first time point and the second first time point is equal to the time interval between the second first time point and the first time point. 如申請專利範圍第10項所述之動態隨機存取記憶體控制方法，更包括：以一第二計數器計數對該第二階層完全再充電的次數； 計時每逢一第二首時間點，即令該第二計數器減一，其中，該等第二階層單堆再充電時間點中對應該第二階層之該等記憶單元堆中一首記憶單元堆者為該第二首時間點；且在該第二計數器為零但有對應於該第二階層之存取指令等待於該指令佇列時，於上述第二階層單堆再充電時間點對該第二階層的該等記憶單元堆逐堆進行再充電，使該第二階層未輪到再充電的記憶單元堆得以被存取。 The dynamic random access memory control method as described in item 10 of the patent application scope further includes: counting the number of times the second level is completely recharged with a second counter; Whenever the second first time point is counted, the second counter is decremented by one. Among these, the second-level single-stack recharge time point corresponds to the first one of the memory cell stacks of the second-level memory cell stacks Is the second first time point; and when the second counter is zero but there is an access command corresponding to the second hierarchy waiting for the command queue, the second counter at the single stack recharge time point The memory cell stacks of the second hierarchy are recharged one by one, so that the memory cell stacks of the second hierarchy that have not been recharged can be accessed. 如申請專利範圍第17項所述之動態隨機存取記憶體控制方法，更包括：在該第一計數器之計數尚未達一第一上限、且無對應於該第一階層之存取指令等待於該指令佇列時，連續對該第一階層執行一次性再充電；且在該第二計數器之計數尚未達一第二上限、且無對應於該第二階層之存取指令等待於該指令佇列時，連續對該第二階層執行一次性再充電。 The dynamic random access memory control method as described in item 17 of the patent application scope further includes: the count of the first counter has not reached a first upper limit, and no access command corresponding to the first level is waiting for When the command queue is executed, the first level is continuously recharged once; and the count of the second counter has not reached a second upper limit, and no access command corresponding to the second level is waiting for the command queue At the time of row, one-time recharge for the second level is performed continuously.
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