TWI680550B - 堆疊式封裝結構及其製法 - Google Patents

堆疊式封裝結構及其製法 Download PDF

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Publication number
TWI680550B
TWI680550B TW108108699A TW108108699A TWI680550B TW I680550 B TWI680550 B TW I680550B TW 108108699 A TW108108699 A TW 108108699A TW 108108699 A TW108108699 A TW 108108699A TW I680550 B TWI680550 B TW I680550B
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Taiwan
Prior art keywords
stacked
package structure
wafer
metal shell
lateral portion
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TW108108699A
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English (en)
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TW202025409A (zh
Inventor
陳明志
Ming-Chih Chen
徐宏欣
Hung-Hsin Hsu
藍源富
Yuan-Fu Lan
許獻文
Hsien-Wen Hsu
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力成科技股份有限公司
Powertech Technology Inc.
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Publication of TWI680550B publication Critical patent/TWI680550B/zh
Publication of TW202025409A publication Critical patent/TW202025409A/zh

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Abstract

本發明係一種堆疊式封裝結構及其製法，該堆疊式封裝結構包含有一金屬殼、一堆疊晶片組、一封膠體及一重佈線層；其中該堆疊晶片組係黏著於該金屬殼內，且該封膠體形成在該金屬殼內並包含該堆疊晶片組，但該堆疊晶片組的金屬墊係自該封膠體外露，至於該重佈線層則形成在該封膠體上，並與該堆疊晶片組之該些金屬墊電性連接；因此，該堆疊式封裝結構包含有金屬殼，可提升散熱效能及增加結構強度。

Description

堆疊式封裝結構及其製法
本發明係關於一種半導體封裝結構及其製法，尤指一種堆疊式封裝結構及其製法。
一種高頻寬記憶體(high bandwidth memory)或混合記憶體模塊(hybrid memory cube)的既有堆疊式封裝結構60如圖5所示，其包含有一有機基板61、一控制晶片62、多個記憶晶片63及一封膠體64；其中該控制晶片62係設置在該有機基板61的一橫向部，且該些記憶晶片63再依序疊設在該控制晶片62上；接著，由該封膠體64形成在該有機基板61之橫向部上並包覆該控制晶片62及該些記憶晶片63於其中。
由於該封膠體64是由聚合物材料製成，上述堆疊式封裝結構60的散熱效果不佳且結構強度也差；此外，該封膠體的一外縱直部沒有覆蓋任金屬層，故該堆疊式封裝結構60也沒有電磁波干擾的遮蔽功能；因此，目前的堆疊式封裝結構60有必提進一步提出改良之。
有鑑於以上既有堆疊式封裝結構的缺陷，本發明主要目的係提供一種新的堆疊式封裝結構及其製法。
欲達上述目的所使用的主要技術手段係令該堆疊式封裝結構包含有：一金屬殼，係包含有一橫向部及多個自該橫向部之內表面一體延伸而出的縱直部；一堆疊晶片組，係包含一具多個金屬墊的主動面，以及一與該主動面相對並黏著於該金屬殼之橫向部的內表面的背面；一封膠體，係包覆該堆疊晶片組；其中該些金屬墊的表面與該金屬殼之各該緃直部之自由端的表面係自該封膠體外露且共平面；以及一重佈線層，係形成於該封膠體上，並電性連接至該堆疊晶片組的該些金屬墊。
綜上所述，本發明的堆疊式封裝結構包含有金屬殼，且該金屬殼的橫向部與緃直部係一體成型，除可提升散熱效率外，亦能增加結構強度；此外，當金屬殼進一步電性連接至系統電源的接地端後，更可為該堆疊式封裝結構提供電磁波干擾的遮蔽功能。
欲達上述目的所使用的主要技術手段係令該堆疊式封裝結構的製法包含有以下步驟：(a)提供一金屬殼；其中該金屬殼包含一橫向部及多個自該橫向部之內表面一體延伸而出的縱直部；(b)將一堆疊晶片組黏著於該橫向部之內表面；其中該堆疊晶片組係具有多個金屬墊的主動面及一與該主動面相對且黏著於該橫向部之內表面的背面；(c)於該金屬殼內形成有一封膠體，以包覆該堆疊晶片組；其中該些金屬墊的表面與該金屬殼之各該緃直部之自由端的表面係自該封膠體外露且共平面；以及 (d)於該封膠體上形成有一重佈線層，以與該堆疊晶片組的金屬墊電性連接。
綜上所述，在本發明堆疊式封裝結構的製法中，該金屬殼及堆疊晶片組是預先準備的，並且在堆疊晶片組黏著於該金屬殼內後，該封膠體可以輕易地成形在該金屬殼內且覆蓋該堆疊晶片組。該重佈線層可形成在該封膠體上，並與該堆疊晶片組的金屬墊電性連接；因此，該金屬殼可以輕易地封裝在堆疊式封裝結構中。本發明的堆疊式封裝結構包含有金屬殼，故可提升散熱效率並增加結構強度；此外，當金屬殼進一步電性連接至系統電源的接地端後，更可為該堆疊式封裝結構提供電磁波干擾的遮蔽功能。
1、1a、1b、1c‧‧‧堆疊式封裝結構
10‧‧‧金屬殼
100‧‧‧黏著層
11‧‧‧橫向部
111‧‧‧內表面
12‧‧‧縱直部
121‧‧‧端
122‧‧‧自由端
20、20a、20b、20c‧‧‧堆疊晶片組
201‧‧‧金屬墊
202‧‧‧背面
21、21a、21b‧‧‧晶片
211‧‧‧矽穿孔
30‧‧‧封膠體
31‧‧‧外表面
40‧‧‧重佈線層
50‧‧‧外接墊層
60‧‧‧堆疊式封裝結構
61‧‧‧有機基板
62‧‧‧控制晶片
63‧‧‧記憶晶片
64‧‧‧封膠體
圖1A：本發明堆疊式封裝結構的第一實施例的剖面圖。
圖1B：本發明堆疊式封裝結構的第二實施例的剖面圖。
圖2A至圖2F：本發明對應圖1A堆疊式封裝結構之製法中不同步驟的剖面圖。
圖3A：本發明堆疊式封裝結構的第三實施例的剖面圖。
圖3B：本發明堆疊式封裝結構的第四實施例的剖面圖。
圖4A至圖4F：本發明對應圖3A堆疊式封裝結構之製法中不同步驟的剖面圖。
圖5：既有堆疊式封裝結構的剖面圖。
本發明提供一種堆疊式封裝結構及其製法，以下配合數個實施例及圖式詳加說明本發明的技術內容。
請參閱圖1所示，本發明堆疊式封裝結構1的第一實施例，其包含有一金屬殼10、一堆疊晶片組20、一封膠體30、一重佈線層40及多個外接墊50。
上述金屬殼10具有一橫向部11及多個自該橫向部11之內表面111一體延伸而出的縱直部12；在本實施例中，該金屬殼10是以一金屬塊蝕刻而成，故各縱直部12靠近該橫向部內表面111的一端121之寬度大於各縱直部12遠離該橫向部內表面11的一自由端122之寬度。
上述橫向部11的內表面111上形成有一黏著層100，供上述堆疊晶片組20黏著於該金屬殼10上。該堆疊晶片組20包含有一主動面及一相對該該主動面的背面202；其中該主動面包含有多個金屬墊201，而該背面202係黏著於該內表面111上的黏著層100。在本實施例中，該堆疊晶片組20包含有多個疊設在相互頂面的晶片21a、21，且相鄰晶片21與晶片20a之間保持一間隔d。在其他實施例中，黏著在黏著層100的晶片21a不具有矽穿孔，且堆疊在該晶片21a上的晶片21數量可以一個或多個。在第一實施例中，至少一個晶片21堆疊在該晶片21a上，且該至少一晶片21具有多個矽穿孔211。再如圖1B所示，本發明堆疊式封裝結構1a的第二實施例，其堆疊晶片組20a包含有二個晶片21、21b，並堆疊在該晶片21a上；其中該二晶片21、21b分別具有多個矽穿孔211，而遠離晶片21a的晶片21b可以是控制晶片，而其餘晶片21及晶片21a可以是記憶體晶片。
上述封膠體30係形成在該金屬殼10內，以包覆該堆疊晶片組20。在本實施例中，該封膠體30的外表面31、該堆疊晶片組20的金屬墊201的表面、該金屬殼10之各緃直部12的自由端122的表面係共平面。該封膠體30包 覆該堆疊晶片組20，但各金屬墊201的表面及各自由端122的表面係外露於該封膠體30外。
上述重佈線層40形成在該封膠體30的外表面31、該堆疊晶片組20之金屬墊201的表面與該些自由端122的表面上。當至少一自由端122透過該重佈線層40電性連接至一系統電源的接地端，該金屬殼10即提供電磁波干擾的遮蔽功能。
上述外接墊50係形成在該重佈線層40上；在本實施例中，該些外接墊50可以是錫球及其類似元件。
以下進一步說明圖1A所示之堆疊式封裝結構1的製法。
首先請參閱圖2A，預先準備一金屬塊10’，再如圖2B所示，進一步蝕刻該金屬塊10’以形成一金屬殼10，如此該金屬殼10即具有一體成型的一橫向部11及多個自該橫向部11內表面111一體延伸而出的緃直部12。在本實施例中，該金屬殼10為四方形，而在另一實施例中，該金屬殼10可以具有四支緃長部12，但不以此為限。又在一實施例中，該金屬殼10的緃長部12數量可以大於或少於四支。
如圖2C所示，將一黏著層100形成於該金屬殼10之橫向部11的內表面111上，再將一堆疊晶片組20設置在該黏著層100上，以黏著於該橫向部11的內表面111上。該堆疊晶片組20可包含有多個晶片21、21a，且在相鄰的晶片之間保持一間隔d。
如圖2D所示，將該金屬殼10連同該堆疊晶片20置放於一灌膠模具內，之後注入液態膠體；接著，待液態膠體凝固後即形成一封膠體30，並包覆該堆疊晶片組20，但該堆疊晶片組20的多個金屬墊201的表面係外露在封膠體30外。在另一實施例中，可藉由研磨該封膠層30直到金屬墊201外露而達成之。在本實施中，晶片21與晶片21a之間的間隔d可一併被液態膠體填充，因此 該封膠體30與晶片21、21a之間間隔d內的膠體22可在同一製程步驟完成。本實施例中，該封膠體30可進一步包覆該些縱直部12，但各緃直部12的自由端122係外露於該封膠體30之外。在本實施例中，該封膠體30的外表面31、該堆疊晶片組20的金屬墊201表面、該金屬殼10之各緃直部12的自由端122表面係共平面。
如圖2E所示，於該封膠層30的外表面31進一步形成一重佈線層40，該重佈線層40係電性連接至該堆疊晶片組20的金屬墊201；此外，該重佈線層40也可以進一步電性連接至該緃直部12的自由端122。
如圖2F所示，於重佈線層40上形成多個外接墊50；在本實施例中，該些外接墊50可以是錫球或導電凸塊。
如圖3A所示，本發明堆疊式封裝結構1b的第三實施例，其與圖1A所示的堆疊式封裝結構1大致相同，惟本實施例的堆疊晶片組20b進一步包含一絕緣層22’，該絕緣層22’係形成在間隔d內。該絕緣層22’的材料可以不同於封膠體30，且可以是異方性導電膠(anisotropic conductive film)、底膠(underfill)材料或類似材料。
如圖3B所示，本發明堆疊式封裝結構1c的第四實施例，其與圖1B所示的堆疊式封裝結構1a大致相同，惟本實施例的堆疊晶片組20c進一步包含多道絕緣層22’，各道絕緣層22’係形成在對應的間隔d內。該絕緣層22’的材料可以不同於封膠體30，且可以是異方性導電膠(anisotropic conductive film)、底膠(underfill)材料或類似材料。
以下進一步說明圖3A所示之堆疊式封裝結構1的製法。
圖4A及圖4B所示為一金屬殼10的製程步驟，與圖2A及圖2B相同，故不再贅述。
如圖4C所示，將一黏著層100形成於該金屬殼10之橫向部11的內表面111上，再將一堆疊晶片組20b設置在該黏著層100上，以黏著於該橫向部11的內表面111上。在本實施例中，該堆疊晶片組20b可進一步包含有一絕緣層22’，該絕緣層22’形成在晶片21與晶片21a之間的間隔d中。
如圖4D所示，將該金屬殼10連同該堆疊晶片20置放於一灌膠模具內，之後注入液態膠體；接著，待液態膠體凝固後即形成一封膠體30，並包覆該堆疊晶片組20b，但該堆疊晶片組20b的多個金屬墊201的表面係外露在封膠體30外。在另一實施例中，可藉由研磨該封膠層30直到金屬墊201外露。在本實施中，該封膠體30可進一步包覆該些縱直部12，但各緃直部12的自由端122係外露於該封膠體30之外。在本實施例中，該封膠體30的外表面31、該堆疊晶片組20b的金屬墊201表面、該金屬殼10之各緃直部12的自由端122表面係共平面。
如圖4E所示，於該封膠層30的外表面31進一步形成一重佈線層40，該重佈線層40係電性連接至該堆疊晶片組20的金屬墊201；此外，該重佈線層40也可以進一步電性連接至該緃直部12的自由端122。
如圖4F所示，於重佈線層40上形成多個外接墊50；在本實施例中，該些外接墊50可以是錫球或導電凸塊。
綜上所述，在本發明堆疊式封裝結構的製法中，該金屬殼及堆疊晶片組是預先準備，並且在堆疊晶片組黏著於該金屬殼內後，該封膠體可以輕易地成形在該金屬殼內且覆蓋該堆疊晶片組。該重佈線層可形成在該封膠體上，並與該堆疊晶片組的金屬墊電性連接；因此，該金屬殼可以輕易地封裝在堆疊式封裝結構中。本發明的堆疊式封裝結構包含有金屬殼，故可提升散熱效率並增加結構強度；此外，當金屬殼進一步電性連接至系統電源的接地端後，更可為該堆疊式封裝結構提供電磁波干擾的遮蔽功能。
以上所述僅是本發明的實施例而已，並非對本發明做任何形式上的限制，雖然本發明已以實施例揭露如上，然而並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明技術方案的範圍內，當可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例，但凡是未脫離本發明技術方案的內容，依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾，均仍屬於本發明技術方案的範圍內。

Claims (17)

  1. 一種堆疊式封裝結構，包括：一金屬殼，係包含有一橫向部及多個自該橫向部之內表面一體延伸而出的縱直部；一堆疊晶片組，係包含：一主動面，係包含多個金屬墊；以及一背面，係與該主動面相對，並黏著於該金屬殼之橫向部的內表面；一封膠體，係包覆該堆疊晶片組；其中該些金屬墊的表面與該金屬殼之各該緃直部之自由端的表面係自該封膠體外露且共平面；以及一重佈線層，係形成於該封膠體上，並電性連接至該堆疊晶片組的該些金屬墊。
  2. 如請求項1所述之堆疊式封裝結構，其中各該縱直部靠近該橫向部之內表面的一端的寬度大於各該縱直部遠離該橫向部之內表面的一自由端之寬度。
  3. 如請求項1所述之堆疊式封裝結構，其中該堆疊晶片組包含多個疊設在相互頂面的晶片，且相鄰晶片之間保持一間隔；其中：該堆疊晶片組的其中一晶片係黏著於該橫向部之內表面，且該晶片作為第一晶片且無矽穿孔；以及堆疊在該第一晶片上的各晶片具有矽穿孔。
  4. 如請求項3所述之堆疊式封裝結構，其中該堆疊晶片組係進一步包含至少一絕緣層，該至少一絕緣層係形成在對應間隔中。
  5. 如請求項4所述之堆疊式封裝結構，其中該絕緣層材料為異方性導電膠、底膠或封膠體材料。
  6. 如請求項4所述之堆疊式封裝結構，其中於該堆疊晶片中，遠離該第一晶片的晶片為一控制晶片，其餘晶片為記憶體晶片。
  7. 如請求項1所述之堆疊式封裝結構，其中該重佈線層係進一步電性連接該金屬殼之該縱直部之自由端。
  8. 如請求項1所述之堆疊式封裝結構，其中於該堆疊晶片組之背面與該橫向部之內表面之間進一步形成有一黏著層。
  9. 一種堆疊式封裝結構的製法，包括以下步驟：(a)提供一金屬殼；其中該金屬殼包含一橫向部及多個自該橫向部之內表面一體延伸而出的縱直部；(b)將一堆疊晶片組黏著於該橫向部之內表面；其中該堆疊晶片組係具有多個金屬墊的主動面及一與該主動面相對且黏著於該橫向部之內表面的背面；(c)於該金屬殼內形成有一封膠體，以包覆該堆疊晶片組；其中該些金屬墊的表面與該金屬殼之各該緃直部之自由端的表面係自該封膠體外露且共平面；以及(d)於該封膠體上形成有一重佈線層，以與該堆疊晶片組的金屬墊電性連接。
  10. 如請求項9所述之堆疊式封裝結構的製法，其中於步驟(a)中，該金屬殼係藉由蝕刻一金屬塊而成，且該金屬殼的各該縱直部靠近該橫向部之內表面的一端的寬度大於各該縱直部遠離該橫向部之內表面的一自由端之寬度。
  11. 如請求項9所述之堆疊式封裝結構的製法，其中步驟(b)係進一步於該橫向部之內表面與該堆疊晶片組之背面之間形成有一黏著層。
  12. 如請求項9所述之堆疊式封裝結構的製法，其中於步驟(b)中，該堆疊晶片組包含多個疊設在相互頂面的晶片，且相鄰晶片之間保持一間隔；其中：該堆疊晶片組的其中一晶片係黏著於該橫向部之內表面，且該晶片作為第一晶片且無矽穿孔；以及堆疊在該第一晶片上的各晶片具有矽穿孔。
  13. 如請求項12所述之堆疊式封裝結構的製法，其中於步驟(c)中，該封膠體係形成於該金屬殼內與各該至少一間隔中。
  14. 如請求項12所述之堆疊式封裝結構的製法，其中：於步驟(b)中，各該間隔係填充有一絕緣材料；以及於步驟(c)中，該封膠體係形成在該金屬殼內。
  15. 如請求項14所述之堆疊式封裝結構的製法，其中該絕緣材料為異方性導電膠或底膠。
  16. 如請求項9至15中任一項所述之堆疊式封裝結構的製法，係進一步包含步驟(e)；其中步驟(e)係形成多個錫球於該重佈線層上。
  17. 如請求項9至15中任一項所述之堆疊式封裝結構的製法，其中於步驟(d)中，該重佈線層係進一步電性連接該金屬殼之該縱直部之自由端。
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