TWI679628B - Display apparatus and method of driving light emitting block thereof - Google Patents
Display apparatus and method of driving light emitting block thereof Download PDFInfo
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- TWI679628B TWI679628B TW107137789A TW107137789A TWI679628B TW I679628 B TWI679628 B TW I679628B TW 107137789 A TW107137789 A TW 107137789A TW 107137789 A TW107137789 A TW 107137789A TW I679628 B TWI679628 B TW I679628B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3406—Control of illumination source
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
一種顯示裝置及其發光區塊的驅動方法。顯示裝置包括多個發光區塊。各個發光區塊包括栓鎖電路、選擇電路、電壓輸出電路、資料電晶體、驅動電晶體、電容及發光二極體。栓鎖電路栓鎖與資料電壓對應的多個數位控制信號。選擇電路依據經栓鎖的數位控制信號提供多個選擇信號。電壓輸出電路依據選擇信號提供驅動電壓,其中反應資料電壓的下降,驅動電壓也隨著下降。資料電晶體接收資料電壓及位移信號。驅動電晶體耦接於資料電晶體、驅動電壓及發光二極體之間。電容耦接於驅動電晶體的控制端及第二端之間。A display device and a driving method of a light emitting block thereof. The display device includes a plurality of light-emitting blocks. Each light-emitting block includes a latch circuit, a selection circuit, a voltage output circuit, a data transistor, a driving transistor, a capacitor, and a light-emitting diode. The latch circuit latches a plurality of digital control signals corresponding to the data voltage. The selection circuit provides a plurality of selection signals according to the latched digital control signals. The voltage output circuit provides a driving voltage according to a selection signal, in which the voltage of the reaction data decreases and the driving voltage also decreases. The data transistor receives data voltage and displacement signals. The driving transistor is coupled between the data transistor, the driving voltage and the light emitting diode. The capacitor is coupled between the control terminal and the second terminal of the driving transistor.
Description
本發明是有關於一種顯示裝置,且特別是有關於一種顯示裝置及其發光區塊的驅動方法。 The present invention relates to a display device, and more particularly, to a display device and a method for driving a light emitting block thereof.
在顯示技術中,發光二極體不斷的微小化,以提供更多的應用。在顯示裝置中,發光二極體可應用為提供背光的背光模組,或者可直接應用為顯示影像的顯示介面。然而,為了使背光模組或顯示介面具有更高的通用性,降低背光模組或顯示介面的功率消耗則是一個重要的課題。 In display technology, light-emitting diodes are continuously miniaturized to provide more applications. In the display device, the light emitting diode may be applied as a backlight module providing a backlight, or may be directly applied as a display interface for displaying an image. However, in order to make the backlight module or display interface more versatile, reducing the power consumption of the backlight module or display interface is an important issue.
本發明提供一種顯示裝置及其發光區塊的驅動方法,可節省功率消耗,但仍保持發光二極體的期望發光亮度。 The invention provides a display device and a driving method of a light emitting block thereof, which can save power consumption, but still maintain a desired light emitting brightness of a light emitting diode.
本發明的顯示裝置,包括多個發光區塊。各個發光區塊包括栓鎖電路、選擇電路、電壓輸出電路、資料電晶體、驅動電晶體、電容及發光二極體。栓鎖電路接收與資料電壓對應的多個 數位控制信號及位移信號,並依據位移信號栓鎖這些數位控制信號。選擇電路耦接栓鎖電路,以接收經栓鎖的這些數位控制信號,並且提供多個選擇信號,其中選擇電路依據經栓鎖的這些數位控制信號致能這些選擇信號的其中之一。電壓輸出電路耦接選擇電路,以接收這些選擇信號,並且提供驅動電壓,其中驅動電壓受控於這些選擇信號,並且反應資料電壓的下降,驅動電壓也隨著下降。資料電晶體具有接收資料電壓的第一端、接收位移信號的控制端及第二端。驅動電晶體具有接收驅動電壓的第一端、耦接資料電晶體的第二端的控制端及第二端。電容耦接於驅動電晶體的控制端及驅動電晶體的第二端之間。發光二極體耦接於驅動電晶體的第二端與系統低電壓之間。 The display device of the present invention includes a plurality of light-emitting blocks. Each light-emitting block includes a latch circuit, a selection circuit, a voltage output circuit, a data transistor, a driving transistor, a capacitor, and a light-emitting diode. The latch circuit receives a plurality of data corresponding to the data voltage. Digital control signals and displacement signals, and latch these digital control signals according to the displacement signals. The selection circuit is coupled to the latch circuit to receive the latched digital control signals and provide a plurality of selection signals. The selection circuit enables one of the selection signals according to the latched digital control signals. The voltage output circuit is coupled to the selection circuit to receive these selection signals and provide a driving voltage, wherein the driving voltage is controlled by these selection signals, and the driving voltage also decreases as the data voltage decreases. The data transistor has a first terminal for receiving a data voltage, a control terminal for receiving a displacement signal, and a second terminal. The driving transistor has a first terminal receiving a driving voltage, a control terminal coupled to a second terminal of the data transistor, and a second terminal. The capacitor is coupled between the control terminal of the driving transistor and the second terminal of the driving transistor. The light emitting diode is coupled between the second terminal of the driving transistor and the system low voltage.
本發明的驅動方法,用以驅動一顯示裝置的多個發光區塊,這些發光區塊個別具有一發光二極體,並且驅動方法包括下列步驟。接收資料電壓以決定由驅動電壓流經發光二極體的發光電流。接收與資料電壓對應的多個數位控制信號,以調整驅動電壓,其中反應資料電壓的下降,驅動電壓也隨著下降。 The driving method of the present invention is used to drive a plurality of light-emitting blocks of a display device. Each of these light-emitting blocks has a light-emitting diode, and the driving method includes the following steps. The data voltage is received to determine the light emitting current flowing through the light emitting diode by the driving voltage. A plurality of digital control signals corresponding to the data voltage are received to adjust the driving voltage. The driving voltage is also reflected as the data voltage decreases.
基於上述,本發明實施例的顯示裝置及其發光區塊的驅動方法,其接收與資料電壓對應的多個數位控制信號,以調整驅動電壓,並且反應資料電壓的下降,驅動電壓也隨著下降。藉此,當發光區塊的發光灰階值越低,可節省更多功率,但仍保持發光二極體的發光亮度。 Based on the above, the display device and the driving method of the light-emitting block of the embodiment of the present invention receive a plurality of digital control signals corresponding to the data voltage to adjust the driving voltage, and the driving voltage also decreases as the data voltage decreases . Therefore, when the light-emitting gray-scale value of the light-emitting block is lower, more power can be saved, but the light-emitting brightness of the light-emitting diode is still maintained.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉 實施例,並配合所附圖式作詳細說明如下。 In order to make the above features and advantages of the present invention more comprehensible, the following enumerated The embodiments will be described in detail with the accompanying drawings.
10、20‧‧‧顯示裝置 10, 20‧‧‧ display device
11‧‧‧位移控制電路 11‧‧‧Displacement control circuit
13‧‧‧資料提供電路 13‧‧‧ data supply circuit
15‧‧‧發光區塊 15‧‧‧light-emitting block
21‧‧‧顯示面板 21‧‧‧Display Panel
100、15‧‧‧發光區塊 100, 15‧‧‧ light-emitting blocks
110‧‧‧栓鎖電路 110‧‧‧ latch circuit
111、113、115‧‧‧栓鎖單元 111, 113, 115‧‧‧
120‧‧‧選擇電路 120‧‧‧Selection circuit
130‧‧‧電壓輸出電路 130‧‧‧Voltage output circuit
210‧‧‧位移暫存器 210‧‧‧Displacement register
220‧‧‧輸入暫存器 220‧‧‧input register
230‧‧‧資料栓鎖器 230‧‧‧Data latch
240‧‧‧準位移位器 240‧‧‧ quasi-displacement device
250‧‧‧數位類比轉換器 250‧‧‧ Digital Analog Converter
260‧‧‧緩衝器 260‧‧‧Buffer
AND1‧‧‧第一及閘 AND1‧‧‧First and Gate
AND2‧‧‧第二及閘 AND2‧‧‧Second and Gate
C1‧‧‧電容 C1‧‧‧capacitor
CLK‧‧‧時脈信號 CLK‧‧‧clock signal
DLX‧‧‧顯示資料 DLX‧‧‧Display Information
Id‧‧‧發光電流 Id‧‧‧ Luminous current
INT‧‧‧第一反相器 INT‧‧‧First inverter
LED1‧‧‧發光二極體 LED1‧‧‧light-emitting diode
LEN‧‧‧栓鎖致能信號 LEN‧‧‧ Latch enable signal
LHS‧‧‧水平信號線 LHS‧‧‧Horizontal Signal Cable
M0~M7‧‧‧開關電晶體 M0 ~ M7‧‧‧‧Switching transistor
NOR1‧‧‧第一反或閘 NOR1‧‧‧First reverse OR gate
NOR2‧‧‧第二反或閘 NOR2‧‧‧Second reverse OR gate
PX‧‧‧液晶畫素 PX‧‧‧LCD Pixel
S0~S2、~‧‧‧信號 S0 ~ S2 ~ ‧‧‧signal
S111~S116、S120、S130‧‧‧曲線 S111 ~ S116, S120, S130‧‧‧curve
Sdit、Sdit0~Sdit2‧‧‧數位控制信號 Sdit, Sdit0 ~ Sdit2‧‧‧ Digital control signal
SET‧‧‧設定信號 SET‧‧‧Set signal
SR_1~SR_3、SR_n‧‧‧位移信號 SR_1 ~ SR_3, SR_n‧‧‧shift signal
STR‧‧‧觸發信號 STR‧‧‧Trigger signal
TD1‧‧‧資料電晶體 TD1‧‧‧Data Transistor
TD2‧‧‧驅動電晶體 TD2‧‧‧Drive Transistor
TG11~TG14、TG21~TG28、TG31~TG38、TG41~TG48‧‧‧傳輸閘 TG11 ~ TG14, TG21 ~ TG28, TG31 ~ TG38, TG41 ~ TG48‧‧‧Transmission gate
VD1‧‧‧驅動電壓 VD1‧‧‧Drive voltage
VDATA‧‧‧資料電壓 VDATA‧‧‧Data voltage
VDD‧‧‧系統高電壓 VDD‧‧‧System high voltage
VDD_max‧‧‧最大驅動電壓準位 VDD_max‧‧‧Maximum driving voltage level
VDD0~VDD7‧‧‧驅動準位 VDD0 ~ VDD7‧‧‧Drive level
VDX‧‧‧類比驅動電壓 VDX‧‧‧ Analog Drive Voltage
VG1、VS1‧‧‧電壓 VG1, VS1‧‧‧‧Voltage
VLS‧‧‧垂直信號線 VLS‧‧‧Vertical Signal Cable
Vref‧‧‧參考電壓 Vref‧‧‧Reference voltage
VSS‧‧‧系統低電壓 VSS‧‧‧System Low Voltage
VTm‧‧‧更動臨界電壓 VTm‧‧‧ Changed threshold voltage
XDB‧‧‧藍色顯示資料 XDB‧‧‧ Blue display data
XDG‧‧‧綠色顯示資料 XDG‧‧‧ green display data
XDR‧‧‧紅色顯示資料 XDR‧‧‧red display data
Y0~Y7‧‧‧選擇信號 Y0 ~ Y7‧‧‧Selection signal
S710、S720‧‧‧步驟 S710, S720‧‧‧ steps
圖1A為依據本發明一實施例的發光區塊的系統示意圖。 FIG. 1A is a system schematic diagram of a light-emitting block according to an embodiment of the present invention.
圖1B為依據本發明一實施例的發光區塊的驅動電晶體的特性示意圖。 FIG. 1B is a characteristic diagram of a driving transistor of a light-emitting block according to an embodiment of the present invention.
圖2為依據本發明一實施例的發光區塊的電路示意圖。 FIG. 2 is a schematic circuit diagram of a light-emitting block according to an embodiment of the present invention.
圖3A為依據本發明一實施例的驅動電壓隨資料電壓變動的模擬示意圖。 FIG. 3A is a simulation diagram of a driving voltage changing with a data voltage according to an embodiment of the present invention.
圖3B為依據本發明一實施例的驅動電壓為固定電壓的模擬示意圖。 FIG. 3B is a simulation diagram of the driving voltage being a fixed voltage according to an embodiment of the present invention.
圖4為依據本發明一實施例的顯示裝置的系統示意圖。 FIG. 4 is a system diagram of a display device according to an embodiment of the invention.
圖5為依據本發明一實施例的資料提供電路的系統示意圖。 FIG. 5 is a system schematic diagram of a data providing circuit according to an embodiment of the present invention.
圖6為依據本發明另一實施例的顯示裝置的系統示意圖。 FIG. 6 is a system diagram of a display device according to another embodiment of the present invention.
圖7為依據本發明一實施例的顯示裝置的發光區塊的驅動方法的流程圖。 FIG. 7 is a flowchart of a driving method of a light emitting block of a display device according to an embodiment of the invention.
除非另有定義,本文使用的所有術語(包括技術和科學術語)具有與本發明所屬領域的普通技術人員通常理解的相同的含義。將進一步理解的是,諸如在通常使用的字典中定義的那些術 語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的含義,並且將不被解釋為理想化的或過度正式的意義,除非本文中明確地這樣定義。 Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that, such as those defined in commonly used dictionaries Terms should be construed to have meanings consistent with their meanings in the context of the related art and the present invention, and will not be construed as idealized or overly formal meanings unless explicitly defined as such herein.
應當理解,儘管術語”第一”、”第二”、”第三”等在本文中可以用於描述各種元件、部件、區域、層及/或部分,但是這些元件、部件、區域、及/或部分不應受這些術語的限制。這些術語僅用於將一個元件、部件、區域、層或部分與另一個元件、部件、區域、層或部分區分開。因此,下面討論的”第一元件”、”部件”、”區域”、”層”或”部分”可以被稱為第二元件、部件、區域、層或部分而不脫離本文的教導。 It should be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, and / or sections, and / Or in part should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer," or "portion" discussed below may be referred to as a second element, component, region, layer, or section without departing from the teachings herein.
這裡使用的術語僅僅是為了描述特定實施例的目的,而不是限制性的。如本文所使用的,除非內容清楚地指示,否則單數形式”一”、”一個”和”該”旨在包括複數形式,包括”至少一個”。”或”表示”及/或”。如本文所使用的,術語”及/或”包括一個或多個相關所列項目的任何和所有組合。還應當理解,當在本說明書中使用時,術語”包括”及/或”包括”指定所述特徵、區域、整體、步驟、操作、元件的存在及/或部件,但不排除一個或多個其它特徵、區域整體、步驟、操作、元件、部件及/或其組合的存在或添加。 The terminology used herein is for the purpose of describing particular embodiments only and is not limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one", unless the content clearly indicates otherwise. "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "including" and / or "including" designate the stated features, regions, wholes, steps, operations, presence of elements and / or components, but do not exclude one or more The presence or addition of other features, areas as a whole, steps, operations, elements, components, and / or combinations thereof.
圖1A為依據本發明一實施例的發光區塊的系統示意圖。請參照圖1A,在本實施例中,發光區塊100是配置於顯示裝置中,並且可以作為顯示面板的畫素或背光模組的發光電路。發光區塊100至少包括栓鎖電路110、選擇電路120、電壓輸出電路 130、資料電晶體TD1、驅動電晶體TD2、電容C1及發光二極體LED1。其中,發光二極體LED1例如為次毫米發光二極體,但本發明實施例不以此為限。 FIG. 1A is a system schematic diagram of a light-emitting block according to an embodiment of the present invention. Please refer to FIG. 1A. In this embodiment, the light-emitting block 100 is a light-emitting circuit configured in a display device and can be used as a pixel of a display panel or a backlight module. The light-emitting block 100 includes at least a latch circuit 110, a selection circuit 120, and a voltage output circuit 130. The data transistor TD1, the driving transistor TD2, the capacitor C1, and the light-emitting diode LED1. The light-emitting diode LED1 is, for example, a sub-millimeter light-emitting diode, but the embodiment of the present invention is not limited thereto.
栓鎖電路110接收與資料電壓VDATA對應的多個數位控制信號Sdit及位移信號SR_n,並依據位移信號SR_n栓鎖這些數位控制信號Sdit,其中n為正整數。選擇電路120耦接栓鎖電路110,以接收經栓鎖的數位控制信號(如信號S0~S2),並且提供多個選擇信號(如Y0~Y2),其中選擇電路120依據經栓鎖的數位控制信號(如信號S0~S2)致能這些選擇信號(如信號Y0~Y2)的其中之一。 The latch circuit 110 receives a plurality of digital control signals Sdit and displacement signals SR_n corresponding to the data voltage VDATA, and latches the digital control signals Sdit according to the displacement signal SR_n, where n is a positive integer. The selection circuit 120 is coupled to the latch circuit 110 to receive the latched digital control signals (such as signals S0 ~ S2) and provide multiple selection signals (such as Y0 ~ Y2). The selection circuit 120 is based on the latched digital signals. Control signals (such as signals S0 ~ S2) enable one of these selection signals (such as signals Y0 ~ Y2).
電壓輸出電路130耦接選擇電路120,以接收這些選擇信號(如Y0~Y2),並且提供驅動電壓VD1。資料電晶體TD1具有接收資料電壓VDTAT的第一端、接收位移信號SR_n的控制端及第二端。驅動電晶體TD2具有接收驅動電壓VD1的第一端、耦接資料電晶體TD1的第二端的控制端及第二端。電容C1耦接於驅動電晶體TD2的控制端及驅動電晶體TD2的第二端之間。發光二極體LED1耦接於驅動電晶體TD2的第二端與系統低電壓VSS之間。 The voltage output circuit 130 is coupled to the selection circuit 120 to receive these selection signals (such as Y0 ~ Y2) and provide a driving voltage VD1. The data transistor TD1 has a first terminal receiving a data voltage VDTAT, a control terminal receiving a displacement signal SR_n, and a second terminal. The driving transistor TD2 has a first terminal receiving the driving voltage VD1, a control terminal coupled to the second terminal of the data transistor TD1, and a second terminal. The capacitor C1 is coupled between the control terminal of the driving transistor TD2 and the second terminal of the driving transistor TD2. The light emitting diode LED1 is coupled between the second terminal of the driving transistor TD2 and the system low voltage VSS.
在本實施例中,驅動電壓VD1受控於選擇信號(如Y0~Y2)而決定其電壓準位,亦即反應資料電壓VDATA的下降,驅動電壓VD1也隨著下降亦即。換言之,在流經發光二極體LED1的發光電流Id維持不變的情況下,資料電壓VDATA越低(可視 為對應的灰階值越低),驅動電壓VD1越低;資料電壓VDATA越高(可視為對應的灰階值越高),驅動電壓VD1越高。 In this embodiment, the driving voltage VD1 is controlled by a selection signal (such as Y0 ~ Y2) to determine its voltage level, that is, the data voltage VDATA is reduced, and the driving voltage VD1 is also decreased as it is. In other words, when the light-emitting current Id flowing through the light-emitting diode LED1 remains unchanged, the lower the data voltage VDATA (visible The lower the corresponding grayscale value), the lower the driving voltage VD1; the higher the data voltage VDATA (which can be considered as the corresponding higher grayscale value), the higher the driving voltage VD1.
由於發光電流Id不變,因此發光二極體LED1的發光亮度不受影響,但是隨著驅動電壓VD1的下降,發光區塊100的整體電力消耗會降低。 Since the light-emitting current Id is unchanged, the light-emitting brightness of the light-emitting diode LED1 is not affected, but as the driving voltage VD1 decreases, the overall power consumption of the light-emitting block 100 will decrease.
圖1B為依據本發明一實施例的發光區塊的驅動電晶體的特性示意圖。請參照圖1A及圖1B,其中曲線S120區隔驅動電晶體TD2的線性區及飽和區,並且驅動電晶體TD2主要是操作於飽和區。曲線S111~S116繪示各個資料電壓VDATA(亦即各個灰階值)隨著驅動電壓VD1變化的曲線,其中曲線S111例如對應灰階值128,曲線S116例如對應灰階值255。一般而言,驅動電壓VD1是為固定值,並且為了適用於所有的灰階值(如曲線S111~S116)所示,驅動電壓VD1會設定為最大驅動電壓準位VDD_max。 FIG. 1B is a characteristic diagram of a driving transistor of a light-emitting block according to an embodiment of the present invention. Please refer to FIG. 1A and FIG. 1B, where the curve S120 separates the linear region and the saturation region of the driving transistor TD2, and the driving transistor TD2 mainly operates in the saturation region. Curves S111 to S116 show the curves of the data voltage VDATA (ie, each gray level value) as a function of the driving voltage VD1. The curve S111 corresponds to a gray level value of 128, and the curve S116 corresponds to a gray level value of 255, for example. Generally speaking, the driving voltage VD1 is a fixed value, and in order to be applicable to all grayscale values (such as the curves S111 to S116), the driving voltage VD1 is set to the maximum driving voltage level VDD_max.
在本實施例中,反應資料電壓VDATA(亦即灰階值)的下降,驅動電壓VD1也隨著下降至大於等於使流經發光二極體LED1的發光電流Id維持不變的最小驅動電壓準位(亦即對應的灰階值曲線S112~S116與曲線S120的交錯點)。亦即,當資料電壓VDATA(亦即灰階值)不為最大值時,驅動電壓VD1可隨著對應的灰階值曲線(如S112~S116)而設定為曲線S120與最大驅動電壓準位VDD_max之間,並且灰階值越高則驅動電壓VD1可不變或越高。 In this embodiment, the response data voltage VDATA (ie, the gray level value) decreases, and the driving voltage VD1 also decreases to a minimum driving voltage level that keeps the light emitting current Id flowing through the light emitting diode LED1 constant. Bit (that is, the intersecting point of the corresponding grayscale value curves S112-S116 and curve S120). That is, when the data voltage VDATA (ie, the gray level value) is not the maximum value, the driving voltage VD1 can be set to the curve S120 and the maximum driving voltage level VDD_max with the corresponding gray level value curve (such as S112 ~ S116) The higher the gray level value, the higher the driving voltage VD1 may be.
進一步來說,如曲線S130所示,為了避免因驅動電晶體TD2的特性問題使得驅動電壓VD1跳到曲線S120左側,亦即流經發光二極體LED1的發光電流Id過度降低,而影響了發光二極體LED1的發光亮度,可以反應資料電壓VDATA的下降,驅動電壓VD1也隨著下降至最小驅動電壓準位(亦即對應的灰階值曲線S112~S116與曲線S120的交錯點)加上增量電壓ΔV(等同於將曲線S120向右偏移增量電壓ΔV)。 Further, as shown by the curve S130, in order to avoid the driving voltage VD1 jumping to the left of the curve S120 due to the characteristics of the driving transistor TD2, that is, the light emitting current Id flowing through the light emitting diode LED1 is excessively reduced, which affects the light emission. The luminous brightness of the diode LED1 can reflect the decrease of the data voltage VDATA, and the driving voltage VD1 also decreases to the minimum driving voltage level (that is, the intersection point of the corresponding grayscale value curves S112 ~ S116 and curve S120) plus Incremental voltage ΔV (equivalent to shifting curve S120 to the right by incremental voltage ΔV).
此時,由於驅動電壓VD1最多設定為最大驅動電壓準位VDD_max,因此除了最大灰階值外,部份灰階值的驅動電壓VD1是設定為最大驅動電壓準位VDD_max,而其他灰階值的驅動電壓VD1是設定小於最大驅動電壓準位VDD_max。舉例來說,當資料電壓VDATA位於更動臨界電壓VTm與最大灰階電壓(亦即對應曲線S111)之間時,驅動電壓VD1維持於最大驅動電壓準位VDD_max。並且,當增量電壓ΔV越大,更動臨界電壓VTm越低。 At this time, since the driving voltage VD1 is set to the maximum driving voltage level VDD_max at most, in addition to the maximum gray level value, the driving voltage VD1 of some gray levels is set to the maximum driving voltage level VDD_max, and other gray levels The driving voltage VD1 is set to be less than the maximum driving voltage level VDD_max. For example, when the data voltage VDATA is between the change threshold voltage VTm and the maximum grayscale voltage (that is, the corresponding curve S111), the driving voltage VD1 is maintained at the maximum driving voltage level VDD_max. And, the larger the incremental voltage ΔV, the lower the change threshold voltage VTm.
圖2為依據本發明一實施例的發光區塊的電路示意圖。請參照圖1A及圖2,在本實施例中,數位控制信號Sdit的數目以3為例(以數位控制信號Sdit0~Sdit2為例),亦即數位控制信號Sdit為3位元的信號,其中數位控制信號Sdit的數目對應資料電壓VDATA的灰階值範圍的位元數,亦即數位控制信號Sdit的位元數可小於等於資料電壓VDATA的灰階值範圍的位元數。並且,數位控制信號Sdit可以是資料電壓VDATA中的多個最高位元。 FIG. 2 is a schematic circuit diagram of a light-emitting block according to an embodiment of the present invention. Please refer to FIG. 1A and FIG. 2. In this embodiment, the number of digital control signals Sdit is 3 as an example (taking digital control signals Sdit0 to Sdit2 as an example), that is, the digital control signal Sdit is a 3-bit signal, where The number of the digital control signals Sdit corresponds to the number of bits of the grayscale value range of the data voltage VDATA, that is, the number of bits of the digital control signal Sdit may be less than or equal to the number of bits of the grayscale value range of the data voltage VDATA. In addition, the digital control signal Sdit may be a plurality of highest bits in the data voltage VDATA.
栓鎖電路110包括多個栓鎖單元(如111、113、115), 個別接收數位控制信號Sdit0~Sdit2,以個別提供栓鎖的數位控制信號Sdit0~Sdit2的其中之一作為信號S0~S2及對應的反相數位控制信號(如信號、、),其中信號S0~S2可視為經栓鎖後的數位控制信號Sdit0~Sdit2,並且信號、、則是信號S0~S2的反相信號。 The latching circuit 110 includes a plurality of latching units (such as 111, 113, and 115). Each of the latching circuits 110 receives digital control signals Sdit0 to Sdit2, and one of the digital control signals Sdit0 to Sdit2 is provided as the signals S0 to S2 and Corresponding inverted digital control signal (e.g. signal , , ), Where the signals S0 ~ S2 can be regarded as the digital control signals Sdit0 ~ Sdit2 after being locked, and the signals , , It is the inverted signal of the signals S0 ~ S2.
各個栓鎖單元(如111、113、115)包括第一反相器INT、第一及閘AND1、第二及閘AND2、第一反或閘NOR1及第二反或閘NOR2。第一反相器INT具有接收對應的一個數位控制信號(如Sdit0~Sdit2)的輸入端及輸出端。第一及閘AND1具有耦接第一反相器INT的輸出端的第一輸入端、接收位移信號SR_n的第二輸入端及輸出端。第二及閘AND2具有接收對應的一個數位控制信號(如Sdit0~Sdit2)的第一輸入端、接收位移信號SR_n的第二輸入端及輸出端。 Each latching unit (eg, 111, 113, 115) includes a first inverter INT, a first AND gate AND1, a second and gate AND2, a first OR gate NOR1, and a second OR gate NOR2. The first inverter INT has an input terminal and an output terminal for receiving a corresponding digital control signal (such as Sdit0 ~ Sdit2). The first AND gate AND1 has a first input terminal coupled to the output terminal of the first inverter INT, a second input terminal and an output terminal that receive the displacement signal SR_n. The second AND gate AND2 has a first input terminal for receiving a corresponding digital control signal (such as Sdit0 ~ Sdit2), a second input terminal and an output terminal for receiving the displacement signal SR_n.
第一反或閘NOR1具有耦接第一及閘AND1的輸出端的第一輸入端、第二輸入端及提供對應的信號(如信號S0~S2)的輸出端。第二反或閘NOR2具有耦接第二及閘AND2的輸出端的第一輸入端、耦接第一反或閘NOR1的輸出端的第二輸入端及耦接第一反或閘NOR1的第二輸入端且提供對應的信號(如信號、、)的輸出端。依據上述,栓鎖單元111接收位移信號SR_n及數位控制信號Sdit0,以提供信號S0及;栓鎖單元113接收位移信號SR_n及數位控制信號Sdit1,以提供信號S1及;栓鎖單元115接收位移信號SR_n及數位控制信號Sdit2,以提供 信號S2及。 The first OR gate NOR1 has a first input terminal, a second input terminal coupled to the output terminals of the first AND gate AND1, and an output terminal that provides corresponding signals (such as signals S0 ~ S2). The second NOR gate NOR2 has a first input terminal coupled to the output of the second NOR gate AND2, a second input terminal coupled to the output of the first NOR gate NOR1, and a second input coupled to the first NOR gate NOR1. And provide corresponding signals (such as signals , , ) Output. According to the above, the latching unit 111 receives the displacement signal SR_n and the digital control signal Sdit0 to provide the signals S0 and ; The latch unit 113 receives the displacement signal SR_n and the digital control signal Sdit1 to provide the signals S1 and ; The latching unit 115 receives the displacement signal SR_n and the digital control signal Sdit2 to provide the signals S2 and .
選擇電路120包括傳輸閘TG11~TG14、TG21~TG28、TG31~TG38及TG41~TG48,傳輸閘TG11~TG14、TG21~TG28、TG31~TG38及TG41~TG48個別自栓鎖電路110接收對應的信號S0~S2中的一個及信號、、中的一個,以決定為導通或截止。並且,部份的傳輸閘(如TG11~TG14、TG21~TG28、TG31~TG38及TG41~TG48)串接於致能電壓準位(在此以系統低電壓VSS為例)與對應的選擇信號(如Y0~Y7)之間,部份的傳輸閘(如TG11~TG14、TG21~TG28、TG31~TG38及TG41~TG48)個別耦接於傳輸閘(如TG11~TG14、TG21~TG28、TG31~TG38及TG41~TG48)的其中之一的輸出端與禁能電壓準位(在此以系統高電壓VDD為例)之間。 The selection circuit 120 includes transmission gates TG11 to TG14, TG21 to TG28, TG31 to TG38, and TG41 to TG48, and transmission gates TG11 to TG14, TG21 to TG28, TG31 to TG38, and TG41 to TG48. Individual self-lock circuits 110 receive corresponding signals S0 ~ S2 one and signal , , One of them is decided to be on or off. In addition, some transmission gates (such as TG11 ~ TG14, TG21 ~ TG28, TG31 ~ TG38, and TG41 ~ TG48) are connected in series to the enable voltage level (here, the system low voltage VSS is taken as an example) and the corresponding selection signal ( (Such as Y0 ~ Y7), some transmission gates (such as TG11 ~ TG14, TG21 ~ TG28, TG31 ~ TG38, and TG41 ~ TG48) are individually coupled to the transmission gates (such as TG11 ~ TG14, TG21 ~ TG28, TG31 ~ TG38). And TG41 ~ TG48) between the output terminal and the disabled voltage level (here, the system high voltage VDD is taken as an example).
傳輸閘TG11具有接收系統低電壓VSS的輸入端、接收信號S2的正控制端、接收信號的負控制端及輸出端。傳輸閘TG12具有接收系統高電壓VDD的輸入端、接收信號的正控制端、接收信號S2的負控制端及耦接傳輸閘TG11的輸出端的輸出端。傳輸閘TG13具有接收系統低電壓VSS的輸入端、接收信號的正控制端、接收信號S2的負控制端及輸出端。傳輸閘TG14具有接收系統高電壓VDD的輸入端、接收信號S2的正控制端、接收信號的負控制端及耦接傳輸閘TG13的輸出端的輸出端。 The transmission gate TG11 has an input terminal for receiving the system low voltage VSS, a positive control terminal for receiving the signal S2, and a receiving signal. Negative control terminal and output terminal. The transmission gate TG12 has an input terminal for receiving the high voltage VDD of the system, and a receiving signal Positive control terminal, negative control terminal of receiving signal S2, and output terminal coupled to output terminal of transmission gate TG11. The transmission gate TG13 has an input terminal for receiving the system low voltage VSS, and receives a signal Positive control terminal, negative control terminal and output terminal of receiving signal S2. The transmission gate TG14 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S2, and a receiving signal. And an output terminal coupled to the output terminal of the transmission gate TG13.
傳輸閘TG21具有耦接傳輸閘TG11的輸出端的輸入端、接收信號S1的正控制端、接收信號的負控制端及輸出端。傳輸 閘TG22具有接收系統高電壓VDD的輸入端、接收信號的正控制端、接收信號S1的負控制端及耦接傳輸閘TG21的輸出端的輸出端。傳輸閘TG23具有耦接傳輸閘TG11的輸出端的輸入端、接收信號的正控制端、接收信號S1的負控制端及輸出端。傳輸閘TG24具有接收系統高電壓VDD的輸入端、接收信號S1的正控制端、接收信號的負控制端及耦接傳輸閘TG23的輸出端的輸出端。 The transmission gate TG21 has an input terminal coupled to the output terminal of the transmission gate TG11, a positive control terminal for receiving the signal S1, and a reception signal. Negative control terminal and output terminal. The transmission gate TG22 has an input terminal for receiving the high voltage VDD of the system, and a receiving signal Positive control terminal, negative control terminal of receiving signal S1, and output terminal coupled to output terminal of transmission gate TG21. The transmission gate TG23 has an input terminal coupled to an output end of the transmission gate TG11, and receives a signal. Positive control terminal, negative control terminal and output terminal of receiving signal S1. The transmission gate TG24 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S1, and a receiving signal. And an output terminal coupled to the output terminal of the transmission gate TG23.
傳輸閘TG25具有耦接傳輸閘TG13的輸出端的輸入端、接收信號S1的正控制端、接收信號的負控制端及輸出端。傳輸閘TG26具有接收系統高電壓VDD的輸入端、接收信號的正控制端、接收信號S1的負控制端及耦接傳輸閘TG25的輸出端的輸出端。傳輸閘TG27具有耦接傳輸閘TG13的輸出端的輸入端、接收信號的正控制端、接收信號S1的負控制端及輸出端。傳輸閘TG28具有接收系統高電壓VDD的輸入端、接收信號S1的正控制端、接收信號的負控制端及耦接傳輸閘TG27的輸出端的輸出端。 The transmission gate TG25 has an input terminal coupled to the output terminal of the transmission gate TG13, a positive control terminal for receiving the signal S1, and a receiving signal. Negative control terminal and output terminal. The transmission gate TG26 has an input terminal for receiving the high voltage VDD of the system, and a receiving signal Positive control terminal, negative control terminal of receiving signal S1, and output terminal coupled to output terminal of transmission gate TG25. The transmission gate TG27 has an input terminal coupled to an output end of the transmission gate TG13, and receives a signal. Positive control terminal, negative control terminal and output terminal of receiving signal S1. The transmission gate TG28 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S1, and a receiving signal. The negative control terminal and the output terminal coupled to the output terminal of the transmission gate TG27.
傳輸閘TG31具有耦接傳輸閘TG21的輸出端的輸入端、接收信號S0的正控制端、接收信號的負控制端及提供選擇信號Y7的輸出端。傳輸閘TG32具有接收系統高電壓VDD的輸入端、接收信號的正控制端、接收信號S0的負控制端及耦接傳輸閘TG31的輸出端的輸出端。傳輸閘TG33具有耦接傳輸閘TG21的輸出端的輸入端、接收信號的正控制端、接收信號S0的負控制 端及提供選擇信號Y6的輸出端。傳輸閘TG34具有接收系統高電壓VDD的輸入端、接收信號S0的正控制端、接收信號的負控制端及耦接傳輸閘TG33的輸出端的輸出端。 The transmission gate TG31 has an input terminal coupled to the output terminal of the transmission gate TG21, a positive control terminal receiving the signal S0, and a receiving signal. Negative control terminal and an output terminal providing a selection signal Y7. The transmission gate TG32 has an input terminal for receiving the high voltage VDD of the system, and a receiving signal The positive control terminal, the negative control terminal receiving the signal S0, and the output terminal coupled to the output terminal of the transmission gate TG31. The transmission gate TG33 has an input terminal coupled to the output end of the transmission gate TG21, and receives a signal. Positive control terminal, negative control terminal receiving signal S0, and output terminal providing selection signal Y6. The transmission gate TG34 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S0, and a receiving signal. The negative control terminal and the output terminal coupled to the output terminal of the transmission gate TG33.
傳輸閘TG35具有耦接傳輸閘TG23的輸出端的輸入端、接收信號S0的正控制端、接收信號的負控制端及提供選擇信號Y5的輸出端。傳輸閘TG36具有接收系統高電壓VDD的輸入端、接收信號的正控制端、接收信號S0的負控制端及耦接傳輸閘TG35的輸出端的輸出端。傳輸閘TG37具有耦接傳輸閘TG23的輸出端的輸入端、接收信號的正控制端、接收信號S0的負控制端及提供選擇信號Y4的輸出端。傳輸閘TG38具有接收系統高電壓VDD的輸入端、接收信號S0的正控制端、接收信號的負控制端及耦接傳輸閘TG37的輸出端的輸出端。 The transmission gate TG35 has an input terminal coupled to the output terminal of the transmission gate TG23, a positive control terminal receiving the signal S0, and a receiving signal. Negative control terminal and an output terminal providing a selection signal Y5. The transmission gate TG36 has an input terminal for receiving the high voltage VDD of the system, and a receiving signal The positive control terminal, the negative control terminal receiving the signal S0, and the output terminal coupled to the output terminal of the transmission gate TG35. The transmission gate TG37 has an input terminal coupled to the output end of the transmission gate TG23, and receives a signal. Positive control terminal, negative control terminal receiving signal S0, and output terminal providing selection signal Y4. The transmission gate TG38 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S0, and a receiving signal. The negative control terminal and the output terminal coupled to the output terminal of the transmission gate TG37.
傳輸閘TG41具有耦接傳輸閘TG25的輸出端的輸入端、接收信號S0的正控制端、接收信號的負控制端及提供選擇信號Y3的輸出端。傳輸閘TG42具有接收系統高電壓VDD的輸入端、接收信號的正控制端、接收信號S0的負控制端及耦接傳輸閘TG41的輸出端的輸出端。傳輸閘TG43具有耦接傳輸閘TG25的輸出端的輸入端、接收信號的正控制端、接收信號S0的負控制端及提供選擇信號Y2的輸出端。傳輸閘TG44具有接收系統高電壓VDD的輸入端、接收信號S0的正控制端、接收信號的負控制端及耦接傳輸閘TG43的輸出端的輸出端。 The transmission gate TG41 has an input terminal coupled to the output terminal of the transmission gate TG25, a positive control terminal receiving the signal S0, and a receiving signal. Negative control terminal and an output terminal providing a selection signal Y3. The transmission gate TG42 has an input terminal for receiving the high voltage VDD of the system, and a receiving signal The positive control terminal, the negative control terminal receiving the signal S0, and the output terminal coupled to the output terminal of the transmission gate TG41. The transmission gate TG43 has an input terminal coupled to the output end of the transmission gate TG25, and receives a signal. Positive control terminal, negative control terminal receiving signal S0, and output terminal providing selection signal Y2. The transmission gate TG44 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S0, and a receiving signal. And an output terminal coupled to the output terminal of the transmission gate TG43.
傳輸閘TG45具有耦接傳輸閘TG27的輸出端的輸入端、 接收信號S0的正控制端、接收信號的負控制端及提供選擇信號Y1的輸出端。傳輸閘TG46具有接收系統高電壓VDD的輸入端、接收信號的正控制端、接收信號S0的負控制端及耦接傳輸閘TG45的輸出端的輸出端。傳輸閘TG47具有耦接傳輸閘TG27的輸出端的輸入端、接收信號的正控制端、接收信號S0的負控制端及提供選擇信號Y0的輸出端。傳輸閘TG48具有接收系統高電壓VDD的輸入端、接收信號S0的正控制端、接收信號的負控制端及耦接傳輸閘TG47的輸出端的輸出端。 The transmission gate TG45 has an input terminal coupled to the output terminal of the transmission gate TG27, a positive control terminal for receiving the signal S0, and a receiving signal. Negative control terminal and an output terminal providing a selection signal Y1. The transmission gate TG46 has an input terminal for receiving the high voltage VDD of the system, and a receiving signal The positive control terminal, the negative control terminal of the receiving signal S0, and the output terminal coupled to the output terminal of the transmission gate TG45. The transmission gate TG47 has an input terminal coupled to the output end of the transmission gate TG27, and receives a signal. Positive control terminal, negative control terminal receiving signal S0, and output terminal providing selection signal Y0. The transmission gate TG48 has an input terminal for receiving the system high voltage VDD, a positive control terminal for receiving the signal S0, and a receiving signal. The negative control terminal and the output terminal coupled to the output terminal of the transmission gate TG47.
電壓輸出電路130包括七個開關電晶體M0~M7,個別具有接收多個驅動準位(VDD0~VDD7)的其中之一的第一端、接收選擇信號(如Y0~Y7)的其中之一的控制端及耦接驅動電壓VD1的第二端。 The voltage output circuit 130 includes seven switching transistors M0 to M7, each of which has a first terminal for receiving one of a plurality of driving levels (VDD0 to VDD7) and one of receiving a selection signal (such as Y0 to Y7). The control terminal and a second terminal coupled to the driving voltage VD1.
依據上述,若數位控制信號Sdit2~Sdit0依序為“111”,則傳輸閘TG11、TG14、TG21、TG24、TG25、TG28、TG31、TG34、TG35、TG38、TG41、TG44、TG45及TG48會導通,其餘傳輸閘會呈現截止。因此,系統低電壓VSS會經由導通的傳輸閘TG11、TG21及TG31傳送至選擇信號Y7,而使選擇信號Y7為致能準位,其餘選擇信號Y0~Y6則為禁能準位。接著,開關電晶體M7導通,且其餘開關電晶體M0~M6為截止,因此驅動準位VDD7(例如為8伏特)會提供至驅動電晶體TD2以作為驅動電壓VD1。 According to the above, if the digital control signals Sdit2 ~ Sdit0 are "111" in sequence, the transmission gates TG11, TG14, TG21, TG24, TG25, TG28, TG31, TG34, TG35, TG38, TG41, TG44, TG45 and TG48 will be turned on, The remaining transmission gates will appear to be closed. Therefore, the system low voltage VSS will be transmitted to the selection signal Y7 through the conductive transmission gates TG11, TG21, and TG31, so that the selection signal Y7 is the enabled level, and the remaining selection signals Y0 to Y6 are disabled levels. Then, the switching transistor M7 is turned on, and the remaining switching transistors M0 to M6 are turned off. Therefore, the driving level VDD7 (for example, 8 volts) is provided to the driving transistor TD2 as the driving voltage VD1.
若數位控制信號Sdit2~Sdit0依序為“110”,則傳輸閘TG11、TG14、TG21、TG24、TG25、TG28、TG32、TG33、TG36、 TG37、TG42、TG43、TG46及TG47會導通,其餘傳輸閘會呈現截止。因此,系統低電壓VSS會經由導通的傳輸閘TG11、TG21及TG33傳送至選擇信號Y6,而使選擇信號Y6為致能準位,其餘選擇信號Y0~Y5、Y7則為禁能準位。接著,開關電晶體M6導通,且其餘開關電晶體M0~M5、M7為截止,因此驅動準位VDD6(例如為7伏特)會提供至驅動電晶體TD2以作為驅動電壓VD1。其餘狀態則以此類推,在此則不再贅述。 If the digital control signals Sdit2 ~ Sdit0 are "110" in sequence, the transmission gates TG11, TG14, TG21, TG24, TG25, TG28, TG32, TG33, TG36, TG37, TG42, TG43, TG46 and TG47 will be turned on, and the remaining transmission gates will be turned off. Therefore, the system low voltage VSS will be transmitted to the selection signal Y6 through the conductive transmission gates TG11, TG21 and TG33, so that the selection signal Y6 is the enable level, and the remaining selection signals Y0 ~ Y5, Y7 are the disable level. Then, the switching transistor M6 is turned on, and the remaining switching transistors M0 to M5 and M7 are turned off. Therefore, the driving level VDD6 (for example, 7 volts) is provided to the driving transistor TD2 as the driving voltage VD1. The rest of the state can be deduced by analogy, and will not be repeated here.
在本實施例中,栓鎖單元111、113、115是以RS正反器為例,但本發明實施例不以此為限。此外,致能電壓準位(例如系統低電壓VSS)與對應的選擇信號(如Y0~Y7)之間串接的傳輸閘(如TG11~TG14、TG21~TG28、TG31~TG38及TG41~TG48)的數量對應數位控制信號(如Sdit0~Sdit2)的數目,並且串接於致能電壓準位(例如系統低電壓VSS)與對應的選擇信號(如Y1~Y7)之間的傳輸閘(如TG11~TG14、TG21~TG28、TG31~TG38及TG41~TG48)個別接收對應不同數位控制信號(如Sdit0~Sdit2)的栓鎖信號(如信號S0~S2、、、)。 In this embodiment, the latch units 111, 113, and 115 are exemplified by RS flip-flops, but the embodiment of the present invention is not limited thereto. In addition, a transmission gate (such as TG11 ~ TG14, TG21 ~ TG28, TG31 ~ TG38, and TG41 ~ TG48) connected in series between the enable voltage level (such as the system low voltage VSS) and the corresponding selection signal (such as Y0 ~ Y7). The number corresponds to the number of digital control signals (such as Sdit0 ~ Sdit2), and is connected in series between the transmission gate (such as TG11) between the enable voltage level (such as the system low voltage VSS) and the corresponding selection signal (such as Y1 ~ Y7). ~ TG14, TG21 ~ TG28, TG31 ~ TG38, and TG41 ~ TG48) individually receive latch signals (such as signals S0 ~ S2, corresponding to different digital control signals (such as Sdit0 ~ Sdit2)). , , ).
圖3A為依據本發明一實施例的驅動電壓隨資料電壓變動的模擬示意圖。圖3B為依據本發明一實施例的驅動電壓為固定電壓的模擬示意圖。請參照圖1A、圖3A及圖3B,在本實施例中,電壓VG1為驅動電晶體TD2的閘極電壓(對應於資料電壓VDATA),電壓VS1為驅動電晶體TD2的源極電壓。由圖3A及圖3B可見到,當電壓VG1為1.45或3.46伏(V)時,驅動電壓 VD1可大幅降低,但發光電流Id僅會小幅度的變動。藉此,在低灰階的情況下,可降低驅動電壓VD1來降低功耗,但發光二極體LED1的發光亮度仍可具有一定程度的維持。 FIG. 3A is a simulation diagram of a driving voltage changing with a data voltage according to an embodiment of the present invention. FIG. 3B is a simulation diagram of the driving voltage being a fixed voltage according to an embodiment of the present invention. Please refer to FIGS. 1A, 3A and 3B. In this embodiment, the voltage VG1 is the gate voltage (corresponding to the data voltage VDATA) of the driving transistor TD2, and the voltage VS1 is the source voltage of the driving transistor TD2. It can be seen from FIGS. 3A and 3B that when the voltage VG1 is 1.45 or 3.46 volts (V), the driving voltage VD1 can be greatly reduced, but the light-emitting current Id changes only slightly. Therefore, in the case of a low gray level, the driving voltage VD1 can be reduced to reduce power consumption, but the light emitting brightness of the light emitting diode LED1 can still be maintained to a certain extent.
圖4為依據本發明一實施例的顯示裝置的系統示意圖。請參照圖4,在本實施例中,顯示裝置10至少包括位移控制電路11、資料提供電路13、發光區塊15、多個垂直信號線LVS及多個水平信號線LHS,其中發光區塊15可參照圖1A所示發光區塊100。其中,位移控制電路11用以提供多個位移信號(如SR_1~SR_3),並且資料提供電路13用以提供資料電壓VDATA及多個數位控制信號Sdit。 FIG. 4 is a system diagram of a display device according to an embodiment of the invention. Referring to FIG. 4, in this embodiment, the display device 10 includes at least a displacement control circuit 11, a data providing circuit 13, a light-emitting block 15, a plurality of vertical signal lines LVS, and a plurality of horizontal signal lines LHS, among which the light-emitting block 15 Please refer to the light emitting block 100 shown in FIG. 1A. The displacement control circuit 11 is used to provide a plurality of displacement signals (such as SR_1 ~ SR_3), and the data providing circuit 13 is used to provide a data voltage VDATA and a plurality of digital control signals Sdit.
發光區塊15耦接對應的多個水平信號線LHS,並且透過對應的水平信號線LHS耦接至位移控制電路11,以接收到對應的位移信號(如SR_1~SR_3)。另一方面,發光區塊15耦接對應的多個垂直信號線LVS,並且透過對應的多個垂直信號線LVS耦接至資料提供電路13,以接收到對應的資料電壓VDATA及對應的多個數位控制信號Sdit。 The light-emitting block 15 is coupled to a plurality of corresponding horizontal signal lines LHS, and is coupled to the displacement control circuit 11 through the corresponding horizontal signal lines LHS to receive corresponding displacement signals (such as SR_1 ~ SR_3). On the other hand, the light-emitting block 15 is coupled to the corresponding plurality of vertical signal lines LVS, and is coupled to the data providing circuit 13 through the corresponding plurality of vertical signal lines LVS to receive the corresponding data voltage VDATA and the corresponding plurality Digital control signal Sdit.
發光區塊15依據對應的位移信號(如SR_1~SR_3)儲存所接收的對應的資料電壓VDATA,同時栓鎖所接收的多個數位控制信號Sdit。發光區塊15依據所儲存的資料電壓VDATA決定發光的亮度,並且透過所栓鎖的多個數位控制信號Sdit,發光區塊15可降低功耗。在本實施例中,這些發光區塊15是直接提供用以形成彩色影像的光線。 The light-emitting block 15 stores the corresponding data voltage VDATA received according to the corresponding displacement signal (such as SR_1 ~ SR_3), and simultaneously locks the received digital control signals Sdit. The light-emitting block 15 determines the brightness of light emission according to the stored data voltage VDATA, and the light-emitting block 15 can reduce power consumption through the latched digital control signals Sdit. In this embodiment, the light-emitting blocks 15 directly provide light for forming a color image.
圖5為依據本發明一實施例的資料提供電路的系統示意圖。請參照圖4及圖5,在本實施例中,資料提供電路13包括位移暫存器210、輸入暫存器220、資料栓鎖器230、準位移位器240、數位類比轉換器250及緩衝器260。位移暫存器210接收設定信號SET及時脈信號CLK,以依據設定信號SET及時脈信號CLK提供依序致能的多個觸發信號STR。輸入暫存器220耦接位移暫存器210,以接收依序致能的多個觸發信號STR,並且接收多個顯示資料(如紅色顯示資料XDR、綠色顯示資料XDG及藍色顯示資料XDB)。接著,輸入暫存器220依據依序致能的多個觸發信號STR依序栓鎖及輸出顯示資料(如紅色顯示資料XDR、綠色顯示資料XDG及藍色顯示資料XDB)。 FIG. 5 is a system schematic diagram of a data providing circuit according to an embodiment of the present invention. Please refer to FIGS. 4 and 5. In this embodiment, the data providing circuit 13 includes a shift register 210, an input register 220, a data latch 230, a quasi-shifter 240, a digital analog converter 250 and Buffer 260. The displacement register 210 receives the setting signal SET and the clock signal CLK to provide a plurality of trigger signals STR that are sequentially enabled according to the setting signal SET and the clock signal CLK. The input register 220 is coupled to the displacement register 210 to receive a plurality of sequentially enabled trigger signals STR and receive a plurality of display data (such as red display data XDR, green display data XDG, and blue display data XDB). . Then, the input register 220 sequentially latches and outputs the display data (such as the red display data XDR, the green display data XDG, and the blue display data XDB) according to a plurality of sequentially enabled trigger signals STR.
資料栓鎖器230耦接輸入暫存器220且接收栓鎖致能信號LEN,以依據栓鎖致能信號LEN栓鎖及輸出自輸入暫存器220接收的顯示資料(如紅色顯示資料XDR、綠色顯示資料XDG及藍色顯示資料XDB)。準位移位器240耦接資料栓鎖器230,以接收來自資料栓鎖器230的顯示資料(如紅色顯示資料XDR、綠色顯示資料XDG及藍色顯示資料XDB),並且提供準位移位後的顯示資料DLX及多個數位控制信號Sdit,其中所述多個數位控制信號Sdit可以是直接將顯示資料(如紅色顯示資料XDR、綠色顯示資料XDG及藍色顯示資料XDB)輸出來形成。 The data latch 230 is coupled to the input register 220 and receives the latch enable signal LEN so as to latch and output display data received from the input register 220 according to the latch enable signal LEN (such as red display data XDR, Green display data XDG and blue display data XDB). The quasi-displacer 240 is coupled to the data latch 230 to receive display data (such as red display data XDR, green display data XDG, and blue display data XDB) from the data latch 230, and provide a quasi-displacement bit. The subsequent display data DLX and a plurality of digital control signals Sdit may be formed by directly outputting display data (such as red display data XDR, green display data XDG, and blue display data XDB).
數位類比轉換器250耦接準位移位器240,以接收準位移位後的顯示資料DLX,並且接收多個參考電壓Vref,以將顯示資 料DLX轉換為類比準位(即電壓準位)後提供類比驅動電壓VDX。緩衝器260耦接數位類比轉換器250,以接收類比驅動電壓VDX,並且據此提供資料電壓VDATA。 The digital analog converter 250 is coupled to the quasi-shifter 240 to receive the quasi-shifted display data DLX, and to receive a plurality of reference voltages Vref to display the display data. After the DLX is converted to the analog level (that is, the voltage level), the analog driving voltage VDX is provided. The buffer 260 is coupled to the digital-to-analog converter 250 to receive the analog driving voltage VDX and provide the data voltage VDATA accordingly.
圖6為依據本發明另一實施例的顯示裝置的系統示意圖。請參照圖4及圖6,顯示裝置20大致上相同於顯示裝置10,其不同之處在於顯示裝置20更包括顯示面板21。顯示面板21配置有以陣列排列的多個液晶畫素PX,並且各個發光區塊15與這些液晶畫素PX的部份重疊,以提供顯示光至重疊的液晶畫素PX。在本實施例中,顯示面板21與發光區塊15可以共用位移控制電路11。 FIG. 6 is a system diagram of a display device according to another embodiment of the present invention. 4 and FIG. 6, the display device 20 is substantially the same as the display device 10. The difference is that the display device 20 further includes a display panel 21. The display panel 21 is configured with a plurality of liquid crystal pixels PX arranged in an array, and each light-emitting block 15 overlaps a portion of these liquid crystal pixels PX to provide display light to the overlapping liquid crystal pixels PX. In this embodiment, the display panel 21 and the light-emitting block 15 can share the displacement control circuit 11.
圖7為依據本發明一實施例的顯示裝置的發光區塊的驅動方法的流程圖。請參照圖7,在本實施例中,驅動方法用以驅動顯示裝置的多個發光區塊,這些發光區塊個別具有一發光二極體,驅動方法包括下列步驟。在步驟S710中,接收資料電壓以決定由驅動電壓流經發光二極體的發光電流。在步驟S720中,接收與資料電壓對應的多個數位控制信號,以調整驅動電壓,其中反應資料電壓的下降,驅動電壓也隨著下降。其中,步驟S710、S720的順序為用以說明,本發明實施例不以此為限。並且步驟S710、S720的細節可參照圖1A、1B、2、3A、3B、4-6的實施例所述,在此則不再贅述。 FIG. 7 is a flowchart of a driving method of a light emitting block of a display device according to an embodiment of the invention. Please refer to FIG. 7. In this embodiment, the driving method is used to drive a plurality of light-emitting blocks of the display device. Each of these light-emitting blocks has a light-emitting diode. The driving method includes the following steps. In step S710, the data voltage is received to determine a light emitting current flowing through the light emitting diode by the driving voltage. In step S720, a plurality of digital control signals corresponding to the data voltage are received to adjust the driving voltage, wherein the driving voltage is also reflected as the data voltage decreases. The sequence of steps S710 and S720 is for illustration, and the embodiment of the present invention is not limited thereto. For details of steps S710 and S720, reference may be made to the embodiments in FIGS. 1A, 1B, 2, 3A, 3B, and 4-6, and details are not described herein again.
綜上所述,本發明實施例的顯示裝置及其發光區塊的驅動方法,其接收與資料電壓對應的多個數位控制信號,以調整驅 動電壓,並且反應資料電壓的下降,驅動電壓也隨著下降。藉此,當發光區塊的發光灰階值越低,可節省更多功率,但仍保持發光二極體的發光亮度。 In summary, the display device and the method for driving the light-emitting block according to the embodiments of the present invention receive a plurality of digital control signals corresponding to the data voltage to adjust the driver. The driving voltage and the voltage of the reaction data decrease, and the driving voltage also decreases. Therefore, when the light-emitting gray-scale value of the light-emitting block is lower, more power can be saved, but the light-emitting brightness of the light-emitting diode is still maintained.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.
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