TWI678784B - 電子封裝件及其製法 - Google Patents
電子封裝件及其製法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims abstract description 136
- 238000004519 manufacturing process Methods 0.000 claims abstract description 35
- 239000000463 material Substances 0.000 claims description 30
- 239000011810 insulating material Substances 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 abstract description 7
- 238000003825 pressing Methods 0.000 abstract description 3
- 229910000679 solder Inorganic materials 0.000 description 12
- 238000004891 communication Methods 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 5
- 239000007769 metal material Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 230000009471 action Effects 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
- H01Q9/04—Resonant antennas
- H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna
- H01Q9/0414—Substantially flat resonant element parallel to ground plane, e.g. patch antenna in a stacked or folded configuration
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0243—Printed circuits associated with mounted high frequency components
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/04—Assemblies of printed circuits
- H05K2201/042—Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10098—Components for radio transmission, e.g. radio frequency identification [RFID] tag, printed or non-printed antennas
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- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
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- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
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Abstract
一種電子封裝件及其製法,係於具有第一天線佈設區之第一基板上形成阻層及支撐體,再將具有第二天線佈設區之第二基板壓合於該阻層及支撐體上,之後移除該阻層,以藉由該支撐體使該第一基板與第二基板之間的距離保持不變,確保該第一天線佈設區與第二天線佈設區之間的天線傳輸功能正常。
Description
本發明係關於一種電子封裝件,特別是關於一種具有天線結構之電子封裝件及其製法。
目前無線通訊技術已廣泛應用於各式各樣的消費性電子產品(如手機、平板電腦等),以利接收或發送各種無線訊號,而為滿足消費性電子產品的便於攜帶性及上網便利性(如觀看多媒體內容),無線通訊模組之製造與設計係朝輕、薄、短、小之需求作開發,其中,平面天線(Patch Antenna)因具有體積小、重量輕與製造容易等特性而廣泛利用在電子產品之無線通訊模組中。
目前的多媒體內容因畫質的提升而造成其檔案資料量變得更大,故無線傳輸的頻寬也需變大,因而產生第五代的無線傳輸(5G),且5G因傳輸頻率較高,其相關無線通訊模組的尺寸的要求也較高。
如第1圖所示,係為習知無線通訊模組1之剖面示意圖。該無線通訊模組1係於設有半導體晶片10之線路板11上側藉由複數銲錫凸塊13堆疊一具有第二天線結構(圖
略)之天線板12,且該線路板11具有接地片(圖略)及天線回饋線路(antenna feed lines)(圖略),並於該線路板11下方形成複數銲球15,其中,該線路板11與該天線板12之間需於特定區域定義為天線作用區A(即該些銲錫凸塊13環繞之區域,其內部不可有點膠或模壓填入物),且需控制該線路板11與該天線板12之間的距離L,以確保該天線板12之第二天線結構與該半導體晶片10之間的傳接訊號品質;若該距離L不符合所需高度,則該線路板11與該天線板12之間的天線訊號傳輸將無法準確傳輸。
再者,習知無線通訊模組1中,因藉由該些銲錫凸塊13堆疊該線路板11與該天線板12,故該些銲錫凸塊13於回銲後之體積及高度之公差大,使該些銲錫凸塊13所排列成之柵狀陣列(grid array)容易產生共面性(coplanarity)不良,導致接點應力(stress)不平衡而容易造成該線路板11與該天線板12之間呈傾斜接置,導致該線路板11與該天線板12之間的距離L產生變化(如其中一側變大),因而造成該天線板12的天線功能不良,進而造成產品之良率下降。
因此,如何克服上述習知技術的問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失,本發明係提供一種電子封裝件,係包括:第一基板,係具有第一天線佈設區;支撐體,係設於該第一基板上;以及第二基板,係壓合至該支
撐體上,使該第一基板與該第二基板藉由該支撐體相互堆疊並控制該第一基板與該第二基板之間的距離,且該第二基板具有對應該第一天線佈設區之第二天線佈設區。
本發明復提供一種電子封裝件之製法,係包括:形成阻層於一具有第一天線佈設區之第一基板上,且該阻層形成有至少一外露部分該第一基板之開口;形成支撐體於該開口中,使該支撐體接觸該第一基板;壓合一具有第二天線佈設區之第二基板於該阻層上,使該第二基板接觸該支撐體,其中,該第二基板係具有對應該第一天線佈設區之第二天線佈設區;以及移除該阻層,使該第一基板與該第二基板藉由該支撐體相互堆疊。
前述之製法中,構成該阻層之材質係為可蝕刻材料。
前述之製法中,該開口未外露該第一天線佈設區。
前述之電子封裝件及其製法中,該第一天線佈設區與該第二天線佈設區之間係為天線作用區。例如,該天線作用區呈現空曠空間。
前述之電子封裝件及其製法中,該構成支撐體之材質係為導電材或絕緣材。
前述之電子封裝件及其製法中,該支撐體係未電性連接該第一天線佈設區及/或第二天線佈設區。
前述之電子封裝件及其製法中,該支撐體係未電性連接該第一基板及/或第二基板。
前述之電子封裝件及其製法中,該支撐體係電性連接該第一基板及/或第二基板。
前述之電子封裝件及其製法中,該支撐體上係形成有包覆材。
前述之電子封裝件及其製法中,復包括設置電子元件於該第一基板上。於一實施例中,該電子元件係位於該第一基板與第二基板之間。
由上可知,本發明之電子封裝件及其製法中,係藉由將該第二基板壓合至該阻層及支撐體之方式以控制該第一基板與第二基板之間的距離,且令該支撐體堆疊該第一基板與該第二基板,而無需使用銲錫材料,使該第一與第二基板之間的距離幾乎保持不變,故相較於習知技術,本發明之電子封裝件不會因該第一與第二基板之間的距離變化過大而影響天線功能,因而能避免產品良率下降之問題。
1‧‧‧無線通訊模組
10‧‧‧半導體晶片
11‧‧‧線路板
12‧‧‧天線板
13‧‧‧銲錫凸塊
15‧‧‧銲球
2,3‧‧‧電子封裝件
20‧‧‧電子元件
200‧‧‧導電凸塊
21‧‧‧第一基板
21a‧‧‧第一表面
21b‧‧‧第二表面
210‧‧‧第一天線結構
211‧‧‧第一線路層
212‧‧‧第一電性接點
213‧‧‧植球墊
22‧‧‧第二基板
220‧‧‧第二天線結構
221‧‧‧第二線路層
222‧‧‧第二電性接點
23,24‧‧‧支撐體
23c‧‧‧側面
25‧‧‧導電元件
26‧‧‧開孔
29‧‧‧阻層
290‧‧‧開口
390‧‧‧開口區
30‧‧‧包覆材
A,S‧‧‧天線作用區
A1‧‧‧第一天線佈設區
A2‧‧‧第二天線佈設區
H‧‧‧高度
L,D‧‧‧距離
第1圖係為習知無線通訊模組之剖面示意圖;以及第2A至2E圖係為本發明之電子封裝件之製法之第一實施例之剖面示意圖;第2C’圖係為第2C圖之另一態樣;第2D’圖係為第2D圖之另一態樣;第2E’圖係為第2E圖之另一態樣;以及第3A至3C圖係為本發明之電子封裝件之製法之第二實施例之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地
瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“第一”、“第二”、及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
第2A至2E圖係為本發明之電子封裝件2之製法之第一實施例之剖面示意圖。
如第2A圖所示,提供一第一基板21,其具有相對之第一表面21a與第二表面21b。
於本實施例中,該第一基板21係為線路板,其定義有相對之第一表面21a與第二表面21b,並於該第一表面21a定義有第一天線佈設區A1,並配置有第一天線結構210,且該第一基板21復包含有第一線路層211,其中,該第一天線結構210係為線路型天線,其可選擇性電性連接或電性隔絕該第一線路層211,且該第一線路層211包含至少一第一電性接點212與複數植球墊213。應可理解地,該第一基板21亦可為其它承載晶片之承載件,並不限
於上述。
如第2B圖所示,形成一阻層29於該第一基板21之第一表面21a上,且該阻層29具有複數外露部分該第一基板21之開口290,以形成支撐體23於該開口290中,使該支撐體23直接接觸該第一基板21。
於本實施例中,該阻層29之材質係為可蝕刻材料,如絕緣材或如鎳、銅之金屬材,其壓合至該第一基板21上,且該開口290未外露該第一天線佈設區A1。
再者,構成該支撐體23之材質可為導電材、絕緣材或其二者組合。於一實施例中,該支撐體23係為如銅或鎳之導電柱,其接合該第一電性接點212,以電性連接該第一基板21,使該第一基板21與該支撐體23以金屬對金屬接合(metal-to-metal bonding)的方式接合。或者,於一實施例中,如第2E’圖所示,該支撐體24係為絕緣柱,其接合該第一基板21之第一表面21a而未電性連接該第一基板21,使該第一基板21與該支撐體24以絕緣材對絕緣材接合的方式接合,也就是說,本案的基板與支撐體的接合方式可為基板製程的壓合(lamination)方式接合或金屬與金屬接合或絕緣材與絕緣材接合,但不依此為限。亦或,於一實施例中,該支撐體23,24可為絕緣材包覆導電核心之態樣、或導電材包覆絕緣核心之態樣。
又,應可理解地,該支撐體23雖為導電柱,但其仍可能未電性導通該第一基板21。換言之,該支撐體23亦可僅作為支撐用,即該第一基板21與該支撐體23非電性
導通,例如,該第一電性接點212作為無電性功能之虛墊(dummy pad),使該支撐體23無法電性導通該第一線路層211。
另外,該阻層29之材質係不同於該支撐體23,24之材質。例如,該阻層29之第一金屬材係為鎳材,而該支撐體23之第二金屬材係為銅材。或者,該阻層29之第一金屬材係為銅材,而該支撐體23之第二金屬材係為鎳材。
如第2C圖所示,將一第二基板22壓合至該阻層29上,並令該第二基板22直接接觸該些支撐體23。
於本實施例中,該第二基板22係為天線板,其定義有對應該第一天線佈設區A1之第二天線佈設區A2,使該第一天線佈設區A1與第二天線佈設區A2之間作為天線作用區S,並於該第二天線佈設區A2上配置有第二天線結構220,且該第二基板22復具有第二線路層221,其中,該第二天線結構220係為線路型天線,其可選擇性電性連接或電性隔絕該第二線路層221,且該第二線路層221包含至少一第二電性接點222。應可理解地,該第二基板22亦可為其它類型之天線板,並不限於上述。
再者,該支撐體23係直接接合於該第一電性接點212與第二電性接點222之間,以電性連接該第一基板21與該第二基板22。或者,該第二電性接點222作為無電性功能之虛墊,使該支撐體23無法電性導通該第二線路層221。
又,該第二天線結構220係感應該第一天線結構210,以訊號傳輸於該第一天線佈設區A1與該第二天線佈設區
A2之間。
另外,該第一電性接點212或第二電性接點222作為無電性功能之虛墊,使該支撐體23無法電性導通該第二天線結構220及第一天線結構210。
如第2D圖所示,以蝕刻方式移除該阻層29,使該第一基板21與該第二基板22藉由該些支撐體23相互堆疊。
於本實施例中,該些支撐體23係位於該天線作用區S周圍,使該天線作用區S呈空曠空間。
再者,於一生產版面上配置有多個天線作用區S時,如第2C’圖所示,可於該第二基板22上形成至少一開孔26,以將蝕刻液體由該開孔26填入該第一基板21與該第二基板22之間而蝕刻移除該阻層29。進一步,可依需求於後續切單製程中,將該開孔26作為切割路徑以移除該開孔26。
又,於另一實施例中,於該第一基板21之同一單位面積上可依數量需求形成該支撐體23,如第2D’圖所示之數量較少之支撐體23且該支撐體23的寬度大於第2D圖的支撐體的寬度。
如第2E圖所示,可將該第一基板21與該第二基板22之位置上、下翻轉,再於該第一基板21之第二表面21b上設置至少一電子元件20,且於複數該植球墊213上形成複數如銲球之導電元件25,進而製得電子封裝件2。後續可回銲該些導電元件25以供接置如電路板或另一線路板之電子結構(圖未示)。
再者,該電子元件20係為主動元件、被動元件或其二者組合等,其中,該主動元件係例如半導體晶片,且該被動元件係例如電阻、電容及電感。例如,該電子元件20係藉由複數如銲錫材料之導電凸塊200以覆晶方式電性連接該第一線路層211;或者,該電子元件20可藉由複數銲線(圖略)以打線方式電性連接該第一線路層211;亦或,該電子元件20可直接接觸該第一線路層211以電性連接該第一線路層211。然而,有關該電子元件20電性連接該第一基板21之方式不限於上述。
又,有關該電子元件20之配置方式繁多(如設於該第一基板21之第一表面21a,使該電子元件20位於該第一基板21與第二基板22之間),並不限於上述。
本發明之電子封裝件2之製法主要藉由將該第二基板22直接壓合至該阻層29上之方式以控制該第一基板21與第二基板22之間的距離D(如第2C圖所示之阻層29之高度H),且令該支撐體23,24堆疊該第一基板21與該第二基板22,而無需使用銲錫材料,使該第一基板21與該第二基板22之間的距離D幾乎保持不變(如該第一基板21與該第二基板22不會相互傾斜),即能控制該距離D之公差小於10um。
因此,相較於習知技術,本發明之電子封裝件2能精確控制該第一基板21與第二基板22之間的距離D,使該距離D不會因變化過大而影響該第一天線結構210與第二天線結構220的功能,因而能有效控制天線品質,進而能
提高產品良率。
第3A至3C圖係為本發明之電子封裝件3之製法之第二實施例之剖面示意圖。本實施例與上述實施例之差異在於新增包覆材,其它製程大致相同,故不再贅述相同處。
如第3A圖所示,係接續第2B圖之製程,於形成該支撐體23於該開口290中後,移除該些支撐體23周圍之阻層29之材質以形成開口區390,使該些支撐體23之側面23c沒有接觸該阻層29。
如第3B圖所示,形成包覆材30於該開口區390中以接觸及包覆該些支撐體23之側面23c,其中,該包覆材30係為絕緣材。
如第3C圖所示,係依照第2C至2E圖之製程依序進行設置第二基板22、移除該阻層29及設置電子元件20與導電元件25等製程,以獲得一具有包覆材30之電子封裝件3。
本發明復提供一種電子封裝件2,3,其包括:一第一基板21、一第二基板22以及至少一支撐體23,24。
所述之第一基板21係具有第一天線佈設區A1。
所述之支撐體23,24係設於該第一基板21上。
所述之第二基板22係直接壓合至該支撐體23,24上,使該第一基板21與該第二基板22藉由該支撐體23,24相互堆疊,且該第二基板22係具有對應該第一天線佈設區A1之第二天線佈設區A2。
於一實施例中,該第一天線佈設區A1與該第二天線
佈設區A2之間係為天線作用區S。例如,該支撐體23,24位於該天線作用區S周圍,使該天線作用區S呈空曠空間。
於一實施例中,該支撐體23,24係為導電材或絕緣材。
於一實施例中,該支撐體23,24係未電性連接該第一天線佈設區A1及/或第二天線佈設區A2。
於一實施例中,該支撐體23,24係未電性連接該第一基板21及/或第二基板22。
於一實施例中,該支撐體23係電性連接該第一基板21及/或第二基板22。
於一實施例中,該些支撐體23之側面23c上係形成有包覆材30,且該包覆材30未形成於該天線作用區S上。
於一實施例中,所述之電子封裝件2復包括至少一電子元件20,係設於該第一基板21上。亦或,該電子元件20係位於該第一基板21與第二基板22之間。
綜上所述,本發明之電子封裝件及其製法,係透過阻層及支撐體的設置並藉由壓合該第二基板之設計,而無需使用銲錫材料接合支撐體與基板,使該第一與第二基板之間的距離能符合所需之大小,故本發明之電子封裝件能確保該天線作用區的天線傳輸功能正常,因而能確保產品良率符合預期。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範
圍所列。
Claims (22)
- 一種電子封裝件,係包括:第一基板,係具有第一天線佈設區;支撐體,係設於該第一基板上;以及第二基板,係壓合至該支撐體上,使該第一基板與該第二基板藉由該支撐體相互堆疊並控制該第一基板與該第二基板之間的距離,且該第二基板具有對應該第一天線佈設區之第二天線佈設區。
- 如申請專利範圍第1項所述之電子封裝件,其中,該第一天線佈設區與該第二天線佈設區之間係為天線作用區。
- 如申請專利範圍第2項所述之電子封裝件,其中,該天線作用區呈空曠空間。
- 如申請專利範圍第1項所述之電子封裝件,其中,構成該支撐體之材質係為導電材或絕緣材。
- 如申請專利範圍第1項所述之電子封裝件,其中,該支撐體係未電性連接該第一天線佈設區及/或第二天線佈設區。
- 如申請專利範圍第1項所述之電子封裝件,其中,該支撐體係未電性連接該第一基板及/或第二基板。
- 如申請專利範圍第1項所述之電子封裝件,其中,該支撐體係電性連接該第一基板及/或第二基板。
- 如申請專利範圍第1項所述之電子封裝件,其中,該支撐體上係形成有包覆材。
- 如申請專利範圍第1項所述之電子封裝件,復包括電子元件,係設於該第一基板上。
- 如申請專利範圍第9項所述之電子封裝件,其中,該電子元件係位於該第一基板與第二基板之間。
- 一種電子封裝件之製法,係包括:形成阻層於一具有第一天線佈設區之第一基板上,且該阻層形成有至少一外露部分該第一基板之開口;形成支撐體於該開口中,使該支撐體接觸該第一基板;壓合一具有第二天線佈設區之第二基板於該阻層上,使該第二基板接觸該支撐體,其中,該第二基板係具有對應該第一天線佈設區之第二天線佈設區;以及移除該阻層,使該第一基板與該第二基板藉由該支撐體相互堆疊。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該第一天線佈設區與該第二天線佈設區之間係為天線作用區。
- 如申請專利範圍第12項所述之電子封裝件之製法,其中,該天線作用區呈現空曠空間。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,構成該阻層之材質係為可蝕刻材料。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該開口未外露該第一天線佈設區。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,構成該支撐體之材質係為導電材或絕緣材。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該支撐體係未電性連接該第一天線佈設區及/或第二天線佈設區。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該支撐體係未電性連接該第一基板及/或第二基板。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該支撐體係電性連接該第一基板及/或第二基板。
- 如申請專利範圍第11項所述之電子封裝件之製法,其中,該支撐體上係形成有包覆材。
- 如申請專利範圍第11項所述之電子封裝件之製法,復包括設置電子元件於該第一基板上。
- 如申請專利範圍第21項所述之電子封裝件之製法,其中,該電子元件係位於該第一基板與第二基板之間。
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TW201937677A (zh) | 2019-09-16 |
US11101566B2 (en) | 2021-08-24 |
US10756438B2 (en) | 2020-08-25 |
US20200343641A1 (en) | 2020-10-29 |
CN110223960A (zh) | 2019-09-10 |
US20190273321A1 (en) | 2019-09-05 |
CN110223960B (zh) | 2021-03-16 |
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