TWI678061B - Digital linear regulator and a power mos array thereof - Google Patents
Digital linear regulator and a power mos array thereof Download PDFInfo
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Abstract
一種適用於數位線性調節器的功率金屬氧化物半導體陣列,包含複數金屬氧化物半導體電路,每一金屬氧化物半導體電路包含第一金屬氧化物半導體電晶體與第二金屬氧化物半導體電晶體,其電性串聯於電源與數位線性調節器的輸出節點之間。第一金屬氧化物半導體電晶體作為電流源,受控於輸出節點的輸出電壓。A power metal oxide semiconductor array suitable for a digital linear regulator includes a plurality of metal oxide semiconductor circuits. Each metal oxide semiconductor circuit includes a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor. Electrically connected in series between the power supply and the output node of the digital linear regulator. The first metal oxide semiconductor transistor is used as a current source and is controlled by the output voltage of the output node.
Description
本發明係有關一種線性調節器,特別是關於一種具動態電流源功率金屬氧化物半導體(MOS)陣列的數位線性調節器。The invention relates to a linear regulator, in particular to a digital linear regulator with a dynamic current source power metal oxide semiconductor (MOS) array.
線性電壓調節器,例如低壓降(low-dropout)調節器為一種直流線性電壓調節器,可適用以調節輸出電壓。由於其尺寸小且設計簡單,因此普遍應用於單晶片系統(system on chip)以提供個別電壓。數位線性調節器由於其低壓操作,因此較佳應用於現代系統。A linear voltage regulator, such as a low-dropout regulator, is a DC linear voltage regulator that can be adapted to regulate the output voltage. Because of its small size and simple design, it is commonly used in single-chip systems (system on chip) to provide individual voltages. Digital linear regulators are preferred for modern systems due to their low voltage operation.
傳統數位線性調節器於非穩定的暫態(例如過衝(overshoot)或下衝(undershoot)電壓)時,由於其須等待下一時脈週期或/且類比至數位轉換(ADC)的轉換時間,因此回復較慢或消耗較大功率。一些數位線性調節器雖然具有改良的暫態回復或較小功耗,然而數位線性調節器會干擾相同接地的其他電路。When a traditional digital linear regulator is in an unstable transient state (such as overshoot or undershoot voltage), it must wait for the next clock cycle or / and the analog-to-digital conversion (ADC) conversion time. Therefore the reply is slower or consumes more power. Although some digital linear regulators have improved transient recovery or lower power consumption, digital linear regulators can interfere with other circuits with the same ground.
因此亟需提出一種新穎的數位線性調節器,以克服傳統數位線性調節器的缺失。Therefore, a novel digital linear regulator is urgently needed to overcome the lack of traditional digital linear regulators.
鑑於上述,本發明實施例的目的之一在於提出一種具動態電流源功率金屬氧化物半導體(MOS)陣列的數位線性調節器。In view of the foregoing, one object of the embodiments of the present invention is to provide a digital linear regulator with a dynamic current source power metal-oxide-semiconductor (MOS) array.
根據本發明實施例,適用於數位線性調節器的功率金屬氧化物半導體陣列包含複數金屬氧化物半導體電路。每一金屬氧化物半導體電路包含第一金屬氧化物半導體電晶體與第二金屬氧化物半導體電晶體,其電性串聯於電源與數位線性調節器的輸出節點之間。其中第一金屬氧化物半導體電晶體作為電流源,受控於輸出節點的輸出電壓。According to an embodiment of the present invention, a power metal oxide semiconductor array suitable for a digital linear regulator includes a plurality of metal oxide semiconductor circuits. Each metal oxide semiconductor circuit includes a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor, which are electrically connected in series between the power source and the output node of the digital linear regulator. The first metal oxide semiconductor transistor is used as a current source and is controlled by the output voltage of the output node.
第一A圖顯示本發明實施例之具動態電流源功率金屬氧化物半導體(MOS)陣列的數位線性調節器(regulator)100的方塊圖,第一B圖例示部分第一A圖的細部方塊圖。本實施例之數位線性調節器100可適用於單晶片系統(system on chip)以提供個別電壓。FIG. 1A shows a block diagram of a digital linear regulator 100 with a dynamic current source power metal-oxide semiconductor (MOS) array according to an embodiment of the present invention. FIG. 1B illustrates a detailed block diagram of part 1A . The digital linear regulator 100 of this embodiment is applicable to a system on chip to provide individual voltages.
在本實施例中,數位線性調節器100可包含微調迴路(fine-loop)控制器11及微調功率金屬氧化物半導體陣列(以下簡稱微調功率陣列)12。於穩態(steady state),數位線性調節器100的調節輸出電壓Vout為穩定的,微調迴路控制器11可開啟微調功率陣列12,其包含有複數微調功率金屬氧化物半導體電晶體,以產生輸出電壓Vout。負載10連接於輸出電壓Vout與地之間,以接收輸出電壓Vout。In this embodiment, the digital linear regulator 100 may include a fine-loop controller 11 and a fine-tuned power metal oxide semiconductor array (hereinafter referred to as a fine-tuned power array) 12. In a steady state, the regulated output voltage Vout of the digital linear regulator 100 is stable, and the trimming loop controller 11 can turn on the trimming power array 12, which includes a complex trimming power metal oxide semiconductor transistor to generate an output Voltage Vout. The load 10 is connected between the output voltage Vout and the ground to receive the output voltage Vout.
數位線性調節器100可包含粗調迴路(coarse-loop)控制器13及粗調功率金屬氧化物半導體陣列(以下簡稱粗調功率陣列)14。於暫態(transient state或不穩態),數位線性調節器100的調節輸出電壓Vout為不穩定的,粗調迴路控制器13可開啟粗調功率陣列14,其包含有複數粗調功率金屬氧化物半導體電晶體,以產生輸出電壓Vout。一般來說,粗調功率陣列14的粗調功率金屬氧化物半導體電晶體之尺寸大於微調功率陣列12的微調功率金屬氧化物半導體電晶體。The digital linear regulator 100 may include a coarse-loop controller 13 and a coarse-tuned power metal oxide semiconductor array (hereinafter referred to as a coarse-tuned power array) 14. In the transient state (transient state or unstable state), the regulated output voltage Vout of the digital linear regulator 100 is unstable. The coarse adjustment loop controller 13 can turn on the coarse adjustment power array 14, which includes complex coarse adjustment power metal oxidation. A semiconductor transistor to generate an output voltage Vout. Generally, the size of the coarse-tuned power metal oxide semiconductor transistor of the coarse-tuned power array 14 is larger than that of the fine-tuned power metal-oxide semiconductor transistor of the fine-tuned power array 12.
本實施例之數位線性調節器100可包含類比至數位轉換器(ADC)暨狀態電路15,用以進行類比至數位轉換,且根據輸出電壓Vout以決定數位線性調節器100的目前狀態(亦即穩態或暫態)。The digital linear regulator 100 in this embodiment may include an analog-to-digital converter (ADC) and a state circuit 15 for performing analog-to-digital conversion, and determine the current state of the digital linear regulator 100 according to the output voltage Vout (that is, Steady state or transient).
本實施例之類比至數位轉換器暨狀態電路15可包含比較器151,其接收數位線性調節器100的輸出電壓Vout與(預設)參考電壓Vref,據以產生比較信號V comp。類比至數位轉換器暨狀態電路15可包含類比至數位轉換器(ADC)152,用以產生(數位)類比至數位轉換輸出,其為輸出電壓Vout與參考電壓Vref的差值。類比至數位轉換器暨狀態電路15可包含狀態電路153,其根據類比至數位轉換輸出以產生事件信號ENT,以代表目前狀態。 The analog-to-digital converter and state circuit 15 of this embodiment may include a comparator 151 that receives the output voltage Vout of the digital linear regulator 100 and the (preset) reference voltage Vref to generate a comparison signal V comp . The analog-to-digital converter and state circuit 15 may include an analog-to-digital converter (ADC) 152 for generating a (digital) analog-to-digital conversion output, which is the difference between the output voltage Vout and the reference voltage Vref. The analog-to-digital converter and status circuit 15 may include a status circuit 153 that generates an event signal ENT according to the analog-to-digital conversion output to represent the current status.
本實施例之微調迴路控制器11主要包含微調迴路移位暫存器111,其接收比較信號V comp,據以產生微調移位輸出F。微調迴路移位暫存器111可包含串聯的正反器(flip flop)(未顯示於圖式),受控於第一時脈信號CLK_f。根據本實施例的特徵之一,微調迴路移位暫存器111可被事件信號ENT開啟,於穩態期間可節省功率。當事件信號ENT為非主動(de-asserted)時,表示輸出電壓Vout為穩定的穩態,則開啟微調迴路移位暫存器111。 The trimming loop controller 11 of this embodiment mainly includes a trimming loop shift register 111 that receives a comparison signal V comp and generates a trimming shift output F accordingly. The trimming loop shift register 111 may include a flip flop (not shown) connected in series, and is controlled by the first clock signal CLK_f. According to one of the features of this embodiment, the trimming loop shift register 111 can be turned on by the event signal ENT, which can save power during the steady state. When the event signal ENT is de-asserted, indicating that the output voltage Vout is stable and steady, the trimming loop shift register 111 is turned on.
本實施例之粗調迴路控制器13主要包含粗調迴路移位暫存器131,其接收比較信號V comp,據以產生粗調移位輸出C。粗調迴路移位暫存器131可接收類比至數位轉換輸出以加速位移。粗調迴路移位暫存器131可包含串聯的正反器(flip flop)(未顯示於圖式),受控於第二時脈信號CLK_c,其快於第一時脈信號CLK_f。根據本實施例的另一特徵,粗調迴路移位暫存器131可被事件信號ENT關閉,於穩態期間可節省功率。當事件信號ENT為主動(asserted)時,表示輸出電壓Vout為不穩定的暫態,則開啟粗調迴路移位暫存器131。另一方面,當事件信號ENT為非主動(de-asserted)時,表示輸出電壓Vout為穩定的穩態,則關閉粗調迴路移位暫存器131。 The coarse-tuning loop controller 13 in this embodiment mainly includes a coarse-tuning loop shift register 131, which receives a comparison signal Vcomp and generates a coarse-shift shift output C accordingly. The coarse-adjustment loop shift register 131 may receive an analog-to-digital conversion output to accelerate the shift. The coarse-tuning loop shift register 131 may include a flip flop (not shown) connected in series, and is controlled by the second clock signal CLK_c, which is faster than the first clock signal CLK_f. According to another feature of this embodiment, the coarse adjustment loop shift register 131 can be turned off by the event signal ENT, and power can be saved during the steady state. When the event signal ENT is asserted, indicating that the output voltage Vout is unstable, the coarse adjustment loop shift register 131 is turned on. On the other hand, when the event signal ENT is de-asserted, indicating that the output voltage Vout is stable and steady, the coarse-tuning loop shift register 131 is turned off.
第二A圖顯示第一A圖之微調功率陣列12的電路圖。微調功率陣列12(自微調迴路移位暫存器111)接收微調移位輸出F,據以產生輸出電壓Vout。在本實施例中,微調功率陣列12可包含複數併聯的金屬氧化物半導體電晶體M0,例如P型金屬氧化物半導體電晶體(PMOS),其源極分別電性連接至電源Vdd,其汲極分別電性連接至輸出節點,其提供輸出電壓Vout。金屬氧化物半導體電晶體M0的閘極分別電性連接微調移位輸出F的位元。The second A diagram shows a circuit diagram of the trimming power array 12 of the first A diagram. The trimming power array 12 (self-trimming loop shift register 111) receives the trimming shift output F, thereby generating an output voltage Vout. In this embodiment, the trimming power array 12 may include a plurality of metal oxide semiconductor transistors M0 in parallel, such as a P-type metal oxide semiconductor transistor (PMOS), whose sources are electrically connected to the power source Vdd and their drains, respectively. Each is electrically connected to an output node, which provides an output voltage Vout. The gates of the metal oxide semiconductor transistor M0 are respectively electrically connected to the bits of the trimming shift output F.
第二B圖顯示第一A圖之粗調功率陣列14的電路圖。粗調功率陣列14(自粗調迴路移位暫存器131)接收粗調移位輸出C,據以產生輸出電壓Vout。在本實施例中,粗調功率陣列14可包含複數金屬氧化物半導體電路141。根據本實施例的另一特徵,每一金屬氧化物半導體電路141可包含第一金屬氧化物半導體電晶體(例如P型金屬氧化物半導體電晶體)M1與第二金屬氧化物半導體電晶體(例如P型金屬氧化物半導體電晶體)M2,其電性串聯於電源Vdd與輸出節點(其提供輸出電壓Vout)之間。其中,第一金屬氧化物半導體電晶體M1的源極電性連接至電源Vdd,其汲極電性連接至第二金屬氧化物半導體電晶體M2的源極,其閘極電性連接至第二金屬氧化物半導體電晶體M2的汲極與輸出節點(其提供輸出電壓Vout)。第二金屬氧化物半導體電晶體M2的閘極分別電性連接粗調移位輸出C的位元。在另一實施例中,微調功率陣列12也可使用第二B圖的電路架構。The second B diagram shows a circuit diagram of the coarse-tuned power array 14 of the first A diagram. The coarse adjustment power array 14 (from the coarse adjustment loop shift register 131) receives the coarse adjustment shift output C, and generates an output voltage Vout accordingly. In this embodiment, the coarse-tuned power array 14 may include a plurality of metal oxide semiconductor circuits 141. According to another feature of this embodiment, each metal oxide semiconductor circuit 141 may include a first metal oxide semiconductor transistor (such as a P-type metal oxide semiconductor transistor) M1 and a second metal oxide semiconductor transistor (such as P-type metal oxide semiconductor transistor) M2, which is electrically connected in series between the power source Vdd and the output node (which provides the output voltage Vout). The source of the first metal oxide semiconductor transistor M1 is electrically connected to the power source Vdd, the drain thereof is electrically connected to the source of the second metal oxide semiconductor transistor M2, and the gate thereof is electrically connected to the second The drain and output node of the metal oxide semiconductor transistor M2 (which provides the output voltage Vout). The gates of the second metal oxide semiconductor transistor M2 are respectively electrically connected to the bits of the coarse-adjustment shift output C. In another embodiment, the trimming power array 12 may also use the circuit architecture of the second B diagram.
第二C圖顯示第二B圖之金屬氧化物半導體電路141的等效電路。在本實施例中,第一金屬氧化物半導體電晶體M1作為電流源,受控於輸出電壓Vout。第一金屬氧化物半導體電晶體M1提供源極至汲極電流I SD(M1),流向輸出節點(其提供輸出電壓Vout)。負載10因此得到負載電流I load,其包含所有金屬氧化物半導體電路141所提供的源極至汲極電流I SD(M1)。於上升(up)暫態時(亦即負載電流I load從低變為高),若輸出電壓Vout下降,則電流源(亦即第一金屬氧化物半導體電晶體M1)因阻抗減少而提供更多的源極至汲極電流I SD(M1),且輸出電壓Vout的下衝(undershoot)可減少。此外,輸出電壓Vout可因此於短時間從非穩定狀態回復。另一方面,於下降(down)暫態時(亦即負載電流I load從高變為低),若輸出電壓Vout上升,則電流源(亦即第一金屬氧化物半導體電晶體M1)因阻抗增加而提供更少的源極至汲極電流I SD(M1),且輸出電壓Vout的過衝(overshoot)可減少。此外,輸出電壓Vout可因此於短時間從非穩定狀態回復。 FIG. 2C shows an equivalent circuit of the metal oxide semiconductor circuit 141 of FIG. 2B. In this embodiment, the first metal oxide semiconductor transistor M1 is used as a current source and is controlled by the output voltage Vout. The first metal-oxide-semiconductor transistor M1 provides a source-to-drain current I SD (M1) and flows to an output node (which provides an output voltage Vout). The load 10 thus obtains a load current I load , which includes the source-to-drain current I SD (M1) provided by all the metal-oxide semiconductor circuits 141. In the up transient state (that is, the load current I load changes from low to high), if the output voltage Vout decreases, the current source (that is, the first metal oxide semiconductor transistor M1) provides more resistance due to the decrease in impedance. With multiple source-to-drain currents I SD (M1) , the undershoot of the output voltage Vout can be reduced. In addition, the output voltage Vout can be recovered from the unstable state in a short time. On the other hand, during the down transient state (that is, the load current I load changes from high to low), if the output voltage Vout rises, the current source (that is, the first metal oxide semiconductor transistor M1) due to the impedance It increases to provide less source-to-drain current I SD (M1) , and the overshoot of the output voltage Vout can be reduced. In addition, the output voltage Vout can be recovered from the unstable state in a short time.
第三圖顯示第一B圖之數位線性調節器100的相關信號的波形。於狀態1(亦即穩態),輸出電壓Vout為穩定,其振幅位於電壓視窗(Vref±ΔV)內。於穩態,關閉粗調迴路移位暫存器131,但開啟微調迴路移位暫存器111以啟動微調功率陣列12,用以提供輸出電壓Vout。一般來說,微調功率陣列12(及微調迴路移位暫存器111)較粗調功率陣列14(及粗調迴路移位暫存器131)的操作速度慢、消耗較少功率且產生較高輸出電壓精準度。由於微調功率陣列12(及微調迴路移位暫存器111)消耗較少功率,數位線性調節器100因此可以降低長期的功率消耗。The third figure shows the waveforms of the related signals of the digital linear regulator 100 in the first B figure. In state 1 (ie, steady state), the output voltage Vout is stable, and its amplitude is within the voltage window (Vref ± ΔV). In the steady state, the coarse-tuning loop shift register 131 is turned off, but the fine-tuning loop shift register 111 is turned on to enable the fine-tuning power array 12 to provide the output voltage Vout. In general, the fine-tuned power array 12 (and the fine-tuned loop shift register 111) is slower than the coarse-tuned power array 14 (and the coarse-tuned loop shift register 131), consumes less power, and generates higher power. Output voltage accuracy. Since the trimming power array 12 (and the trimming loop shift register 111) consumes less power, the digital linear regulator 100 can reduce long-term power consumption.
於狀態2(亦即暫態),輸出電壓Vout為不穩定,其過衝(overshoot)或下衝(undershoot)電壓超出電壓視窗(Vref±ΔV)。於暫態,關閉微調迴路移位暫存器111,但開啟粗調迴路移位暫存器131以啟動粗調功率陣列14,用以提供輸出電壓Vout。由於粗調功率陣列14(及粗調迴路移位暫存器131)的操作速度快,輸出電壓Vout因此可以於短時間從非穩定情況回復。In state 2 (ie, transient state), the output voltage Vout is unstable, and its overshoot or undershoot voltage exceeds the voltage window (Vref ± ΔV). In the transient state, the fine-tuning loop shift register 111 is closed, but the coarse-tuning loop shift register 131 is turned on to activate the coarse-adjustment power array 14 to provide the output voltage Vout. Because the operation speed of the coarse adjustment power array 14 (and the coarse adjustment circuit shift register 131) is fast, the output voltage Vout can be recovered from an unstable situation in a short time.
根據上述實施例,數位線性調節器100提供雙迴路控制機制以產生輸出電壓Vout。其中,於穩態,微調功率陣列12及微調迴路控制器11形成微調迴路,其具有較低的功耗與較高的輸出電壓精準度。另一方面,於暫態,粗調功率陣列14及粗調迴路控制器13形成粗調迴路,其具有較快的操作速度。According to the above embodiment, the digital linear regulator 100 provides a dual-loop control mechanism to generate the output voltage Vout. Among them, in the steady state, the trimming power array 12 and the trimming loop controller 11 form a trimming loop, which has lower power consumption and higher accuracy of output voltage. On the other hand, in the transient state, the coarse adjustment power array 14 and the coarse adjustment loop controller 13 form a coarse adjustment loop, which has a fast operating speed.
第四圖顯示第二B圖之粗調功率陣列14的相關信號的波形。根據本實施例之粗調功率陣列14的特徵之一,第一金屬氧化物半導體電晶體M1作為電流源,受控於輸出電壓Vout。第四圖的虛線顯示粗調功率陣列14未使用第一金屬氧化物半導體電晶體M1的相關信號的波形。根據本實施例,與數位線性調節器100相同接地的其他電路不會受到數位線性調節器100的干擾。The fourth graph shows the waveforms of the relevant signals of the coarse-tuned power array 14 of the second B graph. According to one of the features of the coarse-tuned power array 14 of this embodiment, the first metal oxide semiconductor transistor M1 is used as a current source and is controlled by the output voltage Vout. The dotted line in the fourth figure shows a waveform of a signal related to the coarse adjustment power array 14 without using the first metal oxide semiconductor transistor M1. According to this embodiment, other circuits that are grounded the same as the digital linear regulator 100 are not interfered by the digital linear regulator 100.
以上所述僅為本發明之較佳實施例而已,並非用以限定本發明之申請專利範圍;凡其它未脫離發明所揭示之精神下所完成之等效改變或修飾,均應包含在下述之申請專利範圍內。The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the invention should be included in the following Within the scope of patent application.
100‧‧‧數位線性調節器100‧‧‧ digital linear regulator
10‧‧‧負載 10‧‧‧ load
11‧‧‧微調迴路控制器 11‧‧‧Fine-tuning loop controller
111‧‧‧微調迴路移位暫存器 111‧‧‧Fine-tuning loop shift register
12‧‧‧微調功率金屬氧化物半導體陣列 12‧‧‧Fine-tuning power metal oxide semiconductor array
13‧‧‧粗調迴路控制器 13‧‧‧Coarse adjustment loop controller
131‧‧‧粗調迴路移位暫存器 131‧‧‧Coarse adjustment loop shift register
14‧‧‧粗調功率金屬氧化物半導體陣列 14‧‧‧Coarse-tuned power metal oxide semiconductor array
141‧‧‧金屬氧化物半導體電路 141‧‧‧ metal oxide semiconductor circuit
15‧‧‧類比至數位轉換器暨狀態電路 15‧‧‧ Analog to Digital Converter and State Circuit
151‧‧‧比較器 151‧‧‧ Comparator
152‧‧‧類比至數位轉換器 152‧‧‧ Analog to Digital Converter
MOS‧‧‧金屬氧化物半導體 MOS‧‧‧ Metal Oxide Semiconductor
Vout‧‧‧輸出電壓 Vout‧‧‧Output voltage
Vref‧‧‧參考電壓 Vref‧‧‧Reference voltage
Vcomp‧‧‧比較信號V comp ‧‧‧ comparison signal
ENT‧‧‧事件信號 ENT‧‧‧Event Signal
CLK_f‧‧‧第一時脈信號 CLK_f‧‧‧ the first clock signal
CLK_c‧‧‧第二時脈信號 CLK_c‧‧‧Second clock signal
F‧‧‧微調移位輸出 F‧‧‧fine-tuning shift output
C‧‧‧粗調移位輸出 C‧‧‧Coarse adjustment shift output
M0‧‧‧金屬氧化物半導體電晶體 M0‧‧‧ metal oxide semiconductor transistor
M1‧‧‧第一金屬氧化物半導體電晶體 M1‧‧‧The first metal oxide semiconductor transistor
M2‧‧‧第二金屬氧化物半導體電晶體 M2‧‧‧Second metal oxide semiconductor transistor
Vdd‧‧‧電源 Vdd‧‧‧ Power
ISD(M1)‧‧‧源極至汲極電流I SD (M1) ‧‧‧Source-to-drain current
Iload‧‧‧負載電流I load ‧‧‧ load current
第一A圖顯示本發明實施例之具動態電流源功率金屬氧化物半導體(MOS)陣列的數位線性調節器的方塊圖。 第一B圖例示部分第一A圖的細部方塊圖。 第二A圖顯示第一A圖之微調功率陣列的電路圖。 第二B圖顯示第一A圖之粗調功率陣列的電路圖。 第二C圖顯示第二B圖之金屬氧化物半導體電路的等效電路。 第三圖顯示第一B圖之數位線性調節器的相關信號的波形。 第四圖顯示第二B圖之粗調功率陣列的相關信號的波形。FIG. 1A shows a block diagram of a digital linear regulator with a dynamic current source power metal oxide semiconductor (MOS) array according to an embodiment of the present invention. The first B diagram illustrates a detailed block diagram of a part of the first A diagram. The second A diagram shows a circuit diagram of the fine-tuned power array of the first A diagram. The second diagram B shows a circuit diagram of the coarse-tuned power array of the first diagram A. Figure 2C shows the equivalent circuit of the metal oxide semiconductor circuit in Figure 2B. The third graph shows the waveforms of the related signals of the digital linear regulator of the first B graph. The fourth graph shows the waveforms of the relevant signals of the coarse-tuned power array of the second B graph.
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