TWI675416B - 半導體裝置之製造方法、熱處理裝置及記錄媒體 - Google Patents
半導體裝置之製造方法、熱處理裝置及記錄媒體 Download PDFInfo
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- TWI675416B TWI675416B TW106118172A TW106118172A TWI675416B TW I675416 B TWI675416 B TW I675416B TW 106118172 A TW106118172 A TW 106118172A TW 106118172 A TW106118172 A TW 106118172A TW I675416 B TWI675416 B TW I675416B
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- 238000010438 heat treatment Methods 0.000 title claims description 56
- 239000004065 semiconductor Substances 0.000 title claims description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 238000003860 storage Methods 0.000 title description 2
- 238000005530 etching Methods 0.000 claims abstract description 65
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 48
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 48
- 239000010703 silicon Substances 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 239000002245 particle Substances 0.000 claims abstract description 14
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 11
- 239000007789 gas Substances 0.000 claims description 92
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 claims description 62
- 229910000042 hydrogen bromide Inorganic materials 0.000 claims description 31
- 238000001312 dry etching Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- XMBWDFGMSWQBCA-UHFFFAOYSA-N hydrogen iodide Chemical compound I XMBWDFGMSWQBCA-UHFFFAOYSA-N 0.000 claims description 6
- 229910000043 hydrogen iodide Inorganic materials 0.000 claims description 5
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- 238000004590 computer program Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 abstract description 23
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- 229910017855 NH 4 F Inorganic materials 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
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- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
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- UOERHRIFSQUTET-UHFFFAOYSA-N N-propyl-N-silylpropan-1-amine Chemical compound CCCN([SiH3])CCC UOERHRIFSQUTET-UHFFFAOYSA-N 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- GYQWAOSGJGFWAE-UHFFFAOYSA-N azane tetrafluorosilane Chemical compound N.[Si](F)(F)(F)F GYQWAOSGJGFWAE-UHFFFAOYSA-N 0.000 description 1
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- 229910001220 stainless steel Inorganic materials 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/30608—Anisotropic liquid etching
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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Abstract
本發明提供一種於將由矽構成之導電路徑形成在基板所形成之凹部時,將導電性優良的矽膜加以成膜之技術。本發明係針對晶圓W而藉由異向性蝕刻使單晶矽層101露出,且此晶圓W在表面所形成之凹部110的下層形成有單晶矽層101,並在凹部110的底面及側面,自下層側而依此順成膜有SiN膜102、SiO2
膜103、第一Si膜104。再者,藉由濕式蝕刻去除第一Si膜104的表面的自然氧化膜後,藉由HBr氣體去除第一Si膜104的表面的雜質107及損傷層,其後將第二Si膜111加以成膜。因此,使第二Si膜111密接於SiO2
膜103、並以厚且均勻的膜厚形成。從而,加熱晶圓W時,第二Si膜111的粒子尺寸變大,且導電性良好。
Description
本發明係關於將由矽構成之導電路徑形成在基板的表面所形成之凹部內之技術。
為了對應於近年半導體元件的立體化,吾人對於半導體製造流程要求各種技巧。例如就將三維反及閘(3DNAND)的通道加以形成之程序而言,有下述程序: 在高縱橫比的凹部內將構成導電路徑之矽(例如多晶矽)膜加以成膜,且將此矽膜加以乾式蝕刻。就具體例而言,則係以下程序:在矽氧化層形成凹部,在凹部的底部形成單晶矽層,並利用矽膜覆蓋凹部內後,藉由乾式蝕刻即異向性蝕刻去除底部的矽膜而使單晶矽層露出。
乾式蝕刻後須去除乾式蝕刻時的殘渣,但例如專利文獻1、2所示之濕式蝕刻之中,當高縱橫比且凹部的剖面微小時,則不易將凹部內的矽膜沿深度方向以高均勻性蝕刻並去除蝕刻殘渣。雖然因此於殘留有蝕刻殘渣之狀態下直接在矽膜的表面進一步層疊相同的矽(例如多晶矽)膜,形成電性連接至單晶矽層之矽膜,但為了使矽膜的導電性良好,須進行退火而使矽的粒徑增大。粒徑視矽膜的膜厚越大則越增大,但在附著有蝕刻殘渣等雜質之矽膜的表面進一步形成矽膜時,會使膜厚少了雜質所佔有的大小,就結果而言會抑制粒徑之增大。
專利文獻3記載有使用氯(Cl2
)氣體之矽的乾式蝕刻流程。然而,於使用Cl2
氣體蝕刻晶圓所形成之凹部的內面之情況下,凹部的開口附近的蝕刻量變大,並會切除成V字狀,不易於深度方向維持高均勻性。再者,當作為蝕刻氣體使用之氯附著在壁面時,則有下述問題:於蝕刻後進一步將矽膜加以成膜時,矽會受到蝕刻,成膜速度降低,且成膜後之表面粗糙度惡化。 [先前技術文獻] [專利文獻]
[專利文獻1]日本專利第5813495號公報 [專利文獻2]日本特開2008-166513號公報 [專利文獻3]日本專利第5514162號公報
[發明所欲解決之問題] 本發明係鑒於如此事由而成者,其目的在於提供一種技術,於將由矽構成之導電路徑形成在基板所形成之凹部時,將導電性優良的矽膜加以成膜。 [解決問題之方式]
本發明之半導體裝置之製造方法,在基板上形成半導體裝置,其特徵為包括: 搬入程序,將對於基板上的凹部內所形成之矽膜的一部分加以乾式蝕刻後的該基板,搬入至處理容器內; 蝕刻程序,接著一邊加熱前述基板一邊將選自溴化氫氣體及碘化氫氣體之蝕刻氣體供給至真空環境的處理容器內,將殘留在前述凹部內的側壁之矽膜的一部分或全部加以去除; 成膜程序,然後在前述凹部內將矽膜加以成膜;以及 加熱程序,其後加熱基板,用以使前述矽膜的粒徑增大。
本發明之熱處理裝置,將半導體裝置製造用基板載置在用以形成真空環境之處理容器內所設置之載置部,且將處理容器內加以真空排氣並一邊加熱基板一邊供給處理氣體而針對基板進行熱處理,其特徵為, 具備控制部,係輸出控制信號俾執行下述步驟: 搬入步驟,將對於基板上的凹部內所形成之矽膜的一部分加以乾式蝕刻後的該基板,搬入至前述處理容器內; 蝕刻步驟,接著一邊加熱前述基板一邊將選自溴化氫氣體及碘化氫氣體之蝕刻氣體供給至真空環境的處理容器內,而將殘留在前述凹部內的側壁之矽膜的表面部的蝕刻殘渣或該矽膜加以去除; 成膜步驟,然後在前述凹部內將矽膜加以成膜;以及 加熱步驟,其後加熱基板,用以使前述矽膜的粒徑增大。
本發明之記錄媒體,記錄有使用於熱處理裝置之電腦程式,前述熱處理裝置將半導體裝置製造用基板載置在用以形成真空環境之處理容器內所設置之載置部,且將處理容器內加以真空排氣並一邊加熱基板一邊供給處理氣體,而針對基板進行熱處理,前述記錄媒體之特徵為, 前述電腦程式編入有步驟群,俾執行前述半導體裝置之製造方法。 [發明之效果]
本發明將基板上的凹部內所形成之矽膜的一部分加以乾式蝕刻,藉以利用選自溴化氫氣體及碘化氫氣體之蝕刻氣體,將殘留在凹部內的側壁、且表面附著有蝕刻殘渣之矽膜的一部分或全部加以去除。因此,因為將表面附著有雜質之矽膜沿深度方向以高均勻性去除,所以能於其後的成膜程序將矽膜以厚的膜厚形成在凹部的內面。從而,加熱基板並將矽膜退火後,矽膜的粒子的尺寸變大,且導電性良好。
[實施發明之較佳形態] (第一實施形態) 說明第一實施形態之半導體裝置之製造方法所使用之半導體裝置製造用基板即晶圓W的表面構造的一例。圖1顯示半導體裝置之製造程序的中途階段之晶圓W的表面構造。此表面構造之中,矽氧化層(SiO2
層)100形成有凹部110,且單晶矽層101位在凹部110的下方。在凹部110的內周面,從下層側而依此順而將矽氮化膜(SiN膜)102、矽氧化膜(SiO2
膜)103、及多晶矽即第一矽(Si)膜104加以成膜。
再者,將晶圓W的表面藉由例如CMP(Chemical Mechanical Polishing;化學機械研磨)研磨,去除表面的SiN膜102、SiO2
膜103、及第一Si膜104而露出SiO2
層100。圖1顯示研磨後之晶圓W的表面構造。此外,晶圓W中未形成凹部110之區域埋入有SiN層105。矽氮化膜理論上係以Si3
N4
表示,但本案說明書省略記載為「SiN膜」。如上所述而形成之凹部110(第一Si膜104所圍繞的部分)的縱橫比(深度/線寬)例如係50~150。
將上述晶圓W運送至乾式蝕刻裝置。乾式蝕刻裝置之中,如圖2所示,於真空環境下,藉由處理氣體的電漿依序蝕刻形成在凹部110的底部之第一Si膜104、SiO2
膜103、及SiN膜102,而使形成在凹部110的下方之單晶矽層101露出。因為一連串的蝕刻係以異向性蝕刻進行,所以形成在凹部110的側壁之第一Si膜104不受去除而殘留。又,凹部110的側面(第一Si膜104的表面)附著有蝕刻時出現之殘渣107,且凹部110的底面(單晶矽層101的露出面)因為蝕刻處理後接觸大氣環境,所以形成有自然氧化膜。所以,於將晶圓W搬入至後述立式熱處理裝置之預定時間內,將晶圓W搬入至例如公知之進行濕式蝕刻之液處理裝置。
針對搬入至液處理裝置之晶圓W,如圖3所示例如供給稀氫氟酸液(HF),藉此,由HF進行蝕刻,而去除形成在凹部110的內面之自然氧化膜,特別係成為導電路徑的電阻之單晶矽層101的表面的自然氧化膜。就蝕刻處理之技術而言,列舉一邊使晶圓W吸附在旋轉夾盤而旋轉一邊從上方的噴嘴將蝕刻液供給至晶圓W之技術、或將複數枚晶圓W一起浸漬至貯存有HF之蝕刻槽之技術等。
其後,將晶圓W例如運送至後述立式熱處理裝置,進行第一Si膜104之蝕刻、第二Si膜之成膜、及加熱退火之各流程,其中,各流程的詳細條件係於立式熱處理裝置的動作說明處詳述。首先,如圖4所示,針對晶圓W提供HBr氣體且一併以例如550℃加熱。如後述檢驗試驗1所示,HBr將形成在凹部110的側壁之第一Si膜104沿凹部110的深度方向以高均勻性蝕刻。從而,將凹部110的側壁所附著有之蝕刻殘渣107或靠近表面之蝕刻時的損傷層(因曝露於蝕刻氣體成分而變粗糙的層),沿凹部110的深度方向以高均勻性去除。又,如後述檢驗試驗2所示,HBr氣體能將Si相對於SiO2
及SiN而以極高的選擇性蝕刻。因此,不實質蝕刻第一Si膜104的下層的SiO2
膜103、或SiN膜102。藉此,如圖5所示,凹部110成為已去除第一Si膜104之狀態。
其後,於真空環境下,例如以450℃以上之流程溫度將多晶矽即第二Si膜111加以成膜。凹部110的側面露出有SiO2
膜103,凹部110的底面露出有單晶矽層101。 如圖6所示,使第二Si膜111密接於SiO2
膜103及單晶矽層101而成膜。
再者,將晶圓W加熱至例如450~950℃,而如圖7所示,使第二Si膜111內的Si的粒徑增大。圖7中之元件符號112所示之部分表示加熱後之粒徑已增大狀態之第二Si膜。如此,在凹部110內構成由多晶矽(第二Si膜112)形成之例如NAND電路的通道(導電路徑)。此外,其後將晶圓W運送至例如CMP裝置,去除晶圓W的表面的Si膜,露出SiO2
層100。
本發明之實施形態之半導體裝置之製造方法,係由例如包括已述之液處理裝置、及立式熱處理裝置之半導體製造系統進行,其中,此立式熱處理裝置進行第一Si膜104之蝕刻、第二Si膜111之成膜、及第二Si膜111之退火化。在此,說明立式熱處理裝置及使用此裝置的流程之例。如圖8所示,立式熱處理裝置1具備構成為沿垂直方向延伸之具有頂壁之圓筒形之石英製的反應容器2。反應容器2具備:圓筒狀的內管3;以及具有頂壁之圓筒形的外管4,設置成覆蓋內管3,且配置成與內管3隔著間隙。又,反應容器2的周圍係由絕熱體12圍繞,且絕熱體12的內面橫跨全周而設有用以加熱晶圓W之昇溫用加熱器13。
外管4的下方設有與外管4氣密連接之不鏽鋼製的筒狀的分岐裝置5,且分岐裝置5的下端形成有凸緣7。又,分岐裝置5的內側形成有環狀的支持部6,且連接有已述內管3的下端。凸緣7所圍繞之區域係作為基板搬入出口8而開口,且藉由石英製之圓形的蓋體9而氣密閉合。蓋體9的中央部以沿垂直方向(縱向)延伸之方式支持有:基板保持部即晶舟10,構成為將晶圓W沿垂直方向隔著間隔而載置的櫃架狀。
蓋體9構成為藉由舟昇降裝置11而自由昇降,且當使舟昇降裝置11下降時,則蓋體9從凸緣7離開而將基板搬入出口8開放,且一併使晶舟10下降至將晶圓W加以收納之高度位置為止。而且,將晶圓W收納至晶舟10後,使舟昇降裝置11上昇,藉以使晶舟10上昇至圖8所示之反應容器2內的高度位置為止,且一併使蓋體9接觸凸緣7,將基板搬入出口8氣密封堵。
分岐裝置5中之支持部6的上方側的側面開口有排氣口15,且排氣口15經由排氣管17而連接有真空排氣部19。此外,插設於排氣管17的元件18係閥。 又,分岐裝置5中支持部6的下方側的側面連接有蝕刻氣體供給管20、三支成膜氣體供給管21~23、及吹洗氣體供給管33的一端。蝕刻氣體供給管20的另一端側連接有蝕刻氣體即HBr氣體供給源24,成膜氣體供給管21~23的另一端側各連接有二丙基胺基矽烷(DIPAS)氣體供給源25、乙矽烷(Si2
H6
)供給源26、及甲矽烷(SiH4
)氣體供給源27。又,吹洗氣體供給管33的另一端側連接有吹洗氣體即氮(N2
)氣體供給源34。此外,圖8中的元件29~32、36係流量調整部,元件V1~V5係閥。
又,立式熱處理裝置1設有例如由電腦構成之控制部90。此控制部90具備由程式、記憶體、CPU(Central Processing Unit;中央處理器)構成之資料處理部等,且程式編入有命令(各步驟),其中,前述命令(各步驟)使控制信號從控制部90送往立式熱處理裝置1的各部,用以進行例如執行蝕刻處理、或成膜處理之各步驟。 此程式存放在電腦記錄媒體,例如軟碟、光碟、硬碟、MO(磁光碟)等記憶部,而安裝在控制部90。
說明上述立式熱處理裝置1的作用。將例如已由濕式蝕刻而去除自然氧化膜之晶圓W,於例如濕式蝕刻後在預定設定之時間內載置在晶舟10,並搬入反應容器2內。其次,將晶圓W加熱至250~750℃例如550℃,且一併將反應容器2內的壓力設定為0.1~400Torr例如20Torr(2666Pa),將HBr氣體以50~5000sccm例如500sccm之流量供給。HBr氣體係從支持部6的下方而在內管3的內側上昇並供給至晶圓W,且經由內管3與外管4之間隙,而自排氣口15排氣。此結果,將晶圓W上的第一Si膜104加以蝕刻而去除。
然後,停止HBr氣體之供給,且一併供給惰性氣體例如氮氣,而將反應容器2內替換成惰性氣體例如氮氣。又,將晶圓W的溫度設定為380℃,且一併將反應容器2內的壓力設定為1Torr(133Pa)。其後,停止N2
氣體之供給,且將胺基矽烷系氣體例如DIPAS氣體以200sccm的流量供給至反應容器2內。藉此,在晶圓W的表面形成Si的核即晶種層。
其次,停止DIPAS氣體之供給,將Si2
H6
氣體以350sccm的流量供給至反應容器2內。藉此,使晶圓W的表面所形成之晶種層成長,且使第二Si膜111成長至例如20Å的膜厚。然後,停止Si2
H6
氣體之供給,將晶圓W的溫度設定為470℃、反應容器2內的壓力設定為0.45Torr(60Pa)後,以1500sccm的流量供給SiH4
氣體。藉此,將Si進一步層疊在晶圓W的表面所形成之第二Si膜111,並使第二Si膜111的膜厚成長至例如150Å。 而且,停止SiH4
氣體之供給,將N2
氣體流往反應容器2內,停止Si膜之成膜,且一併將晶圓W以450~950℃例如550℃加熱。藉此,第二Si膜112之中,Si的粒徑增大。
依據上述實施形態,對於圖2所示之膜構造,藉由HBr氣體蝕刻多晶矽即第一Si膜104,因此即使係高縱橫比的凹部110,亦能沿深度方向以高均勻性進行蝕刻。而且如同上述,HBr氣體能相對於SiO2
及SiN而將Si以極高的選擇性加以蝕刻。因此,抑制第一Si膜104的下層的SiO2
膜103、或SiN膜102之蝕刻(不實質蝕刻)。 又,如後述檢驗試驗3所示,由於第二Si膜111的膜厚變厚,而有Si的結晶尺寸變大之傾向。上述實施形態之中,因為未夾雜有蝕刻殘渣等雜質層,所以相應使得第二Si膜111的膜厚變厚,且加熱晶圓W時,於加熱後結晶化的第二Si膜112之中,Si的結晶尺寸變大。因此,得到高導電性。
再者,如檢驗試驗4所示,藉由HBr氣體去除第一Si膜104後,不會有以下情況:將第二Si膜111加以成膜時,第二Si膜111的成膜速度變慢、或第二Si膜111的表面粗糙度惡化。 又,能同樣在立式熱處理裝置1中進行以下程序:去除程序,去除第一Si膜104的表面的雜質107及損傷層;成膜程序,將第二Si膜111加以成膜;以及結晶化程序,加熱晶圓W而使第二Si膜112結晶化。因此,能抑制晶圓W運送之際之有機物之附著、或自然氧化膜之產生。
(第二實施形態) 又,就第二實施形態之半導體裝置之製造方法而言,可藉由乾式蝕刻去除第一Si膜104的表面的自然氧化膜,再者亦可在立式熱處理裝置1內進行乾式蝕刻。例如圖9所示,構成為將HF氣體及NH3
氣體供給至立式熱處理裝置1。此外,圖9簡單記載有圖8所示之立式熱處理裝置1,HF氣體及NH3
氣體係供給至例如圖8所示之分岐裝置5中之支持部6的下方側。
第二實施形態之中,將圖2所示之異向性蝕刻後之晶圓W搬入至圖9所示之立式熱處理裝置1。而且,將HF氣體及NH3
氣體供給至反應容器2內。藉此,HF及NH3
吸附在晶圓W中之凹部110內的自然氧化膜的表面。因為此等氣體與自然氧化膜(SiO2
)反應且產生(NH4
)2
SiF6
(矽氟化銨),所以加熱晶圓而使此(NH4
)2
SiF6
昇華,藉以去除自然氧化膜。只要其後進行HBr氣體之供給所行之第一Si膜104的損傷層之蝕刻,且其後再進行第二Si膜111之成膜即可。第二實施形態之中,於進行自然氧化膜之去除後,能不將晶圓W從裝置取出而進行HBr氣體之供給所行之第一Si膜104的損傷層之蝕刻,且其後進行第二Si膜111之成膜。因此,能抑制將晶圓W在裝置間運送之際的有機物之附著、或自然氧化膜之產生。
再者,能使用將含有氮、氫、氟之化合物加以包含之處理氣體例如氟化銨(NH4
F)氣體而蝕刻Si的自然氧化膜,於此情況下,前述氣體亦與Si的自然氧化膜反應而產生(NH4
)2
SiF6
。從而,於蝕刻Si的自然氧化膜之際,亦可供給氟化銨(NH4
F)(或NH4
FHF)氣體。此外,處理氣體亦可係NH3
氣體、HF氣體、及NH4
F(或NH4
FHF)氣體之混合氣體。
再者,關於HBr之供給所行之第一Si膜104之去除,亦可僅去除第一Si膜104附著有蝕刻殘渣107、且將因異向性蝕刻而受到損傷之損傷層加以包含之表層部分,而殘留第一Si膜104的一部分。又,於去除第一Si膜104中之損傷層及包含雜質之層之際,即使使用碘化氫(HI)氣體取代HBr氣體,亦可期待同樣的效果。
(檢驗試驗1) 為了檢驗本發明之效果,吾人調查:使用HBr氣體而將在晶圓W的SiO2
層100所形成之凹部110內成膜之第一Si膜104加以蝕刻時之凹部110的深度方向中之蝕刻量的均勻性。使用下述晶圓:係如圖10(a)所示,在晶圓W形成有深度1500nm、寬度40nm的大小之凹部110,且表面成膜有第一Si膜104。
針對晶圓W,使用第一實施形態所示之立式熱處理裝置1,且使用HBr氣體進行蝕刻,並在高度位置P1~P5之五處測量蝕刻量。P1表示晶圓W的表面,P2~P4各別表示從凹部110的側壁中之晶圓W的表面的高度往凹部110的深度方向300 nm、600nm、900nm、及1200nm之高度位置。 圖10(b)表示此結果,且顯示在各晶圓W測量之於P1~P5各高度位置中之依P1 ~P5所各自平均的蝕刻量之値。依據此結果,則晶圓W的表面的P1中之蝕刻量係4.25Å,且當將P1的蝕刻量定為100時,則凹部110的內部之P2~P4的蝕刻量係95.3~ 110.9。
如由此結果得知,吾人可說,使用HBr氣體蝕刻凹部110的側壁所形成之Si膜104,而能藉以沿凹部110的深度方向均勻蝕刻。
(檢驗試驗2) 又,為了檢驗本發明之效果,吾人調查HBr氣體所行之Si膜、SiO2
膜、及SiN膜之蝕刻的選擇比。首先,在檢查用晶圓的表面將Si膜、SiO2
膜、及SiN膜各別成膜,且使用第一實施形態所示之立式熱處理裝置1並以550℃加熱而供給HBr氣體進行蝕刻。又,以530℃加熱形成有Si膜之檢查用晶圓,並供給HBr氣體而進行蝕刻。
圖11表示此結果,且顯示與檢查用晶圓的加熱溫度相對之Si膜、SiO2
膜、及SiN膜的蝕刻速度(Å/分)。於將檢查用晶圓以550℃加熱而進行蝕刻之情況下,Si膜受到蝕刻,但SiO2
膜及SiN膜幾乎未受到蝕刻(未受到實質蝕刻)。又,於將檢查用晶圓以550℃加熱之情況下,Si膜亦受到大程度蝕刻。依據此結果,則可說於加熱晶圓W而供給HBr氣體時,能將Si層以相對於SiO2
膜及SiN膜高的選擇比蝕刻。
(檢驗試驗3) 再者,吾人調查在檢查用晶圓將Si膜加以成膜並進行加熱使Si結晶化時之Si膜的膜厚與結晶的大小之關係。藉由第一實施形態所示之立式熱處理裝置1而將成膜為400Å及1500Å之檢查用晶圓各以550℃加熱,調查各粒子尺寸。圖12表示此結果,且係顯示已成膜之Si膜的膜厚與Si的結晶的大小之關係之特性圖。吾人可知隨著圖12所示Si膜的膜厚變厚,而Si的結晶的尺寸變大。
(檢驗試驗4) 視乾式蝕刻氣體的種類,有時因蝕刻後殘存在晶圓W之氣體的成分,而在蝕刻後成膜之膜觀察到表面的粗糙度之劣化等劣化。所以,將第一次之Si膜加以成膜在檢查用晶圓後,藉由HBr氣體蝕刻全部的Si膜後,進行第二次之Si層之成膜並調查表面粗糙度及已成膜之Si膜的膜厚。 第一次之Si層之成膜,係使用第一實施形態所示之立式熱處理裝置1,並將5.0nm設定為目標膜厚而成膜。其次,在相同的立式熱處理裝置1內,供給HBr氣體而全部去除Si層後,在相同的立式熱處理裝置1內,將3.5nm設定為目標膜厚而將Si膜加以成膜。
於第一次之Si膜之成膜,Si膜係成膜為5.1nm,且表面粗糙度Ra係0.167。而且,將第一次之Si膜加以蝕刻後之表面粗糙度Ra係0.198,且於第二次之Si膜之成膜,Si膜係成膜為3.62nm,且表面粗糙度Ra係0.141。 依據此結果,則於進行HBr所行之蝕刻並再次將Si加以成膜時,表面粗糙度Ra未降低。又,Si層的膜厚亦以約略目標膜厚成膜,藉由HBr蝕刻Si膜後成膜效率亦不降低。
1‧‧‧立式熱處理裝置
2‧‧‧反應容器
3‧‧‧內管
4‧‧‧外管
5‧‧‧分岐裝置
6‧‧‧支持部
7‧‧‧凸緣
8‧‧‧基板搬入出口
9‧‧‧蓋體
10‧‧‧晶舟
11‧‧‧舟昇降裝置
12‧‧‧絕熱體
13‧‧‧昇溫用加熱器
15‧‧‧排氣口
17‧‧‧排氣管
18‧‧‧閥
19‧‧‧真空排氣部
20‧‧‧蝕刻氣體供給管
21~23‧‧‧成膜氣體供給管
24‧‧‧HBr氣體供給源
25‧‧‧二丙基胺基矽烷(DIPAS)氣體供給源
26‧‧‧乙矽烷(Si2
H6
)供給源
27‧‧‧甲矽烷(SiH4
)氣體供給源
29~32‧‧‧流量調整部
33‧‧‧吹洗氣體供給管
34‧‧‧吹洗氣體供給源(氮(N2
)氣體供給源)
36‧‧‧流量調整部
90‧‧‧控制部
100‧‧‧SiO2
層
101‧‧‧單晶矽
102‧‧‧SiN膜
103‧‧‧SiO2
膜
104‧‧‧第一Si膜
105‧‧‧SiN層
107‧‧‧殘渣(雜質)
110‧‧‧凹部
111‧‧‧第二Si膜
112‧‧‧第二Si膜
V1~V5‧‧‧閥
W‧‧‧晶圓
【圖1】係將第一實施形態之晶圓的表面附近加以顯示之剖面圖。 【圖2】係將異向性蝕刻後之晶圓的表面附近加以顯示之說明圖。 【圖3】係將凹部內之自然氧化膜之去除加以示意性顯示之說明圖。 【圖4】係將第一Si膜之去除加以示意性顯示之說明圖。 【圖5】係將已進行第一Si膜之去除之晶圓的表面附近加以顯示之剖面圖。 【圖6】係將第二Si成膜後之晶圓的表面附近加以顯示之剖面圖。 【圖7】係將退火處理後之晶圓的表面附近加以顯示之剖面圖。 【圖8】係將立式熱處理裝置加以顯示之剖面圖。 【圖9】係將第二實施形態之立式熱處理裝置加以顯示之剖面圖。 【圖10】(a)、(b)係將凹部的深度方向之蝕刻量加以顯示之特性圖。 【圖11】係將HBr氣體所行之蝕刻速度加以顯示之特性圖。 【圖12】係將Si膜的膜厚與粒子尺寸之關係加以顯示之特性圖。
Claims (10)
- 一種半導體裝置之製造方法,在基板上形成半導體裝置,其特徵為包含: 搬入程序,將已經對於基板上的凹部內所形成之矽膜的一部分加以乾式蝕刻後的該基板,搬入至處理容器內; 蝕刻程序,接著一邊加熱該基板一邊將選自溴化氫氣體及碘化氫氣體之蝕刻氣體供給至真空環境的處理容器內,而將殘留在該凹部內的側壁之矽膜的一部分或全部加以去除; 成膜程序,然後在該凹部內將矽膜加以成膜;以及 加熱程序,其後加熱基板,以使該矽膜的粒徑增大。
- 如申請專利範圍第1項之半導體裝置之製造方法,其中, 該搬入至處理容器內之基板,其矽氧化膜的一部分係露出。
- 如申請專利範圍第1或2項之半導體裝置之製造方法,其中, 該搬入至處理容器內之基板,其矽氮化膜的一部分係露出。
- 如申請專利範圍第1項之半導體裝置之製造方法,其中, 該搬入至處理容器之基板的凹部的底面露出有單晶矽,且該單晶矽與該矽膜一併形成導電路徑。
- 如申請專利範圍第1項之半導體裝置之製造方法,其中, 該蝕刻程序、該成膜程序、及該加熱程序係在同一該處理容器內依序進行。
- 如申請專利範圍第1項之半導體裝置之製造方法,其中, 於該蝕刻程序之前,施行在同一該處理容器內進行化學氧化物移除(COR;Chemical Oxide Removal)處理之程序。
- 如申請專利範圍第1項之半導體裝置之製造方法,其中, 該蝕刻程序的流程溫度係設定為250℃~750℃。
- 一種熱處理裝置,將半導體裝置製造用基板載置在用以形成真空環境之處理容器內所設置之載置部,將處理容器內加以真空排氣並一邊加熱基板一邊供給處理氣體而針對基板進行熱處理,其特徵為, 具備控制部,係輸出控制信號俾執行下述步驟: 搬入步驟,將對於基板上的凹部內所形成之矽膜的一部分加以乾式蝕刻後的基板,搬入至該處理容器內; 蝕刻步驟,接著一邊加熱該基板一邊將選自溴化氫氣體及碘化氫氣體之蝕刻氣體供給至真空環境的處理容器內,而將殘留在該凹部內的側壁之矽膜的表面部的蝕刻殘渣或該矽膜加以去除; 成膜步驟,然後在該凹部內將矽膜加以成膜;以及 加熱步驟,其後加熱基板,以使該矽膜的粒徑增大。
- 如申請專利範圍第8項之熱處理裝置,其中, 該控制部於執行該搬入步驟後,於該蝕刻步驟前更進行化學氧化物移除(COR;Chemical Oxide Removal)步驟。
- 一種記錄媒體,記錄有用於熱處理裝置之電腦程式,該熱處理裝置係將半導體裝置製造用基板載置在用以形成真空環境之處理容器內所設置之載置部,且將處理容器內加以真空排氣並一邊加熱基板一邊供給處理氣體,而針對基板進行熱處理,該記錄媒體之特徵為, 該電腦程式編入有步驟群,俾執行申請專利範圍第1至7任一項之半導體裝置之製造方法。
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US20170358458A1 (en) | 2017-12-14 |
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JP6623943B2 (ja) | 2019-12-25 |
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