TWI675361B

TWI675361B - Display device

Info

Publication number: TWI675361B
Application number: TW107110422A
Authority: TW
Inventors: 林雅婷; 洪銘皓
Original assignee: 友達光電股份有限公司
Priority date: 2018-03-27
Filing date: 2018-03-27
Publication date: 2019-10-21
Also published as: TW201942894A

Abstract

一種顯示裝置，包括第一驅動電路、第二驅動電路及多個畫素。第一驅動電路提供依序的多個掃描信號。第二驅動電路提供多個致能發光信號。多個畫素分別包括發光元件、限流電路及致能電晶體。限流電路接收多個掃描信號的第一掃描信號，並反應於第一掃描信號接收資料電壓，以反應於資料電壓提供驅動電流。致能電晶體接收多個致能發光信號的第一致能發光信號，以反應於第一致能發光信號將驅動電流提供至發光元件。其中，多個致能發光信號的脈波寬度反應於多個畫素內的多個節點的電壓而動態調整。A display device includes a first driving circuit, a second driving circuit, and a plurality of pixels. The first driving circuit provides a plurality of sequential scanning signals. The second driving circuit provides a plurality of enabling light-emitting signals. The plurality of pixels include a light emitting element, a current limiting circuit, and an enabling transistor, respectively. The current-limiting circuit receives a first scan signal of the plurality of scan signals, receives a data voltage in response to the first scan signal, and provides a driving current in response to the data voltage. The enabling transistor receives the first enabling light-emitting signals of the plurality of enabling light-emitting signals, and provides a driving current to the light-emitting element in response to the first enabling light-emitting signals. The pulse widths of the plurality of enabled light-emitting signals are dynamically adjusted in response to the voltages of the plurality of nodes in the plurality of pixels.

Description

顯示裝置Display device

本發明是有關於一種顯示裝置，且特別是有關於一種可以動態調整致能發光信號的發光時間長度的顯示裝置。 The present invention relates to a display device, and more particularly, to a display device capable of dynamically adjusting a light emitting time length of an enabled light emitting signal.

近年來，發光二極體顯示器已成為國內外非常熱門的新興平面顯示器產業，因發光二極體顯示器具有自主發光、廣視角、反應時間快、高發光效率、低操作電壓以及面板厚度薄等特性，並且可製作大尺寸、有可撓曲性面板加上其製程簡單，因此，具備有效降低成本的潛力。 In recent years, light emitting diode displays have become a very popular emerging flat display industry at home and abroad, because light emitting diode displays have the characteristics of autonomous light emission, wide viewing angle, fast response time, high luminous efficiency, low operating voltage, and thin panel thickness. And, it can make large-size, flexible panels and its simple process, so it has the potential to effectively reduce costs.

而目前驅動發光元件的方式，主要分為以電流直接驅動的方式以及電壓轉電流的驅動方式。其中，以電流直接驅動發光元件的方式，其開發上較為困難並且成本較高。而以電壓轉電流來驅動發光元件的方式，則需先經由薄膜電晶體將電壓轉換成電流來驅動發光元件。雖然，電壓轉電流方式易受到電晶體臨界電壓(Threshold Voltage，Vth)的影響而造成畫面亮度不均的問題，但仍是目前有機發光二極體(OLED)畫素陣列或者是微型發光二極體(μLED)畫素陣列時常採用的驅動方式。因此，如何提高發光二極體面板的發光均勻度則成為一個重要的課題。 The current methods of driving light-emitting elements are mainly divided into a direct-current driving method and a voltage-to-current driving method. Among them, the method of directly driving the light-emitting element with electric current is difficult and expensive to develop. In the method of driving a light-emitting element by voltage-to-current driving, a voltage is first converted to a current through a thin-film transistor to drive the light-emitting element. Although the voltage-to-current method is susceptible to the problem of uneven screen brightness caused by the threshold voltage (Threshold Voltage, Vth) of the transistor, it is still currently an organic light-emitting diode (OLED) pixel array or a micro-light-emitting diode. Volume (μLED) pixel array is often used to drive. So how to improve hair The light emitting uniformity of the photodiode panel has become an important issue.

本發明提供一種顯示裝置，能夠動態調整致能發光信號的發光時間比例，使顯示裝置於低灰階時具有效補償機制，並可改善發光效率及發光均勻度，以避免增加功耗及延長元件壽命。 The invention provides a display device, which can dynamically adjust the light-emitting time ratio of an enabled light-emitting signal, so that the display device has an effect compensation mechanism at a low gray level, and can improve light-emitting efficiency and light-emitting uniformity to avoid increasing power consumption and extending components. life.

本發明的顯示裝置包括第一驅動電路、第二驅動電路及多個畫素。第一驅動電路用以提供依序致能的多個掃描信號。第二驅動電路用以提供多個致能發光信號。多個畫素分別包括發光元件、限流電路以及致能電晶體。限流電路耦接第一驅動電路，以接收多個掃描信號的第一掃描信號，並且反應於第一掃描信號接收資料電壓，以反應於資料電壓提供驅動電流。致能電晶體耦接於發光元件及限流電路之間，並且接收多個致能發光信號的第一致能發光信號，以反應於第一致能發光信號將驅動電流提供至發光元件。其中，多個致能發光信號的脈波寬度反應於多個畫素內的多個節點的電壓而動態調整。 The display device of the present invention includes a first driving circuit, a second driving circuit, and a plurality of pixels. The first driving circuit is configured to provide a plurality of scanning signals that are sequentially enabled. The second driving circuit is used for providing a plurality of enabling light-emitting signals. The plurality of pixels each include a light emitting element, a current limiting circuit, and an enabling transistor. The current limiting circuit is coupled to the first driving circuit to receive a first scanning signal of a plurality of scanning signals, and receives a data voltage in response to the first scanning signal, and provides a driving current in response to the data voltage. The enabling transistor is coupled between the light-emitting element and the current-limiting circuit, and receives a first enabling light-emitting signal of a plurality of enabling light-emitting signals to provide a driving current to the light-emitting element in response to the first enabling light-emitting signal. The pulse widths of the plurality of enabled light-emitting signals are dynamically adjusted in response to the voltages of the plurality of nodes in the plurality of pixels.

基於上述，本發明實施例的顯示裝置可以多個畫素中的多個節點電壓來動態調整致能發光信號的脈波寬度，進而動態調整發光時間的比例，使顯示裝置於低灰階時具有效補償機制，並且改善整體發光效率與平衡發光均勻度，以避免增加功耗及延長元件壽命。 Based on the above, the display device of the embodiment of the present invention can dynamically adjust the pulse wave width of the enabled light-emitting signal by using multiple node voltages in multiple pixels, and then dynamically adjust the proportion of the light-emitting time, so that the display device can have Effective compensation mechanism, and improve the overall luminous efficiency and balance luminous uniformity, to avoid increasing power consumption and extending component life.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 In order to make the above features and advantages of the present invention more comprehensible, the following enumerated The embodiments will be described in detail with the accompanying drawings.

100‧‧‧顯示裝置 100‧‧‧ display device

110‧‧‧第一驅動電路 110‧‧‧first drive circuit

120‧‧‧第二驅動電路 120‧‧‧Second driving circuit

130‧‧‧時序控制器 130‧‧‧sequence controller

131‧‧‧控制電路 131‧‧‧Control circuit

140‧‧‧畫素陣列 140‧‧‧ pixel array

141、142、241‧‧‧畫素 141, 142, 241‧‧‧ pixels

141a、241a‧‧‧限流電路 141a, 241a‧‧‧ current limiting circuit

141b、241b‧‧‧致能電晶體 141b, 241b‧‧‧Enable transistor

141c、241c‧‧‧發光元件 141c, 241c‧‧‧light-emitting element

150‧‧‧第三驅動電路 150‧‧‧third driving circuit

A1、A2、B2‧‧‧節點 A1, A2, B2‧‧‧ nodes

B1、C2‧‧‧提供節點 B1, C2‧‧‧ provide nodes

C11、C12、C21‧‧‧儲存電容 C11, C12, C21‧‧‧Storage capacitors

Data‧‧‧資料電壓 Data‧‧‧Data voltage

EM1、EM2、EM(N)、EM(N+1)‧‧‧致能發光信號 EM1, EM2, EM (N), EM (N + 1)

En、En(N)、En(N+1)‧‧‧致能信號 En, En (N), En (N + 1) ‧‧‧ enable signal

Fr(N)、Fr(N+1)、Fr(N+2)‧‧‧畫面期間 Fr (N), Fr (N + 1), Fr (N + 2) ‧‧‧Screen period

Id‧‧‧驅動電流 Id‧‧‧Drive current

OVDD‧‧‧系統高電壓 OVDD‧‧‧System high voltage

OVSS‧‧‧系統低電壓 OVSS‧‧‧System Low Voltage

scan(N-2)、scan(N-1)、scan(N)、scan(N+1)‧‧‧掃描信號 scan (N-2), scan (N-1), scan (N), scan (N + 1) ‧‧‧scan signal

T11、T12、T13、T14、T15、T21、T22、T23、T24、T25‧‧‧電晶體 T11, T12, T13, T14, T15, T21, T22, T23, T24, T25‧‧‧Transistors

TA、TB‧‧‧脈波寬度 TA, TB‧‧‧pulse width

TEM(N)、TEM(N+1)‧‧‧發光時間區間 TEM (N), TEM (N + 1) ‧‧‧ Luminous time interval

VH‧‧‧高電壓準位 VH‧‧‧High Voltage Level

VIN‧‧‧初始電壓 VIN‧‧‧ initial voltage

VL‧‧‧低電壓準位 VL‧‧‧ Low Voltage Level

圖1A繪示本發明一實施例的顯示裝置的電路方塊示意圖。 FIG. 1A is a schematic circuit block diagram of a display device according to an embodiment of the invention.

圖1B繪示本發明圖1A實施例的顯示裝置的各畫面(Frame)期間的驅動信號波形示意圖。 FIG. 1B is a schematic diagram of driving signal waveforms during each frame of the display device according to the embodiment of FIG. 1A of the present invention.

圖2A繪示本發明圖1A實施例的顯示裝置的畫素的另一實施方式的電路方塊示意圖。 FIG. 2A is a schematic circuit block diagram of another embodiment of a pixel of the display device of the embodiment of FIG. 1A according to the present invention.

圖2B繪示本發明圖2A實施例的顯示裝置的各畫面期間的驅動信號波形示意圖。 FIG. 2B is a schematic diagram of driving signal waveforms during each frame period of the display device according to the embodiment of FIG. 2A of the present invention.

圖3繪示本發明另一實施例的顯示裝置的各列(Column)的驅動信號波形示意圖。 FIG. 3 is a schematic diagram of driving signal waveforms of each column of a display device according to another embodiment of the present invention.

圖1A繪示本發明一實施例的顯示裝置的電路方塊示意圖。請參照圖1A，在本實施例中，顯示裝置100包括第一驅動電路110、第二驅動電路120、時序控制器130、畫素陣列140以及第三驅動電路150，其中畫素陣列140包括多個畫素(如141、142)。在此，為了簡化說明，本實施例僅繪示出畫素141、142，但本發明實施例不以此為限。 FIG. 1A is a schematic circuit block diagram of a display device according to an embodiment of the invention. Referring to FIG. 1A, in this embodiment, the display device 100 includes a first driving circuit 110, a second driving circuit 120, a timing controller 130, a pixel array 140, and a third driving circuit 150. The pixel array 140 includes a plurality of pixels. Pixels (such as 141, 142). Here, in order to simplify the description, this embodiment only illustrates pixels 141 and 142, but the embodiment of the present invention is not limited thereto.

第一驅動電路110耦接至畫素陣列140，以提供依序致能的多個掃描信號(如scan(N)、scan(N-1)、scan(N-2))至對應的畫素(如141、142)，其中N為一引導數。第二驅動電路120耦接至畫素陣列140，並且提供多個致能發光信號(如EM1、EM2)至對應的畫素141、142。第三驅動電路150耦接至畫素陣列140，並會提供資料電壓Data至對應的畫素(如141、142)。 The first driving circuit 110 is coupled to the pixel array 140 to provide sequential enablement. Multiple scan signals (such as scan (N), scan (N-1), scan (N-2)) to corresponding pixels (such as 141, 142), where N is a leading number. The second driving circuit 120 is coupled to the pixel array 140 and provides a plurality of enabled light emitting signals (such as EM1 and EM2) to the corresponding pixels 141 and 142. The third driving circuit 150 is coupled to the pixel array 140 and provides data voltage Data to corresponding pixels (such as 141 and 142).

時序控制器130耦接至畫素陣列140及第二驅動電路120。時序控制器130具有控制電路131，並且控制電路131會依據各個畫素(如141、142)中的多個節點的電壓來動態調整多個致能發光信號(如EM1、EM2)的脈波寬度，以調整各個畫素(如141、142)的發光時間的比例。 The timing controller 130 is coupled to the pixel array 140 and the second driving circuit 120. The timing controller 130 has a control circuit 131, and the control circuit 131 dynamically adjusts the pulse widths of a plurality of enabled light-emitting signals (such as EM1 and EM2) according to the voltages of multiple nodes in each pixel (such as 141 and 142). To adjust the proportion of light-emitting time of each pixel (such as 141, 142).

值得一提的，本實施例的控制電路131可預先建立查找表，並透過查找表來查找致能發光信號(如EM1、EM2)的對應發光時間比例，以動態調整致能發光信號(如EM1、EM2)的脈波寬度，但本發明實施例並不限制於此。 It is worth mentioning that the control circuit 131 of this embodiment may establish a look-up table in advance, and use the look-up table to find the corresponding light-emitting time ratio of the enabled light-emitting signals (such as EM1, EM2) to dynamically adjust the enabled light-emitting signals (such as EM1) , EM2), but the embodiment of the present invention is not limited to this.

此外，關於畫素陣列140中的畫素141、142的電路架構，在此以畫素141作為範例進行說明。畫素141包括限流電路141a、致能電晶體141b以及發光元件141c。限流電路141a耦接至第一驅動電路110，並接收來自第一驅動電路110的多個掃描信號(如scan(N)、scan(N-1)、scan(N-2))中的第一掃描信號(在此以scan(N)為例)。接著，限流電路141a依據第一掃描信號scan(N)來接收資料電壓Data，並依據資料電壓Data來提供驅動電流Id。致能電晶體141b耦接於發光元件141c及限流電路141a之間，其控制端會接收多個致能發光信號(如EM1、EM2)中的第一致能發光信號(在此以EM1為例)，並且依據第一致能發光信號EM1來將驅動電流Id提供至發光元件141c。發光元件141c的一端耦接至致能電晶體141b的第二端，另一端則接收系統低電壓OVSS。關於顯示裝置100的畫素陣列140中其他畫素(如142)的電路架構，可參照圖1A的畫素141所示。 In addition, regarding the circuit architecture of the pixels 141 and 142 in the pixel array 140, the pixel 141 is used as an example for description. The pixel 141 includes a current limiting circuit 141a, an enabling transistor 141b, and a light emitting element 141c. The current limiting circuit 141a is coupled to the first driving circuit 110 and receives a plurality of scan signals (such as scan (N), scan (N-1), scan (N-2)) from the first driving circuit 110. A scan signal (take scan (N) as an example here). Then, the current limiting circuit 141a receives the data voltage Data according to the first scan signal scan (N), and provides the driving current Id according to the data voltage Data. The enabling transistor 141b is coupled between the light-emitting element 141c and the current-limiting circuit 141a. Receive a first enabling light emitting signal (such as EM1 here) among a plurality of enabling light emitting signals (such as EM1 and EM2), and provide the driving current Id to the light emitting element 141c according to the first enabling light emitting signal EM1. One end of the light-emitting element 141c is coupled to the second end of the enabling transistor 141b, and the other end receives the system low voltage OVSS. Regarding the circuit architecture of other pixels (such as 142) in the pixel array 140 of the display device 100, reference may be made to the pixel 141 shown in FIG. 1A.

在本實施例中，畫素141中的限流電路141a包括電晶體T11~T15(對應第一電晶體至第五電晶體)、第一儲存電容C11以及第二儲存電容C12。電晶體T11(對應第一電晶體)的第一端耦接至第一儲存電容C11，電晶體T11的控制端接收多個掃描信號(如scan(N)、scan(N-1)、scan(N-2))中的第二掃描信號(在此以scan(N-1)為例)，並且電晶體T11的第二端接收初始電壓VIN。電晶體T12(對應第二電晶體)的第一端接收系統高電壓OVDD，電晶體T12的控制端接收第一致能發光信號(在此以EM1為例)，並且電晶體T12的第二端耦接至電晶體T14第一端。電晶體T13(對應第三電晶體)的第一端耦接至電晶體T11的第一端，電晶體T13的控制端接收第一掃描信號scan(N)，並且電晶體T13的第二端耦接至致能電晶體141b的第一端。 In this embodiment, the current limiting circuit 141 a in the pixel 141 includes transistors T11 to T15 (corresponding to the first to fifth transistors), a first storage capacitor C11 and a second storage capacitor C12. The first terminal of the transistor T11 (corresponding to the first transistor) is coupled to the first storage capacitor C11, and the control terminal of the transistor T11 receives multiple scan signals (such as scan (N), scan (N-1), scan ( N-2)) (the scan (N-1) is taken as an example here), and the second terminal of the transistor T11 receives the initial voltage VIN. The first terminal of the transistor T12 (corresponding to the second transistor) receives the system high voltage OVDD, the control terminal of the transistor T12 receives the first enable light-emitting signal (here EM1 is taken as an example), and the second terminal of the transistor T12 Coupled to the first terminal of transistor T14. The first terminal of the transistor T13 (corresponding to the third transistor) is coupled to the first terminal of the transistor T11, the control terminal of the transistor T13 receives the first scan signal scan (N), and the second terminal of the transistor T13 is coupled Connected to the first terminal of the enabling transistor 141b.

電晶體T14(對應第四電晶體)的第一端耦接至電晶體T12的第二端，電晶體T14的控制端(即節點A1)耦接至電晶體T11的第一端，並且電晶體T14的第二端(即提供節點B1)耦接至致能電晶體141b的第一端。電晶體T15(對應第五電晶體)的第一端耦接至電晶體T12的第二端，電晶體T15的控制端接收第一掃描信號scan(N)，並且電晶體T15的第二端接收資料電壓Data。第一儲存電容C11耦接於系統高電壓OVDD與電晶體T11的第一端之間。第二儲存電容C12則耦接於電晶體T13的第一端與電晶體T13的控制端之間。 The first terminal of transistor T14 (corresponding to the fourth transistor) is coupled to the second terminal of transistor T12, the control terminal of transistor T14 (ie, node A1) is coupled to the first terminal of transistor T11, and the transistor The second terminal of T14 (ie, the providing node B1) is coupled to the first terminal of the enabling transistor 141b. Transistor T15 (corresponding to the fifth transistor) The first terminal is coupled to the second terminal of the transistor T12, the control terminal of the transistor T15 receives the first scan signal scan (N), and the second terminal of the transistor T15 receives the data voltage Data. The first storage capacitor C11 is coupled between the system high voltage OVDD and the first terminal of the transistor T11. The second storage capacitor C12 is coupled between the first terminal of the transistor T13 and the control terminal of the transistor T13.

依據上述，控制電路131可依據各個畫素(如141、142)中的多個節點(如A1、B1)的電壓來動態調整多個致能發光信號(如EM1、EM2)的脈波寬度，以調整各個畫素(如141、142)的發光時間的比例。 According to the above, the control circuit 131 can dynamically adjust the pulse widths of the plurality of enabled light emitting signals (such as EM1 and EM2) according to the voltages of multiple nodes (such as A1 and B1) in each pixel (such as 141 and 142) To adjust the proportion of light emission time of each pixel (such as 141, 142).

在本實施例中，發光元件141c為有機發光二極體(OLED)或者是微型發光二極體(μLED)。並且，電晶體T11~T15在此以P通道電晶體作為例，然而本發明並不限制於此，在某些實施例中，電晶體T11~T15可以是N通道電晶體(NMOS)，發光元件141c可以是無機的發光二極體(LED)或是其他固態發光元件，本技術領域中具有通常知識者可依據實施方式以及通常知識而依照實際需求作適當調整。 In this embodiment, the light emitting element 141c is an organic light emitting diode (OLED) or a micro light emitting diode (μLED). In addition, the transistors T11 to T15 use a P-channel transistor as an example, but the present invention is not limited thereto. In some embodiments, the transistors T11 to T15 may be N-channel transistors (NMOS), and light-emitting elements. 141c may be an inorganic light-emitting diode (LED) or other solid-state light-emitting elements. Those with ordinary knowledge in the technical field may make appropriate adjustments according to the implementation and general knowledge according to actual needs.

承接上述，請同時參照圖1A及圖1B，圖1B繪示本發明圖1A實施例的顯示裝置的各畫面(Frame)期間的驅動信號波形示意圖。在本實施例中，顯示裝置100的驅動信號可反應於各畫面期間(如Fr(N)、Fr(N+1)、Fr(N+2))的不同階段而變。為簡化說明，在此以驅動信號在畫面期間Fr(N)中的電路動作為例進行說明。在本實施例中，第二掃描信號scan(N-1)的作動期間(例如是為低電壓準位VL的期間)會早於第一掃描信號scan(N)的作動期間(例如是為低電壓準位VL的期間)。並且，在第二掃描信號scan(N-1)的作動期間，第一儲存電容C11的跨壓會相關於系統高電壓OVDD及初始電壓VIN之間的壓差，第二儲存電容C12的跨壓會相關於高電壓準位VH及初始電壓VIN之間的壓差。 Following the above, please refer to FIGS. 1A and 1B at the same time. FIG. 1B is a schematic diagram of driving signal waveforms during each frame of the display device of the embodiment of FIG. 1A of the present invention. In this embodiment, the driving signal of the display device 100 may be changed in response to different stages of each frame period (such as Fr (N), Fr (N + 1), Fr (N + 2)). To simplify the description, the circuit operation of the driving signal in the frame period Fr (N) will be described as an example. In this embodiment, the operation period of the second scan signal scan (N-1) (for example, The period during which the voltage is at the low voltage level VL is earlier than the operation period of the first scan signal scan (N) (for example, the period during which is the low voltage level VL). In addition, during the operation period of the second scan signal scan (N-1), the voltage across the first storage capacitor C11 will be related to the voltage difference between the system high voltage OVDD and the initial voltage VIN, and the voltage across the second storage capacitor C12. It will be related to the voltage difference between the high voltage level VH and the initial voltage VIN.

在第一掃描信號scan(N)的作動期間，節點A1的電壓為資料電壓Data減去電晶體(如T14)的臨界電壓，而第一儲存電容C11及第二儲存電容C12的跨壓對應節點A1的電壓而調整。接著，在第一致能發光信號EM1的作動期間，第一儲存電容C11的跨壓會相關於電晶體(如T14)的臨界電壓及資料電壓Data，驅動電流Id會相關於節點A1的電壓，並且經由提供節點B1提供驅動電流Id至發光元件141c，以驅動發光元件141c。 During the operation period of the first scan signal scan (N), the voltage of the node A1 is the data voltage Data minus the threshold voltage of the transistor (such as T14), and the voltage across the first storage capacitor C11 and the second storage capacitor C12 corresponds to the node Adjust the voltage of A1. Then, during the activation period of the first enabling light-emitting signal EM1, the cross-voltage of the first storage capacitor C11 will be related to the threshold voltage and data voltage Data of the transistor (such as T14), and the driving current Id will be related to the voltage of the node A1. And the driving current Id is provided to the light emitting element 141c via the providing node B1 to drive the light emitting element 141c.

此外，在本實施例中，各畫面期間(如Fr(N)、Fr(N+1)、Fr(N+2))分別具有用以致能第一致能發光信號(如EM1)的發光時間區間(如TEM(N)、TEM(N+1))，並且在各發光時間區間(如TEM(N)、TEM(N+1))中，基於控制電路131的判斷結果，第一致能發光信號(如EM1)可以分別具有相同大小或不同大小的工作週期(Duty Cycle)，亦即相對於發光時間區間(如TEM(N)、TEM(N+1))可以具有相同的時間比例或不同的時間比例。 In addition, in this embodiment, each frame period (such as Fr (N), Fr (N + 1), Fr (N + 2)) has a light-emitting time for enabling the first enable light-emitting signal (such as EM1). Interval (such as TEM (N), TEM (N + 1)), and in each emission time interval (such as TEM (N), TEM (N + 1)), based on the judgment result of the control circuit 131, the first enable The light emission signals (such as EM1) can have the same or different duty cycles, that is, they can have the same time ratio or relative to the light emission time interval (such as TEM (N), TEM (N + 1)). Different time proportions.

在本實施例中，在畫面期間Fr(N)的發光時間區間TEM(N)中，第一致能發光信號EM1相對於發光時間區間TEM(N)的時間比例為100%；在畫面期間Fr(N+1)的發光時間區間TEM(N+1)中，第一致能發光信號EM1相對於發光時間區間TEM(N+1)的時間比例為50%。其中，發光時間區間TEM(N)與發光時間區間TEM(N+1)的時間長度會大致相同。 In this embodiment, in the light emission time interval TEM (N) of the frame period Fr (N), the time ratio of the first enable light emission signal EM1 to the light emission time interval TEM (N) is 100%; during the frame period Fr In the emission time interval TEM (N + 1) of (N + 1), The time ratio of the first uniform energy emission signal EM1 to the emission time interval TEM (N + 1) is 50%. The time length of the emission time interval TEM (N) and the emission time interval TEM (N + 1) will be approximately the same.

在本發明的實施例中，控制電路131可以在一個畫面期間(如Fr(N)、Fr(N+1)、Fr(N+2))中，同步調整畫素陣列140中所有畫素(如141、142)的致能發光信號(如EM1、EM2)的脈波寬度，亦即所有致能發光信號(如EM1、EM2)在同一畫面期間(如Fr(N)、Fr(N+1)、Fr(N+2))中致能的脈波寬度相同，以動態調整發光元件141c發光的時間比例。 In the embodiment of the present invention, the control circuit 131 may adjust all pixels in the pixel array 140 (for example, Fr (N), Fr (N + 1), Fr (N + 2)) in a frame period ( (E.g., 141, 142) The pulse width of the enabled light-emitting signals (such as EM1, EM2), that is, all the enabled light-emitting signals (such as EM1, EM2) are in the same picture period (such as Fr (N), Fr (N + 1) ), Fr (N + 2)) have the same enabled pulse wave width to dynamically adjust the time proportion of the light emitting element 141c to emit light.

圖2A繪示本發明圖1A實施例的顯示裝置的畫素的另一實施方式的電路方塊示意圖。請同時參照圖1A及圖2A，在本實施例中，顯示裝置(如顯示裝置100)中的畫素(如141、142)可參照畫素241所示，其中畫素241包括限流電路241a、致能電晶體241b以及發光元件241c。限流電路241a包括電晶體T21~T25(對應第六電晶體至第十電晶體)以及第三儲存電容C21。 FIG. 2A is a schematic circuit block diagram of another embodiment of a pixel of the display device of the embodiment of FIG. 1A according to the present invention. Please refer to FIG. 1A and FIG. 2A at the same time. In this embodiment, the pixels (such as 141 and 142) in the display device (such as the display device 100) can be referred to as the pixels 241, where the pixels 241 include a current limiting circuit 241a , Enabling the transistor 241b and the light-emitting element 241c. The current limiting circuit 241a includes transistors T21 to T25 (corresponding to the sixth transistor to the tenth transistor) and a third storage capacitor C21.

電晶體T21(對應第六電晶體)的第一端接收資料電壓Data、電晶體T21的控制端接收第一掃描信號(在此以scan(N)為例)，並且電晶體T21的第二端耦接至第三儲存電容C21的一端(即節點B2)。電晶體T22(對應第七電晶體)的第一端接收系統高電壓OVDD，電晶體T22的控制端接收致能信號En，以及電晶體T22的第二端耦接至電晶體T21的第二端。電晶體T23(對應第八電晶體)的第一端接收系統高電壓OVDD，電晶體T23的控制端耦接至第三儲存電容C21的另一端(即節點A2)，並且電晶體T23的第二端(即提供節點C2)耦接至致能電晶體241b的第一端。電晶體T24(對應第九電晶體)的第一端耦接至電晶體T23的控制端，電晶體T24的控制端接收第二掃描信號(在此以scan(N-1)為例)，以及電晶體T24的第二端耦接至電晶體T23的第二端。電晶體T25(對應第十電晶體)的第一端耦接至電晶體T23的控制端，電晶體T25的控制端接收第三掃描信號(在此以scan(N-2)為例)，以及電晶體T25的第二端接收初始電壓VIN。致能電晶體241b耦接於發光元件241c及限流電路241a之間，並且致能電晶體241b的控制端接收第一致能發光信號(在此以EM1為例)，以依據第一致能發光信號EM1來將驅動電流Id提供至發光元件241c。發光元件241c的一端耦接至致能電晶體241b的第二端，另一端接收系統低電壓OVSS。 The first terminal of the transistor T21 (corresponding to the sixth transistor) receives the data voltage Data, the control terminal of the transistor T21 receives the first scan signal (here, scan (N) is taken as an example), and the second terminal of the transistor T21 Coupled to one end of the third storage capacitor C21 (ie, node B2). The first terminal of transistor T22 (corresponding to the seventh transistor) receives the high voltage OVDD of the system, the control terminal of transistor T22 receives the enable signal En, and the second terminal of transistor T22 is coupled to the second terminal of transistor T21. . The first terminal of transistor T23 (corresponding to the eighth transistor) receives the system high voltage OVDD, and the control terminal of transistor T23 is coupled Connected to the other end of the third storage capacitor C21 (ie, node A2), and the second end of the transistor T23 (ie, provided node C2) is coupled to the first end of the enable transistor 241b. The first terminal of the transistor T24 (corresponding to the ninth transistor) is coupled to the control terminal of the transistor T23, and the control terminal of the transistor T24 receives the second scan signal (here, scan (N-1) is taken as an example), and The second terminal of the transistor T24 is coupled to the second terminal of the transistor T23. The first terminal of the transistor T25 (corresponding to the tenth transistor) is coupled to the control terminal of the transistor T23, and the control terminal of the transistor T25 receives the third scan signal (here, scan (N-2) is taken as an example), and The second terminal of the transistor T25 receives the initial voltage VIN. The enabling transistor 241b is coupled between the light-emitting element 241c and the current-limiting circuit 241a, and the control terminal of the enabling transistor 241b receives the first enabling light-emitting signal (here, EM1 is taken as an example) to comply with the first enabling The light-emitting signal EM1 supplies a driving current Id to the light-emitting element 241c. One end of the light-emitting element 241c is coupled to the second end of the enabling transistor 241b, and the other end receives the system low voltage OVSS.

承接上述，請同時參照圖2A及圖2B，圖2B繪示本發明圖2A實施例的顯示裝置的各畫面期間的驅動信號波形示意圖。在本實施例中，顯示裝置(例如是圖1A的顯示裝置100)反應於各畫面期間(如Fr(N)、Fr(N+1)、Fr(N+2))的不同階段而變。為簡化說明，在此以驅動信號在畫面期間Fr(N)中的電路動作為例進行說明。 Following the above, please refer to FIGS. 2A and 2B at the same time. FIG. 2B is a schematic diagram of driving signal waveforms during each screen of the display device of the embodiment of FIG. 2A of the present invention. In this embodiment, the display device (for example, the display device 100 in FIG. 1A) changes in response to different stages of each screen period (such as Fr (N), Fr (N + 1), Fr (N + 2)). To simplify the description, the circuit operation of the driving signal in the frame period Fr (N) will be described as an example.

在本實施例中，第二掃描信號scan(N-1)的作動期間(例如是為低電壓準位VL的期間)會早於第一掃描信號scan(N)的作動期間(例如是為低電壓準位VL的期間)，並且第三掃描信號 scan(N-2)的作動期間(例如是為低電壓準位VL的期間)早於第二掃描信號scan(N-1)的作動期間。其中，第三掃描信號scan(N-2)的作動期間與第二掃描信號scan(N-1)的作動期間完全位於致能信號En的作動期間(例如是為低電壓準位VL的期間)內，亦即第三掃描信號scan(N-2)的作動期間與第二掃描信號scan(N-1)的作動期間的總和重疊於致能信號En的作動期間。 In this embodiment, the operation period of the second scan signal scan (N-1) (for example, a period of low voltage level VL) is earlier than the operation period of the first scan signal scan (N) (for example, a low period) Voltage level VL), and the third scan signal The operation period of scan (N-2) (for example, the period for the low voltage level VL) is earlier than the operation period of the second scan signal scan (N-1). The operation period of the third scan signal scan (N-2) and the operation period of the second scan signal scan (N-1) are completely located in the operation period of the enable signal En (for example, the period of the low-voltage level VL). , That is, the sum of the operation period of the third scan signal scan (N-2) and the operation period of the second scan signal scan (N-1) overlaps the operation period of the enable signal En.

在第三掃描信號scan(N-2)的作動期間，節點A2的電壓為初始電壓VIN。與此同時，在致能信號En的作動期間，節點B2的電壓為系統高電壓OVDD，而第三儲存電容C21的跨壓會相關於系統高電壓OVDD及初始電壓VIN之間的壓差。接著，在第二掃描信號scan(N-1)的作動期間，此時同樣為致能信號En的作動期間，節點A2的電壓為系統高電壓OVDD減去電晶體(如T23)的臨界電壓，並且第三儲存電容C21的跨壓會相關於電晶體(如T23)的臨界電壓。 During the operation period of the third scan signal scan (N-2), the voltage of the node A2 is the initial voltage VIN. At the same time, during the activation period of the enable signal En, the voltage of the node B2 is the system high voltage OVDD, and the voltage across the third storage capacitor C21 is related to the voltage difference between the system high voltage OVDD and the initial voltage VIN. Next, during the operation period of the second scan signal scan (N-1), which is also the operation period of the enable signal En at this time, the voltage of the node A2 is the system high voltage OVDD minus the threshold voltage of the transistor (such as T23). And the voltage across the third storage capacitor C21 will be related to the threshold voltage of the transistor (such as T23).

接著，在第一掃描信號scan(N)的作動期間，節點B2的電壓為資料電壓Data，並且節點A2的電壓為資料電壓Data減去電晶體(如T23)的臨界電壓。並且在第一致能發光信號EM1的作動期間，第三儲存電容C21的跨壓會相關於電晶體(如T23)的臨界電壓及資料電壓Data，驅動電流Id會相關於節點A2的電壓，並經由提供節點C2提供驅動電流Id至發光元件241c，以驅動發光元件241c。 Next, during the operation period of the first scan signal scan (N), the voltage of the node B2 is the data voltage Data, and the voltage of the node A2 is the data voltage Data minus the threshold voltage of the transistor (such as T23). And during the activation period of the first enabling light-emitting signal EM1, the cross-voltage of the third storage capacitor C21 will be related to the threshold voltage and data voltage Data of the transistor (such as T23), and the driving current Id will be related to the voltage of the node A2, and A driving current Id is provided to the light emitting element 241c via the providing node C2 to drive the light emitting element 241c.

此外，在本實施例中，各畫面期間(如Fr(N)、Fr(N+1)、 Fr(N+2))分別具有用以致能第一致能發光信號(如EM1)的發光時間區間(如TEM(N)、TEM(N+1))，並且在各發光時間區間(如TEM(N)、TEM(N+1))中，基於控制電路131的判斷結果，第一致能發光信號(如EM1)可以分別具有相同大小或不同大小的工作週期，亦即相對於發光時間區間(如TEM(N)、TEM(N+1))可以具有相同的時間比例或不同的時間比對。 In addition, in this embodiment, each picture period (such as Fr (N), Fr (N + 1), Fr (N + 2)) has a luminescence time interval (such as TEM (N), TEM (N + 1)) to enable the first enable luminescence signal (such as EM1), and in each luminescence time interval (such as TEM In (N), TEM (N + 1)), based on the judgment result of the control circuit 131, the first enabled light emitting signals (such as EM1) may have the same or different duty cycles, that is, relative to the light emission time interval. (Such as TEM (N), TEM (N + 1)) can have the same time ratio or different time alignments.

圖3繪示本發明另一實施例的顯示裝置的各列(Column)的驅動信號波形示意圖。請參照圖3，在本實施例中，圖3所示驅動信號波形大致相同於圖2B所示，其不同之處在於圖3僅繪示一個畫面期間Fr(N)，並且繪示多個致能信號(如En(N)及En(N+1)及多個致能發光信號(如EM(N)、EM(N+1))。在本實施例中，掃描信號(如scan(N-2)、scan(N-1)、scan(N)、scan(N+1))同樣會依序致能，以逐列驅動所有畫素(如141、142、241)。並且，各個致能發光信號(如EM(N)、EM(N+1))用以驅動一列的畫素(如141、142、241)，並且各個致能發光信號(如EM(N)、EM(N+1))在同一畫面期間Fr(N)中致能的脈波寬度(如TA、TB所示)可以相同也可以不同，亦即各個致能發光信號(如EM(N)、EM(N+1))致能的脈波寬度是個別調整的。 FIG. 3 is a schematic diagram of driving signal waveforms of each column of a display device according to another embodiment of the present invention. Please refer to FIG. 3. In this embodiment, the driving signal waveform shown in FIG. 3 is substantially the same as that shown in FIG. 2B. The difference is that FIG. 3 shows only one frame period Fr (N), and shows multiple causes. Energy signals (such as En (N) and En (N + 1) and multiple enabled light emitting signals (such as EM (N), EM (N + 1)). In this embodiment, the scanning signals (such as scan (N -2), scan (N-1), scan (N), scan (N + 1)) will also be enabled in order to drive all pixels (such as 141, 142, 241) column by column. The light-emitting signals (such as EM (N), EM (N + 1)) are used to drive a row of pixels (such as 141, 142, 241), and each of the enabled light-emitting signals (such as EM (N), EM (N + 1)) The pulse widths enabled in Fr (N) during the same picture period (as shown by TA and TB) can be the same or different, that is, each enabled light emitting signal (such as EM (N), EM (N + 1) The enabled pulse width is individually adjusted.

綜上所述，本發明實施例的顯示裝置可依據多個畫素內多個節點的電壓來動態調整致能發光信號的脈波寬度，進而動態調整發光的時間比例，使顯示裝置可於低灰階時具有效補償機制，並且改善整體發光效率及平衡發光均勻度，以避免增加功耗與延長元件壽命。 In summary, the display device of the embodiment of the present invention can dynamically adjust the pulse width of the enabled light-emitting signal according to the voltages of multiple nodes in multiple pixels, and then dynamically adjust the time proportion of light emission, so that the display device can be low Gray-scale time has an effect compensation mechanism, and improves the overall luminous efficiency and balanced luminous uniformity to avoid increasing power consumption And extend component life.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims

一種顯示裝置，包括：一第一驅動電路，用以提供依序致能的多個掃描信號；一第二驅動電路，用以提供多個致能發光信號；以及多個畫素，分別包括：一發光元件；一限流電路，耦接該第一驅動電路，以接收該些掃描信號的一第一掃描信號，並且反應於該第一掃描信號接收一資料電壓，以反應於該資料電壓提供一驅動電流；以及一致能電晶體，耦接於該發光元件及該限流電路之間，並且接收該些致能發光信號的一第一致能發光信號，以反應於該第一致能發光信號將該驅動電流提供至該發光元件；其中，該些致能發光信號的脈波寬度反應於該些畫素內的多個節點的電壓而動態調整。A display device includes: a first driving circuit for providing a plurality of sequentially enabled scanning signals; a second driving circuit for providing a plurality of enabling light-emitting signals; and a plurality of pixels, each including: A light-emitting element; a current-limiting circuit coupled to the first driving circuit to receive a first scanning signal of the scanning signals, and receiving a data voltage in response to the first scanning signal, and providing a data voltage in response to the data voltage A driving current; and a uniform energy transistor, coupled between the light-emitting element and the current-limiting circuit, and receiving a first enabling light-emitting signal of the enabling light-emitting signals in response to the first enabling light-emitting The signal provides the driving current to the light-emitting element. The pulse widths of the enabled light-emitting signals are dynamically adjusted in response to the voltages of the nodes in the pixels.

如申請專利範圍第1項所述的顯示裝置，其中該限流電路包括：一第一電晶體，具有一第一端、接收該些掃描信號的一第二掃描信號的一控制端及接收一初始電壓的一第二端；一第一儲存電容，耦接於一系統高電壓與該第一電晶體的該第一端之間；一第二電晶體，具有接收該系統高電壓的一第一端、接收該第一致能發光信號的一控制端及一第二端；一第三電晶體，具有耦接該第一電晶體的該第一端的一第一端、接收該第一掃描信號的一控制端及耦接該致能電晶體的一第一端的一第二端；一第二儲存電容，耦接於該第三電晶體的該第一端與該第三電晶體的該控制端之間；一第四電晶體，具有耦接該第二電晶體的該第二端的一第一端、耦接該第一電晶體的該第一端的一控制端及耦接該致能電晶體的該第一端的一第二端；以及一第五電晶體，具有耦接該第二電晶體的該第二端的一第一端、接收該第一掃描信號的一控制端及接收該資料電壓的一第二端。The display device according to item 1 of the patent application scope, wherein the current limiting circuit comprises: a first transistor having a first terminal, a control terminal receiving a second scanning signal of the scanning signals, and a receiving terminal A second terminal of the initial voltage; a first storage capacitor coupled between a high voltage of the system and the first terminal of the first transistor; a second transistor having a first capacitor receiving the high voltage of the system One end, a control end and a second end receiving the first enabling light-emitting signal; a third transistor having a first end coupled to the first end of the first transistor, receiving the first A control terminal of the scanning signal and a second terminal coupled to a first terminal of the enabling transistor; a second storage capacitor coupled to the first terminal of the third transistor and the third transistor Between the control terminals; a fourth transistor having a first terminal coupled to the second terminal of the second transistor, a control terminal coupled to the first terminal of the first transistor, and a coupling A second end of the first end of the enabling transistor; and a fifth transistor having a coupling A first end of the second end of the second transistor, a control terminal for receiving the first scan signal and a second terminal for receiving the data voltage.

如申請專利範圍第2項所述的顯示裝置，其中該第二掃描信號的作動期間早於該第一掃描信號的作動期間。The display device according to item 2 of the patent application, wherein an operating period of the second scanning signal is earlier than an operating period of the first scanning signal.

如申請專利範圍第1項所述的顯示裝置，其中該限流電路包括：一第六電晶體，具有接收該資料電壓的一第一端、接收該第一掃描信號的一控制端及一第二端；一第七電晶體，具有接收一系統高電壓的一第一端、接收一致能信號的一控制端及耦接該第六電晶體的該第二端的一第二端；一第八電晶體，具有接收該系統高電壓的一第一端、一控制端及耦接該致能電晶體的一第一端的一第二端；一第三儲存電容，耦接於該第六電晶體的該第二端與該第八電晶體的該控制端之間；一第九電晶體，具有耦接該第八電晶體的該控制端的一第一端、接收該些掃描信號的一第二掃描信號的一控制端及耦接該第八電晶體的該第二端的一第二端；一第十電晶體，具有耦接該第八電晶體的該控制端的一第一端、接收該些掃描信號的一第三掃描信號的一控制端及接收一初始電壓的一第二端。The display device according to item 1 of the patent application scope, wherein the current-limiting circuit includes: a sixth transistor having a first terminal for receiving the data voltage, a control terminal for receiving the first scan signal, and a first Two terminals; a seventh transistor having a first terminal receiving a system high voltage, a control terminal receiving a uniform energy signal, and a second terminal coupled to the second terminal of the sixth transistor; an eighth The transistor has a first terminal, a control terminal receiving a high voltage of the system, and a second terminal coupled to a first terminal of the enabling transistor; a third storage capacitor is coupled to the sixth circuit. Between the second terminal of the crystal and the control terminal of the eighth transistor; a ninth transistor having a first terminal coupled to the control terminal of the eighth transistor and a first terminal receiving the scanning signals A control terminal of two scanning signals and a second terminal coupled to the second terminal of the eighth transistor; a tenth transistor having a first terminal coupled to the control terminal of the eighth transistor, receiving the A control terminal of a third scan signal of the scan signals and an initial A second end of the starting voltage.

如申請專利範圍第4項所述的顯示裝置，其中該第二掃描信號的作動期間早於該第一掃描信號的作動期間，且該第三掃描信號的作動期間早於該第二掃描信號的作動期間。The display device according to item 4 of the patent application, wherein the operating period of the second scanning signal is earlier than the operating period of the first scanning signal, and the operating period of the third scanning signal is earlier than that of the second scanning signal. During operation.

如申請專利範圍第1項所述的顯示裝置，其中該些節點包括各該些畫素的該限流電路提供該驅動電流的一提供節點。The display device according to item 1 of the scope of patent application, wherein the nodes include a providing node for the driving current provided by the current limiting circuit of each of the pixels.

如申請專利範圍第1項所述的顯示裝置，更包括一控制電路，耦接該些畫素及該第二驅動電路，以依據該些畫素的該些節點的電壓動態調整該些致能發光信號的脈波寬度。The display device according to item 1 of the scope of patent application, further includes a control circuit coupled to the pixels and the second driving circuit, so as to dynamically adjust the enabling functions according to the voltages of the nodes of the pixels. Pulse width of the light signal.

如申請專利範圍第7項所述的顯示裝置，其中該控制電路透過一查找表動態調整該些致能發光信號的脈波寬度。The display device according to item 7 of the scope of patent application, wherein the control circuit dynamically adjusts the pulse widths of the enabled light-emitting signals through a look-up table.

如申請專利範圍第7項所述的顯示裝置，其中該控制電路配置於一時序控制器中。The display device according to item 7 of the scope of patent application, wherein the control circuit is configured in a timing controller.

如申請專利範圍第1項所述的顯示裝置，其中在一畫面期間中，該些致能發光信號的脈波寬度為同步調整。The display device according to item 1 of the scope of patent application, wherein during a picture period, the pulse widths of the enabled light-emitting signals are adjusted synchronously.

如申請專利範圍第1項所述的顯示裝置，其中在一畫面期間中，該些致能發光信號的脈波寬度為各別調整。The display device according to item 1 of the scope of patent application, wherein during a picture period, the pulse widths of the enabling light-emitting signals are individually adjusted.

如申請專利範圍第1項所述的顯示裝置，更包括一第三驅動電路，耦接該些畫素，用以提供各該些畫素所需的該資料電壓。The display device according to item 1 of the scope of patent application, further includes a third driving circuit coupled to the pixels to provide the data voltage required by the pixels.

如申請專利範圍第1項所述的顯示裝置，其中該發光元件包括一微型發光二極體及一有機發光二極體的其中之一。The display device according to item 1 of the scope of patent application, wherein the light-emitting element includes one of a micro-light-emitting diode and an organic light-emitting diode.