TWI671882B - Semiconductor chip and method for manufacturing an integrated circuit - Google Patents

Abstract

一種半導體裝置，包含基板及若干經定義於基板內之擴散區，該擴散區係藉由基板之非主動區而彼此分離。該半導體裝置包含若干經定義成以單一共同方向在基板上方延伸之線形閘極軌道，各線形閘極軌道係藉由一或更多線形閘極片段加以定義。將在基板之擴散區及非主動區兩者上方延伸之每一線形閘極軌道，定義成可使線形閘極軌道內之相鄰線形閘極片段的端部之間的分隔距離最小化，同時確保相鄰線形閘極片段之間的適當電隔離。A semiconductor device includes a substrate and a plurality of diffusion regions defined in the substrate. The diffusion regions are separated from each other by an inactive region of the substrate. The semiconductor device includes a plurality of linear gate tracks defined to extend over a substrate in a single common direction, and each linear gate track is defined by one or more linear gate segments. Each linear gate track extending above both the diffusion region and the inactive region of the substrate is defined to minimize the separation distance between the ends of adjacent linear gate segments within the linear gate track, and Ensure proper electrical isolation between adjacent linear gate segments.

Description

半導體晶片及積體電路製造方法Semiconductor wafer and integrated circuit manufacturing method

本發明係關於一種半導體裝置，尤有關於具有可改善微影製程解析度之動態陣列結構之半導體裝置。The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a dynamic array structure capable of improving lithographic process resolution.

關於較高性能及較小晶粒尺寸之推動，迫使半導體產業每兩年便減少約50%的電路晶片面積，減少晶片面積為移動至更新技術提供了經濟利益。減少50%的晶片面積係藉由將特徵部尺寸縮小至25%與30%之間來達成，而能夠縮小特徵部尺寸係藉由改良製造設備與材料而來，例如改良光微影製程已能夠達到更小的特徵部尺寸，而改良化學機械研磨(CMP)在某種程度上已能夠使互連線層之數目增加。The promotion of higher performance and smaller die size has forced the semiconductor industry to reduce circuit chip area by about 50% every two years. Reducing the chip area provides economic benefits for moving to newer technologies. The reduction of 50% of the chip area is achieved by reducing the feature size to between 25% and 30%, and the feature size can be reduced by improving manufacturing equipment and materials. For example, the improved photolithography process has been able to Reaching smaller feature sizes, and improved chemical mechanical polishing (CMP) has been able to increase the number of interconnect layers to some extent.

在光微影之發展中，當最小特徵部尺寸接近用來將特徵部形狀曝光之光源的波長時，相鄰特徵部之間便會發生非預期之交互作用。如今最小特徵尺寸正接近45nm(奈米)，而在光微影製程中所使用之光源的波長仍維持於193nm。在最小特徵尺寸與光微影製程中所使用之光源的波長之間的差值即定義為光微影差距。當光微影差距增加時，光微影製程的解析能力便會下降。In the development of light lithography, when the minimum feature size is close to the wavelength of the light source used to expose the shape of the feature, unexpected interactions between adjacent features will occur. Today, the smallest feature size is close to 45nm (nanometers), and the wavelength of the light source used in the photolithography process is still maintained at 193nm. The difference between the minimum feature size and the wavelength of the light source used in the photolithography process is defined as the photolithography gap. When the photolithography gap increases, the resolution of the photolithography process decreases.

當遮罩上之每一形狀與光互相作用時，即產生干涉圖案；來自鄰近形狀之干涉圖案可產生建設性或破壞性干涉。在建設性干涉的情況下，可能不慎地產生不必要的形狀；在破壞性干涉的情況下，可能不慎地移動期望之形狀。在任一種情況下，均以與所預期者不同之方式印刷出特別的形狀，如此可能引起裝置故障。修正方法例如光學近接修正法(OPC)嘗試由鄰近形狀預測並修改遮罩，使可依需求來製造所印刷之形狀。隨著製程幾何收縮及光交互作用愈形複雜，光交互作用預測的品質正在下降。When each shape on the mask interacts with light, an interference pattern is produced; interference patterns from neighboring shapes can produce constructive or destructive interference. In the case of constructive interference, unnecessary shapes may be inadvertently produced; in the case of destructive interference, the desired shape may be accidentally moved. In either case, a special shape is printed in a different way than expected, which may cause the device to malfunction. Correction methods such as optical proximity correction (OPC) attempt to predict and modify masks from neighboring shapes so that printed shapes can be manufactured on demand. As process geometry shrinks and optical interactions become more complex, the quality of optical interaction predictions is declining.

有鑑於上述，當科技繼續朝向更小半導體裝置特徵部尺寸發展時，吾人需要一解決之道以處理微影間隙議題。In view of the above, as technology continues to move toward smaller semiconductor device feature sizes, we need a solution to address the lithographic gap issue.

在一實施例中揭露了一種半導體裝置，該裝置包含一基板及定義於該基板內之一些擴散區，該等擴散區係藉由該基板之非主動區而彼此分離。該裝置亦包含一些線形閘極軌道，其係經定義成沿單一共同方向而延伸越過基板上方，每一線形閘極軌道係藉由一或多個線形閘極片段加以定義。將延伸越過該基板之擴散區及非主動區上方之每一線形閘極軌道定義成用以最小化該線形閘極軌道內之相鄰線形閘極片段的端部之間的分隔距離，同時確保相鄰線形閘極片段之間有適當的電絕緣；此外，將線形閘極片段定義成具有可變長度，以賦予邏輯閘功能。In one embodiment, a semiconductor device is disclosed. The device includes a substrate and a plurality of diffusion regions defined in the substrate. The diffusion regions are separated from each other by an inactive region of the substrate. The device also includes a number of linear gate tracks that are defined to extend over a substrate in a single common direction. Each linear gate track is defined by one or more linear gate segments. Each linear gate track extending over the diffusion region and inactive region of the substrate is defined to minimize the separation distance between the ends of adjacent linear gate segments within the linear gate track, while ensuring that Adequate electrical insulation is provided between adjacent linear gate segments; in addition, the linear gate segments are defined to have a variable length to give a logic gate function.

在另一實施例中揭露了一種半導體裝置，該裝置包含一基板。將一些擴散區定義於該基板內，以界定電晶體裝置所用之主動區。半導體裝置亦包含一些沿一共同方向而定位於該基板上方之線形閘極片段，若干線形閘極片段係設置於擴散區上方，而設置於擴散區上方之每一線形閘極片段包含經定義於該擴散區上方之必要主動部分及經定義成在該基板除了該擴散區以外之上方延伸之均勻性延伸部分；此外，將線形閘極片段定義成具有可變長度，以賦予邏輯閘功能。該半導體裝置更包含一些設置於該線形閘極片段上方之一高度內之線形導體片段，以便可以一實質上垂直之方向與該線形閘極片段之共同方向相交叉。將該些線形導體片段定義成可最小化在基板上方之共同線內之相鄰線形導體片段之間的端至端(end-to-end)間距。In another embodiment, a semiconductor device is disclosed. The device includes a substrate. A plurality of diffusion regions are defined in the substrate to define active regions used by the transistor device. The semiconductor device also includes a number of linear gate segments positioned above the substrate along a common direction. Several linear gate segments are disposed above the diffusion region, and each linear gate segment disposed above the diffusion region includes A necessary active portion above the diffusion region and a uniform extension portion defined to extend above the substrate except the diffusion region; in addition, a linear gate segment is defined to have a variable length to give a logic gate function. The semiconductor device further includes linear conductor segments disposed within a height above the linear gate segment so that a substantially vertical direction can intersect with a common direction of the linear gate segment. The linear conductor segments are defined to minimize end-to-end spacing between adjacent linear conductor segments within a common line above the substrate.

在另一實施例中揭露了一種閘極接點，該閘極接點包含由一長度及沿其長度之一實質上均勻的橫截面形狀加以定義之線形導電性片段。將該線形導電性片段定位成使其長度沿實質上垂直於其上設有該線形導電性片段之下層閘極的方向延伸，將該線形導電性片段之長度定義成大於該下層閘極的寬度，使該線形導電性片段與該下層閘極重疊。In another embodiment, a gate contact is disclosed. The gate contact includes a linear conductive segment defined by a length and a substantially uniform cross-sectional shape along the length. The linear conductive segment is positioned so that its length extends in a direction substantially perpendicular to the lower gate on which the linear conductive segment is provided, and the length of the linear conductive segment is defined to be greater than the width of the lower gate So that the linear conductive segment overlaps the lower gate.

在另一實施例中揭露了一種接點布局，該接點布局包含一些定義在映射越過基板之共用柵上之接點。該接點布局亦包含一些次解析度接點，其係定義於共用柵上以圍繞每一接點。將每一次解析度接點加以定義，以避免在微影製程中之描繪(rendering)，同時強化接點之解析度。In another embodiment, a contact layout is disclosed. The contact layout includes some contacts defined on a common gate mapped across the substrate. The contact layout also includes some sub-resolution contacts, which are defined on the common grid to surround each contact. Define each resolution contact to avoid rendering in the lithography process and strengthen the resolution of the contact.

本發明之其他態樣及優點將由下列結合附圖的詳細說明、及藉由本發明之實施例加以闡明而變得更明顯。Other aspects and advantages of the present invention will become more apparent from the following detailed description in conjunction with the accompanying drawings, and by the embodiments of the present invention.

在下列說明中敘述了許多特殊細節，以便提供對本發明之徹底了解。然而，熟悉此項技藝者應明瞭：本發明在無這些特殊細節之全部或某部分的情況下仍可加以實施。在其他例子中，為避免不必要地混淆本發明，並未詳細描述已熟知之製程操作。Numerous specific details are set forth in the following description in order to provide a thorough understanding of the present invention. However, those skilled in the art should understand that the present invention can be implemented without all or some of these special details. In other examples, to avoid unnecessarily obscuring the present invention, well-known process operations are not described in detail.

一般而言，吾人設置動態陣列結構以因應與持續增加之微影間隙相關聯之半導體製程變化性。在半導體製造領域中，係將微影間隙定義成待定義之特徵部的最小尺寸與用以在微影製程中產生特徵部之光波長之間的差距，其中特徵部尺寸小於光波長。目前微影製程係利用193nm之光波長；然而，目前特徵部尺寸小至65nm，且預期不久便會逼近小至45nm之尺寸。儘管是65nm的尺寸，形狀仍小於用以定義形狀之光波長的3倍；又，考慮到光的交互作用半徑約為5個光波長，吾人應明瞭以193nm之光源加以曝光的形狀將影響形狀之曝光約5*193nm(1965nm)遠，在考慮特徵部尺寸為65nm時，關於90nm的特徵部尺寸，應明瞭：相較於90nm尺寸的特徵部，約有多至兩倍之尺寸為65nm的特徵部可能位在193nm光源之交互作用半徑1965nm內。Generally speaking, we set up a dynamic array structure to respond to the variability of semiconductor processes associated with the increasing lithographic gap. In the field of semiconductor manufacturing, the lithographic gap is defined as the difference between the minimum size of the feature to be defined and the wavelength of light used to generate the feature in the lithography process, where the size of the feature is smaller than the wavelength of light. The current lithography process uses a light wavelength of 193 nm; however, the size of the feature is currently as small as 65 nm, and it is expected that it will soon approach the size as small as 45 nm. Although it is 65nm in size, the shape is still less than 3 times the wavelength of the light used to define the shape. Considering that the interaction radius of light is about 5 light wavelengths, we should understand that the shape exposed by a 193nm light source will affect the shape The exposure is about 5 * 193nm (1965nm) away. When considering the feature size of 65nm, it should be clear about the feature size of 90nm: compared with the feature size of 90nm, there are about as many as two times the size of 65nm. The features may be located within the interaction radius of 1965nm of the 193nm light source.

由於在光源之交互作用半徑內之特徵部數目增加，對一特定特徵部的曝光有影響之光干涉之程度及複雜性相形重要；此外，與在光源之交互作用半徑內之特徵部相關聯的特殊形狀便對所發生之光交互作用的類型有重大影響。習知上，只要滿足一組設計規則，容許設計者本質上定義任何特徵部形狀的二維拓樸。例如，在晶片的一特定膜層中(亦即在一特定遮罩中)，設計者可能已定義具有互相圍繞之彎曲(bends)的二維變化特徵部。當此種二維變化特徵部之位置彼此緊鄰時，用以使特徵部曝光的光將會以複雜且通常無法預測之方式發生交互作用，隨著特徵部尺寸及相對間距變小，光交互作用愈形複雜且無法預測。As the number of features within the interaction radius of a light source increases, the degree and complexity of light interference that affects the exposure of a particular feature is important; in addition, the features associated with the features within the interaction radius of the light source are important. The particular shape has a significant impact on the type of light interaction that occurs. Conventionally, as long as a set of design rules are satisfied, the designer is allowed to define essentially a two-dimensional topology of any feature shape. For example, in a specific film layer of a wafer (ie, in a specific mask), a designer may have defined a two-dimensional variation feature with bends surrounding each other. When the positions of such two-dimensionally changing features are close to each other, the light used to expose the features will interact in a complex and often unpredictable manner. As the size and relative spacing of the features become smaller, the light interactions Increasingly complex and unpredictable.

習知上，若設計者遵循所建立之設計規則組，可製造出將在具有與設計規則組相關聯之特定機率之結果之產品；否則，就違反設計規則組之設計而言，成功製造結果之產品的機率未知。在關注成功產品製造方面，為說明鄰近二維變化特徵部之間的複雜光交互作用，便將設計規則組大幅擴張，以適當地說明二維變化特徵部之可能組合。此擴張之設計規則組迅速地變得如此複雜且不易使用，以致於應用此擴張之設計規則組變得過於費時、昂貴且容易出錯。例如，擴張之設計規則組需要複雜的驗證；又，擴張之設計規則組可能無法處處適用；此外，即使滿足所有設計規則，亦無法保證製造產率。Conventionally, if a designer follows the established design rule set, he can manufacture a product that will have a specific probability associated with the design rule set; otherwise, for a design that violates the design rule set, the result is successfully manufactured The probability of this product is unknown. In terms of focusing on successful product manufacturing, in order to explain the complex light interaction between adjacent two-dimensionally changing features, the design rule set was greatly expanded to properly illustrate the possible combinations of two-dimensionally changing features. This expanded set of design rules quickly became so complex and difficult to use that the application of this expanded set of design rules became too time-consuming, expensive, and error-prone. For example, the expanded set of design rules requires complex verification; in addition, the expanded set of design rules may not be applicable everywhere; moreover, even if all design rules are met, manufacturing yields cannot be guaranteed.

應明瞭：在產生任意形狀之二維特徵部時精確地預測所有可能之光交互作用通常無法實行；此外，亦可調整設計規則組而包含增大之邊緣，以說明鄰近二維變化特徵部之間的無法預測之光交互作用，而作為。因為建立設計規則係為嘗試涵蓋隨機二維特徵部拓樸，故設計規則可包含大量邊際(margin)；雖然將邊際加入設計規則組中協助了包含相鄰二維變化特徵部之布局部分，但加入此類全域之邊際卻使得不包含相鄰二維變化特徵部之布局部分發生超規格設計(overdesign)的情形，如此導致晶片區域利用及電力效能之最佳化變差。It should be clear that it is often impossible to accurately predict all possible light interactions when generating two-dimensional features with arbitrary shapes; in addition, the design rule set can be adjusted to include enlarged edges to account for the adjacent two-dimensional features. The unpredictable light interacts with each other while acting. Because the design rules are established to try to cover the random 2D feature topologies, the design rules can include a large number of margins. Although adding a margin to the design rule group assists in the layout part that includes adjacent 2D changing feature parts, but Adding such a global margin causes an overdesign situation in the layout portion that does not include adjacent two-dimensional changing feature portions, which results in poor optimization of chip area utilization and power efficiency.

有鑑於上述，應明瞭半導體產率會因來自於由設計相依無約束特徵部拓樸(亦即彼此緊鄰設置之任意二維變化特徵部)所引來之變化性之參數失誤而降低。舉例而言，這些參數失誤可能由無法精確地印刷接點及通孔以及製造程序中之變化性而產生；製造程序中之變化性可包含CMP碟形效應、因光微影、閘極失真、氧化物厚度變化性、佈植變化性、及其他製造相關現象所致之布局特徵部形狀失真。本發明之動態陣列結構係經定義成可說明上述半導體製造程序變化性。In view of the above, it should be understood that the semiconductor yield will be reduced due to variability parameter errors caused by the design-dependent unconstrained feature topology (that is, any two-dimensionally changing feature located next to each other). For example, these parameter errors may be caused by the inability to accurately print contacts and vias, and variability in the manufacturing process; variability in the manufacturing process may include CMP dish effects, due to photolithography, gate distortion, Distortions in layout features due to oxide thickness variability, implant variability, and other manufacturing-related phenomena. The dynamic array structure of the present invention is defined to account for the variability of the semiconductor manufacturing process described above.

圖1顯示根據本發明一實施例之若干布局特徵部及用以產生每一布局特徵部之光強度，尤其所顯示之三相鄰線形布局特徵部(101A-101C)係以實質上平行之關係而設置於一特定遮罩層內。來自一布局特徵部形狀之光強度的分佈係由sinc函數加以表示，sinc函數(103A-103C)表示來自布局特徵部中每一者(分別為101A-101C)之光強度的分佈，相鄰線形布局特徵部(101A-101C)在對應於sinc函數(103A-103C)之波峰的位置處相隔開，如此，與相鄰線形布局特徵部(101A-101C)相關聯之光能量之間的建設性干涉，亦即在sinc函數(103A-103C)之波峰處，可以增強所例示之布局特徵部間距之相鄰形狀(101A-101C)的曝光。與前述一致，在圖1中所示之光交互作用表示一同步的情況。Figure 1 shows a number of layout features and the light intensity used to generate each layout feature according to an embodiment of the invention. In particular, the three adjacent linear layout features (101A-101C) are shown in a substantially parallel relationship. It is disposed in a specific mask layer. The distribution of light intensity from the shape of a layout feature is represented by a sinc function. The sinc function (103A-103C) represents the distribution of light intensity from each of the layout features (101A-101C, respectively). The adjacent lines are The layout features (101A-101C) are separated at positions corresponding to the peaks of the sinc function (103A-103C). In this way, the constructive relationship between the light energy associated with the adjacent linear layout features (101A-101C) Interference, that is, at the peak of the sinc function (103A-103C), can enhance the exposure of adjacent shapes (101A-101C) of the illustrated layout feature pitch. Consistent with the foregoing, the light interaction shown in FIG. 1 represents a synchronized situation.

如圖1所示，當吾人以一規則重複圖案及一適當間距來定義線形布局特徵部時，與各種不同布局特徵部有關聯之光能量之建設性干涉可增強每一布局特徵部之曝光。由建設性光干涉所提供之增強布局特徵部之曝光，可大幅地降低甚至消除使用充份地產生布局特徵部所用之光學近接修正(OPC)及/或初縮遮罩增強技術之需求。As shown in FIG. 1, when we define a linear layout feature with a regular repeating pattern and an appropriate spacing, the constructive interference of light energy associated with various different layout features can enhance the exposure of each layout feature. The exposure of enhanced layout features provided by constructive light interference can greatly reduce or even eliminate the need to use optical proximity correction (OPC) and / or shrinkage mask enhancement techniques used to adequately generate layout features.

當相鄰布局特徵部(101A-101C)相隔之程度使得與一布局特徵部相關聯之sinc函數之波峰對齊與另一布局特徵部相關聯之sinc函數之波谷時，便產生禁止間距(亦即禁止布局特徵部間隔)，如此導致光能量的破壞性干涉。光能量的破壞性干涉使得集中在一特定位置處之光能量減少，因此，為實現與相鄰布局特徵部相關聯之有利建設性光干涉，必須預測將發生sinc函數波峰之建設性重疊之處的布局特徵部間隔。若布局特徵部形狀為矩形、幾近相同尺寸、且朝同一位向，如圖1之布局特徵部(101A-101C)所示，則可實現sinc函數波峰之可預測建設性重疊及相對應之布局特徵部形狀增強。以此方式，可利用來自相鄰布局特徵部形狀之共振光能量，以增強特殊布局特徵部形狀之曝光。When the adjacent layout features (101A-101C) are separated to such an extent that the peaks of the sinc function associated with one layout feature are aligned with the troughs of the sinc function associated with another layout feature, a forbidden spacing (i.e. Disallow layout feature spacing), which will cause destructive interference with light energy. The destructive interference of light energy reduces the light energy concentrated at a specific location. Therefore, in order to achieve beneficial constructive optical interference associated with adjacent layout features, it is necessary to predict where constructive overlap of the sinc function peaks will occur The layout features are spaced. If the shape of the layout feature is rectangular, nearly the same size, and oriented in the same direction, as shown in the layout feature (101A-101C) in Figure 1, the predictable constructive overlap of the sinc function peaks and the corresponding The layout feature shape is enhanced. In this way, the resonance light energy from the shapes of adjacent layout features can be used to enhance the exposure of the shape of a particular layout feature.

圖2顯示根據本發明一實施例之用以定義動態陣列結構之一般化疊層。應明瞭：吾人並非欲以如關於圖2所示之用以定義動態陣列結構之一般化疊層來完全代表CMOS製造程序；然而，吾人將根據標準CMOS製造程序來建立動態陣列。一般而言，動態陣列結構包含動態陣列之下層結構之定義及用以將區域使用最佳化之動態陣列之組裝技術兩者。因此，吾人設計動態陣列以將半導體製造能力最佳化。FIG. 2 shows a generalized stack for defining a dynamic array structure according to an embodiment of the present invention. It should be understood that we do not intend to fully represent the CMOS manufacturing process with a generalized stack that defines a dynamic array structure as shown in Figure 2; however, we will build a dynamic array according to standard CMOS manufacturing processes. Generally speaking, a dynamic array structure includes both the definition of the underlying structure of the dynamic array and the assembly technology used to optimize the area using the dynamic array. Therefore, we design dynamic arrays to optimize semiconductor manufacturing capabilities.

關於動態陣列之下層結構之定義，係將動態陣列以層狀方式設置於基底基板201上，例如在矽基板或絕緣層上覆矽(SOI)基板上。將擴散區203定義於基底基板201上，擴散區203代表基底基板201之選定區，為調整基底基板201之電氣性質的目的而將雜質引入該選定區內部。將擴散接點205定義在擴散區203上方，以連接擴散區203與導體線，例如定義擴散接點205以連接源極及汲極擴散區203與其個別導體網；又，將閘極特徵部207定義於擴散區203上方以形成電晶體閘極。定義閘極接點209以連接閘極特徵部207與導體線，例如定義閘極接點209以連接電晶體閘極與其個別導體網。The definition of the underlying structure of a dynamic array refers to arranging the dynamic array on a base substrate 201 in a layered manner, such as a silicon substrate or a silicon-on-insulator (SOI) substrate. A diffusion region 203 is defined on the base substrate 201, and the diffusion region 203 represents a selected region of the base substrate 201, and impurities are introduced into the selected region for the purpose of adjusting the electrical properties of the base substrate 201. The diffusion contact 205 is defined above the diffusion region 203 to connect the diffusion region 203 and the conductor line, for example, the diffusion contact 205 is defined to connect the source and drain diffusion regions 203 and their individual conductor networks; and the gate feature 207 Defined above the diffusion region 203 to form a transistor gate. The gate contact 209 is defined to connect the gate feature 207 and the conductor line. For example, the gate contact 209 is defined to connect the transistor gate and its individual conductor network.

將互連線層定義於擴散接點205層及閘極接點層209上方。互連線層包含第一金屬(金屬1)層211、第一通孔(通孔1)層213、第二金屬(金屬2)層215、第二通孔(通孔2)層217、第三金屬(金屬3)層219、第三通孔(通孔3)層221、及第四金屬(金屬4)層223，金屬及通孔層能夠電連接各種不同擴散接點205與閘極接點209，使電路的邏輯功能得以實現。應明瞭動態陣列結構並不限於特定數目之互連線層(亦即金屬及通孔層)，在一實施例中，除了第四金屬(金屬4)層223以外，動態陣列尚可包含額外互連線層225；或者，在另一實施例中，動態陣列可包含少於四個金屬層。An interconnect line layer is defined above the diffusion contact layer 205 and the gate contact layer 209. The interconnect layer includes a first metal (metal 1) layer 211, a first via (via 1) layer 213, a second metal (metal 2) layer 215, a second via (via 2) layer 217, a first The three metal (metal 3) layer 219, the third through hole (through hole 3) layer 221, and the fourth metal (metal 4) layer 223. The metal and through hole layer can electrically connect various diffusion contacts 205 to the gate electrode. At point 209, the logic function of the circuit can be realized. It should be understood that the dynamic array structure is not limited to a specific number of interconnect lines (ie, metal and via layers). In one embodiment, in addition to the fourth metal (metal 4) layer 223, the dynamic array may include additional interconnects. The wiring layer 225; or, in another embodiment, the dynamic array may include less than four metal layers.

定義動態陣列，使(除了擴散區層203以外的)膜層在關於可定義於其中之布局特徵部形狀受到限制。具體而言，在除了擴散區層203以外的各層中，僅容許線形布局特徵部。在一特定膜層中之線形布局特徵部之特徵在於具有一致的垂直橫截面形狀且沿單一方向延伸越過基板，因此，線形布局特徵部定義出一維變化之結構。擴散區203不需要為一維變化，然而必要時卻容許其為一維變化。具體而言，可將基板內之擴散區203定義成具有關於與基板之頂面一致之平面的任何二維變化形狀。在一實施例中，限制了擴散彎曲拓樸之數目，使擴散區中之彎曲與形成電晶體閘極之導電材料(例如多晶矽)之間的交互作用可加以預測且可準確地加以模型化。將在一特定膜層中之線形布局特徵部設置成彼此互相平行，如此，在一特定膜層中之線形布局特徵部即沿一共同方向延伸於基板上方並與基板平行。茲將參照圖3~15C以更進一步討論在各種不同層207~223中之線形布局特徵部之特殊結構及相關聯需求。The dynamic array is defined so that the shape of the film layer (except for the diffusion region layer 203) is restricted with respect to the shape of the layout features that can be defined therein. Specifically, in each of the layers other than the diffusion region layer 203, only a linear layout feature is allowed. The linear layout feature in a specific film layer is characterized by having a uniform vertical cross-sectional shape and extending across the substrate in a single direction. Therefore, the linear layout feature defines a one-dimensionally changing structure. The diffusion region 203 need not be changed in one dimension, but it is allowed to be changed in one dimension if necessary. Specifically, the diffusion region 203 in the substrate may be defined to have any two-dimensionally varying shape with respect to a plane consistent with the top surface of the substrate. In one embodiment, the number of diffusion bending topologies is limited, so that the interaction between the bending in the diffusion region and the conductive material (such as polycrystalline silicon) forming the transistor gate can be predicted and accurately modeled. The linear layout features in a specific film layer are arranged parallel to each other. Thus, the linear layout features in a specific film layer extend above the substrate in a common direction and are parallel to the substrate. The special structure and associated requirements of the linear layout features in various layers 207-223 will be discussed further with reference to FIGS. 3-15C.

動態陣列之下層布局方法係利用微影製程中光波的建設性干涉來強化一特定膜層中之相鄰形狀之曝光。因此，係將一特定膜層中之平行、線形布局特徵部之間隔設計成可迴避光駐波之建設性光干涉，使微影修正(例如OPC/RET)最小化或消除。如此，相較於習知基於OPC/RET之微影製程，此處所定義之動態陣列利用了相鄰特徵部之間的光交互作用，而非嘗試補償相鄰特徵部之間的光交互作用。The dynamic array underlying layout method uses constructive interference of light waves in the lithography process to enhance the exposure of adjacent shapes in a specific film layer. Therefore, the spacing of the parallel, linear layout features in a specific film layer is designed to avoid constructive optical interference of standing light waves, and to minimize or eliminate lithographic correction (such as OPC / RET). Thus, compared to the conventional lithography process based on OPC / RET, the dynamic array defined here utilizes the light interaction between adjacent features, rather than trying to compensate for the light interaction between adjacent features.

因為可將一特定線形布局特徵部之光駐波精確地模型化，故可預測與在一特定膜層中平行設置之相鄰線形布局特徵部相關聯之光駐波將如何互相作用，因而可預測用以曝露一線形特徵部之光駐波將如何促成其相鄰線形特徵部之曝光。預測相鄰線形特徵部之間的光交互作用能夠鑑別使得用以產生特定形狀之光將強化其相鄰形狀的最佳特徵部間之間隔，將在一特定膜層中之特徵部間之間隔定義成特徵部間距，其中該間距為一特定膜層中之相鄰線形特徵部之間的中心至中心之分隔距離。Because the light standing waves of a specific linear layout feature can be accurately modeled, it can be predicted how the light standing waves associated with adjacent linear layout features arranged in parallel in a specific film layer will interact with each other. Predict how a standing wave of light used to expose a linear feature will contribute to the exposure of its adjacent linear features. Predicting the light interaction between adjacent linear features can identify the space between the best features that will be enhanced by light used to produce a specific shape, and the space between features in a specific film It is defined as the feature distance, where the distance is the center-to-center separation distance between adjacent linear features in a specific film layer.

為了在相鄰特徵部之間提供所期望之曝光強化，將在一特定膜層中之線形布局特徵部彼此隔開，俾將來自相鄰特徵部之光的建設性及破壞性干涉最佳化，以產生所有附近特徵部之最佳呈現。在一特定膜層中之特徵部至特徵部間隔係正比於用以使特徵部曝光之波長，用以曝光在距一特定特徵部約五個光波長距離內之每一特徵部的光將可強化該特定特徵部之曝光至某種程度。用以曝光相鄰特徵部之光駐波之建設性干涉能夠使製造設備性能最大化，且不會受到關於微影製程期間之光交互作用影響所限制。In order to provide the desired exposure enhancement between adjacent features, the linear layout features in a specific film layer are separated from each other, and the constructive and destructive interference of light from adjacent features is optimized To produce the best representation of all nearby features. The feature-to-feature interval in a particular film layer is proportional to the wavelength used to expose the feature. The light used to expose each feature within a distance of about five light wavelengths from a particular feature will be Enhance the exposure of this specific feature to some extent. The constructive interference of light standing waves used to expose adjacent features can maximize the performance of manufacturing equipment and is not limited by the effects of light interaction during the lithography process.

如上所述，動態陣列包含限制拓樸，其中各膜層內之特徵部必須為以平行方式排列而以一共同方向橫越基板之線形特徵部。在光微影製程中之光交互作用可利用動態陣列之限制拓樸(restricted topology)加以最佳化，使得印刷於遮罩上之圖像本質上與布局中所繪製的形狀相同，亦即本質上達成將布局100%精確地轉印於光阻上。As described above, the dynamic array includes a restricted topology, in which the features in each film layer must be linear features arranged in parallel and crossing the substrate in a common direction. The light interaction in the photolithography process can be optimized using the restricted topology of the dynamic array, so that the image printed on the mask is essentially the same shape as the shape drawn in the layout, that is, the essence Shangda transferred the layout to the photoresist with 100% accuracy.

圖3A顯示根據本發明一實施例之待映射至動態陣列以輔助定義限制拓樸之例示基本網格。可利用基本網格加以輔助，而將線形特徵部以適當之最佳化間距平行排列於動態陣列之各層中。雖然物理上並未將基本網格定義成動態陣列的一部分，但其可被視為在動態陣列之各層上的映射；此外，應瞭解：基本網格係以關於在動態陣列之各層上之位置實質上一致的方式而被映射，如此輔助精確特徵部疊層及排列。FIG. 3A shows an exemplary basic grid to be mapped to a dynamic array to assist in defining a restricted topology according to an embodiment of the present invention. The basic grid can be used for assistance, and the linear features can be arranged in parallel in the layers of the dynamic array at an appropriate optimized pitch. Although the basic grid is not physically defined as part of the dynamic array, it can be considered as a mapping on the layers of the dynamic array. In addition, it should be understood that the basic grid is related to the position on the layers of the dynamic array. They are mapped in a substantially consistent manner, thus assisting the precise feature stacking and arrangement.

在圖3A之示範實施例中，係根據第一參考方向(x)及第二參考方向(y)而將基本網格定義成矩形網格(亦即直角基本網格)。可依需要而定義在第一及第二參考方向上之格點至格點之間隔，以便能夠定義具有最佳特徵部至特徵部之間隔的線形特徵部；此外，在第一方向(x)上之格點間隔可與在第二方向(y)上者不同。在一實施例中，係將單一基本網格映射遍及整個晶粒，以便能夠使在每一層中之各種不同之線形特徵部設置遍及整個晶粒；然而，在其他實施例中，可將個別基本網格映射遍及晶粒之獨立區域，以支援在晶粒之獨立區域內之特徵部間的不同間距要求。圖3B顯示根據本發明一例示實施例之待映射至整個晶粒之獨立區域的獨立基本網格。In the exemplary embodiment of FIG. 3A, the basic grid is defined as a rectangular grid (ie, a right-angle basic grid) according to the first reference direction (x) and the second reference direction (y). The grid-to-grid interval in the first and second reference directions can be defined as needed so that a linear feature with the best feature-to-feature interval can be defined; moreover, in the first direction (x) The interval between the grid points may be different from that in the second direction (y). In one embodiment, a single basic grid is mapped throughout the entire die so that various linear features in each layer can be set throughout the entire die; however, in other embodiments, individual basic grids can be mapped The grid map is spread across independent regions of the die to support different spacing requirements between feature parts within the independent regions of the die. FIG. 3B shows an independent basic grid to be mapped to an independent region of the entire die according to an exemplary embodiment of the present invention.

基本網格係考慮光交互作用功能(亦即sinc函數及製造性能)而加以定義，其中，該製造性能係藉由待用於製造動態陣列之設備及製程加以定義。關於光交互作用功能，係將基本網格定義成使得格點之間的間距能夠將波峰排列成描述映射於相鄰格點上之光能量之sinc函數。因此，可藉由自第一格點拉一直線至第二格點，具體指定針對微影強化而加以最佳化之線形特徵部，其中該直線係代表一特定寬度之矩形結構。應明瞭：可根據其在基本網格上之端點位置及其長度，具體指定在每一層中之各種線形特徵部。The basic grid is defined in consideration of the light interaction function (ie, the sinc function and manufacturing performance), wherein the manufacturing performance is defined by the equipment and process to be used for manufacturing a dynamic array. Regarding the light interaction function, the basic grid is defined so that the spacing between the grid points can arrange the wave peaks into a sinc function describing the light energy mapped on adjacent grid points. Therefore, by drawing a line from the first grid point to the second grid point, a linear feature portion optimized for lithography enhancement can be specifically specified, where the straight line represents a rectangular structure with a specific width. It should be clear that the various linear features in each layer can be specified based on their endpoint positions on the basic grid and their length.

圖3C顯示根據本發明一實施例之例示線形特徵部，其經定義成可與動態陣列相容。線形特徵部301具有一由寬度303及高度307所定義之實質上矩形之橫截面，線形特徵部301沿直線方向延伸至一長度305。在一實施例中，線形特徵部301之橫截面，如同由其寬度303及高度307所定義者，沿著其長度方向實質上為均勻狀；然而，應了解：微影效應可能引起線形特徵部301之端部的圓化。圖3A所示之第一及第二參考方向(x)及(y)分別用以說明動態陣列上之線形特徵部之例示位向，應明瞭：可將線形特徵部301定位成使其長度305沿第一參考方向(x)、第二參考方向(y)或相對於第一及第二參考方向(x)及(y)之對角線方向延伸。不論線形特徵部關於第一及第二參考方向(x)及(y)之特別位向為何，應明瞭線形特徵部係被定義在實質上平行於設置動態陣列之基板之頂面的平面上。又，應瞭解：線形特徵部在由第一及第二參考方向所定義之平面上並無彎曲部分(亦即方向變化)。FIG. 3C shows an exemplary linear feature according to an embodiment of the present invention, which is defined to be compatible with a dynamic array. The linear feature 301 has a substantially rectangular cross section defined by a width 303 and a height 307, and the linear feature 301 extends in a straight direction to a length 305. In an embodiment, the cross-section of the linear feature 301, as defined by its width 303 and height 307, is substantially uniform along its length; however, it should be understood that the lithographic effect may cause the linear feature Rounded end of 301. The first and second reference directions (x) and (y) shown in FIG. 3A are used to illustrate the example orientations of the linear features on the dynamic array. It should be clear that the linear features 301 can be positioned to have a length of 305. Extending in a first reference direction (x), a second reference direction (y), or a diagonal direction with respect to the first and second reference directions (x) and (y). Regardless of the special orientation of the linear features with respect to the first and second reference directions (x) and (y), it should be understood that the linear features are defined on a plane substantially parallel to the top surface of the substrate on which the dynamic array is disposed. It should also be understood that the linear feature does not have a curved portion (ie, a change in direction) on a plane defined by the first and second reference directions.

圖3D顯示根據本發明一實施例之另一例示線形特徵部317，其經定義成可與動態陣列相容。線形特徵部317具有由下寬313、上寬315、及高309所定義之梯形橫截面，線形特徵部317係沿直線方向延伸至長度311。在一實施例中，線形特徵部317之橫截面在其長度311方向上為實質上均勻；然而，應瞭解：微影效應可能會引起線形特徵部317之端部的圓化。圖3A所示之第一及第二參考方向(x)及(y)分別用以說明動態陣列上之線形特徵部之例示位向，應明瞭：可將線形特徵部317定位成使其長度311沿第一參考方向(x)、第二參考方向(y)或相對於第一及第二參考方向(x)及(y)之對角線方向延伸。不論線形特徵部317關於第一及第二參考方向(x)及(y)之特別位向為何，應明瞭線形特徵部317係被定義在實質上平行於設置動態陣列之基板之頂面的平面上。又，應瞭解：線形特徵部317在由第一及第二參考方向所定義之平面上並無彎曲部分(亦即方向變化)。FIG. 3D shows another exemplary linear feature portion 317 according to an embodiment of the present invention, which is defined to be compatible with a dynamic array. The linear feature portion 317 has a trapezoidal cross-section defined by a lower width 313, an upper width 315, and a height 309. The linear feature portion 317 extends in a straight direction to a length 311. In one embodiment, the cross-section of the linear feature 317 is substantially uniform in the direction of its length 311; however, it should be understood that the lithographic effect may cause rounding of the end of the linear feature 317. The first and second reference directions (x) and (y) shown in FIG. 3A are used to illustrate the example orientations of the linear features on the dynamic array. It should be clear that the linear features 317 can be positioned to have a length of 311. Extending in a first reference direction (x), a second reference direction (y), or a diagonal direction with respect to the first and second reference directions (x) and (y). Regardless of the special orientation of the linear feature 317 with respect to the first and second reference directions (x) and (y), it should be understood that the linear feature 317 is defined as a plane substantially parallel to the top surface of the substrate on which the dynamic array is disposed on. It should also be understood that the linear feature portion 317 does not have a curved portion (ie, a change in direction) on a plane defined by the first and second reference directions.

雖然圖3C及3D分別清楚地討論了具有矩形及梯形橫截面之線形特徵部，應瞭解亦可將具有其他橫截面類型之線形特徵部定義於動態陣列內。因此，本質上任何適合橫截面形狀之線形特徵部均可使用，只要將線形特徵部定義成具有在一方向上延伸之長度，且定位成使其長度沿第一參考方向(x)、第二參考方向(y)或相對於第一及第二參考方向(x)及(y)之對角線方向延伸即可。Although FIGS. 3C and 3D clearly discuss linear features with rectangular and trapezoidal cross-sections, respectively, it should be understood that linear features with other cross-sectional types can also be defined within a dynamic array. Therefore, essentially any linear feature suitable for the cross-sectional shape can be used, as long as the linear feature is defined to have a length extending in one direction and positioned so that its length is along the first reference direction (x), the second reference The direction (y) or diagonal directions with respect to the first and second reference directions (x) and (y) may be sufficient.

動態陣列之布局架構遵循基本網格圖案。因此，可利用格點來代表在擴散時方向變化發生於何處、閘極及金屬特徵部設置於何處、接點位於何處、在線形閘極及金屬特徵部中之開口位於何處等。應針對一特定特徵部線寬(例如圖3C中之寬度303)而設定格點之間距(亦即格點至格點之間隔)，使該特定特徵部線寬之相鄰線形特徵部之曝光將彼此強化，其中該線形特徵部係集中於格點上。在一實施例中，參照圖2之動態陣列疊層及圖3A之例示基本網格，第一參考方向(x)上之格點間隔係藉由所需之閘極間距加以設定。在此相同之實施例中，係藉由金屬1及金屬3間距來設定第二參考方向(y)上之格點間距，例如在90nm製程技術(亦即最小特徵部尺寸等於90nm)中，第二參考方向(y)上之格點間距約為0.24微米。在一實施例中，金屬1及金屬2層將具有一共同間距及間隔，但在金屬2層上方亦可使用不同間距及間隔。The layout structure of the dynamic array follows the basic grid pattern. Therefore, grid points can be used to represent where the direction change occurs during diffusion, where the gate and metal features are located, where the contacts are located, where the openings in the linear gate and metal features are located, etc. . For a specific feature line width (such as the width 303 in FIG. 3C), the distance between the grid points (that is, the interval from the grid point to the grid point) should be set to expose the adjacent linear features of the specific feature line width. Strengthen each other, where the linear features are concentrated on the grid points. In one embodiment, referring to the dynamic array stack of FIG. 2 and the illustrated basic grid of FIG. 3A, the grid spacing in the first reference direction (x) is set by the required gate spacing. In this same embodiment, the grid distance in the second reference direction (y) is set by the metal 1 and metal 3 pitches. For example, in the 90nm process technology (that is, the minimum feature size is equal to 90nm), the first The grid spacing in the two reference directions (y) is about 0.24 microns. In one embodiment, the metal 1 and metal 2 layers will have a common pitch and interval, but different pitches and intervals may be used above the metal 2 layer.

將各種不同之動態陣列層定義成使鄰近層中之線形特徵部係以彼此交叉之方式延伸。舉例而言，鄰近層之線形特徵部可以正交方式延伸，亦即彼此垂直；此外，一層之線形特徵部可以一角度(例如約45度)延伸越過鄰近層之線形特徵部。例如，在一實施例中，一層之線形特徵部沿第一參考方向(x)延伸，而鄰近層之線形特徵部則關於第一(x)及第二(y)參考方向之對角線方向延伸。應明瞭：為了在具有以交叉方式設置於相鄰膜層上之線形特徵部之動態陣列中進行設計，可將開口定義於線形特徵部中，而接點及通孔則可依需要加以定義。Various different dynamic array layers are defined such that linear features in adjacent layers extend in a manner crossing each other. For example, the linear features of adjacent layers may extend orthogonally, that is, perpendicular to each other; in addition, the linear features of one layer may extend over the linear features of adjacent layers at an angle (eg, about 45 degrees). For example, in one embodiment, the linear features of one layer extend along the first reference direction (x), and the linear features of adjacent layers are related to the diagonal directions of the first (x) and second (y) reference directions. extend. It should be understood that, in order to design in a dynamic array having linear features arranged in a cross manner on adjacent film layers, openings can be defined in the linear features, and contacts and through holes can be defined as needed.

動態陣列將對於布局形狀中彎曲部分之利用最小化，以消除無法預測之微影交互作用。具體而言，在施行OPC或其他RET處理之前，動態陣列容許擴散層中之彎曲能夠控制裝置尺寸，但不容許在擴散層上方之膜層中之彎曲部分。在擴散層上方之各層中之布局特徵部為直線形(例如圖3C)，且係彼此平行設置。布局特徵部之直線形狀及平行設置方式係施行於必須具有建設性光干涉之可預測性之每一疊層的動態陣列中，以確保可製造性。在一實施例中，布局特徵部之直線形狀及平行設置方式係施行於擴散穿金屬(diffusion through metal)2上方之每一層之動態陣列中。在金屬2上方，布局特徵部可具有不需要建設性光干涉之充分尺寸及形狀，以確保可製造性；然而，在對金屬2上方之布局特徵部圖案化時，存在建設性光干涉可能有益。Dynamic arrays minimize the use of curved parts in layout shapes to eliminate unpredictable lithographic interactions. Specifically, before performing OPC or other RET treatments, the dynamic array allows bending in the diffusion layer to control the device size, but does not allow bending portions in the film layer above the diffusion layer. The layout features in each layer above the diffusion layer are linear (eg, FIG. 3C) and are arranged in parallel with each other. The linear shape and parallel arrangement of the layout features are implemented in a dynamic array of each stack that must have predictability of constructive optical interference to ensure manufacturability. In one embodiment, the linear shape and parallel arrangement of the layout features are implemented in a dynamic array of each layer above diffusion through metal 2. Above the metal 2, the layout features may have a sufficient size and shape that does not require constructive light interference to ensure manufacturability; however, when patterning the layout features above the metal 2, the presence of constructive light interference may be beneficial .

茲參照圖4至14來說明由擴散穿金屬2增建動態陣列層之範例。應明瞭：關於圖4至14說明之動態陣列僅提供作為例子，不應視為傳達動態陣列結構之限制。可根據此處所述之原理使用動態陣列，以便實質上定義任何積體電路設計。Examples of adding a dynamic array layer by diffusion through metal 2 are described with reference to FIGS. 4 to 14. It should be understood that the dynamic arrays described with respect to FIGS. 4 to 14 are provided as examples only and should not be considered as conveying the limitations of the dynamic array structure. Dynamic arrays can be used in accordance with the principles described herein to define virtually any integrated circuit design.

圖4顯示根據本發明一實施例之例示動態陣列之擴散層布局。圖4之擴散層顯示出一p擴散區401及n擴散區403，當根據下層基本網格來定義擴散區時，擴散區並不受到與擴散層上方之膜層相關聯之線形特徵部限制。擴散區401及403包含定義於將於該處設置擴散接點的擴散方塊405，擴散區401及403不包含無關之凸出部或稜角，如此可改善微影解析度之使用並致能更精確之裝置取出。此外，係將n+遮罩區(412及416)及p+遮罩區(410及414)定義成在(x), (y)網格上無無關之凸出部或缺口之矩形，此類型容許採用較大擴散區、不需要OPC/RET，且能夠使用較低解析度及較少成本之微影系統，例如在365nm下之i線照明(i-line illumination)。應明瞭如圖4所示之n+遮罩區416及p+遮罩區410係用於並未使用充分偏壓(well-biasing)之實施例，而在使用充分偏壓之另一實施例中，圖4中所示之n+遮罩區416實際上將會被定義成p+遮罩區。此外，在此可供選擇之實施例中，圖4中所示之p+遮罩區410實際上將會被定義成n+遮罩區。FIG. 4 shows a layout of a diffusion layer of an exemplary dynamic array according to an embodiment of the present invention. The diffusion layer in FIG. 4 shows a p-diffusion region 401 and an n-diffusion region 403. When the diffusion region is defined according to the underlying basic grid, the diffusion region is not limited by the linear features associated with the film layer above the diffusion layer. The diffusion regions 401 and 403 include a diffusion block 405 defined at which a diffusion contact is to be set. The diffusion regions 401 and 403 do not include irrelevant protrusions or corners, which can improve the use of lithographic resolution and enable more accuracy. Take out the device. In addition, the n + mask regions (412 and 416) and p + mask regions (410 and 414) are defined as rectangles without irrelevant protrusions or gaps on the (x), (y) grid. This type allows It uses a larger diffusion area, does not require OPC / RET, and can use a lower resolution and lower cost lithography system, such as i-line illumination at 365nm. It should be understood that the n + mask region 416 and the p + mask region 410 shown in FIG. 4 are for an embodiment that does not use well-biasing, and in another embodiment that uses full bias, The n + mask region 416 shown in FIG. 4 will actually be defined as a p + mask region. In addition, in this alternative embodiment, the p + mask region 410 shown in FIG. 4 will actually be defined as an n + mask region.

圖5顯示根據本發明一實施例之閘極層及擴散接點層，其係位於圖4的擴散層上方並與該擴散層相鄰。如熟悉CMOS技藝人士將明瞭者，閘極特徵部501定義電晶體閘極，而吾人將閘極特徵部501定義成以平行關係沿第二參考方向(y)橫越動態陣列之線形特徵部。在一實施例中，係將閘極特徵部501定義成具有一共同寬度；然而，在另一實施例中，可將一或更多閘極特徵部定義成具有不同寬度，例如圖5即顯示相對於其他閘極特徵部501具有更大寬度之閘極特徵部501A。使閘極特徵部501之間距(中心至中心的間隔)最小化，同時確保由相鄰閘極特徵部501提供最佳微影強化(亦即共振成像)。為討論故，將沿一特定直線延伸越過動態陣列之閘極特徵部501稱為閘極軌道。FIG. 5 shows a gate layer and a diffusion contact layer according to an embodiment of the present invention, which are located above and adjacent to the diffusion layer of FIG. 4. As will be clear to those skilled in CMOS technology, the gate feature 501 defines a transistor gate, and we define the gate feature 501 as a linear feature that traverses a dynamic array along a second reference direction (y) in a parallel relationship. In one embodiment, the gate feature 501 is defined to have a common width; however, in another embodiment, one or more gate features may be defined to have different widths, as shown in FIG. 5 The gate feature 501A having a larger width than the other gate features 501. The distance (center-to-center interval) between the gate feature portions 501 is minimized, and at the same time, the best lithography enhancement (ie, resonance imaging) is provided by adjacent gate feature portions 501. For the sake of discussion, the gate feature 501 extending along a specific straight line across the dynamic array is referred to as a gate track.

當閘極特徵部501穿過擴散區403及401時，便分別形成n通道及p通道電晶體。最佳閘極特徵部501印刷係藉由在每一網格位置處繪製出閘極特徵部501而達成，即使在相同網格位置處可能並無擴散區存在亦然；此外，在動態陣列內部中，長的連續閘極特徵部501易於在閘極特徵部之端部處改良線端縮短效應(line end shortening effect)。又，當所有彎曲部分均自閘極特徵部501移除時，便會明顯地改善閘極印刷。When the gate feature 501 passes through the diffusion regions 403 and 401, n-channel and p-channel transistors are formed, respectively. The best gate feature 501 printing is achieved by drawing the gate feature 501 at each grid position, even if there may not be a diffusion zone at the same grid position; in addition, inside the dynamic array In the middle, the long continuous gate feature 501 is apt to improve the line end shortening effect at the end of the gate feature. In addition, when all the curved parts are removed from the gate feature 501, the gate printing is significantly improved.

為提供用於待施行之特殊邏輯功能之所需電連接，每一閘極軌道可沿直線地橫貫動態陣列之方式被中斷(亦即打斷)任意次數。當需要中斷一特定閘極軌道時，使在中斷點處之閘極軌道片段的端部之間的間隔最小化至可能考慮製造效應及電效應的程度。在一實施例中，當在特定層內之特徵部之間採用一共同之端部至端部間距時，便達到最佳可製造性。In order to provide the required electrical connection for the special logic function to be implemented, each gate track can be interrupted (ie, interrupted) any number of times in a straight line across the dynamic array. When a particular gate track needs to be interrupted, the interval between the ends of the gate track segments at the point of interruption is minimized to the extent that manufacturing and electrical effects may be considered. In one embodiment, the best manufacturability is achieved when a common end-to-end spacing is used between the features in a particular layer.

將在中斷點處之閘極軌道片段的端部之間的間隔最小化可使由鄰近閘極軌道所提供之微影強化及其均勻性最大化。此外，在一實施例中，若相鄰閘極軌道需要加以中斷，即以使個別中斷點彼此偏移之方式來中斷相鄰閘極軌道，以儘量避免鄰近點發生中斷。更具體而言，係將相鄰閘極軌道內之中斷點分別設置成使得視線不存在於所有中斷點，其中該視線被視為以與閘極軌道於基板上方延伸之方向垂直之方式延伸。另外，在一實施例中，閘極可延伸越過在格子(亦即PMOS或NMOS格)之頂部或底部處的邊界，此實施例會使得鄰近格能夠橋接。Minimizing the gap between the ends of the gate track segments at the break point can maximize the lithographic enhancement and its uniformity provided by adjacent gate tracks. In addition, in an embodiment, if the adjacent gate tracks need to be interrupted, the adjacent gate tracks are interrupted in such a manner that the individual interruption points are offset from each other, so as to avoid interruption at adjacent points as much as possible. More specifically, the interruption points in adjacent gate tracks are set so that the line of sight does not exist at all the interruption points, wherein the line of sight is considered to extend perpendicular to the direction in which the gate track extends above the substrate. In addition, in one embodiment, the gate can extend across the boundary at the top or bottom of the grid (ie, PMOS or NMOS grid). This embodiment will enable adjacent grids to bridge.

再關於圖5，擴散接點503係被定義於每一擴散方塊405處，以經由共振成像而增強擴散接點之印刷。擴散方塊405存在於每一擴散接點503附近，以增強在擴散接點503處之電源及接地連線多邊形之印刷。Referring again to FIG. 5, a diffusion contact 503 is defined at each diffusion block 405 to enhance the printing of the diffusion contact via resonance imaging. A diffusion block 405 exists near each diffusion contact 503 to enhance the printing of the power and ground connection polygons at the diffusion contact 503.

閘極特徵部501及擴散接點503共用一共同網格間距；更具體而言，閘極特徵部501之配置相對於擴散接點503而言偏移1/2網格間距。例如若閘極特徵部501及擴散接點503之網格間距為0.36µm，則擴散接點被設置成使其中心之x坐標落在0.36µm之整數倍上，而每一閘極特徵部501中心之x坐標減去0.18µm應該為0.36µm之整數倍。在本實施例中，x坐標係由下列式子加以表示： 擴散接點中心之x坐標=I*0.36µm，其中I為網格數目； 閘極特徵部中心之x坐標=0.18µm +I*0.36µm，其中I為網格數目。The gate feature portion 501 and the diffusion contact 503 share a common grid pitch; more specifically, the configuration of the gate feature 501 is offset from the diffusion contact 503 by a half grid pitch. For example, if the grid distance between the gate feature 501 and the diffusion contact 503 is 0.36µm, the diffusion contact is set so that the x coordinate of its center falls on an integer multiple of 0.36µm, and each gate feature 501 The x coordinate of the center minus 0.18µm should be an integer multiple of 0.36µm. In this embodiment, the x coordinate system is expressed by the following formula: x coordinate of the center of the diffusion contact = I * 0.36µm, where I is the number of grids; x coordinate of the center of the gate feature part = 0.18µm + I * 0.36µm, where I is the number of grids.

動態陣列之基本網格系統確保了所有接點(擴散及閘極)將會落在等於擴散接點網格之一半之倍數的水平網格及由金屬1間距所設定之垂直網格上。在上述實施例中，閘極特徵部及擴散接點網格為0.36µm，擴散接點及閘極接點將會落在為0.18µm之倍數的水平網格上；又，90nm製程技術之垂直網格約為0.24µm。The basic grid system of the dynamic array ensures that all contacts (diffusion and gate) will fall on a horizontal grid equal to a multiple of one-half of the diffused contact grid and a vertical grid set by the metal 1 pitch. In the above embodiment, the grid of the gate feature and the diffusion contact is 0.36 µm, and the diffusion and the gate contact will fall on a horizontal grid which is a multiple of 0.18 µm; and the vertical grid of the 90nm process technology The grid is about 0.24µm.

圖6顯示根據本發明一實施例之閘極接點層，其係經定義於圖5之閘極層上方且與之相鄰。在閘極接點層中，係將閘極接點601繪製成俾能夠將閘極特徵部501連接至上覆金屬導線。一般而言，設計規則將會指定閘極接點601之最佳配置，在一實施例中，係將閘極接點繪製於電晶體末端護套區之頂部上，當設計規則指定長形電晶體末端護套時，此實施例係將動態陣列中之白空間(white space)最小化。在某些製程技術中，可藉由置放若干格子之閘極接點於該格子的中心內而將白空間最小化；此外，應明瞭：在本實施例中，閘極接點601在垂直於閘極特徵部501之方向上係具有超大尺寸，以確保閘極接點601與閘極特徵部501之間有重疊。FIG. 6 shows a gate contact layer according to an embodiment of the present invention, which is defined above and adjacent to the gate layer of FIG. 5. In the gate contact layer, the gate contact 601 is drawn so that the gate feature 501 can be connected to the overlying metal wire. Generally speaking, the design rule will specify the optimal configuration of the gate contact 601. In one embodiment, the gate contact is drawn on the top of the sheath region at the end of the transistor. This embodiment minimizes the white space in the dynamic array when the lens ends are sheathed. In some process technologies, the white space can be minimized by placing the gate contacts of a plurality of grids in the center of the grid; in addition, it should be understood that, in this embodiment, the gate contacts 601 are vertical There is an oversize in the direction of the gate feature 501 to ensure that there is an overlap between the gate contact 601 and the gate feature 501.

圖7A顯示用以與閘極接觸之習知方法，例如多晶矽特徵部。在圖7A之習知結構中，定義了其中設置有閘極接點709之放大矩形閘極區707，此放大矩形閘極區707在閘極中引進了距離705之彎曲，與放大矩形閘極區707相關聯之彎曲產生了非期望之光交互作用，且扭曲了閘極線711。當閘極寬度約與電晶體長度相同時，閘極線的扭曲尤其會引起問題。FIG. 7A shows a conventional method for contacting a gate, such as a polysilicon feature. In the conventional structure of FIG. 7A, an enlarged rectangular gate region 707 having a gate contact 709 provided therein is defined. This enlarged rectangular gate region 707 introduces a curvature of a distance of 705 into the gate, and the enlarged rectangular gate The associated bending of the region 707 creates an undesired optical interaction and distorts the gate line 711. When the gate width is about the same as the transistor length, distortion of the gate line can cause problems in particular.

圖7B顯示根據本發明一實施例加以定義之閘極接點601(例如多晶矽接點)。將閘極接點601繪製成與閘極特徵部501之邊緣重疊，且沿實質上垂直於閘極特徵部501之方向延伸。在一實施例中，係將閘極接點601繪製成使得垂直維度703與用於擴散接點503之垂直維度相同。例如若將擴散接點503之開口設定在0.12µm x 0.12µm，則閘極接點601之垂直維度繪製於0.12µm。然而，在其他實施例中，可將閘極接點601繪製成使得垂直維度703與用於擴散接點503之垂直維度不同。FIG. 7B shows a gate contact 601 (such as a polycrystalline silicon contact) defined according to an embodiment of the present invention. The gate contact 601 is drawn so as to overlap the edge of the gate feature 501 and extends in a direction substantially perpendicular to the gate feature 501. In one embodiment, the gate contact 601 is drawn such that the vertical dimension 703 is the same as the vertical dimension used for the diffusion contact 503. For example, if the opening of the diffusion contact 503 is set at 0.12µm x 0.12µm, the vertical dimension of the gate contact 601 is drawn at 0.12µm. However, in other embodiments, the gate contact 601 may be drawn such that the vertical dimension 703 is different from the vertical dimension used for the diffusion contact 503.

在一實施例中，係將閘極接點601在閘極特徵部501以外的延長部分701設定成使最大重疊係發生在閘極接點601與閘極特徵部501之間，延長部分701係定義成可適應閘極接點601之線端縮短效應以及閘極接點層與閘極特徵部層之間的失準。閘極接點601之長度係定義成可確保閘極接點601與閘極特徵部501之間有最大表面積接觸，其中該最大表面積接觸係由閘極特徵部501之寬度加以定義。In one embodiment, the extension 701 of the gate contact 601 outside the gate feature 501 is set so that the maximum overlap occurs between the gate contact 601 and the gate feature 501, and the extension 701 is It is defined to be able to adapt to the line terminal shortening effect of the gate contact 601 and the misalignment between the gate contact layer and the gate feature layer. The length of the gate contact 601 is defined to ensure a maximum surface area contact between the gate contact 601 and the gate feature 501, wherein the maximum surface area contact is defined by the width of the gate feature 501.

圖8A顯示根據本發明一實施例之金屬1層，其係經定義於圖6之閘極接點層上方並與之相鄰。金屬1層包含若干金屬1軌道801-821，其經定義成可包含以平行關係延伸越過動態陣列之線形特徵部。在圖5之下方閘極層中，金屬1軌道801-821係沿實質上垂直於閘極特徵部501之方向延伸，如此，在本例中，金屬1軌道801-821沿第一參考方向(x)直線地延伸越過動態陣列，金屬1軌道801-821之間距(中心至中心的間隔)得以最小化，同時確保由鄰近金屬1軌道801-821所提供之微影強化之最佳化(亦即共振成像)。例如在一實施例中，金屬1軌道801-821集中在用於90nm製程技術之約0.24µm之垂直網格上。FIG. 8A shows a metal 1 layer according to an embodiment of the present invention, which is defined above and adjacent to the gate contact layer of FIG. 6. The metal 1 layer includes a number of metal 1 tracks 801-821, which are defined to include linear features extending in a parallel relationship across a dynamic array. In the lower gate layer in FIG. 5, the metal 1 track 801-821 extends in a direction substantially perpendicular to the gate feature 501. Thus, in this example, the metal 1 track 801-821 follows the first reference direction ( x) Extending straight across the dynamic array, the distance (center-to-center spacing) between metal 1 tracks 801-821 is minimized, while ensuring the optimization of lithographic enhancement provided by adjacent metal 1 tracks 801-821 (also (Ie resonance imaging). For example, in one embodiment, the metal 1 track 801-821 is concentrated on a vertical grid of about 0.24 μm for 90 nm process technology.

為提供用於待施行之特殊邏輯功能之所需電連接，每一金屬1軌道801-821可沿直線地橫貫動態陣列之方式被中斷(亦即打斷)任意次數。當需要中斷一特定金屬1軌道801-821時，使在中斷點處之金屬1軌道片段的端部之間的間隔最小化至可能考慮製造效應及電效應的程度。將在中斷點處之金屬1軌道片段的端部之間的間隔最小化，可使由鄰近金屬1軌道所提供之微影強化及其均勻性最大化。此外，在一實施例中，若相鄰金屬1軌道需要加以中斷，即以使個別中斷點彼此偏移之方式來中斷相鄰金屬1軌道，以儘量避免鄰近點發生中斷。更具體而言，係將相鄰金屬1軌道內之中斷點分別設置成使得視線不存在於所有中斷點，其中該視線被視為以與金屬1軌道於基板上方延伸之方向垂直之方式延伸。In order to provide the required electrical connection for the special logic function to be implemented, each metal 1 track 801-821 can be interrupted (ie, interrupted) any number of times in a straight line across the dynamic array. When a specific metal 1 track 801-821 needs to be interrupted, the interval between the ends of the metal 1 track segment at the point of interruption is minimized to the extent that manufacturing effects and electrical effects may be considered. Minimizing the spacing between the ends of the metal 1 track segments at the breakpoints can maximize the lithographic enhancement and uniformity provided by the adjacent metal 1 track. In addition, in an embodiment, if the adjacent metal 1 tracks need to be interrupted, the adjacent metal 1 tracks are interrupted in such a manner that the individual interruption points are offset from each other, so as to avoid interruption at adjacent points as much as possible. More specifically, the interruption points in adjacent metal 1 tracks are set so that the line of sight does not exist at all the interruption points, wherein the line of sight is considered to extend perpendicular to the direction in which the metal 1 track extends above the substrate.

在圖8A之實施例中，金屬1軌道801係連接至接地供應器，且金屬1軌道821係連接至電力供應電壓。在圖8A之實施例中，金屬1軌道801及821之寬度與其他金屬1軌道803-819相同；然而，在另一實施例中，金屬1軌道801及821之寬度大於其他金屬1軌道803-819之寬度。圖8B顯示圖8A之金屬1層，其金屬1接地及電力軌道(801A及821A)相對於其他金屬1軌道803-819而言具有較大之軌道寬度。In the embodiment of FIG. 8A, the metal 1 rail 801 is connected to the ground supply, and the metal 1 rail 821 is connected to the power supply voltage. In the embodiment of FIG. 8A, the widths of the metal 1 rails 801 and 821 are the same as those of other metal 1 rails 803-819; however, in another embodiment, the widths of the metal 1 rails 801 and 821 are larger than those of the other metal 1 rails 803- 819 width. FIG. 8B shows the metal 1 layer of FIG. 8A. The metal 1 ground and power rails (801A and 821A) have a larger track width than other metal 1 rails 803-819.

金屬1軌道圖案最佳地係用以將「白空間」(未被電晶體佔據的空間)之使用最佳化。圖8A之實施例包含兩個共享金屬1電力軌道801、821及九個金屬1訊號軌道803-819。金屬1軌道803, 809, 811及819被定義成閘極接點軌道，以便將白空間最小化；定義金屬1軌道813, 815及817以連接p通道源極及汲極；此外，若不需要連接，則可利用九個金屬1訊號軌道803-809中任一者來作為饋通，例如金屬1軌道813及815係用作饋通連接。The metal 1 track pattern is optimally used to optimize the use of "white space" (space not occupied by transistors). The embodiment of FIG. 8A includes two shared metal 1 power tracks 801, 821 and nine metal 1 signal tracks 803-819. Metal 1 tracks 803, 809, 811, and 819 are defined as gate contact tracks to minimize white space; metal 1 tracks 813, 815, and 817 are defined to connect the p-channel source and drain; in addition, if not required Connection, any one of the nine metal 1 signal tracks 803-809 can be used as a feedthrough. For example, metal 1 tracks 813 and 815 are used as feedthrough connections.

圖9顯示根據本發明一實施例之通孔1層，其係經定義於圖8A之金屬1層上方且與之相鄰。通孔901被定義於通孔1層中，以使金屬1軌道801-821連接至較高高度之導線。FIG. 9 shows a through-hole 1 layer according to an embodiment of the present invention, which is defined above and adjacent to the metal 1 layer of FIG. 8A. The through-hole 901 is defined in the first layer of the through-hole so that the metal 1 track 801-821 is connected to a higher-level wire.

圖10顯示根據本發明一實施例之金屬2層，其係經定義於圖9之通孔1層上方且與之相鄰。金屬2層包含若干經定義成以水平方向延伸跨越動態陣列之線形特徵部之金屬2軌道1001，金屬2軌道1001係以實質上垂直於在圖8A之下方金屬1層中之金屬1軌道801-821的方向、且以實質上平行於在圖5之下方閘極層中之閘極軌道501的方向延伸。如此，在本實施例中，金屬2軌道1001係在第二參考方向(y)上直線延伸跨越動態陣列。FIG. 10 shows a metal 2 layer according to an embodiment of the present invention, which is defined above and adjacent to the through-hole 1 layer of FIG. 9. The metal 2 layer includes a number of metal 2 tracks 1001 defined to extend horizontally across the linear features of the dynamic array. The metal 2 track 1001 is substantially perpendicular to the metal 1 track 801 in the metal 1 layer below FIG. 8A. The direction of 821 extends in a direction substantially parallel to the gate track 501 in the gate layer below FIG. 5. As such, in this embodiment, the metal 2 track 1001 extends linearly across the dynamic array in the second reference direction (y).

將金屬2軌道1001之間距(中心至中心間隔)最小化，同時確保由相鄰金屬2軌道所提供之微影強化可達最佳化(亦即共振成像)。應明瞭：可以與在閘極及金屬1層中相同之施行方式，將規則性維持於較高高度之互連線層上。在一實施例中，閘極特徵部501間距及金屬2軌道間距相同。在另一實施例中，接觸閘極間距(例如其間具有擴散接點之多晶矽至多晶矽間隔)大於金屬2軌道間距。在此實施例中，係將金屬2軌道間距任意地設定為接觸閘極間距之2/3或3/4，如此，在此實施例中，閘極軌道及金屬2軌道在每兩個閘極軌道間距及每三個金屬2軌道間距處對齊。例如，在90nm製程技術中，最佳接觸閘極軌道間距為0.36µm，最佳金屬2軌道間距為0.24µm。在另一實施例中，閘極軌道及金屬2軌道在每三個閘極間距及每四個金屬2間距處對齊。例如，在90nm製程技術中，最佳接觸閘極軌道間距為0.36µm，最佳金屬2軌道間距為0.27µm。The distance (center-to-center interval) between the metal 2 tracks 1001 is minimized, and at the same time, the lithography enhancement provided by the adjacent metal 2 tracks can be optimized (that is, resonance imaging). It should be clear that the regularity can be maintained on the interconnect line layer at a higher height in the same way as in the gate and metal 1 layers. In one embodiment, the pitch between the gate feature portions 501 and the metal 2 track pitch are the same. In another embodiment, the contact gate pitch (for example, the polysilicon to polysilicon gap with diffusion contacts in between) is larger than the metal 2 track pitch. In this embodiment, the metal 2 track interval is arbitrarily set to be 2/3 or 3/4 of the contact gate distance. Thus, in this embodiment, the gate track and the metal 2 track are at every two gates. The track pitch is aligned at every three metal 2 track pitches. For example, in 90nm process technology, the optimal contact gate track spacing is 0.36µm, and the optimal metal 2 track spacing is 0.24µm. In another embodiment, the gate tracks and metal 2 tracks are aligned at every three gate pitches and every four metal 2 pitches. For example, in 90nm process technology, the optimal contact gate track spacing is 0.36µm, and the optimal metal 2 track spacing is 0.27µm.

為提供用於待施行之特殊邏輯功能之所需電連接，每一金屬2軌道1001可沿直線地橫貫動態陣列之方式被中斷(亦即打斷)任意次數。當需要中斷一特定金屬2軌道1001時，使在中斷點處之金屬2軌道片段的端部之間的間隔最小化至可能考慮製造效應及電效應的程度。將在中斷點處之金屬2軌道片段的端部之間的間隔最小化，可使由鄰近金屬2軌道所提供之微影強化及其均勻性最大化。此外，在一實施例中，若相鄰金屬2軌道需要加以中斷，即以使個別中斷點彼此偏移之方式來中斷相鄰金屬2軌道，以儘量避免鄰近點發生中斷。更具體而言，係將相鄰金屬2軌道內之中斷點分別設置成使得視線不存在於所有中斷點，其中該視線被視為以與金屬2軌道於基板上方延伸之方向垂直之方式延伸。In order to provide the required electrical connection for the special logic function to be performed, each metal 2 track 1001 can be interrupted (ie, interrupted) any number of times in a straight line across the dynamic array. When a specific metal 2 track 1001 needs to be interrupted, the interval between the ends of the metal 2 track segment at the point of interruption is minimized to the extent that manufacturing effects and electrical effects may be considered. Minimizing the gap between the ends of the metal 2 track segments at the break point can maximize the lithographic enhancement and uniformity provided by the adjacent metal 2 track. In addition, in an embodiment, if the adjacent metal 2 tracks need to be interrupted, the adjacent metal 2 tracks are interrupted in such a manner that the individual interruption points are offset from each other, so as to avoid interruption of adjacent points as much as possible. More specifically, the interruption points in adjacent metal 2 tracks are set so that the line of sight does not exist at all the interruption points, wherein the line of sight is considered to extend perpendicular to the direction in which the metal 2 track extends above the substrate.

如上所述，在閘極層上方之一特定金屬層中之導線可以與第一參考方向(x)或第二參考方向(y)一致之方向貫穿動態陣列；應更明瞭：根據本發明之一實施例，在閘極層上方之一特定金屬層中之導線可以相對於第一參考方向(x)及第二參考方向(y)之第一對角線方向橫貫動態陣列。圖12顯示根據本發明一實施例之導體軌道1201，其係沿相對於第一及第二參考方向(x)及(y)之第二對角線方向橫貫動態陣列。As mentioned above, the wires in a specific metal layer above the gate layer may pass through the dynamic array in a direction consistent with the first reference direction (x) or the second reference direction (y); it should be more clear: according to one of the invention In an embodiment, the wires in a specific metal layer above the gate layer may traverse the dynamic array with respect to the first diagonal direction of the first reference direction (x) and the second reference direction (y). FIG. 12 shows a conductor track 1201 according to an embodiment of the present invention, which traverses the dynamic array along a second diagonal direction with respect to the first and second reference directions (x) and (y).

如同以上所討論之關於金屬1及金屬2軌道，為提供用於待施行之特殊邏輯功能之所需電連接，圖11及12之橫貫對角線之導體軌道1101及1201可沿直線地橫貫動態陣列之方式被中斷(亦即打斷)任意次數。當需要中斷一特定橫貫對角線之導體軌道時，使在中斷點處之對角線導體軌道的端部之間的間隔最小化至可能考慮製造效應及電效應的程度。將在中斷點處之對角線導體軌道的端部之間的間隔最小化，可使由鄰近對角線導體軌道所提供之微影強化及其均勻性最大化。As discussed above for the metal 1 and metal 2 tracks, in order to provide the required electrical connection for the special logic function to be implemented, the diagonally-oriented conductor tracks 1101 and 1201 of Figures 11 and 12 can be dynamically traversed in a straight line The array mode is interrupted (ie, interrupted) any number of times. When it is necessary to interrupt a specific diagonal conductor track, the interval between the ends of the diagonal conductor track at the interruption point is minimized to the extent that manufacturing effects and electrical effects may be considered. Minimizing the spacing between the ends of the diagonal conductor tracks at the breakpoints can maximize the lithographic enhancement and uniformity provided by adjacent diagonal conductor tracks.

動態陣列內之最佳布局密度係藉由施行下列設計規則而達到： 設置至少兩金屬1軌道橫跨n通道裝置區； 設置至少兩金屬1軌道橫跨p通道裝置區； 針對n通道裝置設置至少兩閘極軌道； 針對n通道裝置設置至少兩閘極軌道。The optimal layout density in a dynamic array is achieved by implementing the following design rules: setting at least two metal 1 tracks across the n-channel device area; setting at least two metal 1 tracks across the p-channel device area; setting at least two n-channel devices Two gate tracks; at least two gate tracks are provided for the n-channel device.

由微影之觀點來看，接點及通孔變成最困難之遮罩，此乃由於接點及通孔日益縮小、相距更近、且更雜亂分佈。切痕(接點或通孔)之間距及密度使得可靠地印出形狀變得極為困難，例如切痕形狀可能由於來自相鄰形狀之破壞性干涉或在單獨形狀上缺乏能量而被不正確地印出。若係將切痕正確地印出，相關聯接點或通孔之製造產率極高。可設置次解析度接點以強化真實接點之曝光，只要次解析度接點不會解體即可；又，次解析度接點可具有任何形狀，只要其小於微影製程之解析能力即可。From the perspective of lithography, the contacts and vias have become the most difficult masks because the contacts and vias are becoming smaller, closer to each other, and more cluttered. The distance and density of the cuts (contacts or through holes) makes it extremely difficult to reliably print the shape. For example, the shape of the cuts may be incorrectly due to destructive interference from adjacent shapes or lack of energy on individual shapes. Print out. If the cuts are printed correctly, the manufacturing yield of the related joints or through holes is extremely high. A sub-resolution contact can be set to enhance the exposure of the real contact, as long as the sub-resolution contact will not be disintegrated; in addition, the sub-resolution contact can have any shape as long as it is smaller than the resolution capability of the lithography process. .

圖13A顯示根據本發明一實施例之次解析度接點布局之實施例，該布局係用以透過微影方式來強化擴散接點及閘極接點。次解析度接點1301係以使其在微影系統之解析度以下且將不會被印出之方式形成，次解析度接點1301之功能為透過共振成像而增加在期望接點位置上(例如503, 601)之光能量。在一實施例中，係將次解析度接點1301設置在網格上，使閘極接點601及擴散接點503兩者均被微影強化，例如係將次解析度接點1301設置在等於擴散接點503網格間距之一半的網格上，以對閘極接點601及擴散接點503兩者造成正面影響。在一實施例中，次解析度接點1301之垂直間距係依循閘極接點601及擴散接點503之垂直間距。FIG. 13A shows an embodiment of a sub-resolution contact layout according to an embodiment of the present invention. The layout is used to strengthen the diffusion contact and the gate contact by lithography. The sub-resolution contact 1301 is formed so that it is below the resolution of the lithography system and will not be printed out. The function of the sub-resolution contact 1301 is to increase the desired contact position through resonance imaging ( Such as 503, 601). In one embodiment, the sub-resolution contact 1301 is set on the grid, so that both the gate contact 601 and the diffusion contact 503 are enhanced by lithography. For example, the sub-resolution contact 1301 is set at On a grid equal to one-half of the grid spacing of the diffusion contacts 503, to positively affect both the gate contacts 601 and the diffusion contacts 503. In one embodiment, the vertical distance between the sub-resolution contacts 1301 follows the vertical distance between the gate contact 601 and the diffusion contact 503.

在圖13A中之網格位置1303表示相鄰閘極接點601之間的位置。根據在製造程序中之微影參數，在此網格位置上之次解析度接點1301將可能於兩相鄰閘極接點601之間建立非期望橋接。若可能產生橋接，則可省略在網格位置1303上之次解析度接點1301。雖然圖13A為顯示將次解析度接點1301設置於與待解析之真實特徵部相鄰之處的實施例，應明瞭另一實施例可將次解析度接點設置於每一可利用之網格位置上，以便填滿網格。The grid position 1303 in FIG. 13A indicates the position between adjacent gate contacts 601. According to the lithographic parameters in the manufacturing process, the sub-resolution contact 1301 at this grid position will likely establish an undesired bridge between two adjacent gate contacts 601. If bridging is possible, the sub-resolution contact 1301 at the grid position 1303 may be omitted. Although FIG. 13A shows an embodiment in which the sub-resolution contact 1301 is provided adjacent to the real feature part to be analyzed, it should be understood that another embodiment may set the sub-resolution contact in each available network. Grid position to fill the grid.

圖13B顯示根據本發明一實施例之圖13A之次解析度接點布局，其將次解析度接點定義成可填滿網格至可能的程度。應明瞭：雖然圖13B之實施例以次解析度接點儘可能地填滿網格，仍避免將次解析度接點設置於極可能在相鄰全解析特徵部之間引起非期望橋接之位置處。FIG. 13B shows the sub-resolution contact layout of FIG. 13A according to an embodiment of the present invention, which defines the sub-resolution contacts to fill the grid to the extent possible. It should be understood that although the embodiment of FIG. 13B fills the grid with sub-resolution contacts as much as possible, avoid setting sub-resolution contacts at locations that are likely to cause undesired bridging between adjacent full-resolution features Office.

圖13C顯示根據本發明一實施例之次解析度接點布局之實施例，其係利用各種不同形狀之次解析度接點。可利用另外之次解析度接點形狀，只要次解析度接點在製造程序之解析能力以下即可。圖13C顯示可將光能量集中於相鄰接點之角落上之「X形」次解析度接點1305的使用。在一實施例中，係將「X形」次解析度接點1305之端部延伸，以更強化光能量於相鄰接點之角落處之沉積。FIG. 13C shows an embodiment of a sub-resolution contact layout according to an embodiment of the present invention, which uses sub-resolution contacts of various shapes. The shape of another sub-resolution contact can be used as long as the sub-resolution contact is below the resolution of the manufacturing process. FIG. 13C shows the use of "X-shaped" sub-resolution contacts 1305 that can concentrate light energy on the corners of adjacent contacts. In one embodiment, the ends of the "X-shaped" sub-resolution contacts 1305 are extended to further enhance the deposition of light energy at the corners of adjacent contacts.

圖13D顯示根據本發明一實施例之具有次解析度接點之轉換相移遮罩(APSM)的例示完成圖。如同在圖13A中一般，係利用次解析度接點以微影強化擴散接點503及閘極接點601，當鄰近之形狀產生破壞性干涉圖案時，利用APSM來改善解析度。APSM技術修改遮罩使得行進通過鄰近形狀上之遮罩的光之相位為180度反相，此相偏移之功用為去除破壞性干涉並容許較大之接點密度。例如圖13D中標以正號「+」之接點代表以第一相位之光波加以曝光之接點，而標以減號「-」之接點則代表以相對於第一相位之相位偏移180度之光波加以曝光之接點。應明瞭吾人利用APSM技術以確保相鄰接點係彼此分開。FIG. 13D shows an exemplary completion diagram of a transition phase shift mask (APSM) with sub-resolution contacts according to an embodiment of the invention. As in FIG. 13A, the sub-resolution contact is used to enhance the diffusion contact 503 and the gate contact 601 by lithography. When a neighboring shape generates a destructive interference pattern, APSM is used to improve the resolution. The APSM technology modifies the mask so that the phase of the light traveling through the mask on the adjacent shape is 180 degrees out of phase. The function of this phase shift is to remove destructive interference and allow greater contact density. For example, in FIG. 13D, the contact marked with a positive sign “+” represents a contact exposed by a light wave of the first phase, and the contact marked with a minus sign “-” represents a phase offset of 180 from the first phase The point at which light waves of degree are exposed. It should be understood that I use APSM technology to ensure that adjacent contacts are separated from each other.

隨著特徵部尺寸減少，半導體晶粒能夠包含更多閘極；然而，隨著包含更多閘極，互連線層之密度開始支配晶粒尺寸。此在互連線層上日益增加之需求迫使產生較高高度之互連線層；然而，互連線層之堆疊因下層之拓樸而部分受限，例如當建立互連線層時，可產生島、脊、及溝槽，這些島、脊、及溝槽會導致越過其之互連線中斷。As feature sizes decrease, semiconductor grains can include more gates; however, as more gates are included, the density of the interconnect layer begins to dominate the grain size. This increasing demand on the interconnect layer has forced the creation of higher-level interconnect layers; however, the stacking of interconnect layers is partially limited due to the topology of the underlying layers, such as when establishing interconnect layers The islands, ridges, and trenches are created, and these islands, ridges, and trenches can cause interruptions in interconnecting lines across them.

為減少這些島及溝槽，半導體製程利用化學機械研磨(CMP)程序，以機械地且化學地研磨半導體晶圓之表面，使每一後續互連線層位於實質上平坦之表面上。如同光微影程序，CMP程序之品質與布局圖案有關；具體而言，整個晶粒或晶圓上之布局特徵部分佈不均勻，會使得某些地方去除過多材料而其他地方去除過少材料，如此導致在互連線厚度上之變化及在互連線層之電容及電阻上無法接受之變化，在互連線層內之電容及電阻變化可能改變造成設計失敗之關鍵網之時序。To reduce these islands and trenches, the semiconductor process uses a chemical mechanical polishing (CMP) process to mechanically and chemically polish the surface of the semiconductor wafer so that each subsequent interconnect line layer is located on a substantially flat surface. Like the photolithography process, the quality of the CMP process is related to the layout pattern. Specifically, uneven layout of the layout features on the entire die or wafer will cause too much material to be removed in some places and too little material to be removed elsewhere. As a result of changes in the thickness of the interconnect and unacceptable changes in the capacitance and resistance of the interconnect layer, changes in capacitance and resistance within the interconnect layer may change the timing of the critical network that caused the design to fail.

CMP程序要求將虛擬填充(dummy fill)添加於無互連線形狀之區域中，以使可設置實質上均勻之晶圓拓樸，避免碟形效應並改善中心至邊緣之均勻性。習知上，虛擬填充係設置於設計後階段(post-design)，如此，在習知方法中，設計者並不知道虛擬填充特徵。因此，在設計後階段所設置之虛擬填充可能以尚未被設計者所評估之方式，對設計效能產生不利影響；此外，因在虛擬填充之前的習知拓樸為無約束(亦即非均勻)者，故設計後虛擬填充將不均勻且不可預測。因此，在習知技術中，虛擬填充區域與鄰近主動網之間的電容耦合無法被設計者預測。The CMP procedure requires that dummy fills be added to areas without interconnect shapes so that a substantially uniform wafer topology can be set, avoiding dishing effects, and improving center-to-edge uniformity. Conventionally, the virtual filling system is set at the post-design stage. Therefore, in the conventional method, the designer does not know the virtual filling feature. Therefore, the virtual filling set in the post-design stage may adversely affect the design performance in a way that has not been evaluated by the designer; in addition, the known topology before the virtual filling is unconstrained (that is, non-uniform) Because of this, the virtual filling will be uneven and unpredictable after design. Therefore, in the conventional technology, the capacitive coupling between the virtual filling area and the adjacent active network cannot be predicted by the designer.

如先前所述，此處所揭露之動態陣列藉由自閘極層向上最大地填充所有互連線軌道而提供最佳規則性。若在單一互連線軌道中需要多重網，則以最小分離間隙分開該互連軌道。例如在圖8A中代表金屬1導線之軌道809即代表在相同軌道中之三個獨立網，各網係對應至一特殊軌道片段；更具體而言，有兩多接點網及一浮點網，以填充在軌道片段之間具有最小間距之軌道。實質上完整之軌道填充維持了在整個動態陣列中產生共振圖像之規則圖案；此外，具有最大填充互連線軌道之動態陣列的規則結構確保了虛擬填充係以一均勻方式而設置於整個晶粒中。因此，動態陣列的規則結構協助CMP程序，以在整個晶粒/晶圓中產生實質上均勻之結果。又，動態陣列的規則結構有助於閘極蝕刻均勻性(微負載)；此外，結合最大填充互連線軌道之動態陣列的規則結構，容許設計者在設計相位期間及製造前分析與最大填充軌道相關聯之電容耦合效應As mentioned earlier, the dynamic array disclosed here provides the best regularity by maximally filling all interconnect track from the gate layer up. If multiple nets are required in a single interconnect track, the interconnect tracks are separated with a minimum separation gap. For example, in FIG. 8A, the track 809 representing the metal 1 wire represents three independent networks in the same track, each network corresponding to a special track segment; more specifically, there are two multi-contact networks and a floating-point network. To fill the track with the smallest gap between track segments. The substantially complete track filling maintains a regular pattern that produces resonance images in the entire dynamic array. In addition, the regular structure of the dynamic array with the largest filling interconnect track ensures that the virtual filling system is arranged in a uniform manner throughout the crystal. Grain. Therefore, the regular structure of the dynamic array assists the CMP process to produce substantially uniform results across the die / wafer. In addition, the regular structure of the dynamic array contributes to the gate etching uniformity (micro load). In addition, the regular structure of the dynamic array combined with the maximum filling interconnect track allows the designer to analyze and maximize the filling during the design phase and before manufacturing. Orbit-dependent capacitive coupling effect

因為動態陣列設定在每一遮罩層中之線形特徵部(亦即軌道及接點)之尺寸及間距，故可針對製造設備及程序之最大性能將動態陣列最佳化。換言之，由於就擴散層上方之每一層而言，係將動態陣列限制在規則結構，故製造商能夠針對規則結構之具體特徵而將製造程序最佳化。應明瞭：利用此動態陣列，製造商不需要如在習知無約束布局中一般須關心考慮到大幅變化之任意形狀布局特徵部組合的製造條件。Because the dynamic array sets the size and spacing of the linear features (ie, tracks and contacts) in each mask layer, the dynamic array can be optimized for the maximum performance of manufacturing equipment and processes. In other words, because for each layer above the diffusion layer, the dynamic array is limited to a regular structure, the manufacturer can optimize the manufacturing process for the specific characteristics of the regular structure. It should be clear that with this dynamic array, manufacturers do not need to be concerned with the manufacturing conditions of any shape layout feature combination that takes into account large changes, as in conventional unconstrained layouts.

茲提供如何可將製造設備之性能最佳化之範例如下。考慮一90nm製程具有280nm之金屬2間距，此280nm之金屬2間距並非以設備之最大性能來設定；確切而言，其係由通孔之微影加以設定。去除通孔微影之爭議，設備之最大性能容許約220nm之金屬2間距，如此，金屬2間距之設計規則包含約25%之容限以說明在通孔微影中之光交互作用的不可預測性。Examples of how the performance of manufacturing equipment can be optimized are provided below. Consider a 90nm process with a metal 2 pitch of 280nm. The metal 2 pitch of 280nm is not set by the maximum performance of the device; rather, it is set by the lithography of the through hole. Remove the controversy of through-hole lithography. The maximum performance of the device allows a metal 2 pitch of about 220nm. Thus, the design rule for the metal 2 pitch includes a tolerance of about 25% to explain the unpredictable light interaction in the through-hole lithography Sex.

在動態陣列內所執行之規則結構容許將通孔微影中之光交互作用的不可預測性去除，如此使得金屬2間距之容限減少。此一金屬2間距之容限上之減少允許較密集之設計，亦即容許晶片面積利用之最佳化；另外，利用由動態陣列所提供之限定(亦即規則)拓樸，可減少設計規則上的容限；再者，不僅可減少程序性能以外的超額容限，由動態陣列所提供之限定拓樸亦使得所需設計規則之數目實質上得以減少。例如，無約束拓樸之典型設計規則組可能具有超過600條設計規則，但使用動態陣列所需之設計規則組可能僅有約45條設計規則。因此，利用動態陣列之限定拓樸，可將對照設計規則來分析及確認設計所需之努力減少超過10倍。The regular structure implemented in the dynamic array allows the unpredictability of the light interaction in the through-hole lithography to be removed, thus reducing the tolerance of the metal 2 pitch. This reduction in the tolerance of the metal 2 pitch allows denser designs, that is, optimization of chip area utilization; in addition, the use of the limited (i.e., rule) topology provided by the dynamic array can reduce design rules Moreover, not only can the excess tolerance beyond the performance of the program be reduced, but the limited topology provided by the dynamic array also substantially reduces the number of required design rules. For example, a typical set of design rules for an unconstrained topology may have more than 600 design rules, but the set of design rules required to use a dynamic array may only have about 45 design rules. Therefore, using the limited topology of the dynamic array, the effort required to analyze and confirm the design against the design rules can be reduced by more than 10 times.

當處理動態陣列之遮罩層之特定軌道中的線端至線端(line end-to-line end)間隙(亦即軌道片段至軌道片段間隙)時，係存在有限數目之光交互作用。此有限數目之光交互作用可事先加以識別、預測並準確地補償，如此可戲劇性地減少或完全消除對OPC/RET之需求。針對在線端至線端間隙處之光交互作用的補償係代表如圖所示之特徵部之微影修正，其適與基於(與如圖所示之特徵部相關聯之)交互作用的模型化之修正(例如OPC/RET)相反。When dealing with line end-to-line end gaps (ie, track segment to track segment gaps) in a specific track of the mask layer of a dynamic array, there is a limited number of light interactions. This limited number of light interactions can be identified, predicted and accurately compensated in advance, which can dramatically reduce or completely eliminate the need for OPC / RET. The compensation for the light interaction at the end-to-end gap is the lithographic correction of the characteristic part shown in the figure, which is suitable for modeling based on the interaction (associated with the characteristic part shown in the figure) The correction (such as OPC / RET) is the opposite.

此外，利用動態陣列，對於如圖所示之布局的改變僅在有必要之處施行；反之，OPC係於習知設計流程中之整個布局上施行。在一實施例中，可將一修正模型當作動態陣列之部分布局產生來施行，例如由於有限數目之可能線端間隙交互作用，可將路由器(router)加以程式化，以嵌入具有經定義成其環境之函數(亦即其特殊線端間隙交互作用之函數)之特徵的斷路(line break)。應更明瞭：動態陣列之規則結構使得線端可藉由改變頂點而非增加頂點以進行調整，如此，對照於根據OPC程序之無約束拓樸，動態陣列明顯地降低遮罩生產之成本及風險。又，因為動態陣列中之線端間隙交互作用可在設計相中加以準確地預測，故針對在設計相期間之預測線端間隙交互作用之補償不致增加設計失敗的風險。In addition, with dynamic arrays, changes to the layout shown in the figure are performed only where necessary; otherwise, OPC is performed on the entire layout in the conventional design process. In one embodiment, a modified model can be implemented as part of a dynamic array layout, for example, due to a limited number of possible line-to-gap interactions, a router can be programmed to be embedded with a defined A function of its environment (ie, a function of its special line-to-gap interaction) characteristic line break. It should be more clear: the regular structure of the dynamic array allows the line end to be adjusted by changing vertices instead of adding vertices. In this way, compared to the unconstrained topology according to the OPC program, the dynamic array significantly reduces the cost and risk of mask production . In addition, because the line-end gap interaction in the dynamic array can be accurately predicted in the design phase, the compensation for the predicted line-end gap interaction during the design phase will not increase the risk of design failure.

在習知無約束拓樸中，由於存在設計相依之失敗，故設計者必須具備與製造程序相關聯之物理學知識；而利用此處所揭露之動態陣列之基本網格系統，即可將邏輯設計與物理設計分開。更具體而言，利用動態陣列之規則結構，待於動態陣列內加以評估之有限數目之光交互作用以及動態陣列與設計無關之本質，可利用坐標格點網路連線表(netlist)來代表設計，與物理網路連線表相反。In the conventional unconstrained topology, due to the failure of design dependence, the designer must have the physical knowledge associated with the manufacturing process; and the basic grid system of the dynamic array disclosed here can be used to design the logic Separate from physical design. More specifically, using the regular structure of the dynamic array, the limited number of light interactions to be evaluated in the dynamic array, and the nature of the dynamic array that is not related to the design, can be represented by a grid list of coordinate grids The design is the opposite of a physical network connection table.

利用動態陣列，設計不需要以物理資訊來表示；而且，設計可以符號布局來表示。如此，設計者可由純邏輯觀點來表示設計，而不需要表示物理特徵(例如設計之尺寸)。應明瞭：當基本網格網路連線被翻譯成物理網路連線時，與確實用於動態陣列平台之最適設計規則相匹配。當基本網格動態陣列移至新技術(亦即較小型技術)時，因為在設計表示方式中無物理資料，基本網格網路連線可被直接移至新技術。在一實施例中，基本網格動態陣列系統包含規則資料庫、基本網格(符號的)網路連線、及動態陣列結構。With dynamic arrays, designs need not be represented by physical information; moreover, designs can be represented by symbol layouts. In this way, the designer can represent the design from a purely logical point of view, without the need to represent physical features (such as the size of the design). It should be clear that when a basic grid network connection is translated into a physical network connection, it matches the optimal design rules that are indeed used for dynamic array platforms. When the basic grid dynamic array is moved to a new technology (that is, a smaller technology), because there is no physical data in the design representation, the basic grid network connection can be directly moved to the new technology. In one embodiment, the basic grid dynamic array system includes a rule database, a basic grid (symbolic) network connection, and a dynamic array structure.

應明瞭：基本網格動態陣列消除了與習知無約束結構相關聯之拓樸相關失誤；此外，因為基本網格動態陣列之可製造性無關於設計，故施行於動態陣列上之設計之良率亦無關於設計。因此，由於預先確認了動態陣列之正確性及良率，可以預先確認之良率效能而將基本網格網路連線施行於動態陣列上。It should be clear that the basic grid dynamic array eliminates the topology-related errors associated with the conventional unconstrained structure; in addition, because the manufacturability of the basic grid dynamic array has nothing to do with design, the good design implemented on the dynamic array The rate is also not about design. Therefore, since the correctness and yield of the dynamic array are confirmed in advance, the basic grid network connection can be performed on the dynamic array with the yield performance confirmed in advance.

圖14顯示根據本發明一實施例之半導體晶片結構1400。半導體晶片結構1400代表半導體晶片之示範部分，其包含具有若干定義於其上之導線1403A-1403G之擴散區1401。吾人係將擴散區1401定義於基板1405中，以針對至少一電晶體裝置而定義一主動區，可定義擴散區1401以覆蓋相對於基板1405表面之任意形狀區。FIG. 14 shows a semiconductor wafer structure 1400 according to an embodiment of the present invention. The semiconductor wafer structure 1400 represents an exemplary portion of a semiconductor wafer and includes a diffusion region 1401 having a plurality of wires 1403A-1403G defined thereon. We define the diffusion region 1401 in the substrate 1405 to define an active region for at least one transistor device. The diffusion region 1401 can be defined to cover an arbitrary shape region opposite to the surface of the substrate 1405.

設置導線1403A-1403G，以沿一共同方向1407而延伸於基板1405上方，亦應瞭解吾人限制了若干導線1403A-1403G中之每一者，以使其沿共同方向1407而延伸於擴散區1401上方。在一實施例中，直接地定義於基板1405上方之導線1403A-1403G為多晶矽線。在一實施例中，係定義導線1403A-1403G中之每一者，以在垂直於延伸之共同方向1407之方向上具有實質上相同之寬度1409。在另一實施例中，定義了導線1403A-1403G中的某些導線相對於其他導線具有不同之寬度。然而，不論導線1403A-1403G之寬度為何，導線1403A-1403G中之每一者係根據實質上相同之中心至中心間距1411而與相鄰導線分隔開。The wires 1403A-1403G are provided so as to extend above the substrate 1405 along a common direction 1407. It should also be understood that I have restricted each of a number of wires 1403A-1403G so that they extend above the diffusion area 1401 in a common direction 1407. . In one embodiment, the wires 1403A-1403G directly defined on the substrate 1405 are polycrystalline silicon wires. In one embodiment, each of the wires 1403A-1403G is defined so as to have substantially the same width 1409 in a direction perpendicular to the common direction 1407 of the extension. In another embodiment, it is defined that some of the wires 1403A-1403G have different widths relative to other wires. However, regardless of the width of the wires 1403A-1403G, each of the wires 1403A-1403G is separated from an adjacent wire by a substantially same center-to-center spacing 1411.

如圖14所示，某些導線(1403B-1403E)在擴散區1401上方延伸，而其他導線(1403A, 1403F, 1403G)在基板1405之非擴散部分上方延伸。應瞭解：不論是否將導線1403A-1403G定義於擴散區1401上方，導線1403A-1403G仍維持其寬度1409及間距1411；此外，亦應瞭解：不論是否將導線1403A-1403G定義於擴散區1401上方，導線1403A-1403G實質上仍維持其相同長度1413，藉此使整個基板上導線1403A-1403G之間的微影強化最大化。以此方式，定義於擴散區1401上方之某些導線(例如1403D)包含一必要主動部分1415及一個以上的均勻性延伸部分1417。As shown in FIG. 14, some wires (1403B-1403E) extend above the diffusion region 1401, while other wires (1403A, 1403F, 1403G) extend above the non-diffused portion of the substrate 1405. It should be understood that whether the wires 1403A-1403G are defined above the diffusion region 1401, the wires 1403A-1403G still maintain their width 1409 and the pitch 1411; in addition, it should also be understood: whether or not the wires 1403A-1403G are defined above the diffusion region 1401 The wires 1403A-1403G still substantially maintain the same length 1413, thereby maximizing the lithography enhancement between the wires 1403A-1403G on the entire substrate. In this manner, certain wires (eg, 1403D) defined above the diffusion region 1401 include a necessary active portion 1415 and more than one uniformity extension portion 1417.

應瞭解半導體晶片結構1400代表上述關於圖2-13D之動態陣列之一部分，因此，應瞭解係存在導線(1403B-1403E)之均勻性延伸部分1417，以提供相鄰導線1403A-1403G之微影強化。另外，雖然其並非電路操作所需要，但存在導線1403A, 1403F, 1403G中之每一者，以提供相鄰導線1403A-1403G之微影強化。It should be understood that the semiconductor wafer structure 1400 represents a part of the dynamic array described above with reference to FIGS. 2-13D. Therefore, it should be understood that there is a uniform extension 1417 of the wires (1403B-1403E) to provide lithographic enhancement of adjacent wires 1403A-1403G. . In addition, although it is not required for circuit operation, each of the wires 1403A, 1403F, 1403G exists to provide lithographic enhancement of adjacent wires 1403A-1403G.

必要主動部分1415及均勻性延伸部分1417亦適用於較高高度之互連線層。如先前關於動態陣列結構所述者，相鄰互連線層沿橫截方向(例如垂直或對角線方向)橫貫越過基板，以使施行於動態陣列內之邏輯裝置所需要之選路(routing)/連接性(connectivity)成為可能。如同導線1403A-1403G一般，在互連線層內之每一導線可包含必須部分(必要主動部分)，以使選路/連接性成為可能；且可包含非必須部分(均勻性延伸部分)，以對相鄰導線提供微影強化。又，如同導線1403A-1403G，互連線層內之導線沿一共同方向延伸於基板上方，且其具有實質上相同之寬度，並根據實質上固定之間距而彼此隔開。The necessary active portion 1415 and the uniformity extension portion 1417 are also applicable to a higher-level interconnect line layer. As previously described with respect to the dynamic array structure, adjacent interconnect layers traverse the substrate in a cross-section (e.g., vertical or diagonal) to enable routing required for logic devices implemented in the dynamic array. ) / Connectivity becomes possible. As with the wires 1403A-1403G, each wire in the interconnection layer may include a necessary part (a necessary active part) to enable routing / connectivity; and may include a non-essential part (a uniformity extension part), To provide lithographic enhancement to adjacent wires. Also, like the wires 1403A-1403G, the wires in the interconnect layer extend above the substrate in a common direction, and have substantially the same width and are separated from each other according to a substantially fixed pitch.

在一實施例中，互連線層內之導線在線寬與線距之間實質上遵循著相同比率，例如在90nm之情況下，金屬間距為280nm，線寬與線距均等於140nm。若線寬等於線距，則可將較大導線印刷於較大線間距上。In one embodiment, the wires in the interconnect layer have substantially the same ratio between line width and line pitch. For example, in the case of 90 nm, the metal pitch is 280 nm, and the line width and line pitch are both equal to 140 nm. If the line width is equal to the line pitch, a larger wire can be printed on a larger line pitch.

可將此處所述之發明以電腦可讀碼之形式在電腦可讀媒體上加以具體化，電腦可讀媒體為可儲存之後能被電腦系統讀取之資料的資料儲存裝置，電腦可讀媒體的例子包含硬碟、網路附接儲存器(NAS)、唯讀記憶體、隨機存取記憶體、CD-ROMs、CD-Rs、CD-RWs、磁帶、及其他光學或非光學資料儲存裝置。亦可將電腦可讀媒體分散於與電腦系統相耦合之網路上，使電腦可讀碼以分散方式加以儲存並執行；此外，可開發以電腦可讀碼之形式而施行於電腦可讀媒體上之圖形使用者介面(GUI)，以提供用以施行本發明之任何實施例之使用者介面。The invention described herein can be embodied on a computer-readable medium in the form of a computer-readable code. A computer-readable medium is a data storage device that can store data that can be read by a computer system afterwards. A computer-readable medium Examples include hard drives, network-attached storage (NAS), read-only memory, random access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes, and other optical or non-optical data storage devices . Computer-readable media can also be distributed on a network coupled with computer systems, so that computer-readable codes can be stored and executed in a decentralized manner. In addition, computer-readable codes can be developed and implemented on computer-readable media A graphical user interface (GUI) to provide a user interface for implementing any embodiment of the invention.

雖然已就數個實施例來說明本發明，但應瞭解熟悉此項技藝者在閱讀以上說明書及研究圖式時將會實現各種不同之修改、增加、變更及其均等物。因此，本發明意欲包含落入本發明之真實精神及範圍內之所有此類修改、增加、變更及其均等物。Although the present invention has been described in terms of several embodiments, it should be understood that those skilled in the art will realize various modifications, additions, changes, and equivalents when reading the above description and studying the drawings. Therefore, this invention is intended to include all such modifications, additions, alterations and equivalents thereof which fall within the true spirit and scope of the invention.

101A~103C‧‧‧線形布局特徵部101A ~ 103C‧‧‧Linear layout feature

103A~103C‧‧‧sinc函數103A ~ 103C‧‧‧sinc function

201‧‧‧基板201‧‧‧ substrate

203‧‧‧擴散區203‧‧‧Proliferation zone

205‧‧‧擴散接點205‧‧‧ Diffusion contact

207‧‧‧閘極特徵部207‧‧‧Gate feature

209‧‧‧閘極接點209‧‧‧Gate contact

211‧‧‧金屬1211‧‧‧Metal 1

213‧‧‧通孔1213‧‧‧through hole 1

215‧‧‧金屬2215‧‧‧Metal 2

217‧‧‧通孔2217‧‧‧through hole 2

219‧‧‧金屬3219‧‧‧Metal 3

221‧‧‧通孔3221‧‧‧through hole 3

223‧‧‧金屬4223‧‧‧Metal 4

225‧‧‧額外互連線層225‧‧‧Extra interconnect layer

301‧‧‧線形特徵部301‧‧‧Linear Features

303‧‧‧線形特徵部之寬度303‧‧‧Width of linear features

305‧‧‧線形特徵部之長度305‧‧‧ Length of Linear Feature

307‧‧‧線形特徵部之高度307‧‧‧ height of linear features

309‧‧‧線形特徵部之高度309‧‧‧Height of linear features

311‧‧‧線形特徵部之長度311‧‧‧ Length of linear features

313‧‧‧線形特徵部之下寬313‧‧‧ Wide below linear features

315‧‧‧線形特徵部之上寬315‧‧‧ Wide above linear features

317‧‧‧線形特徵部317‧‧‧Linear Features

401‧‧‧擴散區401‧‧‧ diffusion zone

403‧‧‧擴散區403‧‧‧Proliferation zone

405‧‧‧擴散方塊405‧‧‧ Diffusion Block

410‧‧‧p+遮罩區410‧‧‧p + mask area

412‧‧‧n+遮罩區412‧‧‧n + Mask area

414‧‧‧p+遮罩區414‧‧‧p + Mask area

416‧‧‧n+遮罩區416‧‧‧n + Mask area

501‧‧‧閘極特徵部501‧‧‧Gate Characteristics

501A‧‧‧具有更大寬度之閘極特徵部501A‧‧‧Gate feature with larger width

503‧‧‧擴散接點503‧‧‧ Diffusion contact

601‧‧‧閘極接點601‧‧‧Gate contact

701‧‧‧閘極接點在閘極特徵部以外的延長部分701‧‧‧ Gate extensions other than gate feature

703‧‧‧垂直維度703‧‧‧ vertical dimension

705‧‧‧距離705‧‧‧distance

707‧‧‧放大矩形閘極區707‧‧‧ Enlarge rectangular gate area

709‧‧‧閘極接點709‧‧‧Gate contact

711‧‧‧閘極線711‧‧‧Gate line

801~821‧‧‧金屬1軌道801 ~ 821‧‧‧Metal 1 rail

801A‧‧‧金屬1之接地軌道801A‧‧‧Metal 1 Ground Track

821A‧‧‧金屬1之電力軌道821A‧‧‧Metal 1 Power Rail

901‧‧‧通孔901‧‧‧through hole

1001‧‧‧金屬2軌道1001‧‧‧Metal 2 track

1101‧‧‧導體軌道1101‧‧‧conductor track

1201‧‧‧導體軌道1201‧‧‧Conductor track

1301‧‧‧次解析度接點1301‧‧‧th resolution contacts

1303‧‧‧網格位置1303‧‧‧Grid position

1305‧‧‧「X形」之次解析度接點1305‧‧‧ "X-shaped" sub-resolution contact

1400‧‧‧半導體晶片結構1400‧‧‧Semiconductor wafer structure

1401‧‧‧擴散區1401‧‧‧Proliferation zone

1403A-1403G‧‧‧導線1403A-1403G‧‧‧Wire

1405‧‧‧基板1405‧‧‧ substrate

1407‧‧‧共同方向1407‧‧‧Common direction

1409‧‧‧導線之寬度1409‧‧‧Wire width

1411‧‧‧導線之間距1411‧‧‧Distance between conductors

1413‧‧‧導線之長度1413‧‧‧ length of wire

1415‧‧‧導線之必要主動部分1415‧‧‧ Necessary active part of the wire

1417‧‧‧導線之均勻性延伸部分1417‧‧‧Uniformity extension of wire

圖1顯示根據本發明一實施例之若干布局特徵部及用以產生每一布局特徵部之光強度；FIG. 1 shows a number of layout features and the light intensity used to generate each layout feature according to an embodiment of the present invention;

圖2顯示根據本發明一實施例之用以定義動態陣列結構之一般化疊層；2 shows a generalized stack for defining a dynamic array structure according to an embodiment of the present invention;

圖3A顯示根據本發明一實施例之待映射至動態陣列以輔助定義限制拓樸(restricted topology)之例示基本網格；3A shows an exemplary basic grid to be mapped to a dynamic array to assist in defining a restricted topology according to an embodiment of the present invention;

圖3B顯示根據本發明一例示實施例之待映射至整個晶粒之獨立區域的獨立基本網格；3B shows an independent basic grid to be mapped to an independent region of the entire die according to an exemplary embodiment of the present invention;

圖3C顯示根據本發明一實施例之例示線形特徵部，其經定義成可與動態陣列相容；3C shows an exemplary linear feature according to an embodiment of the present invention, which is defined to be compatible with a dynamic array;

圖3D顯示根據本發明一實施例之另一例示線形特徵部，其經定義成可與動態陣列相容；3D shows another exemplary linear feature according to an embodiment of the present invention, which is defined to be compatible with a dynamic array;

圖4顯示根據本發明一實施例之例示動態陣列之擴散層布局；FIG. 4 shows a layout of a diffusion layer of an exemplary dynamic array according to an embodiment of the present invention; FIG.

圖5顯示根據本發明一實施例之閘極層及擴散接點層，其係位於圖4的擴散層上方並與該擴散層相鄰；5 shows a gate layer and a diffusion contact layer according to an embodiment of the present invention, which are located above and adjacent to the diffusion layer of FIG. 4;

圖6顯示根據本發明一實施例之閘極接點層，其係經定義於圖5之閘極層上方且與之相鄰；6 shows a gate contact layer according to an embodiment of the present invention, which is defined above and adjacent to the gate layer of FIG. 5;

圖7A顯示用以與閘極相接觸之習知方法；FIG. 7A shows a conventional method for contacting a gate electrode;

圖7B顯示根據本發明一實施例加以定義之閘極接點；7B shows a gate contact defined according to an embodiment of the present invention;

圖8A顯示根據本發明一實施例之金屬1層，其係經定義於圖6之閘極接點層上方並與之相鄰；FIG. 8A shows a metal 1 layer according to an embodiment of the present invention, which is defined above and adjacent to the gate contact layer of FIG. 6; FIG.

圖8B顯示圖8A之金屬1層；FIG. 8B shows the metal 1 layer of FIG. 8A;

圖9顯示根據本發明一實施例之通孔1層，其係經定義於圖8A之金屬1層上方且與之相鄰；FIG. 9 shows a layer of via 1 according to an embodiment of the present invention, which is defined above and adjacent to the layer of metal 1 of FIG. 8A;

圖10顯示根據本發明一實施例之金屬2層，其係經定義於圖9之通孔1層上方且與之相鄰；FIG. 10 shows a metal 2 layer according to an embodiment of the present invention, which is defined above and adjacent to the through-hole 1 layer of FIG. 9;

圖11顯示根據本發明一實施例之導體軌道，其係沿相對於第一及第二參考方向(x)及(y)之第一對角線方向橫貫動態陣列；11 shows a conductor track according to an embodiment of the present invention, which traverses a dynamic array along a first diagonal direction with respect to the first and second reference directions (x) and (y);

圖12顯示根據本發明一實施例之導體軌道，其係沿相對於第一及第二參考方向(x)及(y)之第二對角線方向橫貫動態陣列；FIG. 12 shows a conductor track according to an embodiment of the present invention, which traverses a dynamic array along a second diagonal direction with respect to the first and second reference directions (x) and (y);

圖13A顯示根據本發明一實施例之次解析度接點布局之實施例，該布局係用以透過微影方式來強化擴散接點及閘極接點；FIG. 13A shows an embodiment of a sub-resolution contact layout according to an embodiment of the present invention. The layout is used to strengthen the diffusion contact and the gate contact by lithography;

圖13B顯示根據本發明一實施例之圖13A之次解析度接點布局，其將次解析度接點定義成可填滿網格至可能的程度；FIG. 13B shows the sub-resolution contact layout of FIG. 13A according to an embodiment of the present invention, which defines the sub-resolution contacts to fill the grid to the extent possible;

圖13C顯示根據本發明一實施例之次解析度接點布局之實施例，其係利用各種不同形狀之次解析度接點；13C shows an embodiment of a sub-resolution contact layout according to an embodiment of the present invention, which uses sub-resolution contacts of various shapes;

圖13D顯示根據本發明一實施例之具有次解析度接點之轉換相移遮罩(APSM)的例示完成圖；FIG. 13D shows an exemplary completed diagram of an APSM with a sub-resolution contact according to an embodiment of the present invention; FIG.

圖14顯示根據本發明一實施例之半導體晶片結構。FIG. 14 shows a semiconductor wafer structure according to an embodiment of the present invention.

Claims (30)

一種半導體晶片，包含：形成於該半導體晶片之一區域內的複數閘極電極特徵部，該等閘極電極特徵部係依據包含至少七個閘極網格線的一閘極水平網格而加以設置，其中所有閘極網格線在y方向上延伸，其中相鄰的閘極網格線彼此分開一閘極間距，該區域中的每一閘極電極特徵部具有實質上矩形的形狀、且設置成在該y方向上以實質上集中的方式沿著相關聯的一閘極網格線縱向延伸，其中每一閘極網格線上設置有至少一閘極電極特徵部，其中該區域內的至少一閘極電極特徵部形成第一電晶體類型之至少一電晶體的至少一閘極電極而不形成第二電晶體類型之電晶體的閘極電極，其中該區域內的至少一閘極電極特徵部形成該第二電晶體類型之至少一電晶體的至少一閘極電極而不形成該第一電晶體類型之電晶體的閘極電極；至少六個閘極接點構造，形成於該半導體晶片的該區域內，其中該區域內的至少六個閘極電極特徵部具有與該至少六個閘極接點構造之一對應者物理性及電性接觸的個別頂面，該至少六個閘極接點構造的每一者具有實質上矩形的形狀，其一對應之長度大於一對應之寬度，且該對應之長度朝向x方向，該至少六個閘極接點構造係設置並定尺寸為與其所物理性及電性接觸之該閘極電極特徵部的該頂面之兩邊緣重疊；及第一金屬層，形成於該半導體晶片之該區域內之該等閘極電極特徵部的頂面上方，該第一金屬層係設置為金屬層堆疊中從該等閘極電極特徵部之頂面向上計數的第一者，該第一金屬層藉由至少一絕緣體材料與該等閘極電極特徵部之該等頂面分開，其中該第一金屬層包含依據第一金屬垂直網格而設置的第一金屬結構，該第一金屬垂直網格包含至少八個第一金屬網格線，其中所有第一金屬網格線在該x方向上延伸，其中該至少八個第一金屬網格線的至少八者上設置有至少一第一金屬構造，該區域中的每一第一金屬構造具有實質上矩形的形狀、且設置成在該x方向上以實質上集中的方式在一相關聯的第一金屬網格線上縱向延伸，其中該區域包含共同形成一邏輯電路之一部分的該第一電晶體類型的至少四個電晶體及該第二電晶體類型的至少四個電晶體，其中該半導體晶片之該區域內的每一電晶體係部分地藉由對應的一擴散區域形成，其中該半導體晶片之該區域的一些擴散區域係由至少一擴散接點構造物理性及電性接觸，該區域內的每一擴散接點構造係以實質上集中的方式沿著一擴散接點網格的對應之一擴散接點網格線而設置，該擴散接點網格具有在該x方向上量測等於該閘極間距的擴散接點網格線至擴散接點網格線之間隔。A semiconductor wafer includes a plurality of gate electrode features formed in an area of the semiconductor wafer, and the gate electrode features are applied based on a gate horizontal grid including at least seven gate grid lines. Setting, wherein all gate grid lines extend in the y direction, wherein adjacent gate grid lines are separated from each other by a gate pitch, and each gate electrode feature in the region has a substantially rectangular shape, and It is arranged to extend longitudinally along the associated gate grid line in a substantially concentrated manner in the y direction, wherein each gate grid line is provided with at least one gate electrode feature, wherein the The at least one gate electrode feature forms at least one gate electrode of at least one transistor of the first transistor type and does not form a gate electrode of a transistor of the second transistor type, wherein at least one gate electrode in the region The feature forms at least one gate electrode of at least one transistor of the second transistor type without forming a gate electrode of the transistor of the first transistor type; at least six gate contact structures are formed to form In the region of the semiconductor wafer, wherein at least six gate electrode features in the region have individual top surfaces that are in physical and electrical contact with a counterpart of one of the at least six gate contact structures, the at least six Each of the gate contact structures has a substantially rectangular shape, a corresponding length is greater than a corresponding width, and the corresponding length is in the x direction. The at least six gate contact structures are set and determined. The dimensions are such that the two edges of the top surface of the gate electrode feature that are in physical and electrical contact with it overlap; and a first metal layer formed on the gate electrode feature in the region of the semiconductor wafer. Above the top surface, the first metal layer is set to be the first one in the metal layer stack counted upward from the top surface of the gate electrode features. The first metal layer is connected to the gates by at least one insulator material. The top surfaces of the electrode features are separated, wherein the first metal layer includes a first metal structure arranged according to a first metal vertical grid, and the first metal vertical grid includes at least eight first metal grid lines, among them A first metal grid line extends in the x direction, wherein at least one first metal structure is provided on at least eight of the at least eight first metal grid lines, and each first metal structure in the region has A substantially rectangular shape and arranged to extend longitudinally on an associated first metal grid line in a substantially concentrated manner in the x direction, wherein the region contains the first electrical lines that collectively form part of a logic circuit At least four transistors of the crystal type and at least four transistors of the second transistor type, wherein each transistor system in the region of the semiconductor wafer is formed in part by a corresponding diffusion region, wherein the semiconductor Some diffusion regions in this region of the wafer are physically and electrically contacted by at least one diffusion contact structure, and each diffusion contact structure in the area is corresponding to a diffusion contact grid in a substantially concentrated manner. One of the diffusion contact grid lines is provided, and the diffusion contact grid has a distance from the diffusion contact grid line that is equal to the gate pitch measured in the x direction. 如申請專利範圍第1項之半導體晶片，更包含：第二金屬層，形成於該半導體晶片之該區域內之該第一金屬層上方，該第二金屬層係設置為金屬層堆疊中從該等閘極電極特徵部之頂面向上計數的第二者，該第二金屬層藉由至少一絕緣體材料與該第一金屬層分開，該第二金屬層包含依據第二金屬水平網格而設置的第二金屬結構，該第二金屬水平網格包含至少八個第二金屬網格線，其中所有第二金屬網格線在該y方向上延伸，其中該至少八個第二金屬網格線的至少八者上設置有至少一第二金屬構造，該區域中的每一第二金屬構造具有實質上矩形的形狀、且設置成在該y方向上以實質上集中的方式在一相關聯的第二金屬網格線上縱向延伸，其中該區域內的一些第二金屬構造係經由至少一第一金屬至第二金屬通孔構造電性連接至該區域內之至少一第一金屬構造，該區域內的每一第一金屬至第二金屬通孔構造係以實質上集中的方式沿著一相關聯的第二金屬網格線而設置。For example, the semiconductor wafer of the first patent application scope further includes: a second metal layer formed above the first metal layer in the region of the semiconductor wafer, and the second metal layer is arranged in a metal layer stack from the The second one that counts upwards on the top surface of the gate electrode feature, the second metal layer is separated from the first metal layer by at least one insulator material, and the second metal layer includes a second metal layer disposed according to a horizontal grid. A second metal structure, the second metal horizontal grid includes at least eight second metal grid lines, wherein all the second metal grid lines extend in the y direction, wherein the at least eight second metal grid lines At least one of the two is provided with at least one second metal structure, and each second metal structure in the region has a substantially rectangular shape and is arranged in an associated manner in a substantially concentrated manner in the y direction. The second metal grid line extends longitudinally, wherein some second metal structures in the area are electrically connected to at least one first metal structure in the area via at least one first metal to second metal via structure. Each region of the first metal to the second metal via lines configured in a substantially concentrated manner is provided along a second metal gridline associated. 如申請專利範圍第2項之半導體晶片，其中該區域中的每一第一金屬構造具有在該y方向上量測之寬度，該寬度為第一寬度或第二寬度，該第二寬度與該第一寬度不同，該第一金屬層包含具有該第一寬度的至少一第一金屬構造，該第一金屬層包含具有該第二寬度的至少一第一金屬構造。For example, for a semiconductor wafer with a scope of patent application No. 2, wherein each first metal structure in the region has a width measured in the y direction, the width is the first width or the second width, and the second width and the The first width is different. The first metal layer includes at least a first metal structure having the first width, and the first metal layer includes at least a first metal structure having the second width. 如申請專利範圍第3項之半導體晶片，其中形成該第一電晶體類型之至少一電晶體的至少一閘極電極而不形成該第二電晶體類型之電晶體的閘極電極的該區域內之至少一閘極電極特徵部係經由包含至少一第一金屬構造及至少一第二金屬構造的電連接件，而電性連接至形成該第二電晶體類型之至少一電晶體的至少一閘極電極而不形成該第一電晶體類型之電晶體的閘極電極的該區域內之至少一閘極電極特徵部。For example, in the semiconductor wafer of claim 3, in which at least one gate electrode of at least one transistor of the first transistor type is formed without forming a gate electrode of the transistor of the second transistor type The at least one gate electrode feature is electrically connected to at least one gate of at least one transistor that forms the second transistor type through an electrical connector including at least one first metal structure and at least one second metal structure. The electrode does not form at least one gate electrode feature in the region of the gate electrode of the transistor of the first transistor type. 如申請專利範圍第2項之半導體晶片，其中該至少六個閘極接點構造係依據接點垂直網格而設置，該接點垂直網格包含在該x方向上延伸的接點網格線，該至少六個閘極接點構造之每一者係設置成在該x方向上以實質上集中的方式沿著一相關聯的接點網格線縱向延伸，且該至少六個閘極接點構造的至少兩者係設置成亦在該x方向上以實質上集中的方式沿著一相對應的第一金屬網格線縱向延伸。For example, for a semiconductor wafer with a scope of patent application No. 2, the structure of the at least six gate contacts is set according to a vertical grid of contacts, and the vertical grid of contacts includes grid lines of the contacts extending in the x direction. Each of the at least six gate contact structures is arranged to extend longitudinally along an associated contact grid line in a substantially concentrated manner in the x direction, and the at least six gate contacts At least two of the dot structures are arranged to also extend longitudinally along a corresponding first metal grid line in a substantially concentrated manner in the x direction. 如申請專利範圍第2項之半導體晶片，其中該區域中的每一第一金屬構造具有在該y方向上量測之寬度，該寬度為複數寬度的其中一者，該複數寬度包含第一寬度及第二寬度，該第一寬度小於該第二寬度，該第一金屬層包含具有該第一寬度的至少一第一金屬構造，該第一金屬層包含具有該第二寬度的至少一第一金屬構造，其中接觸具有該第一寬度之第一金屬構造的每一第一金屬至第二金屬通孔構造係由一對應的第一金屬網格線相交。For example, for a semiconductor wafer with a scope of claim 2, each first metal structure in the region has a width measured in the y direction, the width is one of a plurality of widths, and the plurality of widths includes the first width And a second width, the first width is smaller than the second width, the first metal layer includes at least a first metal structure having the first width, and the first metal layer includes at least a first width having the second width A metal structure, wherein each first metal to second metal via structure contacting the first metal structure having the first width is intersected by a corresponding first metal grid line. 如申請專利範圍第6項之半導體晶片，其中每一第一金屬至第二金屬通孔構造係由一對應的第一金屬網格線相交。For example, for a semiconductor wafer with a scope of claim 6, each first metal to second metal via structure is intersected by a corresponding first metal grid line. 如申請專利範圍第2項之半導體晶片，其中相鄰的第二金屬網格線係彼此分開一第二金屬間距，該第二金屬間距等於該閘極間距，該第二金屬水平網格與該擴散接點網格對齊。For example, for a semiconductor wafer with the scope of patent application No. 2, the adjacent second metal grid lines are separated from each other by a second metal distance, the second metal distance is equal to the gate distance, and the second metal horizontal grid Diffuse contact grid alignment. 如申請專利範圍第8項之半導體晶片，其中該半導體晶片之該區域中的所有第二金屬構造具有相同的在該x方向上量測之寬度。For example, a semiconductor wafer having a scope of patent application No. 8 in which all the second metal structures in the region of the semiconductor wafer have the same width measured in the x direction. 如申請專利範圍第9項之半導體晶片，更包含：第三金屬層，形成於該半導體晶片之該區域內之該第二金屬層上方，該第三金屬層係設置為金屬層堆疊中從該等閘極電極特徵部之頂面向上計數的第三者，該第三金屬層藉由至少一絕緣體材料與該第二金屬層分開，該第三金屬層包含依據第三金屬垂直網格而設置的第三金屬結構，該第三金屬垂直網格包含至少八個第三金屬網格線，其中所有第三金屬網格線在該x方向上延伸，其中該至少八個第三金屬網格線的至少八者上設置有至少一第三金屬構造，該區域中的每一第三金屬構造具有實質上矩形的形狀、且設置成在該x方向上以實質上集中的方式在一相關聯的第三金屬網格線上縱向延伸，其中該區域內的一些第三金屬構造係經由至少一第二金屬至第三金屬通孔構造電性連接至該區域內之至少一第二金屬構造，其中該區域內的至少一第二金屬至第三金屬通孔構造係以實質上集中的方式沿著一相關聯的第三金屬網格線而設置。For example, the semiconductor wafer under the scope of patent application No. 9 further includes: a third metal layer formed on the second metal layer in the region of the semiconductor wafer, and the third metal layer is arranged in the metal layer stack from the A third person counting the top surface of the gate electrode feature part upward, the third metal layer is separated from the second metal layer by at least one insulator material, and the third metal layer includes a third metal vertical grid The third metal structure, the third metal vertical grid includes at least eight third metal grid lines, wherein all the third metal grid lines extend in the x direction, wherein the at least eight third metal grid lines At least eight of the three are provided with at least one third metal structure, each third metal structure in the region has a substantially rectangular shape, and is arranged in an associated manner in a substantially concentrated manner in the x direction. The third metal grid line extends longitudinally, wherein some third metal structures in the area are electrically connected to at least one second metal structure in the area via at least one second metal to third metal via structure. Wherein the at least one second metal in the region to the third metal via lines configured in a substantially concentrated manner is provided along a third metal gridlines associated. 如申請專利範圍第10項之半導體晶片，其中每一第二金屬至第三金屬通孔構造係由一對應的第二金屬網格線相交。For example, for a semiconductor wafer with a scope of claim 10, each of the second to third metal via structures is intersected by a corresponding second metal grid line. 如申請專利範圍第10項之半導體晶片，其中該區域中的每一第二金屬構造係設置成在第一側上以第二金屬間距與至少一其他第二金屬構造相鄰，並設置成在第二側上以該第二金屬間距與至少一其他第二金屬構造相鄰，其中該第二金屬間距係在該x方向上量測且與該閘極間距相等。For example, the semiconductor wafer of claim 10, wherein each second metal structure in the region is arranged adjacent to at least one other second metal structure at a second metal pitch on the first side, and is arranged at The second metal pitch is adjacent to at least one other second metal structure on the second side, wherein the second metal pitch is measured in the x direction and is equal to the gate pitch. 如申請專利範圍第10項之半導體晶片，更包含：第四金屬層，形成於該半導體晶片之該區域內之該第三金屬層上方，該第四金屬層係設置為金屬層堆疊中從該等閘極電極特徵部之頂面向上計數的第四者，該第四金屬層藉由至少一絕緣體材料與該第三金屬層分開，該第四金屬層包含依據第四金屬水平網格而設置的第四金屬結構，該第四金屬水平網格包含至少八個第四金屬網格線，其中所有第四金屬網格線在該y方向上延伸，其中該至少八個第四金屬網格線的至少八者上設置有至少一第四金屬構造，該區域中的每一第四金屬構造具有實質上矩形的形狀、且設置成在該y方向上以實質上集中的方式在一相關聯的第四金屬網格線上縱向延伸。For example, the semiconductor wafer under the scope of application for patent No. 10 further includes: a fourth metal layer formed on the third metal layer in the region of the semiconductor wafer, and the fourth metal layer is arranged in the metal layer stack from the A fourth one that counts upwards on the top surface of the gate electrode feature, the fourth metal layer is separated from the third metal layer by at least one insulator material, and the fourth metal layer includes a fourth metal layer arranged according to the fourth metal horizontal grid. The fourth metal structure, the fourth metal horizontal grid includes at least eight fourth metal grid lines, wherein all the fourth metal grid lines extend in the y direction, wherein the at least eight fourth metal grid lines There are at least one fourth metal structure provided on at least eight of each, and each fourth metal structure in the region has a substantially rectangular shape and is arranged in an associated manner in a substantially concentrated manner in the y direction. The fourth metal grid line extends longitudinally. 如申請專利範圍第1項之半導體晶片，其中該區域內的該第一電晶體類型之該至少四個電晶體及該第二電晶體類型之至少四個電晶體共同形成反向二對一多工器的一部分。For example, the semiconductor wafer of the first scope of the patent application, wherein the at least four transistors of the first transistor type and the at least four transistors of the second transistor type in the region form a reverse two to one multiple Part of the tool. 如申請專利範圍第1項之半導體晶片，其中該至少六個接點構造的至少一者係與形成該第一電晶體類型之至少一電晶體的至少一閘極電極而不形成該第二電晶體類型之電晶體的閘極電極的該區域內之至少一閘極電極特徵部物理性及電性接觸，且係實質上在該x方向上集中於形成該第一電晶體類型之至少一電晶體的至少一閘極電極而不形成該第二電晶體類型之電晶體的閘極電極的該區域內之至少一閘極電極特徵部。For example, the semiconductor wafer of claim 1, wherein at least one of the at least six contact structures is related to at least one gate electrode forming at least one transistor of the first transistor type without forming the second transistor. At least one gate electrode feature in the region of the gate electrode of the crystal type transistor is in physical and electrical contact, and is substantially concentrated in the x direction to form at least one electrode of the first transistor type. At least one gate electrode of the crystal does not form at least one gate electrode feature in the region of the gate electrode of the transistor of the second transistor type. 如申請專利範圍第1項之半導體晶片，其中該至少六個接點構造的每一者係由一對應的閘極網格線相交。For example, the semiconductor wafer of claim 1, wherein each of the at least six contact structures is intersected by a corresponding gate grid line. 如申請專利範圍第1項之半導體晶片，其中該第一金屬層包含至少八個第一金屬構造，該等第一金屬構造係設置在四個第一金屬層網格線上，使得該至少八個第一金屬構造的不同兩者設置在該四個第一金屬層網格線的各者上，其中該至少八個第一金屬構造的每一者係設置成以第一金屬間距與至少一其他的第一金屬構造相鄰並隔開。For example, the semiconductor wafer of the first patent application range, wherein the first metal layer includes at least eight first metal structures, and the first metal structures are arranged on four first metal layer grid lines such that the at least eight Different two of the first metal structure are disposed on each of the four first metal layer grid lines, wherein each of the at least eight first metal structures is disposed to be spaced from the first metal with at least one other The first metal structures are adjacent and spaced. 如申請專利範圍第1項之半導體晶片，其中在其上設置有至少一第一金屬構造的該至少八個第一金屬網格線之至少八者係以第一金屬間距分開。For example, the semiconductor wafer of claim 1, wherein at least eight of the at least eight first metal grid lines with at least one first metal structure disposed thereon are separated by a first metal pitch. 如申請專利範圍第1項之半導體晶片，更包含：第二金屬層，形成於該半導體晶片之該區域內之該第一金屬層上方，該第二金屬層係設置為金屬層堆疊中從該等閘極電極特徵部之頂面向上計數的第二者，該第二金屬層藉由至少一絕緣體材料與該第一金屬層分開，該第二金屬層包含依據第二金屬水平網格而設置的第二金屬結構，該第二金屬水平網格包含至少八個第二金屬網格線，其中所有第二金屬網格線在該y方向上延伸，其中該至少八個第二金屬網格線的至少八者上設置有至少一第二金屬構造，該區域中的每一第二金屬構造具有實質上矩形的形狀、且設置成在該y方向上以實質上集中的方式在一相關聯的第二金屬網格線上縱向延伸；第三金屬層，形成於該半導體晶片之該區域內之該第二金屬層上方，該第三金屬層係設置為金屬層堆疊中從該等閘極電極特徵部之頂面向上計數的第三者，該第三金屬層藉由至少一絕緣體材料與該第二金屬層分開，該第三金屬層包含依據第三金屬垂直網格而設置的第三金屬結構，該第三金屬垂直網格包含至少八個第三金屬網格線，其中所有第三金屬網格線在該x方向上延伸，其中該至少八個第三金屬網格線的至少八者上設置有至少一第三金屬構造，該區域中的每一第三金屬構造具有實質上矩形的形狀、且設置成在該x方向上以實質上集中的方式在一相關聯的第三金屬網格線上縱向延伸。For example, the semiconductor wafer of the first patent application scope further includes: a second metal layer formed above the first metal layer in the region of the semiconductor wafer, and the second metal layer is arranged in a metal layer stack from the The second one that counts upwards on the top surface of the gate electrode feature, the second metal layer is separated from the first metal layer by at least one insulator material, and the second metal layer includes a second metal layer disposed according to a horizontal grid. A second metal structure, the second metal horizontal grid includes at least eight second metal grid lines, wherein all the second metal grid lines extend in the y direction, wherein the at least eight second metal grid lines At least one of the two is provided with at least one second metal structure, and each second metal structure in the region has a substantially rectangular shape and is arranged in an associated manner in a substantially concentrated manner in the y direction. A second metal grid line extends longitudinally; a third metal layer is formed above the second metal layer in the region of the semiconductor wafer, and the third metal layer is arranged in the metal layer stack from the gate electrodes A third person whose top face is counted upward, the third metal layer is separated from the second metal layer by at least one insulator material, and the third metal layer includes a third metal arranged according to the third metal vertical grid Structure, the third metal vertical grid includes at least eight third metal grid lines, wherein all third metal grid lines extend in the x direction, wherein at least eight of the at least eight third metal grid lines At least one third metal structure is provided thereon, and each third metal structure in the region has a substantially rectangular shape and is arranged in an associated third metal mesh in a substantially concentrated manner in the x direction. The grid extends longitudinally. 如申請專利範圍第19項之半導體晶片，更包含：第四金屬層，形成於該半導體晶片之該區域內之該第三金屬層上方，該第四金屬層係設置為金屬層堆疊中從該等閘極電極特徵部之頂面向上計數的第四者，該第四金屬層藉由至少一絕緣體材料與該第三金屬層分開，該第四金屬層包含依據第四金屬水平網格而設置的第四金屬結構，該第四金屬水平網格包含至少八個第四金屬網格線，其中所有第四金屬網格線在該y方向上延伸，其中該至少八個第四金屬網格線的至少八者上設置有至少一第四金屬構造，該區域中的每一第四金屬構造具有實質上矩形的形狀、且設置成在該y方向上以實質上集中的方式在一相關聯的第四金屬網格線上縱向延伸。For example, the semiconductor wafer under the scope of application for patent No. 19 further includes: a fourth metal layer formed on the third metal layer in the region of the semiconductor wafer, and the fourth metal layer is arranged in a metal layer stack from the A fourth one that counts upwards on the top surface of the gate electrode feature, the fourth metal layer is separated from the third metal layer by at least one insulator material, and the fourth metal layer includes a fourth metal layer arranged according to the fourth metal horizontal grid. The fourth metal structure, the fourth metal horizontal grid includes at least eight fourth metal grid lines, wherein all the fourth metal grid lines extend in the y direction, wherein the at least eight fourth metal grid lines There are at least one fourth metal structure provided on at least eight of each, and each fourth metal structure in the region has a substantially rectangular shape and is arranged in an associated manner in a substantially concentrated manner in the y direction. The fourth metal grid line extends longitudinally. 如申請專利範圍第19項之半導體晶片，其中該區域中的每一第一金屬構造具有在該y方向上量測之寬度，該寬度為複數寬度的其中一者，該複數寬度包含第一寬度及第二寬度，該第一寬度小於該第二寬度，該第一金屬層包含具有該第一寬度的至少一第一金屬構造，該第一金屬層包含具有該第二寬度的至少一第一金屬構造，其中接觸具有該第一寬度之第一金屬構造的每一第一金屬至第二金屬通孔構造係由一對應的第一金屬網格線相交。For example, the semiconductor wafer of claim 19, wherein each first metal structure in the region has a width measured in the y direction, the width is one of a plurality of widths, and the plurality of widths includes the first width And a second width, the first width is smaller than the second width, the first metal layer includes at least a first metal structure having the first width, and the first metal layer includes at least a first width having the second width A metal structure, wherein each first metal to second metal via structure contacting the first metal structure having the first width is intersected by a corresponding first metal grid line. 如申請專利範圍第19項之半導體晶片，其中該區域內的一些第三金屬構造係經由至少一第二金屬至第三金屬通孔構造而電性連接至該區域內的至少一第二金屬構造，每一第二金屬至第三金屬通孔構造係由一對應的第二金屬網格線相交。For example, the semiconductor wafer of claim 19, wherein some third metal structures in the area are electrically connected to at least one second metal structure in the area via at least one second metal to third metal via structure. Each of the second to third metal via structures intersects with a corresponding second metal grid line. 如申請專利範圍第22項之半導體晶片，其中該區域中的每一第三金屬構造具有在該y方向上量測之寬度，該寬度為複數寬度的其中一者，該複數寬度包含第一寬度及第二寬度，該第一寬度小於該第二寬度，該第三金屬層包含具有該第一寬度的至少一第三金屬構造，該第三金屬層包含具有該第二寬度的至少一第三金屬構造，其中接觸具有該第一寬度之第三金屬構造的每一第二金屬至第三金屬通孔構造係由一對應的第三金屬網格線相交。For example, the semiconductor wafer of claim 22, wherein each third metal structure in the region has a width measured in the y direction, the width is one of a plurality of widths, and the plurality of widths includes the first width And a second width, the first width is smaller than the second width, the third metal layer includes at least a third metal structure having the first width, and the third metal layer includes at least a third metal structure having the second width The metal structure, wherein each of the second to third metal through-hole structures contacting the third metal structure having the first width is intersected by a corresponding third metal grid line. 如申請專利範圍第19項之半導體晶片，其中該第一電晶體類型之該至少四個電晶體包含該第一電晶體類型之第一電晶體，其中該第二電晶體類型之該至少四個電晶體包含該第二電晶體類型之第一電晶體，其中形成該第一電晶體類型之該第一電晶體之閘極電極的閘極電極特徵部及形成該第二電晶體類型之該第一電晶體之閘極電極的閘極電極特徵部係形成為沿著相同的閘極網格線縱向延伸，其中在形成該第一電晶體類型之該第一電晶體之閘極電極的閘極電極特徵部與形成該第二電晶體類型之該第一電晶體之閘極電極的閘極電極特徵部之間，不具有其他電晶體設置在該相同的閘極網格線上，其中該半導體晶片之該區域內的每一電晶體係部分地由一對應的擴散區域形成，其中該第一電晶體類型之該第一電晶體的擴散區域係電性連接至該第二電晶體類型之該第一電晶體的擴散區域。For example, the semiconductor wafer of claim 19, wherein the at least four transistors of the first transistor type include a first transistor of the first transistor type, wherein the at least four of the second transistor type The transistor includes a first transistor of the second transistor type, wherein a gate electrode feature forming a gate electrode of the first transistor of the first transistor type and the first transistor of the second transistor type are formed. The gate electrode features of the gate electrode of a transistor are formed to extend longitudinally along the same gate grid line, wherein the gate electrode of the gate electrode of the first transistor of the first transistor type is formed Between the electrode feature and the gate electrode feature forming the gate electrode of the first transistor of the second transistor type, no other transistor is disposed on the same gate grid line, wherein the semiconductor wafer Each transistor system in the region is partially formed by a corresponding diffusion region, wherein the diffusion region of the first transistor of the first transistor type is electrically connected to the second transistor of the second transistor type. Diffusion region of a transistor. 如申請專利範圍第24項之半導體晶片，其中相鄰的第二金屬網格線係彼此分開一第二金屬間距，該第二金屬間距等於該閘極間距，該第二金屬水平網格與該擴散接點網格對齊。For example, a semiconductor wafer with a scope of application for patent No. 24, wherein adjacent second metal grid lines are separated from each other by a second metal distance, the second metal distance is equal to the gate distance, and the second metal horizontal grid and the Diffuse contact grid alignment. 如申請專利範圍第25項之半導體晶片，其中該半導體晶片之該區域中的所有第二金屬構造具有相同的在該x方向上量測之寬度。For example, a semiconductor wafer having a scope of application for item 25, wherein all the second metal structures in the region of the semiconductor wafer have the same width measured in the x direction. 如申請專利範圍第1項之半導體晶片，其中該第一電晶體類型的該至少四個電晶體係集體藉由不包含另一電晶體之一內區域而與該第二電晶體類型的該至少四個電晶體分開。For example, the semiconductor wafer of the first patent application range, wherein the at least four transistor systems of the first transistor type collectively communicate with the at least four transistor types by not including an inner region of another transistor. The four transistors are separated. 如申請專利範圍第27項之半導體晶片，其中該至少六個閘極接點構造的至少一者係設置在該內區域之上，且係物理性及電性接觸並實質上在該x方向上集中於形成至少一電晶體之至少一閘極電極的該區域內之閘極電極特徵部。For example, the semiconductor wafer under the scope of patent application No. 27, wherein at least one of the at least six gate contact structures is disposed above the inner region, and is in physical and electrical contact and substantially in the x direction The gate electrode features are concentrated in the region where at least one gate electrode of the at least one transistor is formed. 一種半導體晶片，包含：形成於該半導體晶片之一區域內的複數閘極電極特徵部，該等閘極電極特徵部係依據包含至少七個閘極網格線的一閘極水平網格而加以設置，其中相鄰的閘極網格線彼此分開一閘極間距，該區域中的每一閘極電極特徵部具有實質上矩形的形狀、且設置成在y方向上以實質上集中的方式沿著相關聯的一閘極網格線縱向延伸，其中每一閘極網格線上設置有至少一閘極電極特徵部，其中該區域內的至少一閘極電極特徵部形成第一電晶體類型之至少一電晶體的至少一閘極電極而不形成第二電晶體類型之電晶體的閘極電極，其中該區域內的至少一閘極電極特徵部形成該第二電晶體類型之至少一電晶體的至少一閘極電極而不形成該第一電晶體類型之電晶體的閘極電極；及複數接點構造，形成於該半導體晶片的該區域內，其中該區域內形成任何電晶體閘極電極的每一閘極電極特徵部具有物理性及電性接觸具有實質上矩形之形狀的一對應之接點構造的個別頂面，其中接觸形成任何電晶體閘極電極之給定閘極電極特徵部的每一接點構造不接觸另一閘極電極特徵部，其中任何具有大於或等於一對應寬度之一對應長度的接點構造係定向為使其對應長度在x方向上延伸，其中該區域內的每一電晶體係部分地由一對應的擴散區域形成，其中該區域內形成任何電晶體之一部分的每一擴散區域具有實質上矩形的形狀，其中該區域包含該第一電晶體類型的至少四個電晶體及該第二電晶體類型的至少四個電晶體，該等電晶體係共同形成一多工器的一部份或一鎖存器的一部分。A semiconductor wafer includes a plurality of gate electrode features formed in an area of the semiconductor wafer, and the gate electrode features are applied based on a gate horizontal grid including at least seven gate grid lines. Set, where adjacent gate grid lines are separated from each other by a gate pitch, and each gate electrode feature in the region has a substantially rectangular shape and is arranged along the y-direction in a substantially concentrated manner. An associated gate grid line extends longitudinally, wherein each gate grid line is provided with at least one gate electrode feature, and at least one gate electrode feature in the area forms a first transistor type. At least one gate electrode of at least one transistor does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate electrode feature in the region forms at least one transistor of the second transistor type At least one gate electrode without forming a gate electrode of the transistor of the first transistor type; and a plurality of contact structures formed in the region of the semiconductor wafer, where the region is formed Each gate electrode feature of any transistor gate electrode has an individual top surface that physically and electrically contacts a corresponding contact structure with a substantially rectangular shape, wherein the contact forms the electrode of any transistor gate electrode. Each contact structure of a fixed gate electrode feature does not contact another gate electrode feature, wherein any contact structure having a corresponding length greater than or equal to a corresponding width is oriented so that its corresponding length is in the x direction An extension, in which each transistor system in the region is partially formed by a corresponding diffusion region, and each diffusion region in the region forming a part of any transistor has a substantially rectangular shape, wherein the region includes the first At least four transistors of a transistor type and at least four transistors of the second transistor type, the transistor systems together form a part of a multiplexer or a part of a latch. 一種半導體晶片，包含：形成於該半導體晶片之一區域內的複數閘極電極特徵部，該等閘極電極特徵部係依據包含至少複數閘極網格線的一閘極水平網格而加以設置，其中相鄰的閘極網格線彼此分開一閘極間距，該區域中的每一閘極電極特徵部具有實質上矩形的形狀、且設置成在y方向上以實質上集中的方式沿著相關聯的一閘極網格線縱向延伸，其中每一閘極網格線上設置有至少一閘極電極特徵部，其中該區域內的至少一閘極電極特徵部形成第一電晶體類型之至少一電晶體的至少一閘極電極而不形成第二電晶體類型之電晶體的閘極電極，其中該區域內的至少一閘極電極特徵部形成該第二電晶體類型之至少一電晶體的至少一閘極電極而不形成該第一電晶體類型之電晶體的閘極電極；及複數接點構造，形成於該半導體晶片的該區域內，其中該區域內之閘極電極特徵部的每一者具有物理性及電性接觸具有實質上矩形之形狀的一對應之接點構造的個別頂面，其中每一接點構造係在x方向上集中於其所物理性接觸的閘極電極特徵部，其中具有實質上矩形之形狀的每一接點構造具有大於或等於一對應寬度的一對應長度，且係定向為使其對應長度在x方向上延伸，其中每一對應的接點構造系僅與一閘極電極特徵部物理性接觸，其中該區域內的每一電晶體係部分地由一對應的擴散區域形成，其中該區域內形成任何電晶體之一部分的每一擴散區域具有實質上矩形的形狀。A semiconductor wafer includes: a plurality of gate electrode features formed in an area of the semiconductor wafer, and the gate electrode features are arranged according to a gate horizontal grid including at least a plurality of gate grid lines , Wherein adjacent gate grid lines are separated from each other by a gate pitch, and each gate electrode feature in the region has a substantially rectangular shape and is arranged to run along the y direction in a substantially concentrated manner. An associated gate grid line extends longitudinally, wherein each gate grid line is provided with at least one gate electrode feature, and at least one gate electrode feature in the area forms at least one of the first transistor type. At least one gate electrode of a transistor does not form a gate electrode of a transistor of a second transistor type, wherein at least one feature of the gate electrode in the region forms at least one transistor of the second transistor type At least one gate electrode without forming a gate electrode of the transistor of the first transistor type; and a plurality of contact structures formed in the region of the semiconductor wafer, wherein a gate in the region Each of the electrode electrode features has an individual top surface that physically and electrically contacts a corresponding contact structure having a substantially rectangular shape, wherein each contact structure is focused on its physical properties in the x direction The feature of the contacted gate electrode, wherein each contact structure having a substantially rectangular shape has a corresponding length greater than or equal to a corresponding width, and is oriented so that its corresponding length extends in the x direction, each of which The corresponding contact structure is only in physical contact with a gate electrode feature, wherein each transistor system in the region is partially formed by a corresponding diffusion region, where each part of any transistor is formed in the region. A diffusion region has a substantially rectangular shape.