TWI669915B - Coding methods - Google Patents
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Abstract
本發明提供多種編碼方法,其中一種編碼方法包括:產生一類循環低密度同位校驗碼,該類循環低密度同位校驗碼具有內置之多個碼本;從該多個碼本中選擇一碼本;以及使用所選擇之該碼本對資料進行編碼。 The present invention provides a plurality of encoding methods, wherein an encoding method includes: generating a type of cyclic low density parity check code, the cyclic low density parity check code having a plurality of built-in codebooks; selecting a code from the plurality of codebooks And encoding the data using the selected codebook.
Description
本發明係關於資訊編碼與解碼,特別關於類循環低密度同位校驗(Quasi-Cyclic-Low-Density Parity-Check,QC-LDPC)編碼(coding)之多種方法及裝置。 The present invention relates to information encoding and decoding, and more particularly to a variety of methods and apparatus for Quasi-Cyclic-Low-Density Parity-Check (QC-LDPC) encoding.
第三代合作夥伴計劃(The 3rd Generation Partnership Project,3GPP)已經批准了多個計劃,來加速第五代(5G)新無線電(New Radio,NR)的規格之開發,因此,可以預期在不久之未來可以推出基於多個標準之5G NR無線通信服務。3GPP也已同意在5G NR資料通道中將使用QC-LDPC。然而,如何進行基於QC-LDPC之編碼與解碼之具體細節尚未定義。 Third Generation Partnership Project (The 3 rd Generation Partnership Project, 3GPP) has approved a number of programs to accelerate the fifth-generation (5G) New Radio (New Radio, NR) the development of specifications, therefore, can be expected in the near future In the future, 5G NR wireless communication services based on multiple standards can be launched. 3GPP has also agreed to use QC-LDPC in the 5G NR data channel. However, the specific details of how to perform QC-LDPC based encoding and decoding have not been defined.
有鑑於此,本發明提供有關於QC-LDPC編碼與解碼之多種新穎概念與機制,可以實施於下一代通信中,不論有線還是無線,包括5G NR無線通信。 In view of this, the present invention provides various novel concepts and mechanisms related to QC-LDPC encoding and decoding, which can be implemented in next generation communications, whether wired or wireless, including 5G NR wireless communications.
根據本發明一實施例之編碼方法,包括:產生一類循環低密度同位校驗碼,該類循環低密度同位校驗碼具有多個碼本(codebooks);從該多個碼本中選擇一碼本;以及使用所選擇之該碼本對資料進行編碼。 An encoding method according to an embodiment of the invention includes: generating a type of cyclic low density parity check code, the cyclic low density parity check code having a plurality of codebooks; selecting a code from the plurality of codebooks And encoding the data using the selected codebook.
根據本發明另一實施例之編碼方法,包括:產生一類循環低密度同位校驗碼;以及使用該類循環低密度同位校驗碼對資料進行編碼,其中,該類循環低密度同位校驗碼之產生進一步包含:為多個擴展因子(lifting factors)之一 第一集合(set)中之每個擴展因子產生各自之一移位值(shift values)表;以及對該多個擴展因子之該第一集合進行優化以產生多個擴展因子之一第二集合,其中,該第一集合之一擴展因子總數大於該第二集合之一擴展因子總數,其中,一第一擴展因子共用一第二擴展因子之一移位值表,其中該第一擴展因子存在於該第一集合中但不存在於該第二集合中,該第二擴展因子同時存在於該第一集合與該第二集合中,以及其中,該第二擴展因子在數值上小於該第一擴展因子,且相較於該第一集合中之其它擴展因子更加接近於該第一擴展因子。 An encoding method according to another embodiment of the present invention includes: generating a type of cyclic low density parity check code; and encoding the data using the cyclic low density parity check code, wherein the cyclic low density parity check code The generation further includes: being one of a plurality of lifting factors Each of the first set of spread factors produces a respective shift values table; and the first set of the plurality of spread factors is optimized to produce a second set of the plurality of spread factors The total number of expansion factors of the first set is greater than the total number of expansion factors of the second set, wherein a first spreading factor shares a shift value table of a second spreading factor, wherein the first spreading factor exists In the first set but not in the second set, the second spreading factor is present in both the first set and the second set, and wherein the second spreading factor is numerically smaller than the first The spreading factor is closer to the first spreading factor than the other spreading factors in the first set.
根據本發明另一實施例之編碼方法,包括:產生一類循環低密度同位校驗碼,該類循環低密度同位校驗碼包含至少一類列正交層(quasi-row orthogonal layer);以及使用該類循環低密度同位校驗碼對資料進行編碼。 An encoding method according to another embodiment of the present invention includes: generating a type of cyclic low density parity check code, the cyclic low density parity check code including at least one type of quasi-row orthogonal layer; The class loop low density parity check code encodes the data.
根據本發明又一實施例之編碼方法,包括:產生一類循環低密度同位校驗碼,該類循環低密度同位校驗碼包含一基礎矩陣(base matrix),該基礎矩陣之一部分形成一核心矩陣(kernel matrix),該核心矩陣對應於至少一門檻值之一碼率(Code Rate,CR);以及使用該類循環低密度同位校驗碼對資料進行編碼,其中,該核心矩陣包含多個位元(bits)之多個列(rows)與多個行(columns),其中,該多個行中之兩個或更多個包含多個截斷行(punctured columns),該多個截斷行具有多個位元之一特定圖樣(pattern)。 An encoding method according to still another embodiment of the present invention includes: generating a type of cyclic low density parity check code, wherein the cyclic low density parity check code comprises a base matrix, and a part of the basic matrix forms a core matrix (kernel matrix), the core matrix corresponding to at least one threshold value (Code Rate, CR); and encoding the data using the cyclic low-density parity check code, wherein the core matrix includes multiple bits a plurality of rows and a plurality of rows, wherein two or more of the plurality of rows include a plurality of punctured columns, the plurality of truncated rows having a plurality of rows One of the bits is a specific pattern.
本發明之多種編碼方法,其優點之一在於提供了利用QC-LDPC碼進行編碼之多種方法。 One of the advantages of the various encoding methods of the present invention is that it provides a variety of methods for encoding using QC-LDPC codes.
100、500‧‧‧QC-LDPC碼 100, 500‧‧‧QC-LDPC code
200‧‧‧邏輯流程 200‧‧‧Logical process
210~250、1110~1140、1210~1230、1310~1330、1410~1430‧‧‧步驟 210~250, 1110~1140, 1210~1230, 1310~1330, 1410~1430‧‧
300‧‧‧類列正交層設計 300‧‧‧Class Orthogonal Layer Design
400‧‧‧混合正交層設計 400‧‧‧Mixed Orthogonal Layer Design
600‧‧‧核心矩陣設計 600‧‧‧core matrix design
700、800‧‧‧示例概念 700, 800‧‧‧ example concepts
900‧‧‧移位參數設計 900‧‧‧Transition parameter design
1000‧‧‧通信系統 1000‧‧‧Communication system
1005‧‧‧第一裝置 1005‧‧‧ first device
1010、1060‧‧‧處理器 1010, 1060‧‧‧ processor
1012、1062‧‧‧編碼器 1012, 1062‧‧ ‧ encoder
1014、1064‧‧‧解碼器 1014, 1064‧‧‧ decoder
1020、1070‧‧‧記憶體 1020, 1070‧‧‧ memory
1022、1072‧‧‧指令 1022, 1072‧‧
1024、1074‧‧‧資料 1024, 1074‧‧‧ data
1030、1080‧‧‧收發器 1030, 1080‧‧‧ transceiver
1032、1082‧‧‧發送器 1032, 1082‧‧‧transmitters
1034、1084‧‧‧接收器 1034, 1084‧‧‧ Receiver
1050‧‧‧第二裝置 1050‧‧‧second device
1100、1200、1300、1400‧‧‧操作 1100, 1200, 1300, 1400‧‧‧ operations
I1-I3‧‧‧資訊矩陣之部分 Part of the I1-I3‧‧‧ information matrix
第1圖為根據本發明一實施方式之多重內置LDPC碼設計之示意圖。 1 is a schematic diagram of a multiple built-in LDPC code design according to an embodiment of the present invention.
第2圖為根據本發明一實施方式之與多重內置LDPC碼設計有關之一示例邏 輯流程200之示意圖。 2 is an example logic related to multiple built-in LDPC code designs according to an embodiment of the present invention. A schematic diagram of the process 200.
第3圖為根據本發明一實施方式之類列正交層設計300之示例示意圖。 FIG. 3 is a diagram showing an example of a column-like orthogonal layer design 300 in accordance with an embodiment of the present invention.
第4圖為根據本發明一實施方式之混合正交層設計400之一示例示意圖。 4 is a schematic diagram of an example of a hybrid orthogonal layer design 400 in accordance with an embodiment of the present invention.
第5圖為根據本發明一實施方式之支援極低碼率之QC-LDPC碼500之示例示意圖。 FIG. 5 is a diagram showing an example of a QC-LDPC code 500 supporting an extremely low code rate according to an embodiment of the present invention.
第6圖為根據本發明一實施方式之核心矩陣設計600之示例示意圖。 FIG. 6 is a diagram showing an example of a core matrix design 600 in accordance with an embodiment of the present invention.
第7圖為根據本發明一實施方式之核心基礎矩陣之示例概念700之示意圖。 FIG. 7 is a schematic diagram of an exemplary concept 700 of a core base matrix in accordance with an embodiment of the present invention.
第8圖為根據本發明另一實施方式之核心基礎矩陣之示例概念800之示意圖。 Figure 8 is a schematic illustration of an example concept 800 of a core base matrix in accordance with another embodiment of the present invention.
第9圖為根據本發明一實施方式之示例移位參數設計900之示意圖。 FIG. 9 is a schematic diagram of an example shift parameter design 900 in accordance with an embodiment of the present invention.
第10圖為根據本發明一實施方式之示例通信系統1000之示意圖。 FIG. 10 is a schematic diagram of an example communication system 1000 in accordance with an embodiment of the present invention.
第11圖為根據本發明一實施例之示例操作1100之示意圖。 11 is a schematic diagram of an example operation 1100 in accordance with an embodiment of the present invention.
第12圖為根據本發明一實施方式之示例操作1200之示意圖。 Figure 12 is a schematic illustration of an example operation 1200 in accordance with an embodiment of the present invention.
第13圖為根據本發明一實施方式之示例操作1300之示意圖。 Figure 13 is a schematic illustration of an example operation 1300 in accordance with an embodiment of the present invention.
第14圖為根據本發明一實施方式之示例操作1400之示意圖。 Figure 14 is a schematic illustration of an example operation 1400 in accordance with an embodiment of the present invention.
在說明書及申請專利範圍當中使用了某些詞彙來指稱特定之元件。所屬領域具有通常知識者應可理解,硬體製造商可能會用不同名詞來稱呼同一個元件。本說明書及申請專利範圍並不以名稱之差異來作為區分元件之方式,而是以元件在功能上之差異來作為區分之準則。在通篇說明書及申請專利範圍當中所提及之「包含」及「包括」為一開放式之用語,故應解釋成「包含但不限定於」。「大致」是指在可接受之誤差範圍內,所屬領域具有通常知識者能夠在一定誤差範圍內解決所述技術問題,基本達到所述技術效果。此外,「耦 接」一詞在此包含任何直接及間接之電性連接手段。因此,若文中描述一第一裝置耦接於一第二裝置,則代表該第一裝置可直接電性連接於該第二裝置,或透過其它裝置或連接手段間接地電性連接至該第二裝置。「連接」一詞在此包含任何直接及間接、有線及無線之連接手段。以下所述為實施本發明之較佳方式,目的在於說明本發明之精神而非用以限定本發明之保護範圍,本發明之保護範圍當視後附之申請專利範圍所界定者為准。 Certain terms are used throughout the description and claims to refer to particular elements. Those of ordinary skill in the art should understand that hardware manufacturers may refer to the same component by different nouns. This specification and the scope of the patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The words "including" and "including" as used throughout the specification and the scope of the patent application are an open term and should be interpreted as "including but not limited to". "About" means that within the acceptable error range, those skilled in the art can solve the technical problem within a certain error range, and basically achieve the technical effect. In addition, "coupling The term "connected" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, the first device can be directly electrically connected to the second device, or can be electrically connected to the second device through other devices or connection means. Device. The term "connected" is used herein to include any direct and indirect, wired and wireless means of connection. The following is a description of the preferred embodiments of the present invention, and is intended to illustrate the scope of the invention, and the scope of the present invention is defined by the scope of the appended claims.
此處記載了有關本發明之詳細實施例與實施方式。然而,應當理解,此處所述之多個實施例與實施方式進用於以多種形式來說明本發明所要求保護之內容。然而,本發明的說明書可以以多種形式來體現,並不應為解釋為僅限於此處所述多個實施例與實施方式;而是提供這些實施例與實施方式以便說明書之記載完整深入,並向所屬領域具有通常知識者全面表達本發明之範圍。在以下說明中,省略了已知之特徵與技術之細節,以避免造成對所呈現之多個實施例與實施方式之不必要之模糊。 Detailed embodiments and embodiments related to the present invention are described herein. It should be understood, however, that the various embodiments and embodiments described herein are intended to illustrate the claimed invention in various forms. However, the description of the present invention may be embodied in a variety of forms and should not be construed as being limited to the various embodiments and embodiments described herein; The scope of the invention is fully described by those of ordinary skill in the art. The details of the known features and techniques are omitted in the following description in order to avoid unnecessary obscuring of the various embodiments and embodiments presented.
值得注意的是,儘管本發明所提供之多種編碼方法及裝置在下文中是以5G NR無線通信進行說明的,本發明所提供之多種編碼方法及裝置之任意變形/推演有可能在根據其他協定、標準及規格所實施之適合之通信中。因此,本發明所提供之機制並不僅限於說明書中之記載。 It should be noted that although the various encoding methods and apparatus provided by the present invention are described below in the context of 5G NR wireless communication, any variants/derivations of the various encoding methods and apparatus provided by the present invention are possible under other protocols, Suitable communications for implementation by standards and specifications. Therefore, the mechanism provided by the present invention is not limited to the description in the specification.
概述 Overview
本發明所提供之多個概念與機制通常是有關與以下領域:多重內置(multi-embedded)低密度同位校驗(LDPC)碼設計、混合正交LDPC層設計(hybrid orthogonal LDPC layer design)、極低(extreme low)碼率(Code Rate,CR)之QC-LDPC支援、核心矩陣設計及移位參數(shift-coefficient)設計。混合正交LDPC層設計之領域包括類列正交層設計與混合正交層設計之新穎概念與機制。這些提出之概念與機制之說明結合參考第1圖至第9圖提供如下。 The various concepts and mechanisms provided by the present invention are generally related to the following fields: multi-embedded low density parity check (LDPC) code design, hybrid orthogonal LDPC layer design, pole QC-LDPC support, core matrix design, and shift-coefficient design for extreme low code rate (CR). The field of hybrid orthogonal LDPC layer design includes novel concepts and mechanisms of class-column orthogonal layer design and hybrid orthogonal layer design. The description of these proposed concepts and mechanisms is provided below with reference to Figures 1 through 9.
第1圖為根據本發明一實施方式之多重內置LDPC碼設計之示意圖。請參考第1圖,根據本發明之QC-LDPC碼100有可能具有內置之多個碼本。 1 is a schematic diagram of a multiple built-in LDPC code design according to an embodiment of the present invention. Referring to FIG. 1, the QC-LDPC code 100 according to the present invention may have a plurality of built-in codebooks.
如第1圖所示,QC-LDPC碼100有可能包括一基礎矩陣,該基礎矩陣包含一同位矩陣與一資訊矩陣,其中該同位矩陣包含多個同位(parity)位元,該資訊矩陣包含多個資訊位元。相應地,該多個碼本中之每個碼本可以包含同位矩陣與資訊矩陣中對應尺寸之一部分,以便該多個碼本各自所對應之尺寸可以各不相同。在第1圖所示之實施例中,一碼本(Codebook)可以表示如下:Codebook=(I1或I2或I3)+P As shown in FIG. 1, the QC-LDPC code 100 may include a basic matrix including a parity matrix and an information matrix, wherein the parity matrix includes a plurality of parity bits, and the information matrix includes multiple Information bits. Correspondingly, each of the plurality of codebooks may include a part of a corresponding size in the parity matrix and the information matrix, so that the sizes of the plurality of codebooks may be different. In the embodiment shown in Fig. 1, a codebook can be expressed as follows: Codebook = (I1 or I2 or I3) + P
其中,標記「I1」表示該資訊矩陣之第一部分,標記「I2」表示資訊矩陣之第二部分,標記「I3」表示資訊矩陣之第三部分,以及標記「P」表示同位矩陣。在此,I1之尺寸(例如,位元之數量及/或記憶體尺寸)大於I2之尺寸,I2之尺寸大於I3之尺寸。 The mark "I1" indicates the first part of the information matrix, the mark "I2" indicates the second part of the information matrix, the mark "I3" indicates the third part of the information matrix, and the mark "P" indicates the parity matrix. Here, the size of I1 (for example, the number of bits and/or the size of the memory) is larger than the size of I2, and the size of I2 is larger than the size of I3.
因此,合成之碼本之尺寸可以根據用以與同位矩陣一起形成碼本之資訊矩陣之部分之尺寸而變化。值得注意的是,儘管第1圖所示之實施例因不同組合I1+P,I2+P和I3+P而顯示不同尺寸之三個碼本,在根據本發明之多種實施方式中,不同尺寸之多個碼本之數量不僅限於三(可以少於或多於三)。 Thus, the size of the synthesized codebook can vary depending on the size of the portion of the information matrix used to form the codebook with the co-located matrix. It should be noted that although the embodiment shown in FIG. 1 displays three codebooks of different sizes due to different combinations I1+P, I2+P and I3+P, in various embodiments according to the present invention, different sizes The number of multiple codebooks is not limited to three (may be less than or more than three).
在一些實施方式中,該多個碼本之每個碼本可以各自對應於多個混合自動重傳請求(Hybrid Automatic Repeat Request,HARQ)線程(threads)之一HARQ線程,該多個HARQ線程各不相同。例如,第一碼本可以對應於第一HARQ線程,該第一碼本之取值範圍為0.33~0.89。第二碼本可以對應於第二HARQ線程,該第二碼本之取值範圍為0.2~0.66。第三碼本可以對應於第三HARQ線程,該第三碼本之最小碼塊尺寸小於400。 In some embodiments, each of the plurality of codebooks may each correspond to one of a plurality of Hybrid Automatic Repeat Request (HARQ) threads, the HARQ thread, each of the plurality of HARQ threads Not the same. For example, the first codebook may correspond to the first HARQ thread, and the first codebook may have a value ranging from 0.33 to 0.89. The second codebook may correspond to the second HARQ thread, and the second codebook may have a value ranging from 0.2 to 0.66. The third codebook may correspond to a third HARQ thread, the third codebook having a minimum code block size of less than 400.
在一些實施方式中,該多個碼本之每個碼本可以各自對應於一資訊節點塊尺寸(Kb)。例如,第一碼本可以對應於第一資訊節點塊尺寸Kb=16。 第二碼本可以對應於第二資訊節點塊尺寸Kb=12。第三碼本可以對應於第三資訊節點塊尺寸KB=5。 In some embodiments, each of the plurality of codebooks can each correspond to an information node block size (Kb). For example, the first codebook may correspond to the first information node block size Kb=16. The second codebook may correspond to the second information node block size Kb=12. The third codebook may correspond to the third information node block size KB=5.
在一些實施方式中,所有碼本可以共用一個基礎矩陣,採用不同之墊零(zero-padding)尺寸。在一些實施方式中,不同碼本可以對應於不同移位參數設計,或者共用一個移位參數設計。 In some embodiments, all codebooks can share a single base matrix with different zero-padding sizes. In some embodiments, different codebooks may correspond to different shift parameter designs, or share one shift parameter design.
在一些實施方式中,從多個碼本中選擇使用哪個碼本可以基於資料傳輸之一初始碼率、該資料之碼塊尺寸或者二者。 In some embodiments, selecting which codebook to use from among the plurality of codebooks may be based on an initial code rate of the data transmission, a code block size of the material, or both.
第2圖為根據本發明一實施方式之與多重內置LDPC碼設計有關之一示例邏輯流程200之示意圖。邏輯流程200可以實施於解碼器或處理器,或者使用編碼器或處理器來實施,以實現本發明所提出之多個概念與多個機制之多種特徵及/或方面。更具體地,邏輯流程200可以是有關於從多個碼本中選擇一碼本。邏輯流程200可以包括區塊210、220、230、240和250中之一個或多個所表示之一個或多個操作、動作或功能。儘管顯示為分離之區塊,根據實施需求,邏輯流程200之多個區塊可以劃分出額外之區塊,組合為更少之區塊,或者省略部分區塊。邏輯流程200可以由以下所述之第一裝置1005與第二裝置1050中之每個來實施。僅用於說明目的而非限制發明之範圍,邏輯流程200之說明在下文中以第二裝置1050之文字說明提供。邏輯流程200可以在從區塊(步驟)210開始。 2 is a schematic diagram of an example logic flow 200 associated with multiple built-in LDPC code designs in accordance with an embodiment of the present invention. Logic flow 200 may be implemented in a decoder or processor, or implemented using an encoder or processor to implement various features and/or aspects of the various concepts and mechanisms presented herein. More specifically, logic flow 200 may be related to selecting a codebook from a plurality of codebooks. Logic flow 200 may include one or more operations, actions, or functions represented by one or more of blocks 210, 220, 230, 240, and 250. Although shown as separate blocks, depending on implementation requirements, multiple blocks of logic flow 200 may be partitioned into additional blocks, combined into fewer blocks, or partially omitted. The logic flow 200 can be implemented by each of the first device 1005 and the second device 1050 described below. The description of the logic flow 200 is provided below with the textual description of the second device 1050 for illustrative purposes only and not for limiting the scope of the invention. The logic flow 200 can begin at block (step) 210.
在步驟210中,邏輯流程200可以包括:第二裝置1050決定待編碼之資料之一碼塊尺寸是否小於一門檻碼塊尺寸。在決定該資料之該碼塊尺寸小於該門檻碼塊尺寸之情形下,邏輯流程200可以從步驟210前進至步驟220。在決定該資料之該碼塊尺寸不小於該門檻碼塊尺寸之情形下,邏輯流程200可以從步驟210前進至步驟230。 In step 210, the logic flow 200 may include the second device 1050 determining whether the code block size of one of the data to be encoded is less than a threshold block size. In the event that it is determined that the code block size of the data is less than the threshold code block size, logic flow 200 may proceed from step 210 to step 220. In the event that it is determined that the code block size of the data is not less than the threshold code block size, logic flow 200 may proceed from step 210 to step 230.
在步驟220中,邏輯流程可以包括:第二裝置1050選擇多個碼本中之一第一碼本(即,使用小尺寸之資訊矩陣與同位矩陣作為基礎矩陣)。 In step 220, the logic flow may include the second device 1050 selecting one of the plurality of codebooks (ie, using a small-sized information matrix and a parity matrix as the base matrix).
在步驟230中,邏輯流程可以包括:第二裝置1050決定用於資料傳輸之一初始碼率(initial code rate)是否大於一門檻碼率。在決定該初始碼率不大於該門檻碼率之情形下,邏輯流程200可以從步驟230前進至步驟240。在決定該初始碼率大於該門檻碼率之情形下,邏輯流程200可以從步驟230前進至步驟250。 In step 230, the logic flow may include the second device 1050 determining whether an initial code rate for data transmission is greater than a threshold rate. In the event that it is determined that the initial code rate is not greater than the threshold rate, logic flow 200 may proceed from step 230 to step 240. In the event that it is determined that the initial code rate is greater than the threshold rate, logic flow 200 may proceed from step 230 to step 250.
在步驟240中,邏輯流程200可以包括:第二裝置1050選擇多個碼本中之一第二碼本(即,使用中尺寸之資訊矩陣與同位矩陣作為基礎矩陣)。 In step 240, the logic flow 200 may include the second device 1050 selecting one of the plurality of codebooks (ie, the information matrix of the in-use size and the parity matrix as the base matrix).
在步驟250中,邏輯流程200可以包括:第二裝置1050選擇多個碼本中之一第三碼本(即,使用大尺寸之資訊矩陣與同位矩陣作為基礎矩陣)。 In step 250, the logic flow 200 may include the second device 1050 selecting one of the plurality of codebooks and the third codebook (ie, using a large-sized information matrix and a parity matrix as the base matrix).
在此,該第三碼本之一尺寸大於該第二碼本之一尺寸。另外,該第二碼本之該尺寸大於該第一碼本之一尺寸。 Here, one of the third codebooks has a size larger than one of the second codebooks. In addition, the size of the second codebook is larger than a size of the first codebook.
第3圖為根據本發明一實施方式之類列正交層設計300之示例示意圖。正交性(Orthogonality)有利於LDPC解碼器之吞吐量效率(throughput efficiency)。在LDPC編碼中,幾個列可以被劃分為一組以形成一層,且該層內之每行都可以是一度(degree one)(即,正交性)。在此情形下,該層稱為一純列正交層(pure row orthogonal layer)。 FIG. 3 is a diagram showing an example of a column-like orthogonal layer design 300 in accordance with an embodiment of the present invention. Orthogonality facilitates the throughput efficiency of the LDPC decoder. In LDPC encoding, several columns can be divided into a group to form a layer, and each row within the layer can be a degree one (i.e., orthogonality). In this case, the layer is referred to as a pure row orthogonal layer.
請參考第3圖,在類列正交層設計300中,幾個列可以被劃分為一組以形成一類列正交層。除一個或多個截斷行之外,該層內之每行可以是一度(即,正交性)。在第3圖之部分(A)所示之示例中,兩個最左側行均為截斷行。 Referring to FIG. 3, in the class column orthogonal layer design 300, several columns can be divided into a group to form a class of column orthogonal layers. Each row within the layer may be one degree (ie, orthogonal) except one or more truncated lines. In the example shown in part (A) of Figure 3, the two leftmost rows are truncated rows.
此外,在類列正交層設計300中,在類列正交層中之多個截斷行內沒有循環(cycle)。在第3圖之部分(B)所示之示例中,由於在兩個截斷行內存在一循環,因此,對應層不視為根據本發明之一類列正交層。 Further, in the class column orthogonal layer design 300, there are no cycles in a plurality of truncated lines in the class column orthogonal layer. In the example shown in part (B) of Fig. 3, since a loop is stored in two truncated lines, the corresponding layer is not regarded as a class of orthogonal layers according to the present invention.
第4圖為根據本發明一實施方式之混合正交層設計400之一示例示意圖。在混合正交層設計400中,QC-LDPC碼可以包括不同度正交性之多個部分(portions)。在第4圖所示之示例中,較暗顏色之多個塊代表多個位元1,較淺顏 色之多個塊代表多個位元0。例如,該多個部分中之第一部分可以是低度正交,並可以對應於一高碼率。同樣地,該多個部分之一第二部分可以是中度正交,並可以對應於一中(medium)碼率。類似地,該多個部分中之一第三部分可以是高度正交,並可以對應於一低碼率。 4 is a schematic diagram of an example of a hybrid orthogonal layer design 400 in accordance with an embodiment of the present invention. In the hybrid orthogonal layer design 400, the QC-LDPC code can include multiple ports of different degrees of orthogonality. In the example shown in Figure 4, multiple blocks of darker colors represent multiple bits, which are lighter. A plurality of blocks of color represent a plurality of bits 0. For example, the first of the plurality of portions can be low orthogonal and can correspond to a high code rate. Likewise, the second portion of one of the plurality of portions can be moderately orthogonal and can correspond to a medium code rate. Similarly, one of the plurality of portions may be highly orthogonal and may correspond to a low code rate.
在第4圖所示之示例中,不同正交度之多個部分包括以下情況:(1)一非列正交部分,包括多個列與多個行,該多個列與該多個行形成對應於相對較高之一個或多個碼率之至少一非列正交層;(2)一類列正交部分,包括多個列與多個行,該多個列與該多個行形成對應於裝置一個或多個中碼率之至少一類列正交層;以及(3)一純列正交層,包括多個列與多個行,該多個列與該多個行形成對應於相對較低之一個或多個碼率之至少一純列正交層。在此,該非列正交部分之該多個行中之每行為正交度為2或更高之行。另外,該類列正交部分之該多個行中之一個或多個行包括正交度為2或更高之多個截斷行。此外,該類列正交部分之該多個行之剩餘多個行包括正交度為1之多個非截斷行。此外,該純列正交部分之該多個行中之每行包括正交度為1之一行。 In the example shown in FIG. 4, the plurality of portions of different orthogonalities include the following cases: (1) a non-column orthogonal portion including a plurality of columns and a plurality of rows, the plurality of columns and the plurality of rows Forming at least one non-column orthogonal layer corresponding to a relatively high one or more code rates; (2) a class of column orthogonal portions including a plurality of columns and a plurality of rows, the plurality of columns forming the plurality of rows Corresponding to at least one type of column orthogonal layer of one or more medium code rates of the device; and (3) a pure column orthogonal layer comprising a plurality of columns and a plurality of rows, the plurality of columns forming corresponding to the plurality of rows At least one pure column orthogonal layer of relatively low one or more code rates. Here, each of the plurality of rows of the non-column orthogonal portion has a row orthogonality of 2 or higher. In addition, one or more of the plurality of rows of the orthogonal portion of the class include a plurality of truncated rows having an orthogonality of 2 or higher. Furthermore, the remaining plurality of rows of the plurality of rows of the orthogonal portion of the class include a plurality of non-truncated rows having an orthogonality of one. Further, each of the plurality of rows of the pure column orthogonal portion includes one row having an orthogonality of one.
第5圖為根據本發明一實施方式之支援極低碼率之QC-LDPC碼500之示例示意圖。請參考第5圖,QC-LDPC碼500可以包括多個同位位元之一同位矩陣與多個資訊位元之一資訊矩陣。該資訊矩陣可以包括一列或多列位元,每列位元之正交度為2。此外,正交度為2之該一列或多列位元中每列正交度為2之多個位元中之每個位元,可以是之前所使用之同位位元或之前所發送之資訊位元。 FIG. 5 is a diagram showing an example of a QC-LDPC code 500 supporting an extremely low code rate according to an embodiment of the present invention. Referring to FIG. 5, the QC-LDPC code 500 may include one of a plurality of parity bits and one information matrix of a plurality of information bits. The information matrix may include one or more columns of bits, each of which has a degree of orthogonality of two. In addition, each of the plurality of bits having a degree of orthogonality of 2 in the one or more columns of the orthogonality of 2 may be the previously used parity or previously transmitted information. Bit.
第6圖為根據本發明一實施方式之核心矩陣設計600之示例示意圖。請參考第6圖,在核心矩陣設計600中,一QC-LDPC碼可以包含一基礎矩陣,該基礎矩陣之一部分形成一核心矩陣,該核心矩陣對應於具有至少一門檻值之一碼率。例如,在第6圖所示之示例中,該核心矩陣支援一碼率0.89。 FIG. 6 is a diagram showing an example of a core matrix design 600 in accordance with an embodiment of the present invention. Referring to FIG. 6, in the core matrix design 600, a QC-LDPC code may include a basic matrix, and a portion of the basic matrix forms a core matrix corresponding to a code rate having at least one threshold value. For example, in the example shown in Figure 6, the core matrix supports a code rate of 0.89.
第7圖為根據本發明一實施方式之核心基礎矩陣之示例概念700之示 意圖。請參考第7圖,該核心矩陣可以包含多個列與多個行之多個位元,其中有兩個或更多個行為截斷行,該多個截斷行具有多個位元之一特定圖樣(例如,一個或多個位元0)。在一些實施方式中,多個截斷行中之多個位元之該特定圖樣可以包含多個位元0所形成之一等腰直角三角形,該等腰直角三角形之直角對應於該多個截斷行之一左上角處之一位元0。 Figure 7 is a diagram showing an exemplary concept 700 of a core base matrix in accordance with an embodiment of the present invention. intention. Referring to FIG. 7, the core matrix may include a plurality of columns of a plurality of columns and a plurality of rows, wherein there are two or more behavioral truncation rows having a specific pattern of one of the plurality of bits (for example, one or more bits 0). In some embodiments, the specific pattern of the plurality of bits in the plurality of truncated lines may comprise an isosceles right triangle formed by the plurality of bits 0, and the right angle of the isosceles right triangle corresponds to the plurality of truncated lines One of the bits 0 in the upper left corner.
該核心矩陣可以包含一同位矩陣,該同位矩陣包括多個列與多個行之多個位元。該核心矩陣也可以包含一資訊矩陣,該資訊矩陣包含多個列與多個行之多個位元。該同位矩陣包含具有一Wi-Fi圖樣(Wi-Fi pattern)之一矩陣(例如,像Wi-Fi圖形之同位矩陣)。此外,該資訊矩陣之多於一列之多個位元可以包括具有高密度之多個位元1而沒有或只有一個位元0之多個列。該多列之一底部列之多個位元可以包含第一數量之位元1。該第一數量可以等於該多個截斷行之一數量,或者比該多個截斷行之數量大1。 The core matrix may comprise a co-located matrix comprising a plurality of columns of a plurality of columns and a plurality of rows. The core matrix may also include an information matrix comprising a plurality of columns of a plurality of columns and a plurality of rows. The co-located matrix includes a matrix having a Wi-Fi pattern (eg, a parity matrix like a Wi-Fi pattern). In addition, a plurality of bits of more than one column of the information matrix may include a plurality of columns having a high density of one bit 1 and no or only one bit 0. A plurality of bits of the bottom column of one of the plurality of columns may include a first number of bits 1. The first amount may be equal to one of the plurality of truncated rows or one greater than the number of the plurality of truncated rows.
在第7圖之部分(A)所示之示例中,最初幾列(例如,三列)由像Wi-Fi之同位矩陣所構成,以及資訊矩陣具有非常高密度之多個位元1。更具體地,該資訊矩陣中之每列所包括之位元,若非全部為位元1,則大部分為位元1,沒有或者只有1個位元0。在任意次數之行置換(permutation)及/或列置換(例如,至少一行置換、至少一列置換、或其任意組合)後,截斷行包括一個或多個位元0之一特定圖樣。一個邊緣區塊(edge block)可以對應於同位變量節點(Variable Node,VN)區塊。兩個邊緣區塊可以對應於兩個截斷行(例如,VN0和VN1)。在存在四個邊緣區塊之情形下,第四個邊緣區塊可以被加入以增加最短距離。 In the example shown in part (A) of Fig. 7, the first few columns (for example, three columns) are composed of a parity matrix like Wi-Fi, and the information matrix has a plurality of bits 1 of very high density. More specifically, the bits included in each column of the information matrix, if not all of the bits 1, are mostly bit 1, with no or only one bit 0. After any number of rows of permutations and/or column permutations (eg, at least one row permutation, at least one column permutation, or any combination thereof), the truncated row includes one or more of the particular patterns of one of the bits 0. An edge block may correspond to a variable node (VN) block. Two edge blocks may correspond to two truncated lines (eg, VN0 and VN1). In the case where there are four edge blocks, a fourth edge block can be added to increase the shortest distance.
在第7圖之部分(B)所示之示例中,顯示了截斷行之一示例圖樣。對於尺寸為m x n之基礎矩陣,並假設p行被截斷,使用多個位元0之等腰直角三角形來構建一m x p矩陣,該三角形之直角對應於該多個截斷行之一左上角處之一位元0。該一個或多個截斷行中之其它位元可以被隨機選擇為0或1。由於可能執 行列置換及/或行置換,因此,特定圖樣之實際位置有可能與該一個或多個截斷行之左上角不同。 In the example shown in part (B) of Fig. 7, an example pattern of the truncated line is shown. For a base matrix of size mxn, and assuming that the p-row is truncated, an isosceles right-angled triangle of a plurality of bits 0 is used to construct an mxp matrix whose right angle corresponds to one of the upper left corners of one of the plurality of truncated lines Bit 0. The other of the one or more truncated lines may be randomly selected to be 0 or 1. Due to possible execution Row and column permutation and/or row permutation, therefore, the actual position of a particular pattern may be different from the upper left corner of the one or more truncated lines.
第8圖為根據本發明另一實施方式之核心基礎矩陣之示例概念800之示意圖。在概念800中,核心矩陣包括一Wi-Fi圖樣(或像Wi-Fi圖形之同位矩陣)、多個截斷行、以及該資訊矩陣之剩餘部分。該資訊矩陣之該剩餘部分可以使用多個維度分佈(degree distributions)中之一個來設計。例如,該核心矩陣可以包括5列位元與20行位元。該20行位元之一VN度可以包括下列其中一個:[2,2,2,2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3],[2,2,2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3],[2,2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3],以及[2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3]。該5列位元之一檢測節點(Check Node,CN)度可以包括下列其中一個:[13,10,14,17,2],[13,10,13,17,2],[13,10,13,18,3],[13,11,13,18,2],[13,10,14,18,2],[13,10,13,19,2],[14,10,13,18,1],[13,11,13,18,1],[13,10,14,18,1],[13,11,13,19,1],[13,10,13,18,2],以及[13,10,13,18,1]。 Figure 8 is a schematic illustration of an example concept 800 of a core base matrix in accordance with another embodiment of the present invention. In concept 800, the core matrix includes a Wi-Fi pattern (or a parity matrix like a Wi-Fi graphic), a plurality of truncated lines, and the remainder of the information matrix. This remainder of the information matrix can be designed using one of a plurality of degree distributions. For example, the core matrix can include 5 columns of bits and 20 rows of bits. One of the 20 rows of VN degrees may include one of the following: [2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,3,3],[2,2,2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3],[ 2,2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3], and [2,2,3,3 , 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3]. One of the five columns of Check Node (CN) degrees may include one of the following: [13, 10, 14, 17, 2], [13, 10, 13, 17, 2], [13, 10 ,13,18,3],[13,11,13,18,2],[13,10,14,18,2],[13,10,13,19,2],[14,10,13 ,18,1],[13,11,13,18,1],[13,10,14,18,1],[13,11,13,19,1],[13,10,13,18 , 2], and [13, 10, 13, 18, 1].
第9圖為根據本發明一實施方式之示例移位參數設計900之示意圖。對於每個擴展因子,可以存在一移位值表,該移位值表包括對應之多個移位值。不同擴展因子之這些移位值表可以使用巢套設計(nested designed)。在移位參數設計900中,多個擴展因子之一有效集合可以定義為用於LDPC編碼。在第9圖所示之示例中,多個擴展因子之該有效集合包括下列不同值之多個擴展因子:Z=16,Z=24,Z=32,Z=48,Z=64,Z=96,Z=128,Z=192,Z=256以及Z=384。在移位參數設計900中,多個擴展因子之該有效集合可以被優化為獲取多個擴展因子之一優化集合。該優化集合中之擴展因子之數量小於該有效集合中之擴展因子之數量。可以使用被設計用於最接近且小於或等於該優化集合內之擴展因子之多個移位值之移位值表。例如,為擴展因子Z=32所設計之多個移位值之移位值表可以被擴展因子Z=48所共用。類似地,為擴展因子Z=128所設計之 移位值表可以被擴展因子Z=192所共用。 FIG. 9 is a schematic diagram of an example shift parameter design 900 in accordance with an embodiment of the present invention. For each spreading factor, there may be a shift value table comprising a corresponding plurality of shift values. These shift value tables for different spreading factors can be nested designed. In the shift parameter design 900, one of a plurality of spreading factors may be defined as being used for LDPC encoding. In the example shown in FIG. 9, the effective set of the plurality of spreading factors includes a plurality of spreading factors of the following different values: Z=16, Z=24, Z=32, Z=48, Z=64, Z= 96, Z=128, Z=192, Z=256 and Z=384. In shift parameter design 900, the active set of multiple spread factors can be optimized to obtain an optimized set of one of a plurality of spread factors. The number of spreading factors in the optimized set is less than the number of spreading factors in the active set. A table of shift values that are designed for a plurality of shift values that are closest to and less than or equal to the spread factor within the optimized set can be used. For example, a shift value table for a plurality of shift values designed for the spreading factor Z=32 can be shared by the spreading factor Z=48. Similarly, designed for the expansion factor Z=128 The shift value table can be shared by the spreading factor Z=192.
僅用於說明目的而非限制,在根據本發明之一LDPC碼本中,使用Z,j{0,1,2,3,4,5},可以將多個擴展因子(Z)之一優化集合定義為四個集合。對應之多個移位值可以使用四個移位參數表來表示,該四個移位參數表可以對應於移位參數{288,352,416,480}之移位參數。對於有效集合φ內之任意擴展因子Z=a x 2j,對應之移位參數可以透過來獲取,其中,pm,n為用於â x 25之移位參數表中之第(m,n)個元素之移位參數,其中,â為{9,11,13,15}內之最大值,â小於或等於a,且。此外,f(Z)為干擾,是Z之函數,並可使用一表來表示。 For illustrative purposes only and not limitation, in an LDPC codebook according to the present invention, Z is used. ,j {0, 1, 2, 3, 4, 5}, one of a plurality of expansion factors (Z) can be defined as four sets. The corresponding plurality of shift values may be represented using four shift parameter tables, which may correspond to shift parameters of the shift parameters {288, 352, 416, 480}. For any expansion factor Z=ax 2j within the effective set φ, the corresponding shift parameter can be transmitted through To obtain, where pm,n are the shift parameters of the (m,n)th element in the shift parameter table of â x 25, where â is the largest within {9,11,13,15} Value, â is less than or equal to a, and . In addition, f(Z) is a disturbance and is a function of Z and can be represented using a table.
說明實施方式 Description of implementation
第10圖為根據本發明一實施方式之示例通信系統1000之示意圖。通信系統可以包括第一裝置1005與第二裝置1050,第一裝置1005與第二裝置1050可以透過通信鏈路1040彼此通信。通信鏈路1040在一些實施方式中可以是一無線鏈路,在另一些實施方式中也可以是有線鏈路。第一裝置1005與第二裝置1050中之每個可以作為一通信裝置來執行多種功能,以實施與QC-LDPC編碼有關之此處所述概念、機制、技術、操作及方法,包括與第1圖至第9圖中之一些或全部有關之內容以及下文所述之操作1100、1200及1300。更具體地,第一裝置1005與第二裝置1050中之每個可以實施與多重內置LDPC碼設計、混合正交LDPC層設計、極低碼率之QC-LDPC支援、核心矩陣設計及移位參數設計有關之所提出概念與機制之各方面。 FIG. 10 is a schematic diagram of an example communication system 1000 in accordance with an embodiment of the present invention. The communication system can include a first device 1005 and a second device 1050, which can communicate with one another via a communication link 1040. Communication link 1040 may be a wireless link in some embodiments, or a wired link in other embodiments. Each of the first device 1005 and the second device 1050 can perform a variety of functions as a communication device to implement the concepts, mechanisms, techniques, operations, and methods described herein in connection with QC-LDPC encoding, including with the first Figures to some or all of the contents of Figure 9 and operations 1100, 1200, and 1300 described below. More specifically, each of the first device 1005 and the second device 1050 can be implemented with multiple built-in LDPC code designs, hybrid orthogonal LDPC layer design, very low bit rate QC-LDPC support, core matrix design, and shift parameters. Design aspects of the proposed concepts and mechanisms.
第一裝置1005與第二裝置1050中之每個可以是一電子裝置中之一部分,該電子裝置可以是一通信裝置、一計算裝置、一便攜式或行動裝置、或一可穿戴式裝置。例如,第一裝置1005可以實施為一Wi-Fi存取點、一智慧型手機、一智慧型手錶、一智慧型手環、一智慧型項鍊、一個人數位助理、或一計算裝 置(如一平板電腦、一膝上型電腦、一筆記本電腦、一台式電腦或一伺服器)。同樣地,第二裝置1050可以實施為一Wi-Fi行動客戶端(Client)或站台(station)、一智慧型手機、一智慧型手錶、一智慧型手環、一智慧型項鍊、一個人數位助理、或一計算裝置(如一平板電腦、一膝上型電腦、一筆記本電腦、一台式電腦或一伺服器)。可替代地,第一裝置1005與第二裝置1050可以實施為一個或多個積體電路(Integrated-Circuit,IC)晶片之形式,例如但不僅限於,一個或多個單核處理器、一個或多個多核處理器、或一個或多個複雜指令集合計算(Complex-Instruction-Set-Computing,CISC)處理器。 Each of the first device 1005 and the second device 1050 can be part of an electronic device, which can be a communication device, a computing device, a portable or mobile device, or a wearable device. For example, the first device 1005 can be implemented as a Wi-Fi access point, a smart phone, a smart watch, a smart bracelet, a smart necklace, a number of assistants, or a computing device. Set (such as a tablet, a laptop, a laptop, a desktop computer or a server). Similarly, the second device 1050 can be implemented as a Wi-Fi mobile client (client) or station, a smart phone, a smart watch, a smart bracelet, a smart necklace, and a number of assistants. Or a computing device (such as a tablet, a laptop, a laptop, a desktop computer, or a server). Alternatively, the first device 1005 and the second device 1050 may be implemented in the form of one or more integrated-circuit (IC) chips, such as but not limited to, one or more single-core processors, one or Multiple multi-core processors, or one or more Complex-Instruction-Set-Computing (CISC) processors.
第一裝置1005與第二裝置1050中之每個可以分別包括第10圖所示之這些組件中之至少一些。例如,第一裝置1005可以包括至少一處理器1010,以及第二裝置1050可以包括至少一處理器1060。另外,第一裝置1005可以包括一記憶體1020及/或一收發器1030,收發器1030配置為無線發送與接收資料(例如,符合一個或多個3GPP標準、協定、規格及/或任意適用之無線協定與標準)。記憶體1020與收發器1030中之每個可以可通信及可操作性地耦接於處理器1010。類似地,第二裝置1050也可以包括一記憶體1070及/或一收發器1080,其中收發器1080配置為無線發送與接收資料(例如,符合IEEE 802.11規格及/或任意可適用之無線協定及標準)。記憶體1070與收發器1080中之每個可以可通信及可操作性地耦接於處理器1060。第一裝置1005與第二裝置1050中之每個可以進一步包括其它組件(例如,功率系統、顯示裝置及用戶介面裝置),這些其它組件與本發明所提供之機制沒有緊密關聯,因而並未顯示於第10圖中或在此處進行說明,以達到簡化及簡潔之目的。 Each of the first device 1005 and the second device 1050 may include at least some of the components shown in FIG. 10, respectively. For example, the first device 1005 can include at least one processor 1010, and the second device 1050 can include at least one processor 1060. In addition, the first device 1005 can include a memory 1020 and/or a transceiver 1030 configured to wirelessly transmit and receive data (eg, conforming to one or more 3GPP standards, protocols, specifications, and/or any applicable Wireless protocols and standards). Each of the memory 1020 and the transceiver 1030 can be communicably and operatively coupled to the processor 1010. Similarly, the second device 1050 can also include a memory 1070 and/or a transceiver 1080, wherein the transceiver 1080 is configured to wirelessly transmit and receive data (eg, conforming to the IEEE 802.11 specification and/or any applicable wireless protocol and standard). The memory 1070 and each of the transceivers 1080 can be communicably and operatively coupled to the processor 1060. Each of the first device 1005 and the second device 1050 may further include other components (eg, a power system, a display device, and a user interface device) that are not closely related to the mechanisms provided by the present invention and thus are not displayed This is illustrated in Figure 10 or here for simplification and simplification.
收發器1030可以配置為在單一頻帶(frequency band)或多個頻帶上進行無線通信。收發器1030可以包括發送器1032與接收器1034,發送器1032能夠無線發送資料,接收器1034能夠無線接收資料。同樣地,收發器1080可以配置 為在單一頻帶或多個頻帶上進行無線通信。收發器1080可以包括發送器1082與收發器1084,發送器1082能夠無線發送資料,接收器1084能夠無線接收資料。 The transceiver 1030 can be configured to communicate wirelessly over a single frequency band or multiple frequency bands. The transceiver 1030 can include a transmitter 1032 and a receiver 1034, the transmitter 1032 can wirelessly transmit data, and the receiver 1034 can receive data wirelessly. Similarly, transceiver 1080 can be configured To perform wireless communication in a single frequency band or multiple frequency bands. The transceiver 1080 can include a transmitter 1082 and a transceiver 1084, the transmitter 1082 can wirelessly transmit data, and the receiver 1084 can receive data wirelessly.
記憶體1020與記憶體1070中之每個可以為一存儲裝置,配置為儲存一個或多個代碼、程序及/或指令之集合及/或儲存其中之資料。在第10圖所示之示例中,記憶體1020儲存處理器可執行之指令1022之一個或多個集合與儲存其中之資料1024,以及記憶體1070儲存處理器可執行之指令1072之一個或多個集合及儲存其中之資料1074。記憶體1020與記憶體1070中之每個可以使用適合之技術來實施,並可包括揮發性記憶體及/或非揮發性記憶體。舉例而言,記憶體1020與記憶體1070中之每個可以包括一類隨機存取記憶體(RAM),如動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、閘流體隨機存取記憶體(Thyristor RAM,T-RAM)及/或零電容隨機存取記憶體(Z-RAM)。可替代地或額外地,記憶體1020與記憶體1070中之每個可以包括一類唯讀記憶體(ROM),如遮罩式唯讀記憶體(mask ROM)、可程式化ROM(PROM)、可擦除可程式化ROM(EPROM)及/或電可擦除可程式化ROM(EEPROM)。可替代地或可額外地,記憶體1020與記憶體1070中之每個可以包括一類非揮發性記憶體(Non-Volatile Random-Access Memory,NVRAM),如閃存記憶體、固態記憶體、鐵電隨機存取記憶體(Ferroelectric RAM,FeRAM)、磁阻隨機存取記憶體(Magnetoresistive RAM,MRAM)及/或相位改變記憶體(phase-change memeory)。 Each of the memory 1020 and the memory 1070 can be a storage device configured to store one or more code, programs, and/or sets of instructions and/or stored therein. In the example shown in FIG. 10, memory 1020 stores one or more sets of processor-executable instructions 1022 and stored therein data 1024, and memory 1070 stores one or more of processor-executable instructions 1072. Collect and store the information 1074. Each of memory 1020 and memory 1070 can be implemented using suitable techniques and can include volatile memory and/or non-volatile memory. For example, each of the memory 1020 and the memory 1070 may include a type of random access memory (RAM) such as dynamic random access memory (DRAM), static random access memory (SRAM), thyristor. Random access memory (Thyristor RAM, T-RAM) and / or zero capacitance random access memory (Z-RAM). Alternatively or additionally, each of the memory 1020 and the memory 1070 may include a type of read only memory (ROM), such as a mask-type read ROM (ROM), a programmable ROM (PROM), Erasable programmable ROM (EPROM) and/or electrically erasable programmable ROM (EEPROM). Alternatively or additionally, each of the memory 1020 and the memory 1070 may include a non-Volatile Random-Access Memory (NVRAM) such as a flash memory, a solid state memory, or a ferroelectric Random access memory (Ferroelectric RAM, FeRAM), magnetoresistive random access memory (MRAM) and/or phase-change memeory.
在一方面,處理器1010與處理器1060中之每個可以實施為一個或多個單核處理器、一個或多個多核處理器、或一個或多個CISC處理器之形式。換言之,即使此處使用一單數形式「一處理器」來指代處理器1010與處理器1060中之每個,處理器1010與處理器1060中之每個可以包括在根據本發明之一些實施方式中之多個處理器,以及在根據本發明之另一些實施例中之單個處理器。在另一方面,處理器1010與處理器1060中之每個可以實施為使用配置並用於實 現根據本發明之特定目的之多個電子組件之硬體(以及,可選擇為,韌體)形式,這些電子組件可以例如但不僅限於,一個或多個電晶體、一個或多個二極體、一個或多個電容、一個或多個電阻、一個或多個電感、一個或多個憶阻器(memristors)或一個或多個變容二極體(varactors)。換言之,在至少一些實施方式中,處理器1010與處理器1060中之每個為一特殊用途機器,被特別設計、安排及配置用於執行根據本發明多種實施方式之包括QC-LDPC編碼之特定任務。 In one aspect, each of processor 1010 and processor 1060 can be implemented in the form of one or more single core processors, one or more multi-core processors, or one or more CISC processors. In other words, even though a singular "one processor" is used herein to refer to each of processor 1010 and processor 1060, each of processor 1010 and processor 1060 may be included in some embodiments in accordance with the present invention. A plurality of processors, and a single processor in still other embodiments in accordance with the invention. In another aspect, each of the processor 1010 and the processor 1060 can be implemented as a usage configuration and used in real In the form of hardware (and, optionally, firmware) of a plurality of electronic components according to the specific objects of the present invention, such electronic components may be, for example but not limited to, one or more transistors, one or more diodes One or more capacitors, one or more resistors, one or more inductors, one or more memristors, or one or more varactors. In other words, in at least some embodiments, each of processor 1010 and processor 1060 is a special purpose machine specifically designed, arranged, and configured to perform the specifics including QC-LDPC encoding in accordance with various embodiments of the present invention. task.
處理器1010,作為一特殊用途機器,可以包括非通用與特別設計之硬體電路,被設計安排及配置用於執行與根據本發明多個實施方式之QC-LDPC編碼有關之特定任務。在一方面,處理器1010可以執行儲存於記憶體1020中之代碼、程序及/或指令1022之一個或多個集合,以根據本發明多個實施方式來執行多個操作以產生QC-LDPC編碼。在另一方面,處理器1010可以包括一編碼器1012與一解碼器1014,編碼器1012與解碼器1014集合在一起用於根據本發明多個實施例執行多個特定任務以產生QC-LDPC編碼。例如,編碼器1012可以配置為根據本發明之多個概念與機制對資料進行編碼。類似地,解碼器1014可以配置為根據本發明之多個概念與機制對資料進行解碼。 The processor 1010, as a special purpose machine, may include non-universal and specially designed hardware circuits that are designed and configured to perform specific tasks associated with QC-LDPC encoding in accordance with various embodiments of the present invention. In one aspect, processor 1010 can execute one or more sets of code, programs, and/or instructions 1022 stored in memory 1020 to perform multiple operations to generate QC-LDPC encoding in accordance with various embodiments of the present invention. . In another aspect, processor 1010 can include an encoder 1012 and a decoder 1014 that are combined with decoder 1014 for performing a plurality of specific tasks to generate QC-LDPC encoding in accordance with various embodiments of the present invention. . For example, encoder 1012 can be configured to encode data in accordance with a number of concepts and mechanisms of the present invention. Similarly, decoder 1014 can be configured to decode data in accordance with a number of concepts and mechanisms of the present invention.
處理器1060,作為一特殊用途機器,可以包括非通用與特別設計之硬體電路,被設計安排及配置用於執行與根據本發明多個實施方式之QC-LDPC編碼有關之特定任務。在一方面,處理器1060可以執行儲存於記憶體1070中之代碼、程序及/或指令1072之一個或多個集合,以根據本發明多個實施方式來執行多個操作以產生QC-LDPC編碼。在另一方面,處理器1060可以包括一編碼器1062與一解碼器1064,編碼器1062與解碼器1064集合在一起用於根據本發明多個實施例執行多個特定任務以產生QC-LDPC編碼。例如,編碼器1062可以配置為根據本發明之多個概念與機制對資料進行編碼。同樣地,解碼器1064可以配置為根據本發明之多個概念與機制對資料進行解碼。 The processor 1060, as a special purpose machine, may include non-universal and specially designed hardware circuits that are designed and configured to perform particular tasks associated with QC-LDPC encoding in accordance with various embodiments of the present invention. In one aspect, processor 1060 can execute one or more sets of code, programs, and/or instructions 1072 stored in memory 1070 to perform multiple operations to generate QC-LDPC encoding in accordance with various embodiments of the present invention. . In another aspect, processor 1060 can include an encoder 1062 and a decoder 1064 that are combined together to perform a plurality of specific tasks to generate QC-LDPC encoding in accordance with various embodiments of the present invention. . For example, encoder 1062 can be configured to encode data in accordance with a number of concepts and mechanisms of the present invention. Likewise, decoder 1064 can be configured to decode data in accordance with a number of concepts and mechanisms of the present invention.
第一裝置1005與第二裝置1050中之每個可以配置為實施以下所述之操作1100、1200及1300中之每個。因此,為避免冗餘及簡潔起見,第一裝置1005與第二裝置1050之多個操作,以及處理器1010與處理器1060,在下文中以操作1100、1200及1300進行說明。值得注意的是,儘管以下說明提供了第一裝置1005之文字說明,以下說明同樣適用於第二裝置1050。 Each of the first device 1005 and the second device 1050 can be configured to implement each of the operations 1100, 1200, and 1300 described below. Therefore, to avoid redundancy and brevity, multiple operations of the first device 1005 and the second device 1050, as well as the processor 1010 and the processor 1060, are described below with operations 1100, 1200, and 1300. It should be noted that although the following description provides a textual description of the first device 1005, the following description is equally applicable to the second device 1050.
第11圖為根據本發明一實施例之示例操作1100之示意圖。操作1100可以代表實施本發明所提供概念及機制之一方面,例如,與第1圖至第9圖之一些或全部有關之說明。更具體地,操作1100可以代表本發明所提供之與多重內置LDPC碼設計及移位參數設計有關之多個概念與機制。操作1100可以包括如區塊1110、1120、1130及1140中之一個或多個所顯示之一個或多個操作、動作或功能。儘管顯示為分離之區塊,根據實施需求,操作1100之多個區塊可以劃分出額外之區塊,組合為更少之區塊,或者省略部分區塊。此外,操作1100之多個區塊/子區塊可以按照第11圖所示之順序來執行,或者也可替換為不同之順序來執行。操作1100可以由通信系統1000及其任意變形來實施。例如,操作1100可以實施於第一裝置1005及/或第二裝置1050之中,或者由第一裝置1005及/或第二裝置1050來實施。出於說明目的而非限制發明之範圍,操作1100在下文中以第一裝置1005進行說明。操作1100可以從區塊(步驟)1110開始。 11 is a schematic diagram of an example operation 1100 in accordance with an embodiment of the present invention. Operation 1100 may represent one aspect of implementing the concepts and mechanisms provided by the present invention, for example, relating to some or all of Figures 1 through 9. More specifically, operation 1100 can represent a number of concepts and mechanisms provided by the present invention related to multiple built-in LDPC code designs and shift parameter designs. Operation 1100 can include one or more operations, actions, or functions as displayed by one or more of blocks 1110, 1120, 1130, and 1140. Although shown as separate blocks, depending on implementation requirements, multiple blocks of operation 1100 may divide additional blocks, combine into fewer blocks, or omit portions of the blocks. Moreover, the plurality of blocks/sub-blocks of operation 1100 may be performed in the order shown in FIG. 11, or may be replaced with a different order. Operation 1100 can be implemented by communication system 1000 and any variations thereof. For example, operation 1100 can be implemented in first device 1005 and/or second device 1050, or implemented by first device 1005 and/or second device 1050. Operation 1100 is described below with first device 1005 for purposes of illustration and not limitation of the scope of the invention. Operation 1100 can begin at block (step) 1110.
在步驟1110中,操作1100可以包括:第一裝置1005之處理器1010產生包含內置之多個碼本之一QC-LDPC碼。操作1100可以從步驟1110前進至1120。 In step 1110, operation 1100 can include the processor 1010 of the first device 1005 generating a QC-LDPC code including one of a plurality of built-in codebooks. Operation 1100 can proceed from step 1110 to 1120.
在步驟1120中,操作1100可以包括:處理器1010從該多個碼本中選擇一碼本。操作1100可以從步驟1120前進至步驟1130。 In step 1120, operation 1100 can include the processor 1010 selecting a codebook from the plurality of codebooks. Operation 1100 can proceed from step 1120 to step 1130.
在步驟1130中,操作1100可以包括:處理器1010使用所選擇之碼本對資料進行編碼。操作1100可以從步驟1130前進至步驟1140。 In step 1130, operation 1100 can include the processor 1010 encoding the data using the selected codebook. Operation 1100 can proceed from step 1130 to step 1140.
在步驟1140中,操作1100可以包括:處理器1010透過收發器1030發 送編碼後之資料(例如,向第二裝置1050發送)。 In step 1140, operation 1100 can include: processor 1010 transmitting through transceiver 1030 The encoded data is sent (e.g., sent to the second device 1050).
在一些實施方式中,該多個碼本中之每個碼本可以各自對應於多個HARQ線程中之一HARQ線程,該多個HARQ線程各不相同。 In some embodiments, each of the plurality of codebooks may each correspond to one of a plurality of HARQ threads, the plurality of HARQ threads being different.
在一些實施方式中,在產生具有內置之多個碼本之QC-LDPC碼時,操作1100可以包括:處理器1010產生該QC-LDPC碼,該QC-LDPC碼包括一基礎矩陣與一移位參數矩陣。該基礎矩陣可以包括一同位矩陣與一資訊矩陣,其中,該同位矩陣包含多個同位位元,該資訊矩陣包含多個資訊位元。該多個碼本中之每個碼本可以包括該同位矩陣與該資訊矩陣中對應各自尺寸之一部分,以便該多個碼本之多個尺寸各不相同。 In some embodiments, when generating a QC-LDPC code having a plurality of built-in codebooks, operation 1100 can include: processor 1010 generating the QC-LDPC code, the QC-LDPC code including a base matrix and a shift Parameter matrix. The basic matrix may include a parity matrix and an information matrix, wherein the parity matrix includes a plurality of parity bits, and the information matrix includes a plurality of information bits. Each of the plurality of codebooks may include the co-located matrix and a portion of a corresponding respective size in the information matrix such that the plurality of codebooks have different sizes.
在一些實施方式中,該多個碼本中之每個碼本可以各自對應於該移位參數矩陣之多個設計之一設計。 In some embodiments, each of the plurality of codebooks can each be designed corresponding to one of a plurality of designs of the shift parameter matrix.
在一些實施方式中,在產生具有內置之多個碼本之QC-LDPC碼時,操作1100可以包括:處理器1010為多個擴展因子之一第一集合中之每個擴展因子產生各自之一移位值表。此外,操作1100可以包括:處理器1010對該多個擴展因子之該第一集合進行優化以產生多個擴展因子之一第二集合。該第一集合之多個擴展因子之數量可以大於該第二集合之多個擴展因子之數量。存在於該第一集合中但不存在於該第二集合中之一第一擴展因子可以共用同時存在於該第一集合與該第二集合中之一第二擴展因子之一移位值表。該第二擴展因子有可能在數值上小於該第一擴展因子,並相較於該第一集合中之其它擴展因子更加接近於該第一擴展因子。 In some embodiments, when generating a QC-LDPC code having a plurality of built-in codebooks, the operation 1100 can include the processor 1010 generating one of each of the first set of the plurality of spreading factors. Shift value table. Moreover, operation 1100 can include the processor 1010 optimizing the first set of the plurality of spreading factors to generate a second set of the plurality of spreading factors. The number of the plurality of spreading factors of the first set may be greater than the number of the plurality of spreading factors of the second set. One of the first spreading factors present in the first set but not present in the second set may share a shift value table that is present in both the first set and the second set of one of the second set. The second spreading factor is likely to be numerically less than the first spreading factor and is closer to the first spreading factor than the other spreading factors in the first set.
在一些實施方式中,在從該多個碼本中選擇該碼本時,操作1100可以包括:基於用於資料傳輸之一初始碼率、該資料之一碼塊尺寸或二者,處理器1010從該多個碼本中選擇該碼本。 In some embodiments, when the codebook is selected from the plurality of codebooks, operation 1100 can comprise, based on one of an initial code rate for data transmission, a code block size of the data, or both, processor 1010 The codebook is selected from the plurality of codebooks.
在一些實施方式中,在從該多個碼本中選擇該碼本時,操作1100可 以包括:處理器1010執行多個操作(例如,類似於邏輯流程200所包含之操作)。例如,操作1100可以包括:處理器1010決定該資料之碼塊尺寸是否小於一門檻碼塊尺寸。當該資料之碼塊尺寸小於該門檻碼塊尺寸時,作為回應,操作1100可以包括:處理器1010選擇該多個碼本之一第三碼本。當該資料之碼塊尺寸不小於該門檻碼塊尺寸時,作為回應,操作1100可以包括:處理器1010決定用於資料傳輸之一初始碼率是否大於一門檻碼率。當該初始碼率不大於該門檻碼率時,作為回應,操作1100可以包括:處理器1010選擇該多個碼本之一第二碼本。當該初始碼率大於該門檻碼率時,作為回應,操作1100可以包括:處理器1010選擇該多個碼本之一第一碼本。該第一碼本之尺寸有可能大於該第二碼本之尺寸。該第二碼本之尺寸有可能大於該第三碼本之尺寸。 In some embodiments, when the codebook is selected from the plurality of codebooks, operation 1100 can be To include: The processor 1010 performs a number of operations (eg, similar to the operations included in the logic flow 200). For example, operation 1100 can include the processor 1010 determining whether the code block size of the data is less than a threshold block size. When the code block size of the data is less than the threshold code block size, in response, operation 1100 can include the processor 1010 selecting one of the plurality of codebooks and the third codebook. When the code block size of the data is not less than the threshold code block size, in response, operation 1100 can include the processor 1010 determining whether an initial code rate for one of the data transmissions is greater than a threshold rate. When the initial code rate is not greater than the threshold rate, in response, operation 1100 can include the processor 1010 selecting one of the plurality of codebooks and the second codebook. When the initial code rate is greater than the threshold rate, in response, operation 1100 can include the processor 1010 selecting one of the plurality of codebooks for the first codebook. The size of the first codebook may be larger than the size of the second codebook. The size of the second codebook may be larger than the size of the third codebook.
可替代地或額外地,在從該多個碼本中選擇該碼本時,操作1100可以包括:處理器1010執行多個其它操作。例如,操作1100可以包括:處理器1010決定該資料之一碼塊尺寸。基於該決定結果,操作1100可以包括:處理器1010選擇該多個碼本之一第一碼本,以作為決定該碼塊尺寸大於一第一門檻碼塊尺寸之回應。另外,操作1100可以包括:處理器1010選擇該多個碼本之一第二碼本,以作為決定該碼塊尺寸大於一第二門檻碼塊尺寸之回應。此外,操作1100可以包括:處理器1010選擇該多個碼本之一第三碼本,以作為決定該碼塊尺寸大於一第三門檻碼塊尺寸之回應。該第一門檻碼塊尺寸又肯呢個大於該第二門檻碼塊尺寸。該第二門檻碼塊尺寸有可能大於該第三門檻碼塊尺寸。該第一碼本之尺寸有可能大於該第二碼本之尺寸。該第二碼本之尺寸有可能大於該第三碼本之尺寸。 Alternatively or additionally, when the codebook is selected from the plurality of codebooks, operation 1100 can include the processor 1010 performing a plurality of other operations. For example, operation 1100 can include the processor 1010 determining a code block size for the data. Based on the result of the decision, operation 1100 can include the processor 1010 selecting a first codebook of the plurality of codebooks as a response to determine that the code block size is greater than a first threshold code block size. Additionally, operation 1100 can include the processor 1010 selecting a second codebook of the plurality of codebooks as a response to determine that the code block size is greater than a second threshold code block size. Moreover, operation 1100 can include the processor 1010 selecting a third codebook of the plurality of codebooks as a response to determine that the code block size is greater than a third threshold code block size. The size of the first threshold block is greater than the size of the second threshold block. The second threshold code block size may be larger than the third threshold code block size. The size of the first codebook may be larger than the size of the second codebook. The size of the second codebook may be larger than the size of the third codebook.
第12圖為根據本發明一實施方式之示例操作1200之示意圖。操作1200可以代表實施本發明所提供之多個概念與機制(如與第1圖至第9圖所示之一些或全部有關之說明)之一方面。更具體地,操作1200可以代表與混合正交 LDPC層設計及極低碼率之QC-LDPC支援有關之本發明所提出之多個概念與機制之一方面。操作1200可以包括區塊1210、1220及1230中之一個或多個所示之一個或多個操作、動作或功能。儘管顯示為分離之區塊,根據實施需求,操作1200之多個區塊可以劃分出額外之區塊,組合為更少之區塊,或者省略部分區塊。此外,操作1200之多個區塊/子區塊可以按照第12圖所示之順序來執行,或者也可以按照其它不同順序來執行。操作1200可以由通信系統1000及其任意變形來實施。例如,操作1200可以實施於第一裝置1005及/或第二裝置1050之中,或者由第一裝置1005及/或第二裝置1050來實施。僅用於說明目的而非限制發明之範圍,操作1200之說明在下文中以第一裝置1005之文字說明提供。操作1200可以在從區塊(步驟)1210開始。 Figure 12 is a schematic illustration of an example operation 1200 in accordance with an embodiment of the present invention. Operation 1200 may represent one aspect of implementing the various concepts and mechanisms provided by the present invention, such as those described in connection with some or all of Figures 1 through 9. More specifically, operation 1200 can represent orthogonal to hybrid The LDPC layer design and the extremely low bit rate QC-LDPC support one aspect of the various concepts and mechanisms proposed by the present invention. Operation 1200 can include one or more of the operations, actions, or functions illustrated by one or more of blocks 1210, 1220, and 1230. Although shown as separate blocks, depending on implementation requirements, multiple blocks of operation 1200 may divide additional blocks, combine into fewer blocks, or omit portions of the blocks. Moreover, the plurality of blocks/sub-blocks of operation 1200 may be performed in the order shown in FIG. 12, or may be performed in other different orders. Operation 1200 can be implemented by communication system 1000 and any variations thereof. For example, operation 1200 can be implemented in first device 1005 and/or second device 1050, or implemented by first device 1005 and/or second device 1050. The description of operation 1200 is provided below with the textual description of first device 1005 for illustrative purposes only and not for limiting the scope of the invention. Operation 1200 can begin at block (step) 1210.
在步驟1210中,操作1200可以包括:第一裝置1005之處理器1010產生一QC-LDPC碼,該QC-LDPC碼包含至少一類列正交層。操作1200可以從步驟1210前進至步驟1220。 In step 1210, operation 1200 can include the processor 1010 of the first device 1005 generating a QC-LDPC code, the QC-LDPC code including at least one type of column orthogonal layer. Operation 1200 can proceed from step 1210 to step 1220.
在步驟1220中,操作1200可以包括:處理器1010使用該QC-LDPC碼對資料進行編碼。操作1200可以從步驟1220前進至步驟1230。 In step 1220, operation 1200 can include the processor 1010 encoding the data using the QC-LDPC code. Operation 1200 can proceed from step 1220 to step 1230.
在步驟1230中,操作1200可以包括:處理器1010透過收發器1030發送編碼後之資料(例如,向第二裝置1050發送)。 In step 1230, operation 1200 can include the processor 1010 transmitting the encoded data (eg, to the second device 1050) via the transceiver 1030.
在一些實施方式中,該至少一類列正交層可以包括多個列與多個行之多個位元,該至少已類列正交層之該多個行之一個或多個行可以包括正交度為2或更高之至少一截斷行。該至少一類列正交層之該多個行之剩餘行可以包括正交度為1或0之非截斷行。 In some embodiments, the at least one type of column orthogonal layer may include a plurality of columns of a plurality of columns and a plurality of rows, and the one or more rows of the plurality of rows of the at least listed column orthogonal layer may include positive At least one truncated line with a degree of intersection of 2 or higher. The remaining rows of the plurality of rows of the at least one type of column orthogonal layer may include non-truncated rows having an orthogonality of 1 or 0.
在一些實施方式中,在多個截斷行內有可能沒有循環。 In some embodiments, there may be no loops within multiple truncated rows.
在一些實施方式中,QC-LDPC碼可以包括一混合正交設計,該混合正交設計具有不同正交度之多個部分。低正交度之該多個部分之一第一部分有 可能對應於一高碼率,高正交度之該多個部分之一第二部分有可能對應於一低碼率。 In some embodiments, the QC-LDPC code can include a hybrid orthogonal design having portions of different orthogonalities. One of the plurality of portions of low orthogonality has A second portion of the plurality of portions that may correspond to a high code rate, high orthogonality, may correspond to a low code rate.
在一些實施方式中,不同正交度之該多個部分包括下列一些或全部:(1)一非列正交部分,包括多個列與多個行,該多個列與該多個行形成至少一非列正交層;(2)一類列正交部分,包括多個列與多個行,該多個列與該多個行形成至少一類列正交層;以及(3)一純列正交層,包括多個列與多個行,該多個列與該多個行形成至少一純列正交層。該非列正交部分之該多個行可以包括正交度為2或更高之至少一截斷行與正交度為1或0之多個非截斷行。該類列正交部分之該多個行中之一個或多個行可以包括正交度為2或更高之至少一截斷行。該類列正交部分之該多個行之該多個剩餘行可以包括正交度為1或0之多個非截斷行。該純列正交部分之該多個行中之每行可以包括正交度為1或0之一行。 In some embodiments, the plurality of portions of different orthogonalities comprise some or all of the following: (1) a non-column orthogonal portion comprising a plurality of columns and a plurality of rows, the plurality of columns forming the plurality of rows At least one non-column orthogonal layer; (2) a type of column orthogonal portion comprising a plurality of columns and a plurality of rows, the plurality of columns forming at least one type of column orthogonal layer with the plurality of rows; and (3) a pure column The orthogonal layer includes a plurality of columns and a plurality of rows, and the plurality of columns and the plurality of rows form at least one pure column orthogonal layer. The plurality of rows of the non-column orthogonal portion may include at least one truncated row having an orthogonality of 2 or higher and a plurality of non-truncated rows having an orthogonality of 1 or 0. One or more of the plurality of rows of the orthogonal portion of the class of columns may include at least one truncated row having an orthogonality of 2 or higher. The plurality of remaining rows of the plurality of rows of the orthogonal portion of the column may include a plurality of non-truncated rows having an orthogonality of 1 or 0. Each of the plurality of rows of the pure column orthogonal portion may include one row having an orthogonality of 1 or 0.
在一些實施方式中,QC-LDPC碼可以包括一同位矩陣與一資訊矩陣,其中,該同位矩陣包含多個同位位元,該資訊矩陣包含多個資訊位元。該資訊矩陣與該同位矩陣中之一個或多個列可以包括每列位元正交度為2之一個或多個列。 In some embodiments, the QC-LDPC code can include a parity matrix and an information matrix, wherein the parity matrix includes a plurality of parity bits, and the information matrix includes a plurality of information bits. The information matrix and one or more columns in the co-located matrix may include one or more columns with a bit orthogonality of 2 per column.
在一些實施方式中,正交度為2之該一個或多個列之正交度為2之多個位元之每個位元可以包括一之前使用之同位位元或一之前發送之資訊位元。 In some embodiments, each of the plurality of bits having an orthogonality of 2 and the one or more columns having a degree of orthogonality of 2 may include a previously used parity bit or a previously transmitted information bit. yuan.
第13圖為根據本發明一實施方式之示例操作1300之示意圖。操作1300可以表示諸如與第1圖至第9圖之一些或全部有關之本發明所提出之多個概念與機制之一方面。更具體地,操作1300可以表示與核心矩陣設計有關之本發明所提出之多個概念與機制之一方面。操作1300可以包括如區塊1310、1320及1330中之一個或多個所示之一個或多個操作、動作或功能。儘管顯示為分離之區塊,根據實施需求,操作1300之多個區塊可以劃分出額外之區塊,組合為更少之區塊,或者省略部分區塊。此外,操作1300之多個區塊/子區塊可以按照第 13圖所示之順序來執行,或者也可以按照其它不同順序來執行。操作1300可以由通信系統1000及其任意變形來實施。例如,操作1300可以實施於第一裝置1005及/或第二裝置1050之中,或者由第一裝置1005及/或第二裝置1050來實施。僅用於說明目的而非限制發明之範圍,操作1300之說明在下文中以第一裝置1005之文字說明提供。操作1300可以在從區塊(步驟)1310開始。 Figure 13 is a schematic illustration of an example operation 1300 in accordance with an embodiment of the present invention. Operation 1300 may represent one of a number of concepts and mechanisms proposed by the present invention, such as related to some or all of Figures 1 through 9. More specifically, operation 1300 can represent one of a number of concepts and mechanisms proposed by the present invention related to core matrix design. Operation 1300 can include one or more operations, actions, or functions as illustrated by one or more of blocks 1310, 1320, and 1330. Although shown as separate blocks, depending on implementation requirements, multiple blocks of operation 1300 may divide additional blocks, combine into fewer blocks, or omit portions of the blocks. In addition, multiple blocks/subblocks of operation 1300 may be in accordance with The order shown in Figure 13 is performed, or it can be performed in other different orders. Operation 1300 can be implemented by communication system 1000 and any variations thereof. For example, operation 1300 can be implemented in first device 1005 and/or second device 1050, or implemented by first device 1005 and/or second device 1050. The description of operation 1300 is provided below with the textual description of first device 1005 for illustrative purposes only and not for limiting the scope of the invention. Operation 1300 can begin at block (step) 1310.
在步驟1310中,操作1300可以包括:第一裝置1005之處理器1010產生一QC-LDPC碼,該QC-LDPC碼包括一基礎矩陣,該基礎矩陣之一部分形成一核心矩陣,該核心矩陣對應於具有至少一門檻值之一碼率。操作1300可以從步驟1310前進至步驟1320。 In step 1310, operation 1300 may include: the processor 1010 of the first device 1005 generates a QC-LDPC code, the QC-LDPC code includes a basic matrix, and a portion of the basic matrix forms a core matrix, the core matrix corresponding to Has a code rate of at least one threshold. Operation 1300 can proceed from step 1310 to step 1320.
在步驟1320中,操作1300可以包括:處理器1010使用該QC-LDPC碼對資料進行編碼。操作1300可以從步驟1320前進至步驟1330。 In step 1320, operation 1300 can include the processor 1010 encoding the data using the QC-LDPC code. Operation 1300 can proceed from step 1320 to step 1330.
在步驟1330中,操作1300可以包括:處理器1010透過收發器1030發送編碼後之資料(例如,向第二裝置1050發送)。 In step 1330, operation 1300 can include the processor 1010 transmitting the encoded data (eg, to the second device 1050) via the transceiver 1030.
在一些實施方式中,該碼率可以為0.89。 In some embodiments, the code rate can be 0.89.
在一些實施方式中,該核心矩陣可以包括多個列與多個行之多個位元。該多個行中之兩個或更多個可以包括具有多個位元之一特定圖樣之多個截斷行。 In some embodiments, the core matrix can include multiple columns of multiple columns and multiple rows. Two or more of the plurality of rows may include a plurality of truncated rows having a particular pattern of one of the plurality of bits.
在一些實施方式中,在經過任意次數之行置換及/或列置換(例如,至少一次行置換、至少一次列置換、或二者之任意組合)後,該多個截斷行之多個位元之該特定圖樣可以在該多個截斷行內包括一個或多個位元0。在行置換及/或列置換後之包括一個或多個位元0之特定圖樣之兩個示例如第7圖之部分(A)所示。在一些實施方式中,該多個截斷行中之多個位元之該特定圖樣可以包括多個位元0之一等腰直角三角形,該三角形之一直角對應於該多個截斷行之一左上角處之一位元0。該多個位元0之一等腰直角三角形之一示例如第7圖之部分 (B)所示。 In some embodiments, after any number of row permutations and/or column permutations (eg, at least one row permutation, at least one column permutation, or any combination of the two), the plurality of truncated rows are separated by a plurality of bits The particular pattern can include one or more bits 0 within the plurality of truncated lines. Two examples of a particular pattern comprising one or more bits 0 after row permutation and/or column permutation are shown in part (A) of Figure 7. In some embodiments, the specific pattern of the plurality of bits in the plurality of truncated lines may include one of a plurality of bit 0 isosceles right triangles, and the right angle of the triangle corresponds to one of the plurality of truncated lines One of the bits at the corner is 0. One of the plurality of bits 0 is an example of an isosceles right triangle as shown in Figure 7 (B) is shown.
在一些實施方式中,核心矩陣可以包括一同位矩陣,該同位矩陣包括多個列與多個行之多個位元。該核心矩陣也可以包括一資訊矩陣,該資訊矩陣包括多個列與多個行之多個位元。該同位矩陣可以包括具有一Wi-Fi圖樣之一矩陣。除該核心矩陣之該多個截斷行之外,該資訊矩陣之多於一列位元可以包括具有高密度位元1而沒有或只有一個位元0之多個列。該高密度位元之該多個列可以對應於該Wi-Fi圖樣之多個列。 In some embodiments, the core matrix can include a co-located matrix that includes a plurality of columns of a plurality of columns and a plurality of rows. The core matrix may also include an information matrix comprising a plurality of columns of a plurality of columns and a plurality of rows. The parity matrix can include a matrix having a Wi-Fi pattern. In addition to the plurality of truncated lines of the core matrix, more than one column of the information matrix may include a plurality of columns having a high density bit 1 and no or only one bit 0. The plurality of columns of the high density bits may correspond to a plurality of columns of the Wi-Fi pattern.
在一些實施方式中,該多個列之多個位元之一底部列可以包括第一數量之位元1。該第一數量可以等於該多個截斷行之數量,或者比該多個截斷行之數量大1、2或3(例如,大一些)。在一些實施方式中,該底部列中之該第一數量之多個位元1可以對應於該多個截斷行與該核心矩陣之一最右側行,其中該核心矩陣與該Wi-Fi圖樣之一右側交接。 In some embodiments, the bottom column of one of the plurality of columns of the plurality of columns can include the first number of bits 1. The first number may be equal to the number of the plurality of truncated lines or greater than the number of the plurality of truncated lines by 1, 2 or 3 (eg, larger). In some embodiments, the first number of the plurality of bits 1 in the bottom column may correspond to the plurality of truncated lines and one of the rightmost rows of the core matrix, wherein the core matrix and the Wi-Fi pattern A right hand is handed over.
在一些實施方式中,該核心矩陣可以包括5列位元與20行位元。該20行位元之一VN度可以包括下列其中一個:[2,2,2,2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3],[2,2,2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3],[2,2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3]以及[2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3]。該5列位元之一檢測節點度可以包括下列其中一個::[13,10,14,17,2],[13,10,13,17,2],[13,10,13,18,3],[13,11,13,18,2],[13,10,14,18,2],[13,10,13,19,2],[14,10,13,18,1],[13,11,13,18,1],[13,10,14,18,1],[13,11,13,19,1],[13,10,13,18,2]以及[13,10,13,18,1]。 In some embodiments, the core matrix can include 5 columns of bits and 20 rows of bits. One of the 20 rows of VN degrees may include one of the following: [2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,3,3],[2,2,2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3],[ 2,2,2,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3] and [2,2,3,3, 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3]. One of the five columns of detection nodes may include one of the following:: [13, 10, 14, 17, 2], [13, 10, 13, 17, 2], [13, 10, 13, 18, 3], [13,11,13,18,2],[13,10,14,18,2],[13,10,13,19,2],[14,10,13,18,1] , [13,11,13,18,1],[13,10,14,18,1],[13,11,13,19,1],[13,10,13,18,2] and [ 13,10,13,18,1].
第14圖為根據本發明一實施方式之示例操作1400之示意圖。操作1400可以代表諸如與第9圖有關之說明之本發明所提出之多個概念與機制之一方面。更具體地,操作1400可以表示與移位參數設計有關之本發明所提出之多個概念與機制之一方面。操作1400可以包括如區塊1410、1420與1430以及子區 塊1412與1414中之一個或多個所示之一個或多個操作、動作或功能。儘管顯示為分離之區塊,根據實施需求,操作1400之多個區塊可以劃分出額外之區塊,組合為更少之區塊,或者省略部分區塊。此外,操作1400之多個區塊/子區塊可以按照第14圖所示之順序來執行,或者也可以按照其它不同順序來執行。操作1400可以由通信系統1000及其任意變形來實施。例如,操作1400可以實施於第一裝置1005及/或第二裝置1050之中,或者由第一裝置1005及/或第二裝置1050來實施。僅用於說明目的而非限制發明之範圍,操作1400之說明在下文中以第一裝置1005之文字說明提供。操作1400可以在從區塊(步驟)1410開始。 Figure 14 is a schematic illustration of an example operation 1400 in accordance with an embodiment of the present invention. Operation 1400 may represent one of a number of concepts and mechanisms proposed by the present invention, such as those described in connection with FIG. More specifically, operation 1400 can represent one of a number of concepts and mechanisms proposed by the present invention related to shift parameter design. Operation 1400 can include, for example, blocks 1410, 1420, and 1430, and sub-areas One or more of the operations, actions or functions illustrated by one or more of blocks 1412 and 1414. Although shown as separate blocks, depending on implementation requirements, multiple blocks of operation 1400 may divide additional blocks, combine into fewer blocks, or omit portions of the blocks. Moreover, the plurality of blocks/sub-blocks of operation 1400 may be performed in the order shown in FIG. 14, or may be performed in other different orders. Operation 1400 can be implemented by communication system 1000 and any variations thereof. For example, operation 1400 can be implemented in first device 1005 and/or second device 1050, or implemented by first device 1005 and/or second device 1050. The description of operation 1400 is provided below in the text of first device 1005 for illustrative purposes only and not for limiting the scope of the invention. Operation 1400 can begin at block (step) 1410.
在步驟1410中,操作1400可以包括:第一裝置1005之處理器1010產生一QC-LDPC碼。操作1400可以從步驟1410前進至步驟1420。 In step 1410, operation 1400 can include the processor 1010 of the first device 1005 generating a QC-LDPC code. Operation 1400 can proceed from step 1410 to step 1420.
在步驟1420中,操作1400可以包括:處理器1010使用該QC-LDPC碼對資料進行編碼。操作1400可以從步驟1420前進至步驟1430。 In step 1420, operation 1400 can include the processor 1010 encoding the data using the QC-LDPC code. Operation 1400 can proceed from step 1420 to step 1430.
在步驟1430中,操作1400可以包括:處理器1010透過收發器1030發送編碼後之資料(例如,向第二裝置1050)。 In step 1430, operation 1400 can include the processor 1010 transmitting the encoded data (e.g., to the second device 1050) via the transceiver 1030.
在產生該QC-LDPC碼時,操作1400可以包括:處理器1010執行子區塊(步驟)1412與1414所表示之多個操作。 In generating the QC-LDPC code, operation 1400 can include the processor 1010 performing a plurality of operations represented by the sub-blocks (steps) 1412 and 1414.
在步驟1412中,操作1400可以包括:處理器1010為多個擴展因子之一第一集合中之每個擴展因子產生各自之一移位值表,該移位值表包括多個移位值。操作1400可以從步驟1412前進至步驟1414。 In step 1412, operation 1400 can include the processor 1010 generating a respective one of a shift value table for each of the first set of the plurality of spread factors, the shift value table including a plurality of shift values. Operation 1400 can proceed from step 1412 to step 1414.
在步驟1414中,操作1400可以包括:處理器1010對該多個擴展因子之該第一集合進行優化以產生多個擴展因子之一第二集合。 In step 1414, operation 1400 can include the processor 1010 optimizing the first set of the plurality of spreading factors to generate a second set of the plurality of spreading factors.
該第一集合中多個擴展因子之一數量有可能大於該第二集合之多個擴展因子之一數量。存在於該第一集合但不存在於該第二集合中之一第一擴展因子可以共用同時存在於該第一集合與該第二集合中之一第二擴展因子之一移 位值表。該第二擴展因子可以在數值上小於該第一擴展因子,並相較於該第一集合中之其它擴展因子更加接近於該第一擴展因子。 The number of one of the plurality of spreading factors in the first set is likely to be greater than the number of one of the plurality of spreading factors of the second set. One of the first spreading factors present in the first set but not in the second set may share one of the second spreading factors present in the first set and the second set Bit value table. The second spreading factor may be numerically less than the first spreading factor and closer to the first spreading factor than other spreading factors in the first set.
補充說明 Supplementary explanation
此處所述之實質內容有時顯示為不同之組件,這些組件可以包含於或耦接於不同之其它組件。應當理解,此處所述之架構僅為舉例說明,事實上也可以實施為可實現相同功能之多種其它架構。在概念層面,可實現相同功能之任意排佈之多個組件進行有效「關聯(associated)」,以便實現所需之功能。因此,此處進行組合以實現特定功能之任意兩組件可視為彼此「有關聯」,以便實現所需之功能,而不論其架構或中間組件。類似地,如此關聯之任意兩組件也可以視為彼此「操作性連接(operably connected)」或「操作性耦接(operably coupled)」,以實現所需功能。操作性耦接之具體實施例包括但不僅限於實體濕式耦合(physically mateable)及/或實體交互(physically interacting)組件及/或無線可交互(wirelessly interactable)及/或無線交互(wirelessly interacting)組件及/或邏輯交互(logically interacting)及/或邏輯可交互(logically interactable)組件。 The substance described herein is sometimes shown as distinct components, which may be included or coupled to different other components. It should be understood that the architectures described herein are merely illustrative and may be implemented in various other architectures that perform the same functions. At the conceptual level, multiple components of any arrangement that perform the same function are effectively "associated" to achieve the desired functionality. Therefore, any two components herein combined to achieve a particular function can be seen as "associated" with each other to achieve the desired functionality, regardless of its architecture or intermediate components. Similarly, any two components so associated can also be considered as "operably connected" or "operably coupled" to each other to achieve the desired functionality. Specific embodiments of operative coupling include, but are not limited to, physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting components And/or logically interacting and/or logically interactable components.
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
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