TWI669716B - Memory storage apparatus and forming method of resistive memory device thereof - Google Patents
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Abstract
一種記憶體儲存裝置及其電阻式記憶體元件成型方法。對冗餘電阻式記憶體元件施加測試成型電壓，並讀取對應的測試電流。依據測試成型電壓、測試電流、成型電流電壓特性資料以及目標成型電流決定施加於主記憶體晶胞區塊的成型電壓。A memory storage device and a resistive memory element forming method thereof. Apply a test forming voltage to the redundant resistive memory device and read the corresponding test current. The molding voltage applied to the main memory cell block is determined according to the test molding voltage, the test current, the molding current voltage characteristic data, and the target molding current.
Description
本發明是有關於一種記憶體裝置，且特別是有關於一種電阻式記憶體儲存裝置及其電阻式記憶體元件的成型方法。The present invention relates to a memory device, and more particularly to a resistive memory storage device and a method of forming the same.
近年來電阻式記憶體（諸如電阻式隨機存取記憶體（Resistive Random Access Memory，RRAM））的發展極為快速，是目前最受矚目之未來記憶體的結構。由於電阻式記憶體具備低功耗、高速運作、高密度以及相容於互補式金屬氧化物半導體（Complementary Metal Oxide Semiconductor，CMOS）製程技術之潛在優勢，因此非常適合作為下一世代之非揮發性記憶體元件。對可靠度測試以及商業化而言，電阻式記憶體元件的高溫資料保持能力（High Temperature Data Retention，HTDR）具有決定性的影響。在現有技術中，為了改善高溫資料保持能力，或有利用調整製程、演算法修正或電性參數調整來達到此一目的，但仍有相當大的努力空間。In recent years, resistive memory (such as Resistive Random Access Memory (RRAM)) has developed extremely rapidly and is currently the most attractive structure of future memory. Resistive memory is ideal for low-power, high-speed operation, high density, and compatibility with Complementary Metal Oxide Semiconductor (CMOS) process technology, making it ideal for next generation non-volatile Memory component. For reliability testing and commercialization, the High Temperature Data Retention (HTDR) of resistive memory components has a decisive influence. In the prior art, in order to improve the high-temperature data retention capability, or to adjust the process, algorithm correction or electrical parameter adjustment to achieve this purpose, there is still considerable room for effort.
RRAM是一種非揮發性記憶體，其中的RRAM單元各自包括上電極板、下電極板、及夾在上、下電極板之間的介電材料層。介電材料層通常是絕緣的，而透過在上電極板上施加合適電壓以對記憶胞進行成型操作（forming operation），可在介電材料層中形成穿過介電材料層的導電路徑（通常稱為導電絲（conductive filament，CF））。The RRAM is a non-volatile memory in which the RRAM cells each include an upper electrode plate, a lower electrode plate, and a dielectric material layer sandwiched between the upper and lower electrode plates. The layer of dielectric material is typically insulating, and by applying a suitable voltage to the upper electrode plate to perform a forming operation on the memory cell, a conductive path through the layer of dielectric material can be formed in the layer of dielectric material (typically It is called a conductive filament (CF).
形成導電絲後，便可透過在上電極板上施加適當的電壓對其進行重置操作（reset operation），令導電絲斷開，導致在RRAM單元上出現高阻值狀態（high resistance state，HRS）。之後，可再透過在上電極板上施加適當的電壓對RRAM單元進行設定操作（set operation），重新形成導電絲，導致在RRAM單元上出現低阻值狀態（low resistance state，LRS）。透過反覆的設定操作及重置操作，可控制RRAM的阻值狀態(LRS或HRS)，LRS和HRS可用於指示“0”或“1”的數位信號，從而提供相關的記憶體功能。After the conductive wire is formed, a reset operation can be performed by applying an appropriate voltage on the upper electrode plate to disconnect the conductive wire, resulting in a high resistance state (HRS) on the RRAM cell. ). Thereafter, the RRAM cell can be set operation by applying an appropriate voltage to the upper electrode plate to reform the conductive wire, resulting in a low resistance state (LRS) on the RRAM cell. The RRAM resistance state (LRS or HRS) can be controlled by repeated set operations and reset operations. The LRS and HRS can be used to indicate a digital signal of "0" or "1" to provide associated memory functions.
在現有技術中，由於RRAM的製程及所使用的材料日新月異，因此如何快速而有效地找出適當的操作條件已是RRAM開發過程中相當重要的一項議題。若採用了不佳的操作條件，很可能造成在測試的過程中誤判材料的相關因素，進而影響RRAM的開發時程及效能。由於成型操作是決定導電絲態樣的關鍵步驟，因此，具體找出適當的成型操作的電壓範圍，將有利於形成較佳的導電絲，從而提供良好的導電路徑。In the prior art, since the process of the RRAM and the materials used are changing with each passing day, how to find the proper operating conditions quickly and effectively has become a very important issue in the RRAM development process. If poor operating conditions are used, it is likely to cause factors related to the material misjudgment during the test, which will affect the development time and performance of the RRAM. Since the forming operation is a critical step in determining the conductive filament pattern, it is advantageous to find a suitable voltage range for the molding operation to form a preferred conductive filament, thereby providing a good conductive path.
本發明提供一種記憶體儲存裝置及其電阻式記憶體元件成型方法，可針對每一晶粒(die)的導電絲成型電壓進行最佳化，以得到最佳的高溫資料保持能力（High Temperature Data Retention，HTDR）。The invention provides a memory storage device and a resistive memory element forming method thereof, which can optimize the forming voltage of the conductive wire for each die to obtain the optimal high temperature data retention capability (High Temperature Data) Retention, HTDR).
本發明的記憶體儲存裝置包括記憶體晶胞陣列以及記憶體控制電路。記憶體晶胞陣列包括主記憶體晶胞區塊以及冗餘記憶體晶胞區塊。主記憶體晶胞區塊包括多個以陣列方式排列的電阻式記憶體元件。冗餘記憶體晶胞區塊包括多個以陣列方式排列的冗餘電阻式記憶體元件。記憶體控制電路耦接記憶體晶胞陣列，對至少一冗餘電阻式記憶體元件施加測試成型電壓，並讀取對應的測試電流，依據測試成型電壓、測試電流、成型電流電壓特性資料以及目標成型電流決定施加於主記憶體晶胞區塊的成型電壓。The memory storage device of the present invention includes a memory cell array and a memory control circuit. The memory cell array includes a main memory cell block and a redundant memory cell block. The main memory cell block includes a plurality of resistive memory elements arranged in an array. The redundant memory cell block includes a plurality of redundant resistive memory elements arranged in an array. The memory control circuit is coupled to the memory cell array, applies a test forming voltage to at least one redundant resistive memory component, and reads a corresponding test current according to the test forming voltage, the test current, the forming current voltage characteristic data, and the target. The molding current determines the molding voltage applied to the main memory cell block.
在本發明的一實施例中，上述的記憶體控制電路包括成型控制電路、成型電壓產生器以及成型電流感測電路。成型電壓產生器耦接成型控制電路以及記憶體陣列，受控於成型控制電路而產生測試成型電壓以及成型電壓。成型電流感測電路耦接成型控制電路以及記憶體陣列，讀取測試電流，以產生測試電流信號至成型控制電路，成型控制電路依據測試成型電壓、測試電流信號、成型電流電壓特性資料以及目標成型電流決定成型電壓，並控制成型電壓產生器對主記憶體晶胞區塊施加成型電壓。In an embodiment of the invention, the memory control circuit includes a molding control circuit, a molding voltage generator, and a molding current sensing circuit. The molding voltage generator is coupled to the molding control circuit and the memory array, and is controlled by the molding control circuit to generate a test molding voltage and a molding voltage. The molding current sensing circuit is coupled to the molding control circuit and the memory array, and reads the test current to generate a test current signal to the molding control circuit. The molding control circuit is formed according to the test forming voltage, the test current signal, the molding current voltage characteristic data, and the target molding. The current determines the forming voltage and controls the forming voltage generator to apply a forming voltage to the main memory cell block.
本發明還提供一種記憶體儲存裝置的電阻式記憶體元件成型方法，記憶體儲存裝置包括記憶體陣列，記憶體晶胞陣列包括主記憶體晶胞區塊以及冗餘記憶體晶胞區塊，電阻式記憶體元件成型方法包括下列步驟。對至少一冗餘電阻式記憶體元件施加測試成型電壓，並讀取對應的測試電流。依據測試成型電壓、測試電流、成型電流電壓特性資料以及目標成型電流決定施加於主記憶體晶胞區塊的成型電壓。將成型電壓施加於主記憶體晶胞區塊。The invention also provides a resistive memory component forming method for a memory storage device, the memory storage device comprising a memory array, the memory cell array comprising a main memory cell block and a redundant memory cell block, The resistive memory element forming method includes the following steps. A test forming voltage is applied to at least one of the redundant resistive memory elements and a corresponding test current is read. The molding voltage applied to the main memory cell block is determined according to the test molding voltage, the test current, the molding current voltage characteristic data, and the target molding current. A molding voltage is applied to the main memory cell block.
基於上述，本發明的實施例透過先對至少一冗餘電阻式記憶體元件施加測試成型電壓，並讀取對應的測試電流，然後再依據測試成型電壓、測試電流、成型電流電壓特性資料以及目標成型電流來決定施加於主記憶體晶胞區塊的成型電壓。如此便可針對每一晶粒形成導電絲所使用的成型電壓進行最佳化，以得到最佳的高溫資料保持能力。Based on the above, the embodiment of the present invention first applies a test forming voltage to at least one redundant resistive memory device, and reads a corresponding test current, and then according to the test forming voltage, the test current, the forming current voltage characteristic data, and the target. The molding current determines the molding voltage applied to the main memory cell block. In this way, the molding voltage used for forming the conductive filaments for each of the crystal grains can be optimized to obtain an optimum high-temperature data retention capability.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
以下提出多個實施例來說明本發明，然而本發明不僅限於所例示的多個實施例。又實施例之間也允許有適當的結合。在本申請說明書全文(包括申請專利範圍)中所使用的「耦接」一詞可指任何直接或間接的連接手段。舉例而言，若文中描述第一裝置耦接於第二裝置，則應該被解釋成該第一裝置可以直接連接於該第二裝置，或者該第一裝置可以透過其他裝置或某種連接手段而間接地連接至該第二裝置。此外，「訊號」一詞可指至少一電流、電壓、電荷、溫度、資料、電磁波或任何其他一或多個訊號。The invention is illustrated by the following examples, but the invention is not limited to the illustrated embodiments. Further combinations are also allowed between the embodiments. The term "coupled" as used throughout the specification (including the scope of the claims) may be used in any direct or indirect connection. For example, if the first device is described as being coupled to the second device, it should be construed that the first device can be directly connected to the second device, or the first device can be connected through other devices or some kind of connection means. Connected to the second device indirectly. In addition, the term "signal" may refer to at least one current, voltage, charge, temperature, data, electromagnetic wave or any other one or more signals.
圖1是依照本發明一實施例之記憶體儲存裝置的概要示意圖。本實施例之記憶體儲存裝置包括記憶體控制電路102以及記憶體晶胞陣列104。記憶體晶胞陣列104耦接至記憶體控制電路102。記憶體晶胞陣列104包括主記憶體晶胞區塊106以及冗餘記憶體晶胞區塊108，記憶體儲存裝置可例如為電阻式隨機存取記憶體（resistive random access memory，RRAM）裝置。其中主記憶體晶胞區塊106包括多個以陣列方式排列的電阻式記憶體元件(未繪示)，冗餘記憶體晶胞區塊108包括多個以陣列方式排列的冗餘電阻式記憶體元件(未繪示)。1 is a schematic diagram of a memory storage device in accordance with an embodiment of the present invention. The memory storage device of this embodiment includes a memory control circuit 102 and a memory cell array 104. The memory cell array 104 is coupled to the memory control circuit 102. The memory cell array 104 includes a main memory cell block 106 and a redundant memory cell block 108. The memory storage device can be, for example, a resistive random access memory (RRAM) device. The main memory cell block 106 includes a plurality of resistive memory elements (not shown) arranged in an array, and the redundant memory cell block 108 includes a plurality of redundant resistive memories arranged in an array. Body element (not shown).
記憶體控制電路102可對主記憶體晶胞區塊106以及冗餘記憶體晶胞區塊108中的電阻式記憶體元件進行成型程序（forming procedure）。成型程序是指對電阻式記憶體元件進行初始化的過程。在此過程中，電阻式記憶體元件兩端的電極持續被施加偏壓，以對介電層產生一個外加電場。當外加電場超過臨界值時，介電層會發生介電崩潰現象而產生導電絲，從而由高阻態（High Resistance State，HRS）轉變為低阻態（Low Resistance State，LRS）。此種崩潰並非永久，介電層的阻值仍可依據後續所施加的電壓而被改變。The memory control circuit 102 can perform a forming procedure on the resistive memory elements in the main memory cell block 106 and the redundant memory cell block 108. The molding process refers to the process of initializing a resistive memory component. During this process, the electrodes at both ends of the resistive memory element are continuously biased to create an applied electric field to the dielectric layer. When the applied electric field exceeds the critical value, a dielectric breakdown occurs in the dielectric layer to generate a conductive filament, thereby changing from a High Resistance State (HRS) to a Low Resistance State (LRS). This breakdown is not permanent and the resistance of the dielectric layer can still be changed depending on the voltage applied subsequently.
進一步來說，本實施例的記憶體控制電路102在進行成型程序時，可先對冗餘記憶體晶胞區塊108中的冗餘電阻式記憶體元件施加測試成型電壓，自位元線讀取對應的測試電流，並依據測試成型電壓、測試電流、成型電流電壓特性資料以及目標成型電流決定施加於主記憶體晶胞區塊106中的電阻式記憶體元件的成型電壓。詳細而言，本實施例的記憶體控制電路102可具有根據主記憶體晶胞區塊106所需達到的目標成型電流所設定的成型電流電壓特性資料，用以指示測試成型電壓、測試電流與成型電壓間的關係。其中成型電流電壓特性資料可例如包括成型電流電壓特性曲線或成型電流電壓特性查找表，成型電流電壓特性曲線、成型電流電壓特性查找表以及目標成型電流視記憶體儲存裝置的製程或電路設計方式可能有所不同，但對於具有相同製程的電路設計方式的記憶體儲存裝置則具有相近的特性。Further, the memory control circuit 102 of the present embodiment may first apply a test forming voltage to the redundant resistive memory device in the redundant memory cell block 108 during the molding process, and read the self-bit line. The corresponding test current is taken, and the forming voltage of the resistive memory element applied to the main memory cell block 106 is determined according to the test molding voltage, the test current, the molding current voltage characteristic data, and the target molding current. In detail, the memory control circuit 102 of the present embodiment may have molding current voltage characteristic data set according to a target molding current required by the main memory cell block 106 to indicate a test forming voltage, a test current, and The relationship between the forming voltages. The molding current voltage characteristic data may include, for example, a molding current voltage characteristic curve or a molding current voltage characteristic lookup table, a molding current voltage characteristic curve, a molding current voltage characteristic lookup table, and a process or circuit design manner of the target molding current depending memory storage device. The difference is different, but the memory storage device with the same process design has similar characteristics.
在一些實施例中，可利用成型電流電壓特性曲線來決定成型電壓。舉例來說，成型電流電壓特性曲線可例如為具有預設斜率的直線，在本實施例中預設斜率可例如為17，形成導電絲最佳的目標成型電流可例如為31μA，然不以此為限。當記憶體控制電路102對冗餘記憶體晶胞區塊108中的冗餘電阻式記憶元件施加1.9V的測試成型電壓後，若所讀取到的測試電流為25μA，則施加於主記憶體晶胞區塊106的成型電壓將等於1.9+(31-25)/17=2.253V。以此類推，若所讀取到的測試電流為27μA，則施加於主記憶體晶胞區塊106的成型電壓將等於1.9+(31-27)/17=2.135V。其中測試成型電壓及成型電壓可包括閘極電壓以及汲極電壓，本實施例為以閘極電壓的計算進行說明，汲極電壓也可以相同的方式進行最佳化，在此不再贅述。In some embodiments, the molding current voltage characteristic can be utilized to determine the molding voltage. For example, the molding current voltage characteristic curve may be, for example, a straight line having a preset slope. In the present embodiment, the preset slope may be, for example, 17, and the target forming current for forming the conductive filament may be, for example, 31 μA, but not Limited. When the memory control circuit 102 applies a test forming voltage of 1.9 V to the redundant resistive memory element in the redundant memory cell block 108, if the read test current is 25 μA, it is applied to the main memory. The forming voltage of the cell block 106 will be equal to 1.9 + (31 - 25) / 17 = 2.253V. By analogy, if the read current is 27 μA, the forming voltage applied to the main memory cell block 106 will be equal to 1.9+(31-27)/17=2.135V. The test forming voltage and the forming voltage may include a gate voltage and a drain voltage. In this embodiment, the gate voltage is calculated, and the drain voltage may be optimized in the same manner, and details are not described herein.
在其他實施例中，也可利用查表的方式來決定成型電壓。舉例來說，表1為成型電流電壓特性查找表的一實施例，其指示根據施加於冗餘記憶體元件的測試成型電壓以及讀取到的測試電流，主記憶體晶胞區塊106要達到目標成型電流時，所需施加的成型電壓。 測試成型電壓 測試電流 成型電壓 1.9 V 31μA 1.90 V 30μA 1.96 V 29μA 2.02 V 28μA 2.08 V 27μA 2.14 V 26μA 2.19 V 25μA 2.25 V 24μA 2.31 V 23μA 2.37 V 22μA 2.43 V 21μA 2.49 V 表1 In other embodiments, the look-up voltage can also be determined by means of a look-up table. For example, Table 1 is an embodiment of a molded current voltage characteristic lookup table indicating that the main memory cell block 106 is to be reached based on the test molding voltage applied to the redundant memory device and the read test current. The molding voltage to be applied when the target is shaping current. Test forming voltage Test current Forming voltage 1.9 V 31μA 1.90 V 30μA 1.96 V 29μA 2.02 V 28μA 2.08 V 27μA 2.14 V 26μA 2.19 V 25μA 2.25 V 24μA 2.31 V 23μA 2.37 V 22μA 2.43 V 21μA 2.49 V Table 1
如表1所示，記憶體控制電路102可先將固定的測試成型電壓施加於冗餘電阻式記憶體元件，再依據自冗餘電阻式記憶體元件讀取到的測試電流來決定主記憶體晶胞區塊106的成型電壓，如此可不需如上述實施例依據成型電流電壓特性曲線進行成型電壓的計算，而可節省運算資源。例如當測試電流為24μA時，可直接查表得知其對應的成型電壓為2.31 V。As shown in Table 1, the memory control circuit 102 can first apply a fixed test molding voltage to the redundant resistive memory component, and then determine the main memory according to the test current read from the redundant resistive memory component. The forming voltage of the cell block 106 can eliminate the need to calculate the forming voltage according to the forming current-voltage characteristic curve as in the above embodiment, thereby saving computational resources. For example, when the test current is 24μA, the corresponding forming voltage can be directly found to be 2.31 V.
在部分實施例中，為確保測試電流的準確性，記憶體控制電路102依據自多個冗餘電阻式記憶體元件讀取出的測試電流值來計算用於估測成型電壓的測試電流，例如可將多個冗餘電阻式記憶體元件的中位數電流值作為估測成型電壓的測試電流，亦或是將多個冗餘電阻式記憶體元件的測試電流平均值作為估測成型電壓的測試電流。In some embodiments, to ensure the accuracy of the test current, the memory control circuit 102 calculates a test current for estimating the molding voltage based on the test current value read from the plurality of redundant resistive memory elements, for example, The median current value of the plurality of redundant resistive memory components can be used as the test current for estimating the molding voltage, or the average of the test currents of the plurality of redundant resistive memory components can be used as the estimated forming voltage. Test current.
如上所述，本實施例的記憶體儲存裝置可藉由對冗餘記憶體晶胞區塊108進行成型程序來推測出對主記憶體晶胞區塊106施加的成型電壓的電壓值，以最佳化導電絲的形成，提高記憶體儲存裝置的高溫資料保持能力，而增加記憶體儲存裝置的可靠性。此外，利用本實施例的導電絲成型程序，可針對每一晶粒形成導電絲所使用的成型電壓各自進行最佳化，如此可改善晶粒間變異(die-to-die variation)或晶圓間變異(wafer-to-wafer variation)所造成的導電絲缺陷的問題。As described above, the memory storage device of the present embodiment can estimate the voltage value of the molding voltage applied to the main memory cell block 106 by performing a molding process on the redundant memory cell block 108. The formation of the conductive wire improves the high temperature data retention capability of the memory storage device and increases the reliability of the memory storage device. In addition, by using the conductive wire forming program of the present embodiment, the forming voltages used for forming the conductive filaments for each of the crystal grains can be optimized, thereby improving die-to-die variation or wafer. The problem of conductive wire defects caused by wafer-to-wafer variation.
值得注意的是，在部分實施例中，記憶體控制電路102在對主記憶體晶胞區塊106施加成型電壓後，可判斷對應的成型電流是否已達到目標成型電流，若未達到目標成型電流，記憶體控制電路102可再對主記憶體晶胞區塊106施加成型電壓直到成型電流達到目標成型電流。It should be noted that, in some embodiments, after the forming voltage is applied to the main memory cell block 106, the memory control circuit 102 can determine whether the corresponding molding current has reached the target molding current, and if the target molding current is not reached. The memory control circuit 102 can then apply a forming voltage to the main memory cell block 106 until the forming current reaches the target forming current.
圖2是依照本發明另一實施例之記憶體儲存裝置的概要示意圖。進一步來說，圖1實施例的記憶體控制電路102可包括成型控制電路202、成型電壓產生器204以及成型電流感測電路206，成型電壓產生器204耦接成型控制電路202以及記憶體晶胞陣列104，成型電流感測電路206耦接成型控制電路202以及記憶體晶胞陣列104。其中成型控制電路202可控制成型電壓產生器204產生上述的測試成型電壓至記憶體晶胞陣列104中的冗餘記憶體晶胞區塊。成型電流感測電路206則可讀取對應測試成型電壓的測試電流而產生測試電流信號，並將測試電流信號傳送給成型控制電路202。成型控制電路202可依據測試成型電壓、測試電流信號、成型電流電壓特性資料以及目標成型電流決定成型電壓，並控制成型電壓產生器對主記憶體晶胞區塊106施加成型電壓。其中成型控制電路202決定成型電壓的細節實施方式與上述實施例相同，因此在此不再贅述。2 is a schematic diagram of a memory storage device in accordance with another embodiment of the present invention. Further, the memory control circuit 102 of the embodiment of FIG. 1 may include a molding control circuit 202, a molding voltage generator 204, and a molding current sensing circuit 206. The molding voltage generator 204 is coupled to the molding control circuit 202 and the memory unit cell. The array 104, the molding current sensing circuit 206 is coupled to the molding control circuit 202 and the memory cell array 104. The molding control circuit 202 can control the molding voltage generator 204 to generate the above-mentioned test molding voltage to the redundant memory cell block in the memory cell array 104. The molding current sensing circuit 206 can read the test current corresponding to the test molding voltage to generate a test current signal, and transmit the test current signal to the molding control circuit 202. The molding control circuit 202 can determine the molding voltage according to the test molding voltage, the test current signal, the molding current voltage characteristic data, and the target molding current, and control the molding voltage generator to apply a molding voltage to the main memory cell block 106. The detailed implementation manner in which the molding control circuit 202 determines the molding voltage is the same as that in the above embodiment, and therefore will not be described herein.
圖3是依照本發明一實施例之記憶體儲存裝置的電阻式記憶體元件成型方法的流程圖。由上述實施例可知，記憶體儲存裝置的電阻式記憶體元件成型方法可至少包括下列步驟。首先，對至少一冗餘電阻式記憶體元件施加測試成型電壓，並讀取對應的測試電流(步驟S302)，其中測試成型電壓包括閘極電壓以及汲極電壓。接著，依據測試成型電壓、測試電流、成型電流電壓特性資料以及目標成型電流決定施加於主記憶體晶胞區塊的成型電壓(步驟S304)，其中成型電流電壓特性資料可例如包括成型電流電壓特性曲線或成型電流電壓特性查找表，成型電流電壓特性曲線可例如為具有預設斜率的直線，成型電流電壓特性查找表可指示為達到目標成型電流，測試成型電壓以及測試電流所對應的成型電壓。此外測試電流可例如將多個冗餘電阻式記憶體元件的中位數電流值作為估測成型電壓的測試電流，亦或是將多個冗餘電阻式記憶體元件的測試電流平均值作為估測成型電壓的測試電流。最後，再將估測出的成型電壓施加於主記憶體晶胞區塊的電阻式記憶體元件(步驟S306)。3 is a flow chart of a method of forming a resistive memory device of a memory storage device in accordance with an embodiment of the present invention. It can be seen from the above embodiments that the resistive memory element forming method of the memory storage device can include at least the following steps. First, a test forming voltage is applied to at least one of the redundant resistive memory elements, and a corresponding test current is read (step S302), wherein the test forming voltage includes a gate voltage and a drain voltage. Then, the molding voltage applied to the main memory cell block is determined according to the test molding voltage, the test current, the molding current voltage characteristic data, and the target molding current (step S304), wherein the molding current voltage characteristic data may include, for example, molding current voltage characteristics. The curve or the shaped current voltage characteristic lookup table may be, for example, a straight line having a preset slope, and the shaped current voltage characteristic lookup table may indicate the target forming current, the test forming voltage, and the forming voltage corresponding to the test current. In addition, the test current can be, for example, the median current value of the plurality of redundant resistive memory components as the test current for estimating the molding voltage, or the average of the test currents of the plurality of redundant resistive memory components. Test current for forming voltage. Finally, the estimated molding voltage is applied to the resistive memory element of the main memory cell block (step S306).
綜上所述，本發明的實施例藉由對冗餘記憶體晶胞區塊進行成型程序來推測出對主記憶體晶胞區塊施加的成型電壓的電壓值，以最佳化導電絲的形成，提高記憶體儲存裝置的高溫資料保持能力，而增加記憶體儲存裝置的可靠性，且由於一般記憶體陣列中皆會包括冗餘記憶體晶胞區塊，因此並不會有增加電路面積的問題。此外，利用上述實施例的導電絲成型程序針對每一晶粒形成導電絲所使用的成型電壓進行最佳化，可有效改善晶粒間變異或晶圓間變異所造成的導電絲缺陷的問題。In summary, the embodiment of the present invention infers the voltage value of the molding voltage applied to the main memory cell block by modeling the redundant memory cell block to optimize the conductive wire. Forming, improving the high temperature data retention capability of the memory storage device, increasing the reliability of the memory storage device, and since the memory array is included in the general memory array, there is no increase in circuit area. The problem. Further, by using the conductive wire forming program of the above embodiment, the molding voltage used for forming the conductive filaments for each of the crystal grains is optimized, and the problem of the conductive filament defects caused by the inter-die variation or the inter-wafer variation can be effectively improved.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
102‧‧‧記憶體控制電路102‧‧‧Memory Control Circuit
104‧‧‧記憶體晶胞陣列 104‧‧‧Memory cell array
106‧‧‧主記憶體晶胞區塊 106‧‧‧Main memory cell block
108‧‧‧冗餘記憶體晶胞區塊 108‧‧‧Redundant memory cell block
202‧‧‧成型控制電路 202‧‧‧Molding control circuit
204‧‧‧成型電壓產生器 204‧‧‧Formed voltage generator
206‧‧‧成型電流感測電路 206‧‧‧Formed current sensing circuit
S302~S306‧‧‧步驟 S302~S306‧‧‧Steps
圖1是依照本發明實施例的一種記憶體儲存裝置的示意圖。 圖2是依照本發明另一實施例的一種記憶體儲存裝置的示意圖。 圖3是依照本發明實施例的一種記憶體儲存裝置的電阻式記憶體元件成型方法流程圖。1 is a schematic diagram of a memory storage device in accordance with an embodiment of the present invention. 2 is a schematic diagram of a memory storage device in accordance with another embodiment of the present invention. 3 is a flow chart of a method for forming a resistive memory device of a memory storage device in accordance with an embodiment of the invention.
Claims (11)
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