TWI667728B - 晶片接合裝置、晶片接合的方法以及晶片封裝結構 - Google Patents

晶片接合裝置、晶片接合的方法以及晶片封裝結構 Download PDF

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Publication number
TWI667728B
TWI667728B TW106137307A TW106137307A TWI667728B TW I667728 B TWI667728 B TW I667728B TW 106137307 A TW106137307 A TW 106137307A TW 106137307 A TW106137307 A TW 106137307A TW I667728 B TWI667728 B TW I667728B
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Taiwan
Prior art keywords
wafer
circuit structure
positioning
redistribution circuit
pick
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TW106137307A
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English (en)
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TW201917813A (zh
Inventor
Shu-Wei Kuo
郭書瑋
Wei-Yuan Cheng
鄭惟元
Shau-Fei Cheng
鄭少斐
Original Assignee
Industrial Technology Research Institute
財團法人工業技術研究院
Intellectual Property Innovation Corporation
創智智權管理顧問股份有限公司
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Application filed by Industrial Technology Research Institute, 財團法人工業技術研究院, Intellectual Property Innovation Corporation, 創智智權管理顧問股份有限公司 filed Critical Industrial Technology Research Institute
Priority to TW106137307A priority Critical patent/TWI667728B/zh
Priority to CN201711269385.1A priority patent/CN109727889A/zh
Priority to US15/856,065 priority patent/US10366965B2/en
Publication of TW201917813A publication Critical patent/TW201917813A/zh
Application granted granted Critical
Publication of TWI667728B publication Critical patent/TWI667728B/zh

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Abstract

一種晶片接合裝置，適於將晶片與重佈線路結構彼此接合。晶片接合裝置包括取放模組以及定位模組。取放模組適於拾取以及放置晶片。定位模組可移動地連接至取放模組。定位模組包括至少一定位凸起，其中至少一定位凸起朝向重佈線路結構所包括的至少一定位凹槽延伸。此外，一種用於晶片接合的方法以及晶片封裝結構亦被提出。

Description

晶片接合裝置、晶片接合的方法以及晶片封裝結構
本發明的實施例是有關於一種晶片接合裝置、晶片接合的方法以及晶片封裝結構。
在高度情報化社會的今日，各種電子裝置的市場不斷地急速擴張著。晶片封裝技術亦需配合電子裝置的數位化、網路化、區域連接化以及使用人性化的趨勢發展。為達成上述的要求，必須強化電子元件的高速處理化、多功能化、積集(integration)化、小型輕量化及低價化等多方面的要求，於是晶片封裝技術也跟著朝向微型化、高密度化發展。其中，覆晶(flip-cip)接合技術由於係以凸塊(bump)與線路基板接合，較習知導線連結(wire bonding)法大幅縮短了配線長度，有助晶片與承載器間訊號傳遞速度的提昇，因此已漸成為高密度封裝的主流。
一般而言，在覆晶接合的製程中，主要是利用線路基板上的反光點(fiducial mark)進行光學對位。然而，對於具有高腳 數及/或高密度排列的晶片常需有較高的對位精度(alignment accuracy)。因此，如何進一步提升覆晶接合製程的對位精度進而提升產品的良率(yield)，實已成目前亟欲解決的課題。
本發明一實施例提供一種晶片接合裝置，其可以提升晶片接合製程的對位精度進而提升產品的良率。
本發明一實施例提供一種晶片接合的方法，其具有較佳的良率。
本發明一實施例提供一種晶片封裝結構，其具有較佳的良率。
本發明一實施例的晶片接合裝置，適於將晶片與重佈線路結構彼此接合，晶片接合裝置包括取放模組以及定位模組。取放模組適於拾取以及放置晶片。定位模組可移動地連接至取放模組。定位模組包括至少一定位凸起，其中至少一定位凸起朝向重佈線路結構所包括的至少一定位凹槽延伸。
本發明一實施例提供一種晶片接合的方法，其包括以下步驟。提供前述的晶片接合裝置。以晶片接合裝置的取放模組拾取晶片。將晶片接合裝置移動至重佈線路結構上方，以使被取放模組拾取的晶片與重佈線路結構之間具有間距。將至少一定位凸起對準重佈線路結構的至少一定位凹槽。令拾取晶片的取放模組朝向重佈線路結構移動，以使晶片與重佈線路結構彼此電性連接。
本發明一實施例的晶片封裝結構，其包括晶片、重佈線路結構、底膠以及密封體。重佈線路結構電性連接至晶片，且重佈線路結構包括與晶片不重疊的至少一凹槽。底膠位於晶片與重佈線路結構之間。密封體包覆晶片、重佈線路結構以及底膠，其中密封體與底膠至少其中一者填充於至少一凹槽。
本發明一實施例的晶片封裝結構，其包括晶片、重佈線路結構、底膠以及密封體。重佈線路結構電性連接至晶片，且重佈線路結構包括至少一方位辨識(orientation recognition)標記。底膠位於晶片與重佈線路結構之間。密封體包覆晶片、重佈線路結構以及底膠，其中密封體與底膠至少其中一者覆蓋至少一方位辨識標記。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
100、700、800‧‧‧晶片接合裝置
100’‧‧‧晶片接合單元
110‧‧‧取放模組
110a‧‧‧取放面
111‧‧‧取放部
112‧‧‧軸部
113‧‧‧通氣孔
120‧‧‧定位模組
121‧‧‧滑移構件
122‧‧‧感壓裝置
123‧‧‧定位構件
124、724‧‧‧定位凸起
124a‧‧‧折腳部分
724b‧‧‧定位凸點
125‧‧‧光學感測器
200、300、400、500‧‧‧晶片封裝結構
210‧‧‧晶片
210a‧‧‧主動面
210b‧‧‧晶背表面
211‧‧‧接觸墊
212‧‧‧保護層
230a‧‧‧第一導電端子
220、920‧‧‧重佈線路結構
220a、920a‧‧‧晶片連接面
220b‧‧‧晶片接合區
220c‧‧‧定位區
222‧‧‧介電層
223‧‧‧導電層
230b‧‧‧第二導電端子
221、321、421、521‧‧‧定位凹槽
221a‧‧‧折腳溝渠
221b、421b、521b‧‧‧凹槽側壁
221c‧‧‧凹槽深度
230‧‧‧導電連接件
240‧‧‧底膠
241‧‧‧黏著材料
242‧‧‧填料
242a‧‧‧粒徑
250‧‧‧密封體
d1‧‧‧第一間距
d2‧‧‧第二間距
R1‧‧‧第一區域
R2‧‧‧第二區域
R3‧‧‧邊緣區域
圖1A是依照本發明的第一實施例的晶片接合裝置的側視示意圖。
圖1B是圖1A的晶片接合裝置的底視示意圖。
圖2A、圖2B、圖2D至圖2H是依照本發明的第一實施例的晶片接合的方法的剖面示意圖。
圖2C是圖2B的晶片接合的方法中的重佈線路結構的上視示 意圖。
圖3是依照本發明的第二實施例的晶片封裝結構的局部剖面示意圖。
圖4是依照本發明的第三實施例的晶片封裝結構的局部剖面示意圖。
圖5是依照本發明的第四實施例的晶片封裝結構的局部剖面示意圖。
圖6A是依照本發明的一實施例的晶片封裝結構的局部剖面示意圖。
圖6B是圖6A中區域R2的放大圖。
圖7是依照本發明的第五實施例的晶片接合裝置的底視示意圖。
圖8是依照本發明的第六實施例的晶片接合裝置的底視示意圖。
圖9是依照本發明的第七實施例的晶片接合的方法中的重佈線路結構的上視示意圖。
圖1A是依照本發明的第一實施例的晶片接合裝置的側視示意圖。圖1B是圖1A的晶片接合裝置的底視示意圖。晶片接合裝置100包括取放模組110以及定位模組120，以適於將晶片210(繪示於圖2A)與重佈線路結構220(繪示於圖2B)彼此接 合，且可在晶片210與重佈線路結構220接合的過程中將晶片210定位至欲與重佈線路結構220彼此接合的區域。詳細的晶片接合的方法將於後續的段落中描述。
取放模組110可以包括彼此相連的取放部111以及軸部112。軸部112可以與定位模組120連接，且可使定位模組120沿著軸部112上下滑移。如圖1B所示，取放部111相對於軸部112的取放面110a具有多個通氣孔113。在取放模組110拾取或移動晶片210的過程中可以對通氣孔113進行抽氣，以使通氣孔113內的氣壓小於環境的氣壓，而使晶片210可以被吸取而固定在取放部111的取放面110a上。在放置晶片210的過程中可以對通氣孔113進行通氣，以使通氣孔113內的氣壓大於或等於環境的氣壓，而使晶片210在被放置於欲放置的區域(如：對應的重佈線路結構220上)之後與取放部111彼此分離。在一些實施例中，通氣孔113也可以進行氣體清洗(air purge)，以在晶片210接合的過程中維持良好的潔淨度(cleanliness)。
定位模組120可以包括滑移(Slip)構件121、感壓裝置(force Sensor)122以及定位構件123。滑移構件121例如可以為移動地連接至軸部112的離合器、卷盤或滑移齒輪，以使定位模組120可以沿著軸部112的延伸方向滑移至預定的位置之後，再使定位模組120固定於軸部112。感壓裝置122配置於滑移構件121與定位構件123之間。感壓裝置122可以包括壓電材料、應變規(Strain Gauge)等類似的壓力感測器，以在定位模組120進行 對準的過程中可用於接收外力源，且可以在接收外力源之後輸出對應的感測訊號。定位構件123可以包括至少一個定位凸起124，其中定位凸起124的凸出方向可以與取放面110a所面對的方向相同。如此一來，定位構件123可以藉由凸出的定位凸起124以在放置晶片210的過程中進行對準(alignment)，以提升放置晶片210的過程中的對位精度，進而提升晶片接合過程的良率。
在本實施例中，定位凸起124的可以為多個彼此分離的凸起結構，但本發明不限於此。在其他實施例中，定位凸起124可以為環繞取放模組110的環形凸起結構。
在本實施例中，定位凸起124可以是以非點對稱(non-point symmetry)的方式設置。舉例而言，如圖1B所示，在一平行於取放面110a的虛擬平面(如：紙面)上，定位凸起124所對應的圖案不會具有對稱點(symmetric point)。如此一來，可以在放置晶片210的過程中進行方位辨識(orientation recognition)，以降低晶片210放置的過程中錯位、反向或轉向的可能。
在一些實施例中，定位凸起124可以包括類似於L形的折腳部分124a，以降低在放置晶片210的過程中被取放模組110拾取的晶片210與重佈線路結構220之間產生相對旋轉的可能。
在本實施例中，定位構件123可以更包括圍繞定位凸起124的光學感測器125。光學感測器125例如由感光耦合元件(Charge-Coupled Device；CCD)、互補性氧化金屬半導體 (Complementary Metal-Oxide Semiconductor；CMOS)或其他適宜的感光元件所構成的距離感測器(proximity sensor)。在晶片210放置的過程之前，可以先藉由光學感測器125進行光學(如：雷射或紅外光)掃描或光學偵測，以確認晶片210放置的位置；或是在晶片210放置的過程中，藉由光學掃描或光學偵測，以同時進行晶片210放置的位置的修正或校正。
圖2A、圖2B、圖2D至圖2H是依照本發明的第一實施例的晶片接合的方法的剖面示意圖。圖2C是圖2B的晶片接合的方法中的重佈線路結構的上視示意圖。值得注意的是，本實施例中的晶片接合的方法可以是藉由圖1A及圖1B中所繪示的晶片接合裝置來進行，故類似的構件以相同的標號表示，且具有類似的功能，並省略描述。
晶片接合的方法可以包括以下步驟。首先，提供晶片接合裝置100。在本實施例中，可以藉由圖1A中所繪示的晶片接合裝置100來進行晶片接合，但本發明不限於此。在其他實施例中，也可以藉由類似的晶片接合裝置來進行晶片接合。
接著，請參照圖2A，以所述晶片接合裝置100的取放模組110拾取晶片210。
在本實施例中，晶片210可以具有彼此相對的主動面(active surface)210a以及晶背表面(backside surface)210b。晶片210的主動面210a上可以包括接觸墊(contact pad)211、保護層(passivation layer)212以及第一導電端子230a。接觸墊211 例如為鋁墊、銅墊或其他適宜的金屬墊。保護層212的材質例如為氧化矽、氮化矽或其他適宜的絕緣、阻水及/或阻氣材質。第一導電端子230a例如為導電柱、導電凸塊、焊料或上述之組合。第一導電端子230a可以位於保護層212的開口上，且可以藉由接觸墊211與晶片210的內連線(interconnection)電性連接。
在本實施例中，可以先將晶片接合裝置100移動至晶片210的晶背表面210b上方。接著，可以藉由對通氣孔113(繪示於圖1B)進行抽氣，以使通氣孔113內的氣壓小於環境的氣壓，而使取放部111的取放面110a與晶片210的晶背表面210b相接觸，且使晶片210可以被固定於取放部111的取放面110a上。
接著，請參照圖2B，在晶片210被晶片接合裝置100的取放模組110拾取之後，將已拾取晶片210的晶片接合裝置100移動至重佈線路結構220上方。被取放模組110拾取的晶片210與重佈線路結構220之間具有第一間距d1，以避免在定位之前晶片210與重佈線路結構220相接觸，而降低晶片210及/或重佈線路結構220因不預期地接觸而產生受損的可能性。在覆晶接合製程中，第一間距d1通常指的是晶片210上最接近重佈線路結構220的構件(如：晶片210上的第一導電端子230a)與重佈線路結構220上最接近晶片210的構件(如：重佈線路結構220上的第二導電端子230b)之間的最短距離。
請同時參照圖2B以及圖2C。重佈線路結構220的晶片連接面220a上具有晶片接合區220b以及圍繞晶片接合區220b的 定位區220c。
在本實施例中，重佈線路結構220可以包括至少一定位凹槽221、多個介電層222、多個導電層223以及多個第二導電端子230b。導電層223以及介電層222可以彼此交互堆疊，且不同的導電層223之間可以藉由介電層222中的導通孔(through via)而彼此電性連接。第二導電端子230b位於晶片連接面220a上且位於晶片接合區220b內。定位凹槽221位於定位區220c內且自介電層222的表面向內凹陷。定位凹槽221可以是未貫穿重佈線路結構220的盲孔及/或溝渠，且定位凹槽221未暴露出重佈線路結構220內的任何可用於信號傳遞的導電元件(如：用於信號傳遞的導電層223及/或導通孔)。
在本實施例中，重佈線路結構220的定位凹槽221可以與定位模組120的定位凸起124彼此對應分佈。也就是說，定位凹槽221可以是多個彼此分離盲孔及/或凹槽，也可以是環繞晶片接合區220b的環形溝渠。並且，定位凹槽221可以是以非點對稱的方式配置。換句話說，定位凹槽221可以作為方位辨識標記(orientation recognition mark)，而可以用於方位辨識。除此之外，定位凹槽221可以包括L形的折腳溝渠221a。定位凹槽221的折腳溝渠221a可以對應於定位凸起124的折腳部分124a，以降低在放置晶片210的過程中晶片210與重佈線路結構220之間產生相對旋轉的可能。
在本實施例中，定位凹槽221的凹槽側壁221b與晶片連 接面220a垂直，但本發明不限於此。
在本實施例中，定位凹槽221的凹槽深度221c為大於或等於3微米(micrometer；μm)，但本發明不限於此。
在本實施例中，定位凹槽221與晶片接合區220b之間具有第二間距d2，且第二間距d2小於或等於10微米，但本發明不限於此。
接著，請參照圖2D，將已拾取晶片210的晶片接合裝置100的定位凸起124對準重佈線路結構220的定位凹槽221。舉例而言，可使定位模組120沿著軸部112向重佈線路結構220滑移。若定位凸起124接觸至定位凹槽221且確認晶片210放置的位置正確時，感壓裝置122可以接收因接觸所產生的對應反作用力，並傳送出對應的感測訊號，以驅使定位模組120沿著軸部112向遠離於重佈線路結構220的方向滑移，而可以進行晶片210放置步驟。相反地，若定位凸起124未與定位凹槽221相接觸及/或確認晶片210放置的位置不正確時，感壓裝置122可以傳送出另一對應的感測訊號，以不僅驅使定位模組120沿著軸部112向遠離於重佈線路結構220的方向滑移，也可以驅使已拾取晶片210的晶片接合裝置100沿著平行於晶片連接面220a的方向移動，以進行再一次的定位校正。
在一些實施例中，在確認晶片210被放置的位置正確之後，可以在令定位模組120沿著軸部112向遠離於重佈線路結構220的方向滑移之後，再進行晶片210的放置步驟。
在一些實施例中，在確認晶片210被放置的位置正確之後，可以在令定位模組120沿著軸部112向遠離於重佈線路結構220的方向滑移的同時，一併進行晶片210的放置步驟。
在一些實施例中，可以藉由光學感測器125對晶片連接面220a進行快速掃描，以在進行晶片210的放置步驟之前，先確認晶片210被放置的位置。
在一些實施例中，可以藉由光學感測器125對晶片連接面220a進行快速掃描，以在進行晶片210的放置步驟的同時，持續地確認晶片210被放置的位置。舉例而言，在進行晶片210的放置步驟的同時，若光學感測器125偵測到晶片210被放置的位置有所偏移，則可以中止(stop)或暫停(pause)晶片210的放置步驟，且令已拾取晶片210的晶片接合裝置100沿著平行於晶片連接面220a的方向移動，以進行再一次的定位校正。
在一些實施例中，光學感測器125可以對位於晶片連接面220a上的定位凹槽221進行掃描。舉例而言，光學感測器125可以掃描定位凹槽221的圖案及/或深度。由於定位凹槽221與晶片210放置區具有固定的相對位置關係，因此可以藉由掃描定位凹槽221以確認晶片210被放置的位置。
接著，請參照圖2E，令拾取晶片210的取放模組110朝向重佈線路結構220移動，以進行晶片210的放置步驟。具體而言，可以令拾取晶片210的取放模組110朝向重佈線路結構220移動，以使位於晶片210上的第一導電端子230a直接接觸位於重 佈線路結構220上的第二導電端子230b，而使晶片210與重佈線路結構220藉由第一導電端子230a以及第二導電端子230b而彼此電性連接。
接著，請參照圖2F，可以藉由高週波加熱(high-frequency induction hardening)、迴焊(reflow)、熱風加熱等適宜的焊接製程，以使第一導電端子230a以及第二導電端子230b熔接，以形成連接於晶片210以及重佈線路結構220之間的導電連接件230。在形成導電連接件230之後，可以令電性連接至重佈線路結構220的晶片210與取放模組110彼此分離。值得注意的是，為了維持晶片210與重佈線路結構220彼此之間連接的穩定性(stability)，可以依據製程上的需求也可以在形成導電連接件230之後及其後續任意的步驟之後，再令電性連接至重佈線路結構220的晶片210與取放模組110彼此分離。
接著，請參照圖2G，可以在晶片210以及重佈線路結構220之間形成底膠(underfill)240。底膠240可以覆蓋晶片210的主動面210a、重佈線路結構220的部分晶片連接面220a以及位於晶片210與重佈線路結構220之間的導電連接件230，以提升晶片210與重佈線路結構220彼此之間連接的穩定性。在一些實施例中，底膠240可以降低濕氣或氧氣直接接觸晶片210的主動面210a以及導電連接件230的可能，以維持晶片210與重佈線路結構220之間的良好導電性。一般而言，底膠240可以包含黏著材料241(繪示於圖6B)以及填料(filler)242(繪示於圖6B)，填 料242分佈於黏著材料241中且彼此分離。黏著材料241例如為矽膠、環氧樹脂(epoxy)或其他適宜的聚合物。填料242例如為金屬粒子、金屬氧化物粒子、碳粒或其他適宜的填充粒子，以提升底膠240的黏著力。除此之外，填料242也可以為導熱粒子，以提升底膠240的導熱性。
在本實施例中，底膠240填充於至少一個定位凹槽221內，以降低底膠240自重佈線路結構220的晶片連接面220a剝離(peeling)的可能。具體而言，請同時參照圖6A以及圖6B，圖6A是依照本發明的一實施例的晶片封裝結構200的局部剖面示意圖，圖6B是圖6A中第二區域R2的放大圖。詳細而言，圖6A所繪示為底膠240直接覆蓋於重佈線路結構220的晶片連接面220a上，且未填充於定位凹槽221內的區域的剖面示意圖。在圖6B中，在重佈線路結構220的晶片連接面220a上，於介電層222以及底膠240相接觸的邊緣區域R3，由於在區域R3中底膠240的厚度小於填料242的粒徑242a，而使填料242無法分佈於邊緣區域R3的黏著材料241內。因此，相較於填充於定位凹槽221內的部分底膠240，位於邊緣區域R3內的底膠240較容易造成剝離的可能。在本實施例中，由於至少部分的底膠240填充於定位凹槽221內而可穩固地連接於重佈線路結構220，因此縱使部分的區域(如：邊緣區域R3)較容易造成剝離，但也不會造成底膠240自重佈線路結構220的晶片連接面220a上完全剝離。如此一來，在晶片210的接合過程中，也可以使良率提升。
接著，請參照圖2H，可以在重佈線路結構220的晶片連接面220a上形成密封體250，以覆蓋重佈線路結構220、底膠240以及晶片210。一般而言，密封體250可以是藉由模塑製程(molding process)所形成的模塑化合物(molding compound)。在一些實施例中，密封體250可以是由例如是環氧樹脂或其他適宜樹脂等絕緣材料所形成。
在本實施例中，密封體250覆蓋於晶片210的晶背表面210b上，但本發明不限於此。在其他的實施例中，密封體250可以暴露出晶片210的晶背表面210b。
在本實施例中，密封體250未填充於定位凹槽221，但本發明不限於此。在其他實施例中，密封體250可以部分填充於定位凹槽221。
經過上述製程後即可大致上完成本實施例的晶片封裝結構200的製作。如圖2H所示，即為本發明的第一實施例的晶片封裝結構的剖面示意圖。上述的晶片封裝結構200包括晶片210、重佈線路結構220、底膠240以及密封體250。晶片210的主動面210a與重佈線路結構220的晶片連接面220a彼此面對，且晶片210與重佈線路結構220可以藉由導電連接件230而彼此電性連接。重佈線路結構220包括位於晶片連接面220a上的至少一凹槽(即為定位凹槽221)。定位凹槽221可以於晶片210接合的過程中作為方位辨識標記，且定位凹槽221與晶片210不重疊。底膠240位於晶片210與重佈線路結構220之間，且底膠240至少填充於部分 的定位凹槽221內。密封體250包覆晶片210、重佈線路結構220以及底膠240。
在本實施例中，定位凹槽221的數量可以是多個且彼此分離，且多個定位凹槽221所構成的圖案環繞晶片210，但本發明不限於此。在其他實施例中，定位凹槽221可以為環繞晶片210的環形凹槽。
在本實施例中，定位凹槽221是以非點對稱的方式配置。換句話說，在一平行於晶片連接面220a的虛擬平面(如：於圖2C中的紙面)上，定位凹槽221所構成的對應圖案不會具有對稱點。
圖3是依照本發明的第二實施例的晶片封裝結構的局部剖面示意圖，且圖3中對晶片封裝結構300所繪示的局部區域為對應於圖2H中對晶片封裝結構200所繪示的第一區域R1。請參考圖3，在本實施例中，晶片封裝結構300與晶片封裝結構200相似，其類似的構件以相同的標號表示，且具有類似的功能，並省略描述。而晶片封裝結構300與晶片封裝結構200的主要差別在於：底膠240以及密封體250可以填充於同一個定位凹槽321。
圖4是依照本發明的第三實施例的晶片封裝結構的局部剖面示意圖，且圖4中對晶片封裝結構400所繪示的局部區域為對應於圖2H中對晶片封裝結構200所繪示的第一區域R1。請參考圖4，在本實施例中，晶片封裝結構400與晶片封裝結構200相似，其類似的構件以相同的標號表示，且具有類似的功能，並省略描述。而晶片封裝結構400與晶片封裝結構200的主要差別 在於：定位凹槽421的凹槽側壁421b與重佈線路結構220的晶片連接面220a不垂直。在本實施例中，密封體250未填充於定位凹槽421，但本發明不限於此。在其他實施例中，密封體250可以部分填充於定位凹槽421。
圖5是依照本發明的第四實施例的晶片封裝結構的局部剖面示意圖，且圖5中對晶片封裝結構500所繪示的局部區域為對應於圖2H中對晶片封裝結構200所繪示的第一區域R1。請參考圖5，在本實施例中，晶片封裝結構500與晶片封裝結構200相似，其類似的構件以相同的標號表示，且具有類似的功能，並省略描述。而晶片封裝結構500與晶片封裝結構200的主要差別在於：在定位凹槽521的凹槽側壁521b與重佈線路結構220的晶片連接面220a之間的介電層222具有圓角(round corner)。在本實施例中，密封體250未填充於定位凹槽521，但本發明不限於此。在其他實施例中，密封體250可以部分填充於定位凹槽521。
圖7是依照本發明的第五實施例的晶片接合裝置的底視示意圖。請參考圖7，在本實施例中，晶片接合裝置700與晶片接合裝置100相似，其類似的構件以相同的標號表示，且具有類似的功能，並省略描述。而晶片接合裝置700與晶片接合裝置100的主要差別在於：定位模組120的定位凸起724為環繞取放模組110的環形凸起。
在本實施例中，定位凸起724可以具有至少一個定位凸點724b，以使定位凸起724可以是以非點對稱的方式設置。
圖8是依照本發明的第六實施例的晶片接合裝置的底視示意圖。請參考圖8，在本實施例中，晶片接合裝置800與晶片接合裝置100相似，其類似的構件以相同的標號表示，且具有類似的功能，並省略描述。而晶片接合裝置800與晶片接合裝置100的主要差別在於：晶片接合裝置800可以包括多個晶片接合單元100’。單一個晶片接合單元100’可以類似於晶片接合裝置100。也就是說，單一個晶片接合單元100’可以具有各自的取放模組110以及定位模組120。多個晶片接合單元100’可以藉由機構裝置或訊號控制而彼此連動(linkage)，以提升製程上的生產量(throughput)。在本實施例中，晶片接合單元100’的數量是以四個為例且為陣列(array)排列，但本發明不限於此。
圖9是依照本發明的第七實施例的晶片接合的方法中的重佈線路結構的上視示意圖。請參考圖8，在本實施例中，重佈線路結構920與重佈線路結構220相似，其類似的構件以相同的標號表示，且具有類似的功能，並省略描述。而重佈線路結構920與重佈線路結構220的主要差別在於：在重佈線路結構920的晶片連接面920a上具有多個晶片接合區220b。各個晶片接合區220b具有對應的多個第二導電端子230b以及至少一個定位凹槽221，而可以與多個晶片210彼此接合且於接合過程中進行定位。
在本實施例中，在晶片210與重佈線路結構920彼此接合之後，可以進行單一化製程(如：切割製程)，以形成類似於圖2H所示具有單一個晶片210的晶片封裝結構。
綜上所述，本發明一實施例的晶片接合裝置，其具有至少一定位凸起，而可以提升晶片接合製程的對位精度進而提升產品的良率。本發明一實施例的晶片接合方法是藉由具有至少一定位凸起的晶片接合裝置將晶片結合至具有少一個定位凹槽的重佈線路結構上，因而在晶片接合製程中具有較佳的精度且具有較佳的良率。本發明一實施例的晶片封裝結構，其具有少一個定位凹槽的重佈線路結構，且密封體與底膠至少其中一者填充於定位凹槽，因此在製造過程上可以具有較佳的精度，且產品具有較佳的良率。
雖然本揭露已以實施例揭露如上，然其並非用以限定本揭露，任何所屬技術領域中具有通常知識者，在不脫離本揭露的精神和範圍內，當可作些許的更動與潤飾，故本揭露的保護範圍當視後附的申請專利範圍所界定者為準。

Claims (20)

  1. 一種晶片接合裝置，適於將晶片與重佈線路結構彼此接合，且所述晶片接合裝置包括： 取放模組，適於拾取以及放置所述晶片；以及 定位模組，可移動地連接至所述取放模組，且所述定位模組包括至少一定位凸起，其中所述至少一定位凸起朝向所述重佈線路結構所包括的至少一定位凹槽延伸。
  2. 如申請專利範圍第1項所述的晶片接合裝置，其中所述定位模組更包括位於所述取放模組與所述至少一定位凸起之間的感壓裝置。
  3. 如申請專利範圍第1項所述的晶片接合裝置，其中所述定位模組更包括圍繞所述至少一定位凸起以及所述取放模組的光學感測器。
  4. 如申請專利範圍第1項所述的晶片接合裝置，其中在所述取放模組取放所述晶片的方向上，所述至少一定位凸起與所述取放模組不重疊。
  5. 如申請專利範圍第1項所述的晶片接合裝置，其中所述至少一定位凸起包括彼此分離的多個定位凸起。
  6. 如申請專利範圍第1項所述的晶片接合裝置，其中所述至少一定位凸起包括環繞所述取放模組的至少一環形凸起。
  7. 如申請專利範圍第1項所述的晶片接合裝置，其中所述至少一定位凸起對應於所述至少一定位凹槽分佈。
  8. 如申請專利範圍第1項所述的晶片接合裝置，其中所述至少一定位凹槽以非點對稱的方式配置。
  9. 一種晶片接合的方法，包括： 提供如申請專利範圍第1項所述的晶片接合裝置； 以所述晶片接合裝置的取放模組拾取晶片； 將所述晶片接合裝置移動至所述重佈線路結構上方，以使被所述取放模組拾取的所述晶片與所述重佈線路結構之間具有間距； 將所述至少一定位凸起對準所述重佈線路結構的至少一定位凹槽；以及 令拾取所述晶片的所述取放模組朝向所述重佈線路結構移動，以使所述晶片與所述重佈線路結構彼此電性連接。
  10. 如申請專利範圍第9項所述的晶片接合的方法，其中將所述至少一定位凸起對準所述至少一定位凹槽的步驟包括： 令所述定位模組朝向所述重佈線路結構移動，以使朝向所述重佈線路結構延伸的所述至少一定位凸起嵌入所述至少一定位凹槽。
  11. 如申請專利範圍第9項所述的晶片接合的方法，其中所述定位模組更包括光學感測器，且將所述至少一定位凸起對準所述至少一定位凹槽的步驟包括藉由所述光學感測器對準。
  12. 如申請專利範圍第11項所述的晶片接合的方法，其中將所述至少一定位凸起對準所述重佈線路結構的至少一定位凹槽的步驟是在令拾取所述晶片的所述取放模組朝向所述重佈線路結構移動的步驟之前進行。
  13. 如申請專利範圍第11項所述的晶片接合的方法，其中將所述至少一定位凸起對準所述重佈線路結構的至少一定位凹槽的步驟是與令拾取所述晶片的所述取放模組朝向所述重佈線路結構移動的步驟同時進行。
  14. 如申請專利範圍第9項所述的晶片接合的方法，更包括：令電性連接至所述重佈線路結構的所述晶片與所述取放模組彼此分離。
  15. 一種晶片封裝結構，包括： 晶片； 重佈線路結構，電性連接至所述晶片，且所述重佈線路結構包括與所述晶片不重疊的至少一凹槽； 底膠，位於所述晶片與所述重佈線路結構之間；以及 密封體，包覆所述晶片、所述重佈線路結構以及所述底膠，其中所述密封體與所述底膠至少其中一者填充於所述至少一凹槽。
  16. 如申請專利範圍第15項所述的晶片封裝結構，其中所述至少一凹槽以非點對稱的方式配置。
  17. 如申請專利範圍第15項所述的晶片封裝結構，其中所述至少一凹槽為未貫穿所述重佈線路結構的盲孔及/或溝渠。
  18. 一種晶片封裝結構，包括： 晶片； 重佈線路結構，電性連接至所述晶片，且所述重佈線路結構包括至少一方位辨識標記； 底膠，位於所述晶片與所述重佈線路結構之間；以及 密封體，包覆所述晶片、所述重佈線路結構以及所述底膠，其中所述密封體與所述底膠至少其中一者覆蓋所述至少一方位辨識標記。
  19. 如申請專利範圍第18項所述的晶片封裝結構，其中所述至少一方位辨識標記為位於所述重佈線路結構面對所述晶片的表面上。
  20. 如申請專利範圍第18項所述的晶片封裝結構，其中所述至少一方位辨識標記為自所述重佈線路結構的表面向內延伸的凹陷。
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