TWI665878B

TWI665878B - Polar code generating method, and electronic device and non-transitory computer-readable storage medium therefor

Info

Publication number: TWI665878B
Application number: TW107104653A
Authority: TW
Inventors: 黃昱銘; 施智懷; 李祥邦; 張錫嘉
Original assignee: 旺宏電子股份有限公司
Priority date: 2018-02-09
Filing date: 2018-02-09
Publication date: 2019-07-11
Also published as: TW201935861A

Abstract

一種極化碼產生方法，包括步驟如下：建立多個極化矩陣，該些極化矩陣經由多個第一輸入通道接收多個第一輸入位元，並透過多個第一輸出通道提供多個第一輸出位元；從該些極化矩陣的該些第一輸入通道中，挑選至少一待強化輸入通道；提供再極化矩陣，再極化矩陣經由多個第二輸入通道接收多個第二輸入位元，並透過多個第二輸出通道提供多個第二輸出位元，該些第二輸出位元中的一部分係作為提供至待強化輸入通道的第一輸出位元；提供極化碼，極化碼包括該些第一輸出位元以及該些第二輸出位元中非作為第一輸出位元的剩餘部分。 A method for generating a polarization code includes the following steps: establishing a plurality of polarization matrices, the plurality of polarization matrices receiving a plurality of first input bits through a plurality of first input channels, and providing a plurality of first input channels through a plurality of first output channels; A first output bit; selecting at least one input channel to be strengthened from the first input channels of the polarization matrices; providing a repolarization matrix, and the repolarization matrix receives a plurality of first input channels via a plurality of second input channels; Two input bits, and a plurality of second output bits are provided through a plurality of second output channels, and some of the second output bits are used as the first output bits provided to the input channel to be enhanced; The polarized code includes the first output bits and the remaining portions of the second output bits that are not the first output bits.

Description

極化碼產生方法及應用其的電子裝置及非暫態電腦可讀取儲存媒體 Method for generating polar code and electronic device and non-transitory electricity using same Brain-readable storage media

本揭露是關於一種極化碼產生方法及應用其的電子裝置及非暫態電腦可讀取儲存媒體。 This disclosure relates to a method for generating a polar code, an electronic device using the same, and a non-transitory computer-readable storage medium.

極化碼(polar code)是一種改良的錯誤更正碼。極化碼的編碼機制主要是利用極化矩陣，將輸入位元通道極化成相對可靠的位元通道以及相對不可靠的位元通道。可靠的位元通道可用來傳輸資料位元(information bit)，而不可靠的位元通道則是用來傳輸凍結位元(frozen bit)。只要極化碼的長度(chunk size)足夠長，可確保無損地傳輸資料位元。換言之，當極化碼的長度增加，可讓錯誤率趨近於0。 Polar code is an improved error correction code. The encoding mechanism of a polar code is mainly to use a polarization matrix to polarize an input bit channel into a relatively reliable bit channel and a relatively unreliable bit channel. Reliable bit channels are used to transmit information bits, while unreliable bit channels are used to transmit frozen bits. As long as the chunk size is long enough, data bits can be transmitted losslessly. In other words, as the length of the polarization code increases, the error rate approaches zero.

目前極化碼的碼長往往需限制在2的冪次方，導致系統複雜度的增加。另外，輸入位元通道的可靠度排序深受極化轉換的輸出通道的狀態影響。一旦輸出通道發生變化，即便採取相同的極化矩陣，輸入位元通道的可靠度排序也將隨之變動。一旦誤用較不可靠的位元通道來傳輸資料位元，將導致錯誤更正的性能降低。 At present, the code length of a polarization code is often limited to a power of 2, which leads to an increase in system complexity. In addition, the reliability ordering of the input bit channels is greatly affected by the state of the output channels of polarization conversion. Once the output channel changes, even with the same polarization moment Array, the reliability order of the input bit channel will also change accordingly. Misuse of a less reliable bit channel to transmit data bits will result in reduced performance for error correction.

本揭露是關於一種極化碼產生方法及應用其的電子裝置及非暫態電腦可讀取儲存媒體。根據本揭露實施例，處理器可設置多個極化矩陣，並針對該些極化矩陣中特定的輸入位元通道進行再極化，以改善通道可靠度。另外，因為再極化程序，本揭露的極化碼的碼長將不受2的冪次方的限制，進而降低系統設計的複雜度。 This disclosure relates to a method for generating a polar code, an electronic device using the same, and a non-transitory computer-readable storage medium. According to the embodiment of the present disclosure, the processor may set a plurality of polarization matrices, and perform repolarization on specific input bit channels in the polarization matrices to improve channel reliability. In addition, because of the repolarization procedure, the code length of the polarized code disclosed in this disclosure will not be limited by the power of two, thereby reducing the complexity of system design.

根據一實施例，提出一種極化碼產生方法，其可由包括處理器的電子裝置執行，並包括步驟如下：建立多個極化矩陣，該些極化矩陣經由多個第一輸入通道接收多個第一輸入位元，並對該些第一輸入位元進行第一極化編碼，以透過多個第一輸出通道提供多個第一輸出位元；從該些極化矩陣的該些第一輸入通道中，挑選至少一待強化輸入通道；提供再極化矩陣，再極化矩陣經由多個第二輸入通道接收多個第二輸入位元，並對該些第二輸入位元進行第二極化編碼，以透過多個第二輸出通道提供多個第二輸出位元，該些第二輸出位元中的一部分係作為提供至待強化輸入通道的第一輸出位元；提供極化碼，極化碼包括該些第一輸出位元以及該些第二輸出位元中的剩餘部分。 According to an embodiment, a method for generating a polarization code is proposed, which can be executed by an electronic device including a processor, and includes the steps of: establishing a plurality of polarization matrices, the plurality of polarization matrices receiving a plurality of A first input bit, and performing first polarization encoding on the first input bits to provide a plurality of first output bits through a plurality of first output channels; from the first of the polarization matrices, Among the input channels, at least one input channel to be strengthened is selected; a repolarization matrix is provided, and the repolarization matrix receives a plurality of second input bits through a plurality of second input channels, and performs a second operation on the second input bits. Polarization encoding to provide a plurality of second output bits through a plurality of second output channels, and a part of the second output bits is used as a first output bit provided to the input channel to be strengthened; a polarization code is provided The polarization code includes the first output bits and the remaining portions of the second output bits.

根據一實施例，提出一種非暫態電腦可讀取儲存媒體(non-transitory computer-readable storage medium)，其儲存可供處理器執行的一或多個指令，以使包括處理器的電子裝置執行步驟如下：建立多個極化矩陣，該些極化矩陣經由多個第一輸入通道接收多個第一輸入位元，並對該些第一輸入位元進行第一極化編碼，以透過多個第一輸出通道提供多個第一輸出位元；從該些極化矩陣的該些第一輸入通道中，挑選至少一待強化輸入通道；提供再極化矩陣，再極化矩陣經由多個第二輸入通道接收多個第二輸入位元，並對該些第二輸入位元進行第二極化編碼，以透過多個第二輸出通道提供多個第二輸出位元，該些第二輸出位元中的一部分係作為提供至待強化輸入通道的第一輸出位元；提供極化碼，極化碼包括該些第一輸出位元以及該些第二輸出位元中的剩餘部分。 According to an embodiment, a non-transitory computer-readable storage medium is provided. Storing one or more instructions for execution by the processor, so that the electronic device including the processor performs the following steps: establishing a plurality of polarization matrices that receive a plurality of first inputs via a plurality of first input channels And perform first polarization coding on the first input bits to provide multiple first output bits through multiple first output channels; from the first input channels of the polarization matrices , Select at least one input channel to be strengthened; provide a repolarization matrix, the repolarization matrix receives multiple second input bits through multiple second input channels, and performs second polarization encoding on the second input bits To provide a plurality of second output bits through a plurality of second output channels, and a part of the second output bits is used as a first output bit provided to the input channel to be strengthened; a polarization code is provided, and polarization is provided The code includes the first output bits and the remainder of the second output bits.

根據一實施例，提出一種電子裝置，其包括記憶體以及處理器。記憶體儲存至少一指令。處理器耦接記憶體，並執行該至少一指令而實施步驟如下：建立多個極化矩陣，該些極化矩陣經由多個第一輸入通道接收多個第一輸入位元，並對該些第一輸入位元進行第一極化編碼，以透過多個第一輸出通道提供多個第一輸出位元；從該些極化矩陣的該些第一輸入通道中，挑選至少一待強化輸入通道；提供再極化矩陣，再極化矩陣經由多個第二輸入通道接收多個第二輸入位元，並對該些第二輸入位元進行第二極化編碼，以透過多個第二輸出通道提供多個第二輸出位元，該些第二輸出位元中的一部分係作為提供至待強化輸入通道的第一輸出位元；提供極化碼，極化碼包括該些第一輸出位元以及該些第二輸出位元中的剩餘部分。 According to an embodiment, an electronic device is provided, which includes a memory and a processor. The memory stores at least one command. The processor is coupled to the memory and executes the at least one instruction to implement the following steps: establishing a plurality of polarization matrices, the plurality of polarization matrices receiving a plurality of first input bits through a plurality of first input channels, and The first input bit is subjected to first polarization encoding to provide a plurality of first output bits through a plurality of first output channels; and at least one input to be strengthened is selected from the first input channels of the polarization matrices. Channel; providing a repolarization matrix, the repolarization matrix receives a plurality of second input bits through a plurality of second input channels, and performs second polarization encoding on the second input bits to pass through a plurality of second The output channel provides a plurality of second output bits, and some of the second output bits are provided to the input channel to be enhanced. The first output bit is provided; a polarization code is provided, and the polarization code includes the first output bits and a remaining portion of the second output bits.

為了對本揭露之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式詳細說明如下： In order to have a better understanding of the above and other aspects of this disclosure, the following specific examples are described in detail below in conjunction with the drawings:

GM、GM₁~GM_k、GM_H、GM_M、GM_L、GM_H1、GM_H2、GM_L1、GM_L2‧‧‧極化矩陣 GM, GM ₁ ~ GM _k , GM _H , GM _M , GM _L , GM _H1 , GM _H2 , GM _L1 , GM _L2 ‧‧‧ polarization matrix

RGM、RGM_A、RGM_B、RGM_C‧‧‧再極化矩陣 RGM, RGM _A , RGM _B , RGM _C ‧‧‧ repolarization matrix

102‧‧‧運算單元 102‧‧‧ Computing Unit

U₁~U₈、U_i、U_i+1‧‧‧輸入位元 U ₁ ~ U ₈ , U _i , U _{i + 1} ‧‧‧ input bit

U₃’~U₁₀’‧‧‧第一輸入位元 U ₃ '~ U ₁₀ ' ‧‧‧First input bit

X₁~X₈‧‧‧輸出位元 X ₁ ~ X ₈ ‧‧‧ output bits

X₃’~X₁₀’‧‧‧第一輸出位元 X ₃ '~ X ₁₀ ' ‧‧‧ the first output bit

X₁’、X₂’‧‧‧第二輸出位元 X ₁ ', X ₂ ' ‧‧‧Second output bit

V₁~V₁₀‧‧‧原始輸入位元 V ₁ ~ V ₁₀ ‧‧‧Original input bit

Y₁~Y₈‧‧‧讀取資料 Y ₁ ~ Y ₈ ‧‧‧Read data

W₁~W₈‧‧‧輸出通道 W ₁ ~ W ₈ ‧‧‧Output channel

S202、S204、S206、S208‧‧‧步驟 S202, S204, S206, S208‧‧‧ steps

N₁、N₂、...、N_k、N_A、N_B、N_H、N_M、N_L‧‧‧第一輸出通道的個數 N ₁ , N ₂ , ..., N _k , N _A , N _B , N _H , N _M , N _L ‧‧‧ number of first output channels

q_1~q_k、q_H、q_M、q_L、q_H1、q_H2、q_L1、q_L2‧‧‧待強化輸入通道的個數 q _{1 ~} q _k , q _H , q _M , q _L , q _H1 , q _H2 , q _L1 , q _L2 ‧‧‧Number of input channels to be strengthened

q、q_A、q_B、q_C‧‧‧第二輸出位元的剩餘部分的位元數量 q, q _A , q _B , q _C ‧‧‧ the number of bits in the remainder of the second output bit

q_r、q_rA、q_rB、q_rC‧‧‧再極化矩陣的第二輸入通道的數量 q _r , q _rA , q _rB , q _rC ‧‧‧Number of second input channels of the repolarization matrix

502‧‧‧第一階段 502‧‧‧Phase 1

504‧‧‧第二階段 504‧‧‧Phase 2

506‧‧‧第三階段 506‧‧‧Phase III

第1A圖繪示極化轉換的示意圖。 FIG. 1A shows a schematic diagram of polarization conversion.

第1B圖繪示極化矩陣中的一運算單元的示意圖。 FIG. 1B is a schematic diagram of an operation unit in the polarization matrix.

第2圖繪示根據本揭露一實施例的極化碼產生方法的流程圖。 FIG. 2 is a flowchart of a method for generating a polar code according to an embodiment of the disclosure.

第3圖繪示根據本揭露一實施例的極化轉換示意圖。 FIG. 3 is a schematic diagram of polarization conversion according to an embodiment of the disclosure.

第4圖繪示根據本揭露一實施例的極化轉換示意圖。 FIG. 4 is a schematic diagram of polarization conversion according to an embodiment of the present disclosure.

第5圖繪示根據本揭露一實施例的通道錯誤率模擬圖。 FIG. 5 is a channel error rate simulation diagram according to an embodiment of the disclosure.

第6圖繪示根據本揭露一實施例的極化轉換示意圖。 FIG. 6 is a schematic diagram of polarization conversion according to an embodiment of the present disclosure.

第7圖繪示根據本揭露一實施例的極化轉換示意圖。 FIG. 7 is a schematic diagram of polarization conversion according to an embodiment of the disclosure.

第8A圖繪示根據本揭露一實施例的極化碼結構。 FIG. 8A illustrates a polar code structure according to an embodiment of the disclosure.

第8B圖繪示根據第8A圖實施例的極化轉換示意圖。 FIG. 8B is a schematic diagram of polarization conversion according to the embodiment in FIG. 8A.

本揭露提出一種極化碼產生方法及應用其的電子裝置及非暫態電腦可讀取儲存媒體。本揭露的極化碼產生方法可由電子裝置執行。電子裝置例如包括記憶體以及處理器。記憶體可儲存至少一指令。處理器耦接記憶體，並可執行的記憶體中的指令，以實現本揭露的極化碼產生方法。處理器例如是微控制單元(microcontroller)、微處理器(microprocessor)、數位訊號處理器(digital signal processor)、特殊應用積體電路(application specific integrated circuit，ASIC)、數位邏輯電路、現場可程式邏輯閘陣列(field programmable gate array，FPGA)、或其它具有運算處理功能的硬體元件。本揭露的極化碼產生方法亦可實作成由一或多個指令所構成的軟體程式，此軟體程式可儲存於非暫態電腦可讀取儲存媒體(non-transitory computer-readable storage medium)，例如硬碟、光碟、隨身碟、記憶體，當處理器從非暫態電腦可讀取儲存媒體載入此軟體程式時，可執行本揭露的極化碼產生方法。 This disclosure proposes a method for generating a polar code, an electronic device using the same, and a non-transitory computer-readable storage medium. The disclosed method for generating a polar code can be executed by an electronic device. The electronic device includes, for example, a memory and a processor. Memory can be saved to One less instruction. The processor is coupled to the memory and can execute instructions in the memory to implement the polarization code generating method disclosed in the present disclosure. The processor is, for example, a microcontroller, a microprocessor, a digital signal processor, an application specific integrated circuit (ASIC), a digital logic circuit, or a field programmable logic Gate programmable array (field programmable gate array, FPGA), or other hardware components with arithmetic processing functions. The disclosed method for generating a polar code can also be implemented as a software program composed of one or more instructions. This software program can be stored in a non-transitory computer-readable storage medium. For example, a hard disk, a compact disk, a flash drive, and a memory. When the processor loads the software program from a non-transitory computer-readable storage medium, the polar code generating method disclosed in this disclosure can be performed.

第1A圖繪示極化轉換的示意圖。如第1A圖所示，一組輸入位元U₁~U₈由左至右經過極化矩陣GM的極化轉換而形成對應的一組輸出位元X₁~X₈。輸入位元X₁~X₈可視為一組極化碼(polar code)而被寫入一組輸出通道W₁~W₈當中。在儲存設備的應用中，輸出通道W₁~W₈可分別視為一記憶胞。輸出通道W₁~W₈的輸出值為Y₁~Y₈。 FIG. 1A shows a schematic diagram of polarization conversion. As shown in FIG. 1A, a set of input bits U ₁ to U ₈ undergo polarization conversion from the polarization matrix GM from left to right to form a corresponding set of output bits X ₁ to X ₈ . The input bits X ₁ to X ₈ can be regarded as a set of polar codes and written into a set of output channels W ₁ to W ₈ . In the application of the storage device, the output channels W ₁ to W ₈ can be regarded as a memory cell, respectively. The output values of output channels W ₁ to W ₈ are Y ₁ to Y ₈ .

極化矩陣GM包括多個運算單元102。在第1A圖的例子中，極化矩陣GM是由串接的3階運算單元102所形成。透過極化矩陣GM，接收輸入位元U₁~U₈的輸入位元通道可被極化成可靠的輸入位元通道以及不可靠的輸入位元通道。根據第1A圖的極化矩陣GM，若輸出通道W₁~W₈皆為獨立且相同的分布(identical independent distributed，i.i.d.)，則接收輸入位元U₄、U₆、U₇、U₈的輸入位元通道將被極化成較可靠的通道，而接收輸入位元U₁、U₂、U₃、U₅的輸入位元通道則是被極化成較不可靠的通道。 The polarization matrix GM includes a plurality of operation units 102. In the example of FIG. 1A, the polarization matrix GM is formed by a third-order arithmetic unit 102 connected in series. Through the polarization matrix GM, the input bit channels receiving the input bits U ₁ to U ₈ can be polarized into a reliable input bit channel and an unreliable input bit channel. According to the polarization matrix GM in FIG. 1A, if the output channels W ₁ to W ₈ are all independently and identically distributed (iid), then the input bits U ₄ , U ₆ , U ₇ , and U ₈ are received. The input bit channels will be polarized into more reliable channels, while the input bit channels that receive input bits U ₁ , U ₂ , U ₃ , U ₅ are polarized into less reliable channels.

第1B圖繪示極化矩陣GM中的一運算單元102的示意圖。運算單元102例如是互斥或(XOR)邏輯閘。利用XOR邏輯閘的特性，傳送輸入位元U_i+1的輸入通道會被強化其可靠度，而傳送輸入位元U_i的輸入通道則會被弱化其可靠度。換言之，相較於承載輸入位元U_i的輸入通道，承載輸入位元U_i+1的輸入通道會被極化成相對可靠的通道。透過上述方式，可以實現提供任意可靠性排序的極化矩陣。 FIG. 1B is a schematic diagram of an operation unit 102 in the polarization matrix GM. The arithmetic unit 102 is, for example, a mutually exclusive OR (XOR) logic gate. Utilizing the characteristics of the XOR logic gate, the input channel transmitting the input bit U _{i + 1} will be enhanced in its reliability, and the input channel transmitting the input bit U _i will be weakened in its reliability. In other words, compared to the input channel carrying the input bit U _i , the input channel carrying the input bit U _{i + 1} is polarized into a relatively reliable channel. In the above manner, a polarization matrix that provides an arbitrary reliability order can be realized.

第2圖繪示根據本揭露一實施例的極化碼產生方法的流程圖。步驟S202，處理器建立多個極化矩陣，該些極化矩陣經由多個第一輸入通道接收多個第一輸入位元，並對該些第一輸入位元進行第一極化編碼，以透過多個第一輸出通道提供多個第一輸出位元。 FIG. 2 is a flowchart of a method for generating a polar code according to an embodiment of the disclosure. Step S202: The processor establishes a plurality of polarization matrices, the plurality of polarization matrices receive a plurality of first input bits through a plurality of first input channels, and performs first polarization encoding on the first input bits to A plurality of first output bits are provided through a plurality of first output channels.

第一極化編碼例如是指透過該些極化矩陣，分別對該些第一輸入位元所作的極化轉換。各個極化矩陣的設計可以是任意的，並可透過任何已知的極化碼建構(code construction)技術來實現。 The first polarization coding refers to, for example, polarization conversions performed on the first input bits through the polarization matrices. The design of each polarization matrix can be arbitrary and can be implemented by any known polarization code construction technology.

步驟S204，處理器從該些極化矩陣的該些第一輸入通道中，挑選至少一待強化輸入通道。被挑選的待強化輸入通道將被作進一步再極化處理，以提升通道的可靠度。 In step S204, the processor selects at least one input channel to be enhanced from the first input channels of the polarization matrices. The selected input channels to be strengthened will be further repolarized to improve channel reliability.

步驟S206，處理器提供再極化矩陣，再極化矩陣經由多個第二輸入通道接收多個第二輸入位元，並對該些第二輸入位元進行第二極化編碼，以透過多個第二輸出通道提供多個第二輸出位元，該些第二輸出位元中的一部分係作為提供至待強化輸入通道的第一輸出位元。 In step S206, the processor provides a repolarization matrix, and the repolarization matrix receives a plurality of second input bits through a plurality of second input channels, and performs second polarization encoding on the second input bits to pass through the plurality of second input bits. Each second output channel provides a plurality of second output bits, and some of the second output bits are used as the first output bits provided to the input channel to be enhanced.

第二極化編碼是指透過再極化矩陣，對該些第二輸入位元所作的極化轉換。再極化矩陣的設計可以是任意的，並可透過任何已知的極化碼建構技術來實現。再極化矩陣的部分第二輸入通道可用來接收對應待強化輸入通道的原始資料位元。再極化矩陣可被設計成強化承載此些原始資料位元的第二輸入通道的可靠度。另一方面，剩下被再極化矩陣弱化的第二輸入通道則可用來傳輸凍結位元。 The second polarization coding refers to the polarization conversion of the second input bits through the repolarization matrix. The design of the repolarization matrix can be arbitrary and can be realized by any known polarization code construction technology. Part of the second input channel of the repolarization matrix can be used to receive the original data bits corresponding to the input channel to be enhanced. The repolarization matrix can be designed to enhance the reliability of the second input channel carrying these original data bits. On the other hand, the remaining second input channel weakened by the repolarization matrix can be used to transmit frozen bits.

步驟S208，處理器提供極化碼，極化碼包括該些第一輸出位元以及該些第二輸出位元中非作為第一輸入位元的剩餘部分。由於第二輸出位元的剩餘部分的位元數量可以是任意的，故極化碼的整體碼長並不需受限於2的冪次方。 In step S208, the processor provides a polarization code, and the polarization code includes the first output bits and the remaining portions of the second output bits that are not the first input bits. Since the number of bits in the remaining portion of the second output bit can be arbitrary, the overall code length of the polarized code need not be limited to a power of two.

第3圖繪示根據本揭露一實施例的極化轉換示意圖。在第3圖中，極化轉換係由k個極化矩陣GM₁~GM_k以及一再極化矩陣RGM實現，其中k為正整數。極化矩陣GM₁、GM₂、...、GM_k分別有N₁、N₂、...、N_k個第一輸入通道(繪示於極化矩陣GM₁~GM_k的左側)以及N₁、N₂、...、N_k個第一輸出通道(繪示於極化矩陣GM₁~GM_k的右側)，其中N₁~N_k為正整數。針對極化矩陣GM₁的N₁個第一輸入通道，當中有q₁個第一輸入通道被挑選為待強化輸入通道而被提供至再極化矩陣RGM進行再極化，而剩下的N₁-q₁個第一輸入通道則是直接接收原始資料(raw data)位元作為第一輸入位元；類似地，極化矩陣GM₂有q₂個第一輸入通道被挑選為待強化輸入通道而被提供至再極化矩陣RGM，而剩下的N₂-q₂個第一輸入通道則是直接接收對應的原始資料位元作為第一輸入位元；類似地，極化矩陣GM_k有q_k個第一輸入通道被挑選為待強化輸入通道而被提供至再極化矩陣RGM進行再極化，而剩下的N_k-q_k個第一輸入通道則是直接接收原始資料位元作為第一輸入位元，其中q_1~q_k為非負整數。 FIG. 3 is a schematic diagram of polarization conversion according to an embodiment of the disclosure. In Figure 3, the polarization conversion system is implemented by k polarization matrices GM ₁ to GM _k and a repolarization matrix RGM, where k is a positive integer. The polarization matrices GM ₁ , GM ₂ , ..., GM _k have N ₁ , N ₂ , ..., N _k first input channels (shown on the left of the polarization matrices GM ₁ ~ GM _k ), and N ₁ , N ₂ , ..., N _k first output channels (shown on the right side of the polarization matrices GM ₁ to GM _k ), where N ₁ to N _k are positive integers. For the N ₁ first input channels of the polarization matrix GM ₁ , q ₁ first input channel is selected as the input channel to be strengthened and provided to the repolarization matrix RGM for repolarization, and the remaining N ₁ -q ₁ first input channel directly receives raw data bits as the first input bit; similarly, the polarization matrix GM ₂ has q ₂ first input channels which are selected as the input to be enhanced Channels are provided to the repolarization matrix RGM, and the remaining N ₂ -q ₂ first input channels directly receive corresponding original data bits as first input bits; similarly, the polarization matrix GM _k Q _k first input channels are selected as input channels to be strengthened and provided to the repolarization matrix RGM for repolarization, and the remaining N _k -q _k first input channels directly receive raw data bits As the first input bit, q _{1 ~} q _{k are} non-negative integers.

再極化矩陣RGM共有q_r個第二輸入通道(繪示於再極化矩陣RGM的左側)以及q_r個第二輸出通道(繪示於再極化矩陣RGM的右側)，其中q_r=q+(q₁+q₂+...+q_k)。再極化矩陣RGM提供的多個第二輸出位元中，一部分係提供至極化矩陣GM₁的q₁個待強化輸入通道、極化矩陣GM₂的q₂個待強化輸入通道、...、以及極化矩陣GM_k的q_k個待強化輸入通道，而該些第二輸出位元的剩餘部分的位元數量q=q_r-(q₁+q₂+...+q_k)。在一實施例中，該些第二輸出位元的剩餘部分的位元數量(q)與待強化輸入通道的通道數量(q₁+q₂+...+q_k)相同，此時q_r=2q，但應注意本揭露並不以此為限。 The repolarization matrix RGM has q _r second input channels (shown on the left side of the repolarization matrix RGM) and q _r second output channels (shown on the right side of the repolarization matrix RGM), where q _r = q + (q ₁ + q ₂ + ... + q _k ). A plurality of second output bits provided RGM repolarization matrix, a portion of the matrix system to provide extremely GM q ₁ is _an input channel to be reinforced, the polarization matrix GM q ₂ _two input channels to be fortified, ... And q _k input channels to be strengthened of the polarization matrix GM _k , and the number of bits of the remainder of the second output bits q = q _r- (q ₁ + q ₂ + ... + q _k ) . In an embodiment, the number of bits (q) of the remaining portions of the second output bits is the same as the number of channels (q ₁ + q ₂ + ... + q _k ) of the input channel to be enhanced. At this time, q _r = 2q, but it should be noted that this disclosure is not limited to this.

在第3圖中，極化轉換所產生的極化碼係由N₁+N₂+...+N_k個第一輸出位元以及q個第二輸出位元所構成，該q個第二輸出位元可視為極化碼中因再極化程序而產生的額外位元。 In Fig. 3, the polarization code generated by polarization conversion is composed of N ₁ + N ₂ + ... + N _k first output bits and q second output bits. The two output bits can be regarded as extra bits generated by the repolarization procedure in the polarized code.

為幫助理解本揭露，相關細節係配合第4圖及第5圖作說明。 To help understand this disclosure, relevant details are described in conjunction with Figures 4 and 5.

第4圖繪示根據本揭露一實施例的極化轉換示意圖。在第4圖中，極化轉換係由2個極化矩陣GM₁、GM₂以及一個再極化矩陣RGM實現。其中極化矩陣GM₁用以將第一輸入位元U₃’~U₆’轉換成對應的第一輸出位元X₃~X₆；而極化矩陣GM₂用以將第一輸入位元U₇’~U₁₀’轉換成對應的第一輸出位元X₇~X₁₀。 FIG. 4 is a schematic diagram of polarization conversion according to an embodiment of the present disclosure. In Fig. 4, the polarization conversion system is implemented by two polarization matrices GM ₁ and GM ₂ and one repolarization matrix RGM. The polarization matrix GM _{1 is} used to convert the first input bits U ₃ ′ ~ U ₆ ′ to the corresponding first output bits X ₃ to X ₆ ; and the polarization matrix GM _{2 is} used to convert the first input bits U ₇ '~ U ₁₀ ' are converted into corresponding first output bits X ₇ ~ X ₁₀ .

在第4圖的例子中，傳輸第一輸入位元U₅以及U₈的第一輸入通道被選作待強化輸入通道，而其他的第一輸出通道則是傳輸原始位元資料。因此，除了第一輸入位元U₅及U₈，其他的第一輸入位元U₃、U₄、U₆、U₇、U₉、及U₁₀係未經再極化矩陣RGM處理的原始輸入位元V₃、V₄、V₆、V₇、V₉、及V₁₀。 In the example in FIG. 4, the first input channels transmitting the first input bits U ₅ and U ₈ are selected as the input channels to be enhanced, and the other first output channels are transmitting the original bit data. Therefore, in addition to the first input bits U ₅ and U ₈ , the other first input bits U ₃ , U ₄ , U ₆ , U ₇ , U ₉ , and U ₁₀ are original without the repolarization matrix RGM processing. Enter the bits V ₃ , V ₄ , V ₆ , V ₇ , V ₉ , and V ₁₀ .

與第一輸入位元U₅、U₈對應的兩個原始輸入位元V₅、V₈與另外兩個原始輸入位元V₁、V₂將作為提供至再極化矩陣RGM的第二輸入通道的第二輸入位元。在此實施例中，再極化矩陣RGM是以2階的XOR邏輯閘來實現，但應注意本揭露並不以此為限。再極化矩陣RGM的邏輯閘階數可以是任意的。 The first input bit U _5, U ₈ bits corresponding to the two original input V _5, V ₈ with two original input bit V _1, V ₂ as a second input is provided to the matrix of RGM repolarization The second input bit of the channel. In this embodiment, the repolarization matrix RGM is implemented by a second-order XOR logic gate, but it should be noted that this disclosure is not limited thereto. The number of logic gates of the repolarization matrix RGM can be arbitrary.

再極化矩陣RGM具有4個第二輸出通道，其中2個第二輸出通道負責對極化矩陣GM₁、GM₂分別提供第一輸入位元U₅、U₈，而剩餘的2個第二輸出通道則是負責提供第二輸出位元X₁、X₂，其中第二輸出位元X₁、X₂將作為輸出極化碼的一部分。 The repolarization matrix RGM has four second output channels, of which two second output channels are responsible for providing the first input bits U ₅ and U ₈ to the polarization matrices GM ₁ and GM ₂ respectively, and the remaining two second output channels The output channel is responsible for providing the second output bits X ₁ and X ₂ , and the second output bits X ₁ and X ₂ will be used as a part of the output polarization code.

透過再極化矩陣RGM，可將傳輸原始輸入位元V₅、V₈的第二輸入通道再極化成相對可靠的通道，進而對極化矩陣GM₁、GM₂中傳輸第一輸入位元U₅及U₈的第一輸入通道作強化，而極化碼的碼長也只需增加2個位元(此例中即第二輸出位元X₁’及X₂’)。 Through the repolarization matrix RGM, the second input channel transmitting the original input bits V ₅ and V ₈ can be re-polarized into a relatively reliable channel, and the first input bit U can be transmitted in the polarization matrices GM ₁ and GM ₂ . The first input channels of ₅ and U ₈ are strengthened, and the code length of the polarization code only needs to be increased by 2 bits (in this example, the second output bits X ₁ ′ and X ₂ ′).

第5圖繪示根據本揭露一實施例的通道錯誤率模擬圖。在第一階段502，極化轉換尚未執行，故對應通道指標1~8的8個第一輸入通道的模擬錯誤率皆相同。在第二階段504，8個第一輸入通道的模擬錯誤率經過極化矩陣而被極化成不同值，其中對應通道指標4~8的第一輸入通道係較對應通道指標1~3的第一輸入通道具有較低的錯誤率，故較可靠。在第三階段506，對應通道指標4、5的第一輸入通道被選作待強化輸入通道進行再極化，故其錯誤率明顯降低。 FIG. 5 is a channel error rate simulation diagram according to an embodiment of the disclosure. In the first stage 502, the polarization conversion has not been performed, so the simulation error rates of the eight first input channels corresponding to the channel indexes 1 to 8 are all the same. In the second stage 504, the simulation error rates of the eight first input channels are polarized into different values through the polarization matrix. Among them, the first input channel corresponding to the channel indicators 4 to 8 is the first one corresponding to the channel indicators 1 to 3. The input channel has a lower error rate and is therefore more reliable. In the third stage 506, the first input channel corresponding to the channel indicators 4, 5 is selected as the input channel to be strengthened for repolarization, so its error rate is significantly reduced.

根據本揭露實施例，不同的極化矩陣可針對不同的儲存單元作為輸出通道作配置，以提供適應性的極化轉換。為幫助理解，相關細節係配合第6、7、8A、8B圖作說明。 According to the embodiments of the present disclosure, different polarization matrices can be configured for different storage units as output channels to provide adaptive polarization conversion. To help understanding, relevant details are explained in conjunction with Figures 6, 7, 8A, and 8B.

第6圖繪示根據本揭露一實施例的極化轉換示意圖。一般而言，儲存MLC高位元資料的儲存單元的通道特性與儲存MLC低位元資料的儲存單元的通道特性並不會相同。若是對具有不同通道特性的儲存單元採用單一組極化矩陣，將可能減低整體的錯誤更正性能。因此，根據第6圖的實施例，不同的極化矩陣係針對MLC的不同的邏輯資料頁(例如，高位元資料、低位元資料)作設置。高位元例如是指MLC所儲存的2個位元中的其中一個位元，而低位元則是指MLC所儲存的2個位元中的另一個位元。舉例來說，針對MLC儲存的2位元資料「10」，高位元例如是指位元1(在其他例子中，或為位元0)，而低位元例如是指位元0(在其他例子中，或為位元1)。 FIG. 6 is a schematic diagram of polarization conversion according to an embodiment of the present disclosure. Generally speaking, the channel characteristics of a storage unit storing high-level MLC data are not the same as the channel characteristics of a storage unit storing low-level MLC data. If a single set of polarization matrices is used for storage cells with different channel characteristics, the overall error correction performance may be reduced. Therefore, according to the embodiment of FIG. 6, different polarization matrices are set for different logical data pages (for example, high-order data, low-order data) of the MLC. High bit e.g. It refers to one of the 2 bits stored in the MLC, and the lower bit refers to the other of the 2 bits stored in the MLC. For example, for the 2-bit data "10" stored in the MLC, the high bit refers to bit 1 (in other examples, or bit 0), and the low bit refers to bit 0 (in other examples) Medium, or bit 1).

如第6圖所示，極化轉換係由二個極化矩陣GM_H、GM_L以及一個再極化矩陣RGM_A實現，其中極化矩陣GM_H負責提供包括N_H個第一輸出位元的第一組輸出位元，該第一組輸出位元係表示MLC的高位元資料；極化矩陣GM_L負責提供包括N_L個第一輸出位元的第二組輸出位元，該第二組輸出位元係表示MLC的低位元資料。再極化矩陣RGM_A係以2階的XOR邏輯閘來實現。在其他實施例中，再極化矩陣RGM_A可透過任意階數的邏輯閘來實現。 As shown in Fig. 6, the polarization conversion system is implemented by two polarization matrices GM _H and GM _L and a repolarization matrix RGM _A. The polarization matrix GM _H is responsible for providing N _H The first group of output bits represents the high-order data of the MLC; the polarization matrix GM _L is responsible for providing a second group of output bits including N _L first output bits, the second group The output bits represent the low-order data of the MLC. The repolarization matrix RGM _A is implemented by a second-order XOR logic gate. In other embodiments, the repolarization matrix RGM _A may be implemented by a logic gate of any order.

極化矩陣GM_H和極化矩陣GM_L分別有q_H和q_L個第一輸入通道被選作待強化輸入通道，以透過再極化矩陣RGM_A改善其可靠度，其中再極化矩陣RGM_A具有q_rA個第二輸入通道，極化碼中因再極化矩陣RGM_A產生的額外位元數量為q_A=q_rA-(q_H+q_L)。在一實施例中，q_rA=2q_A。 The polarization matrix GM _H and polarization matrix GM _L have q _H and q _L first input channels, respectively, which are selected as the input channels to be strengthened to improve their reliability through the repolarization matrix RGM _A , where the repolarization matrix RGM _A has q _rA second input channels, and the number of extra bits generated by the repolarization matrix RGM _A in the polarization code is q _A = q _rA- (q _H + q _L ). In one embodiment, q _rA = 2q _A.

第7圖繪示根據本揭露又一實施例的極化轉換示意圖。根據第7圖的實施例，不同的極化矩陣係針對三階記憶胞(triple-level cell，TLC)中不同的邏輯資料頁(例如高位元資料、中位元資料、低位元資料)作設置。其中高位元、中位元、低位元分別表示TLC所儲存的3位元資料中的3個位元。 FIG. 7 is a schematic diagram of polarization conversion according to another embodiment of the present disclosure. According to the embodiment of FIG. 7, different polarization matrices are set for different logical data pages (such as high-bit data, middle-bit data, and low-bit data) in a triple-level cell (TLC). . The high bit, the middle bit, and the low bit represent the three bits of the three bits of data stored in the TLC.

如第7圖所示，極化轉換係由三個極化矩陣GM_H、GM_M、GM_L以及一再極化矩陣RGM_B實現，其中極化矩陣GM_H負責提供包括N_H個第一輸出位元的第一組輸出位元，該第一組輸出位元係表示TLC的高位元資料；極化矩陣GM_M負責提供包括N_M個第一輸出位元的第二組輸出位元，該第二組輸出位元係表示TLC的中位元資料；極化矩陣GM_L負責提供包括N_L個第一輸出位元的第三組輸出位元，該第三組輸出位元係表示TLC的低位元資料。在此例中，再極化矩陣RGM_B係以3階的XOR邏輯閘來實現。在其他實施例中，再極化矩陣RGM_B可透過任意階數的邏輯閘來實現。 As shown in Figure 7, the polarization conversion system is implemented by three polarization matrices GM _H , GM _M , GM _L, and a repolarization matrix RGM _B. The polarization matrix GM _H is responsible for providing N _H first output bits. The first set of output bits is the first set of output bits representing the high-order data of the TLC; the polarization matrix GM _M is responsible for providing the second set of output bits including N _M first output bits. The two sets of output bits represent the median data of the TLC; the polarization matrix GM _L is responsible for providing the third set of output bits including N _L first output bits, and the third set of output bits represents the lower bits of the TLC Metadata. In this example, the repolarization matrix RGM _B is implemented as a 3rd order XOR logic gate. In other embodiments, the repolarization matrix RGM _B may be implemented by a logic gate of any order.

極化矩陣GM_H、GM_M及GM_L分別有q_H、q_M及q_L個第一輸入通道被選作待強化輸入通道，以透過再極化矩陣RGM_B改善其可靠度，其中再極化矩陣RGM_B具有q_rB個第二輸入通道，極化碼中因再極化矩陣RGM_B產生的額外位元數量q_B=q_rB-(q_H+q_M+q_L)。在一實施例中，q_rB=2q_B。 The polarization matrices GM _H , GM _M, and GM _L have q _H , q _M, and q _L first input channels, respectively, which are selected as input channels to be strengthened to improve their reliability through the repolarization matrix RGM _B. The transformation matrix RGM _B has q _rB second input channels, and the number of extra bits generated by the repolarization matrix RGM _B in the polarization code is q _B = q _rB- (q _H + q _M + q _L ). In one embodiment, q _rB = 2q _B.

接著請同時參考第8A圖以及第8B圖。第8A圖繪示根據本揭露一實施例的極化碼結構。第8B圖繪示根據第8A圖實施例的極化轉換示意圖。 Please refer to FIG. 8A and FIG. 8B at the same time. FIG. 8A illustrates a polar code structure according to an embodiment of the disclosure. FIG. 8B is a schematic diagram of polarization conversion according to the embodiment in FIG. 8A.

根據此實施例，極化碼中的高位元資料以及低位元資料分別包括個N _A+N _B+個位元。極化矩陣GM_H1以及GM_H2分別負責提供極化碼的高位元資料中的N_B及N_A個第一輸出位元；而極化矩陣GM_L1以及GM_L2則分別負責提供極化碼的低位元資料中的N_B及N_A 個第一輸出位元，其中N_A不等於N_B。也就是說，極化矩陣GM_H1、GM_H2(或GM_L1、GM_L2)係分別提供位元數量相異的兩組輸出位元，其中一組輸出位元包括N_B個第一輸出位元，另一組輸出位元包括N_A個第一輸出位元。 According to this embodiment, the high-order data and low-order data in the polarization code include N _A + N _B + Bits. The polarization matrices GM _H1 and GM _H2 are responsible for providing the N _B and N _A first output bits in the high-bit data of the polarization code, while the polarization matrices GM _L1 and GM _L2 are responsible for providing the low-order bits of the polarization code N _B and N _A first output bits in the metadata, where N _{A is} not equal to N _B. In other words, the polarization matrices GM _H1 and GM _H2 (or GM _L1 and GM _L2 ) respectively provide two sets of output bits with different numbers of bits, where one set of output bits includes N _B first output bits , Another set of output bits includes N _A first output bits.

另外，極化矩陣GM_H1、GM_H2、GM_L1、GM_L2分別有q_H1、q_H2、q_L1、q_L2個第一輸入通道被選作待強化輸入通道，以透過再極化矩陣RGM_C改善其可靠度，其中再極化矩陣RGM_C具有q_rC個第二輸入通道，極化碼中因再極化矩陣RGM_C產生的額外位元數量q_C=q_rC-(q_H1+q_H2+q_L1+q_L2)。在一實施例中，q_rC=2q_C。 In addition, the polarization matrices GM _H1 , GM _H2 , GM _L1 , and GM _L2 have q _H1 , q _H2 , q _L1 , and q _L2 first input channels selected as the input channels to be strengthened to pass through the repolarization matrix RGM _C Improve its reliability, where the repolarization matrix RGM _C has q _rC second input channels, and the number of extra bits generated by the repolarization matrix RGM _C in the polarization code q _C = q _rC- (q _H1 + q _H2 + q _L1 + q _L2 ). In one embodiment, q _rC = 2q _C.

透過上述方式，可實現一(2×(N _A+N _B+)，K)的極化碼，其中2×(N _A+N _B+)表示極化碼的總位元長度，K表示極化碼中的資料位元數。舉例來說，N_A=4096、N_B=512，q_C=24，K=8192。 Through the above method, a (2 × ( N _A + N _B + ), K), where 2 × ( N _A + N _B + ) Represents the total bit length of the polarization code, and K represents the number of data bits in the polarization code. For example, N _A = 4096, N _B = 512, q _C = 24, K = 8192.

應注意的是，在上述各實施例中，再極化矩陣和極化矩陣之間的連接並不需要被限制成：前一半的通道負責傳輸額外位元(如第8B圖中兩組的q_C/2個通道)，而後一半的通道由待強化輸入通道(如第8B圖中多個極化矩陣的q_H1、q_H2、q_L1、q_L2個通道)所構成。在一些實施例中，當再極化的長度很大時，再極化矩陣和極化矩陣之間的連接配置可能不會如此規律。 It should be noted that in the above embodiments, the connection between the repolarization matrix and the polarization matrix does not need to be limited to: the first half of the channel is responsible for transmitting extra bits (such as _C / 2 channels), and the latter half of the channels are composed of input channels to be strengthened (such as q _H1 , q _H2 , q _L1 , q _L2 channels of multiple polarization matrices in FIG. 8B). In some embodiments, when the length of the repolarization is large, the connection configuration between the repolarization matrix and the polarization matrix may not be so regular.

綜上所述，本揭露提供一種極化碼產生方法及應用其的電子裝置及非暫態電腦可讀取儲存媒體。根據本揭露實施例，處理器可設置多個極化矩陣，並針對該些極化矩陣中特定的輸入位元通道進行再極化，以改善通道可靠度。另外，再極化機制可額外產生的輸出位元，可讓極化碼的整體碼長不受2的冪次方的限制，進而降低系統設計的複雜度。 In summary, the present disclosure provides a method for generating a polar code, an electronic device using the same, and a non-transitory computer-readable storage medium. According to the embodiment of the disclosure, the processor may set a plurality of polarization matrices and target specific inputs in the polarization matrices. Bit channels are repolarized to improve channel reliability. In addition, the repolarization mechanism can generate additional output bits, so that the overall code length of the polarized code is not limited by the power of two, thereby reducing the complexity of the system design.

雖然本揭露已以實施例揭露如上，然其並非用以限定本揭露。本揭露所屬技術領域中具有通常知識者，在不脫離本揭露之精神和範圍內，當可作各種之更動與潤飾。因此，本揭露之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present disclosure has been disclosed above by way of example, it is not intended to limit the present disclosure. Those with ordinary knowledge in the technical field to which this disclosure pertains can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the scope of the appended patent application.

Claims

一種極化碼產生方法，由包括一處理器的電子裝置執行，該極化碼產生方法包括：建立複數個極化矩陣，該些極化矩陣經由複數個第一輸入通道接收複數個第一輸入位元，並對該些第一輸入位元進行一第一極化編碼，以透過複數個第一輸出通道提供複數個第一輸出位元；從該些極化矩陣的該些第一輸入通道中，挑選至少一待強化輸入通道；提供一再極化矩陣，該再極化矩陣經由複數個第二輸入通道接收複數個第二輸入位元，並對該些第二輸入位元進行一第二極化編碼，以透過複數個第二輸出通道提供複數個第二輸出位元，該些第二輸出位元中的一部分係作為提供至該至少一待強化輸入通道的第一輸出位元；以及提供一極化碼，該極化碼包括該些第一輸出位元以及該些第二輸出位元的一剩餘部分；其中，該些極化矩陣的各該些第一輸出位元分別用以表示一邏輯資料頁的資料。A method for generating a polar code is executed by an electronic device including a processor. The method for generating a polar code includes: establishing a plurality of polarization matrices, the plurality of polarization matrices receiving a plurality of first inputs via a plurality of first input channels; And perform a first polarization encoding on the first input bits to provide a plurality of first output bits through the plurality of first output channels; from the first input channels of the polarization matrices Selecting at least one input channel to be strengthened; providing a repolarization matrix that receives a plurality of second input bits via a plurality of second input channels and performs a second on the second input bits Polarization encoding to provide a plurality of second output bits through a plurality of second output channels, a portion of which is used as a first output bit provided to the at least one input channel to be enhanced; and A polarization code is provided, and the polarization code includes the first output bits and a remaining portion of the second output bits; wherein each of the first output bits of the polarization matrices is used for Data shows a logical data page.

如申請專利範圍第1項所述之極化碼產生方法，其中該些第一輸出位元包括一第一組輸出位元以及一第二組輸出位元，該第一組輸出位元表示一高位元資料，該第二組輸出位元表示一低位元資料，該極化碼產生方法更包括：透過該些極化矩陣中的一第一極化矩陣提供該第一組輸出位元；以及透過該些極化矩陣中的一第二極化矩陣提供該第二組輸出位元。The method for generating a polar code according to item 1 of the scope of patent application, wherein the first output bits include a first set of output bits and a second set of output bits, and the first set of output bits represents a High-bit data, the second set of output bits representing low-bit data, and the method for generating a polarization code further comprises: providing the first set of output bits through a first polarization matrix of the polarization matrices; and The second set of output bits is provided through a second polarization matrix of the polarization matrices.

如申請專利範圍第1項所述之極化碼產生方法，其中該些第一輸出位元包括一第一組輸出位元、一第二組輸出位元以及一第三組輸出位元，該第一組輸出位元表示至少一三階記憶胞的高位元資料，該第二組輸出位元表示該至少一三階記憶胞的中位元資料，該第三組輸出位元表示該至少一三階記憶胞的低位元資料，該極化碼產生方法更包括：透過該些極化矩陣中的一第一極化矩陣提供該第一組輸出位元；透過該些極化矩陣中的一第二極化矩陣提供該第二組輸出位元；以及透過該些極化矩陣中的一第三極化矩陣提供該第三組輸出位元。The method for generating a polar code according to item 1 of the scope of patent application, wherein the first output bits include a first set of output bits, a second set of output bits, and a third set of output bits. The first set of output bits represents the high-order data of at least one third-order memory cell, the second set of output bits represents the median data of the at least one third-order memory cell, and the third set of output bits represents the at least one The low-order data of the third-order memory cell, and the method for generating the polarization code further includes: providing the first set of output bits through a first polarization matrix of the polarization matrices; and passing one of the polarization matrices The second polarization matrix provides the second set of output bits; and the third polarization matrix provides a third set of output bits through a third polarization matrix.

如申請專利範圍第1項所述之極化碼產生方法，其中該些第一輸出位元包括一第一組輸出位元以及一第二組輸出位元，該第一組輸出位元的位元數量與該第二組輸出位元的位元數量相異，該極化碼產生方法更包括：透過該些極化矩陣中的一第一極化矩陣提供該第一組輸出位元；以及透過該些極化矩陣中的一第二極化矩陣提供該第二組輸出位元。The method of generating a polar code according to item 1 of the scope of patent application, wherein the first output bits include a first set of output bits and a second set of output bits, and the bits of the first set of output bits The number of elements is different from the number of bits of the second set of output bits. The method for generating a polarization code further includes: providing the first set of output bits through a first polarization matrix of the polarization matrices; and The second set of output bits is provided through a second polarization matrix of the polarization matrices.

如申請專利範圍第1項所述之極化碼產生方法，其中該些第二輸出位元的該剩餘部分的位元數量與該至少一待強化輸入通道的通道數量相同，該些第二輸出位元的該剩餘部分的位元數量為q，該再極化矩陣的該些第二輸入通道的通道數量為2q，其中q為正整數，且該些第二輸出位元的該剩餘部分係作為凍結位元。The method for generating a polar code according to item 1 of the scope of patent application, wherein the number of bits of the remaining portion of the second output bits is the same as the number of channels of the at least one input channel to be enhanced, and the second outputs The number of bits of the remaining portion of the bit is q, and the number of channels of the second input channels of the repolarization matrix is 2q, where q is a positive integer, and the remaining portion of the second output bits is As a frozen bit.

一種非暫態電腦可讀取儲存媒體，該非暫態電腦可讀取儲存媒體儲存一或多個指令，該一或多個指令可供一處理器執行，以使包括該處理器的一電子裝置執行如申請專利範圍第1項所述之極化碼產生方法之操作。A non-transitory computer-readable storage medium stores one or more instructions. The one or more instructions can be executed by a processor to enable an electronic device including the processor. Perform the operation of the method for generating a polar code as described in item 1 of the scope of patent application.

一種電子裝置，包括：一記憶體，儲存至少一指令；以及一處理器，耦接該記憶裝置，該處理器執行該至少一指令而用以：建立複數個極化矩陣，該些極化矩陣經由複數個第一輸入通道接收複數個第一輸入位元，並對該些第一輸入位元進行一第一極化編碼，以透過複數個第一輸出通道提供複數個第一輸出位元；從該些極化矩陣的該些第一輸入通道中，挑選至少一待強化輸入通道；提供一再極化矩陣，該再極化矩陣經由複數個第二輸入通道接收複數個第二輸入位元，並對該些第二輸入位元進行一第二極化編碼，以透過複數個第二輸出通道提供複數個第二輸出位元，該些第二輸出位元中的一部分係作為提供至該至少一待強化輸入通道的第一輸出位元；以及提供一極化碼，該極化碼包括該些第一輸出位元以及該些第二輸出位元的一剩餘部分；其中，該些極化矩陣的各該些第一輸出位元分別用以表示一邏輯資料頁的資料。An electronic device includes: a memory storing at least one instruction; and a processor coupled to the memory device, the processor executing the at least one instruction for: establishing a plurality of polarization matrices, the polarization matrices Receiving a plurality of first input bits via a plurality of first input channels, and performing a first polarization encoding on the first input bits to provide a plurality of first output bits through the plurality of first output channels; Selecting at least one input channel to be strengthened from the first input channels of the polarization matrices; providing a repolarization matrix that receives a plurality of second input bits via a plurality of second input channels, And performing a second polarization encoding on the second input bits to provide a plurality of second output bits through the plurality of second output channels, and a part of the second output bits is provided to the at least A first output bit of an input channel to be strengthened; and providing a polarizing code, the polarizing code including the first output bits and a remaining portion of the second output bits; Each of the plurality of first output bits are used to represent a matrix of a logical data page of data.

如申請專利範圍第7項所述之電子裝置，其中該些第一輸出位元包括一第一組輸出位元以及一第二組輸出位元，該第一組輸出位元表示至少一多階記憶胞的高位元資料，該第二組輸出位元表示該至少一多階記憶胞的低位元資料，該處理器更用以：透過該些極化矩陣中的一第一極化矩陣提供該第一組輸出位元；以及透過該些極化矩陣中的一第二極化矩陣提供該第二組輸出位元。The electronic device according to item 7 of the scope of patent application, wherein the first output bits include a first set of output bits and a second set of output bits, and the first set of output bits represents at least one multi-order High bit data of the memory cell, the second set of output bits representing the low bit data of the at least one multi-level memory cell, the processor is further configured to provide the data through a first polarization matrix of the polarization matrices A first set of output bits; and providing a second set of output bits through a second polarization matrix of the polarization matrices.

如申請專利範圍第7項所述之電子裝置，其中該些第一輸出位元包括一第一組輸出位元、一第二組輸出位元以及一第二組輸出位元，該第一組輸出位元表示至少一三階記憶胞的高位元資料，該第二組輸出位元表示該至少一三階記憶胞的中位元資料，該第三組輸出位元表示該至少一三階記憶胞的低位元資料，該處理器更用以：透過該些極化矩陣中的一第一極化矩陣提供該第一組輸出位元；透過該些極化矩陣中的一第二極化矩陣提供該第二組輸出位元；以及透過該些極化矩陣中的一第三極化矩陣提供該第三組輸出位元。The electronic device according to item 7 of the scope of patent application, wherein the first output bits include a first set of output bits, a second set of output bits, and a second set of output bits. The first set of bits The output bits represent the high-order data of at least one third-order memory cell, the second set of output bits represent the median data of the at least one third-order memory cell, and the third set of output bits represent the at least one third-order memory Low-bit data of the cell, the processor is further configured to: provide the first set of output bits through a first polarization matrix in the polarization matrices; through a second polarization matrix in the polarization matrices Providing the second set of output bits; and providing the third set of output bits through a third polarization matrix of the polarization matrices.

如申請專利範圍第7項所述之電子裝置，其中該些第一輸出位元包括一第一組輸出位元以及一第二組輸出位元，該第一組輸出位元的位元數量與該第二組輸出位元的位元數量相異，該處理器更用以：透過該些極化矩陣中的一第一極化矩陣提供該第一組輸出位元；以及透過該些極化矩陣中的一第二極化矩陣提供該第二組輸出位元；其中該些第二輸出位元的該剩餘部分的位元數量與該至少一待強化輸入通道的通道數量相同，該些第二輸出位元的該剩餘部分的位元數量為q，該再極化矩陣的該些第二輸入通道的通道數量為2q，其中q為正整數，且該些第二輸出位元的該剩餘部分係作為凍結位元。The electronic device according to item 7 of the scope of patent application, wherein the first output bits include a first set of output bits and a second set of output bits, and the number of bits of the first set of output bits and The number of bits of the second set of output bits is different, and the processor is further configured to: provide the first set of output bits through a first polarization matrix of the polarization matrices; and pass through the polarizations A second polarization matrix in the matrix provides the second set of output bits; wherein the number of bits of the remaining portion of the second output bits is the same as the number of channels of the at least one input channel to be enhanced, and the first The number of bits of the remaining portion of the two output bits is q, and the number of channels of the second input channels of the repolarization matrix is 2q, where q is a positive integer, and the remaining of the second output bits is Some are used as frozen bits.