TWI665860B - System controller and method for regulating power converter - Google Patents

System controller and method for regulating power converter Download PDF

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Publication number
TWI665860B
TWI665860B TW106140199A TW106140199A TWI665860B TW I665860 B TWI665860 B TW I665860B TW 106140199 A TW106140199 A TW 106140199A TW 106140199 A TW106140199 A TW 106140199A TW I665860 B TWI665860 B TW I665860B
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threshold
input signal
predetermined duration
signal
longer
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TW106140199A
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Chinese (zh)
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TW201907651A (en
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曹亞明
羅強
林元
方烈義
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昂寶電子（上海）有限公司
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

公開了用於調節電源變換器的系統控制器和方法。例如，該系統控制器包括第一控制器端子和第二控制器端子。該系統控制器被配置為在第一控制器端子處接收輸入信號，並至少部分基於輸入信號在第二控制器端子處生成驅動信號，以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流。另外，該系統控制器還被配置為確定輸入信號在等於或長於第一預定持續時間的第一時段內是否保持大於第一閾值。 A system controller and method for regulating a power converter are disclosed. For example, the system controller includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a driving signal at a second controller terminal based at least in part on the input signal to turn on or off the transistor to affect the power converter The current associated with the secondary winding. In addition, the system controller is further configured to determine whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration.

Description

用於調節電源變換器的系統控制器和方法    System controller and method for regulating power converter   

本發明涉及積體電路。更具體地，本發明提供了利用輸出感測和同步整流方案的系統和方法。僅通過示例，本發明已經應用於電源變換系統。但是將認識到，本發明具有更寬的應用範圍。 The invention relates to an integrated circuit. More specifically, the present invention provides systems and methods that utilize output sensing and synchronous rectification schemes. By way of example only, the present invention has been applied to a power conversion system. However, it will be recognized that the invention has a wider range of applications.

第1圖是示出了傳統返馳式電源變換系統的簡化圖。該電源變換系統100包括：一次繞組110、二次繞組112、功率開關120、電流感測電阻器122、整流二極體124、電容器126、隔離回饋組件128、以及控制器102。控制器102包括：欠壓鎖定元件104、脈衝寬度調變發生器106、閘極驅動器108、前沿消隱(Leading Edge Blanking,LEB)元件116、以及過流保護(Over Current Protection,OCP)元件114。例如，功率開關120是雙極型電晶體。在另一示例中，功率開關120是場效應電晶體。 FIG. 1 is a simplified diagram showing a conventional flyback power conversion system. The power conversion system 100 includes a primary winding 110, a secondary winding 112, a power switch 120, a current sensing resistor 122, a rectifying diode 124, a capacitor 126, an isolation feedback component 128, and a controller 102. The controller 102 includes: an undervoltage lockout element 104, a pulse width modulation generator 106, a gate driver 108, a leading edge blanking (LEB) element 116, and an over current protection (OCP) element 114 . For example, the power switch 120 is a bipolar transistor. In another example, the power switch 120 is a field effect transistor.

電源變換系統100實現了包括一次繞組110和二次繞組112的變壓器，以使一次側上的AC輸入電壓190和二次側上的輸出電壓192相隔離。隔離回饋元件128處理關於輸出電壓192的資訊並生成回饋信號136。控制器102接收回饋信號136並生成閘極驅動信號(Gate)130，以接通和關斷開關120從而調節輸出電壓192。例如，隔離回饋元件128包括：誤差放大器、補償網路、和光耦合器。 The power conversion system 100 implements a transformer including a primary winding 110 and a secondary winding 112 to isolate the AC input voltage 190 on the primary side and the output voltage 192 on the secondary side. The isolated feedback element 128 processes the information about the output voltage 192 and generates a feedback signal 136. The controller 102 receives the feedback signal 136 and generates a gate driving signal (Gate) 130 to turn on and off the switch 120 to adjust the output voltage 192. For example, the isolated feedback element 128 includes an error amplifier, a compensation network, and an optocoupler.

雖然返馳式電源變換系統100可被用於輸出電壓調節，但是在沒有高成本的附加電路的情況下，電源變換系統100經常不能獲得好的輸出電流控制。此外，在二次側中所需的輸出電流感測電阻器通常降低了電源變換系統100的效率。 Although the flyback power conversion system 100 can be used for output voltage regulation, the power conversion system 100 often cannot obtain good output current control without high-cost additional circuits. In addition, the output current sensing resistor required in the secondary side generally reduces the efficiency of the power conversion system 100.

第2A圖是示出了另一傳統返馳式電源變換系統的簡化圖。該電源變換系統200包括：系統控制器202、一次繞組210、二次繞組212、輔助繞組214、功率開關220、電流感測電阻器230、兩個整流二極體260和262、兩個電容器264和266、以及兩個電阻器268和270。例如，功率開關220是雙極型電晶體。在另一示例中，功率開關220是MOS電晶體。 FIG. 2A is a simplified diagram showing another conventional flyback power conversion system. The power conversion system 200 includes a system controller 202, a primary winding 210, a secondary winding 212, an auxiliary winding 214, a power switch 220, a current sensing resistor 230, two rectifying diodes 260 and 262, and two capacitors 264. And 266, and two resistors 268 and 270. For example, the power switch 220 is a bipolar transistor. In another example, the power switch 220 is a MOS transistor.

關於輸出電壓250的資訊可通過輔助繞組214提取以便調節輸出電壓250。當功率開關220閉合(例如，接通)時，能量被存儲在包括一次繞組210和二次繞組212的變壓器中。然後，當功率開關220斷開(例如，關斷)時，存儲的能量被釋放到二次側，並且輔助繞組214的電壓映射二次側上的輸出電壓。系統控制器202接收指示流過一次繞組210的一次電流276的電流感測信號272、和關於二次側的退磁過程的回饋信號274。例如，開關220的開關週期包括開關220閉合(例如，接通)的接通時間段和開關220斷開(例如，關斷)的關斷時間段。 Information about the output voltage 250 can be extracted through the auxiliary winding 214 to adjust the output voltage 250. When the power switch 220 is closed (eg, turned on), energy is stored in a transformer including a primary winding 210 and a secondary winding 212. Then, when the power switch 220 is turned off (eg, turned off), the stored energy is released to the secondary side, and the voltage of the auxiliary winding 214 maps the output voltage on the secondary side. The system controller 202 receives a current sensing signal 272 indicating a primary current 276 flowing through the primary winding 210 and a feedback signal 274 regarding a demagnetization process on the secondary side. For example, the switching period of the switch 220 includes an on period during which the switch 220 is closed (eg, on) and an off period during which the switch 220 is off (eg, off).

第2B圖是以斷續傳導模式(Discontinuous Conduction Mode,DCM)操作的返馳式電源變換系統200的簡化傳統時序圖。波形292表示作為時間函數的輔助繞組214的電壓254，而波形294表示作為時間函數的流過二次繞組212的第二電流278。 FIG. 2B is a simplified conventional timing diagram of the flyback power conversion system 200 operating in a discontinuous conduction mode (DCM). A waveform 292 represents the voltage 254 of the auxiliary winding 214 as a function of time, and a waveform 294 represents a second current 278 flowing through the secondary winding 212 as a function of time.

例如，如第2B圖所示，開關220的開關週期Ts開始於時刻t0，結束於時刻t3；接通時間段Ton開始於時刻t0，結束於時刻t1；退磁時段Tdemag開始於時刻t1，結束於時刻t2；關斷時間段Toff開始於時刻t1，結束於時刻t3。在另一示例中，t0 t1 t2 t3。在DCM中，關斷時間段Toff大大長於退磁時段Tdemag。 For example, as shown in FIG. 2B, the switching period T s of the switch 220 starts at time t 0 and ends at time t 3 ; the on time period T on starts at time t 0 and ends at time t 1 ; the demagnetization period T demag It starts at time t 1 and ends at time t 2 ; the off-time period T off starts at time t 1 and ends at time t 3 . In another example, t 0 t 1 t 2 t 3 . In DCM, the off-time period T off is much longer than the demagnetization period T demag .

在退磁時段Tdemag期間，開關220保持斷開，一次電流276保持在低值(例如，接近零)。二次電流278從值296(例如，在t1處)下降，如波形294所示。退磁過程在二次電流278具有低值298(例如，接近零)的時刻t2結束。二次電流278在開關週期的剩餘部分保持在 值298處。下一個開關週期直到退磁過程完成之後一段時間(例如，在t3處)才開始。 During the demagnetization period T demag , the switch 220 remains open, and the primary current 276 remains at a low value (eg, near zero). The secondary current 278 decreases from the value 296 (for example, at t 1 ), as shown by the waveform 294. The demagnetization process ends at time t 2 when the secondary current 278 has a low value of 298 (eg, near zero). The secondary current 278 remains at the value 298 for the remainder of the switching cycle. The next switching cycle does not begin until some time after the demagnetization process is complete (for example, at t 3 ).

如第1圖和第2A圖所示，電源變換系統100和電源變換系統200中的每個電源變換系統在二次側使用整流二極體(例如，第1圖中的二極體124和圖2中的二極體260)來整流。整流二極體的正向電壓通常在0.3V-0.8V的範圍內。該正向電壓在操作中經常導致顯著的功率損耗，從而導致電源變換系統的低效。例如，當電源變換系統具有5V/1A的輸出位準時，具有0.3V-0.4V的正向電壓的整流二極體在滿載(例如，1A)下導致大約0.3W-0.4W的功率損耗。系統效率的降低大約是4%-6%。 As shown in FIGS. 1 and 2A, each of the power conversion system 100 and the power conversion system 200 uses a rectifying diode on the secondary side (for example, the diode 124 and the figure in FIG. 1). 2 diode 260) to rectify. The forward voltage of the rectified diode is usually in the range of 0.3V-0.8V. This forward voltage often results in significant power loss during operation, resulting in inefficient power conversion systems. For example, when the power conversion system has an output level of 5V / 1A, a rectified diode with a forward voltage of 0.3V-0.4V causes a power loss of about 0.3W-0.4W at full load (eg, 1A). The reduction in system efficiency is approximately 4% -6%.

此外，為了使電源變換系統200獲得較低的待機功率損耗，開關頻率經常保持較低以降低無載或輕載條件下的開關損耗。但是，當電源變換系統200從無載/輕載條件變為滿載條件時，輸出電壓250可能突然下降，並且該電壓下降可能不會被系統控制器202立刻感測到，因為系統控制器202通常只在每個開關週期的退磁過程中能夠感測輸出電壓。因此，電源變換系統200的動態性能在無載/輕載條件下的低開關頻率處經常不能令人滿意。例如，電源變換系統200具有5V/1A的輸出位準，並且輸出電容器264具有1000μF的電容。在無載/輕載條件下，開關頻率是1kHz，對應於1ms的開關週期。如果輸出負載從無載/輕載條件(例如，0A)變為滿載條件(例如，1A)，則輸出電壓250下降1V(例如，從5V到4V)，這在某些應用中通常是不能接受的。 In addition, in order to obtain a lower standby power loss for the power conversion system 200, the switching frequency is often kept low to reduce the switching loss under no-load or light-load conditions. However, when the power conversion system 200 changes from a no-load / light-load condition to a full-load condition, the output voltage 250 may drop suddenly, and the voltage drop may not be immediately sensed by the system controller 202, because the system controller 202 usually The output voltage can only be sensed during the demagnetization of each switching cycle. Therefore, the dynamic performance of the power conversion system 200 is often unsatisfactory at low switching frequencies under no-load / light-load conditions. For example, the power conversion system 200 has an output level of 5V / 1A, and the output capacitor 264 has a capacitance of 1000 μF. Under no-load / light-load conditions, the switching frequency is 1kHz, which corresponds to a switching period of 1ms. If the output load changes from no-load / light-load condition (for example, 0A) to full-load condition (for example, 1A), the output voltage 250 drops by 1V (for example, from 5V to 4V), which is generally unacceptable in some applications of.

第3圖是示出具有二次同步整流器(Synchronous Rectifier,SR)的傳統電源變換系統的簡化圖。該電源變換系統2300(例如，返馳式電源變換器)包括：一次側脈衝寬度調變(Pulse Width Modulation,PWM)控制器2302、一次繞組2304、二次繞組2306、二次側同步整流器(SR)控制器2308、電晶體2310(例如，Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)、輸出電容性負載2312、 輸出電阻性負載2314、以及功率開關2330(例如，電晶體)。二次側同步整流器(SR)控制器2308包括端子2390、2392、2394、和2396。 FIG. 3 is a simplified diagram showing a conventional power conversion system having a secondary synchronous rectifier (SR). The power conversion system 2300 (eg, a flyback power converter) includes a primary-side pulse width modulation (PWM) controller 2302, a primary winding 2304, a secondary winding 2306, and a secondary-side synchronous rectifier (SR ) Controller 2308, transistor 2310 (for example, Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), output capacitive load 2312 Outputs a resistive load 2314, and a power switch 2330 (eg, a transistor). The secondary-side synchronous rectifier (SR) controller 2308 includes terminals 2390, 2392, 2394, and 2396.

如第3圖中所示，端子2390接收指示電晶體2310的端子2364(例如，電晶體2310的汲極端子)處的電壓的電壓信號2362，並且端子2392向電晶體2310(例如，MOSFET)輸出驅動信號2366。另外，端子2394接收指示輸出電壓的電壓信號2316，其中，輸出電壓由輸出電容性負載2312和輸出電阻性負載2314接收。另外，端子2396被偏置到二次側地。 As shown in FIG. 3, the terminal 2390 receives a voltage signal 2362 indicating the voltage at the terminal 2364 (for example, the drain terminal of the transistor 2310) of the transistor 2310, and the terminal 2392 outputs to the transistor 2310 (for example, a MOSFET) Driving signal 2366. In addition, the terminal 2394 receives a voltage signal 2316 indicating an output voltage, wherein the output voltage is received by the output capacitive load 2312 and the output resistive load 2314. In addition, the terminal 2396 is biased to the secondary ground.

一次側脈衝寬度調變(PWM)控制器2302生成驅動信號2332(例如，Vg1)並且將驅動信號2332輸出到功率開關2330(例如，電晶體)，二次側同步整流器(SR)控制器2308生成驅動信號2366(例如，Vg)並將驅動信號2366輸出到電晶體2310(例如，MOSFET)。 The primary-side pulse width modulation (PWM) controller 2302 generates a driving signal 2332 (for example, V g1 ) and outputs the driving signal 2332 to a power switch 2330 (for example, a transistor), and a secondary-side synchronous rectifier (SR) controller 2308 A driving signal 2366 (for example, V g ) is generated and output to the transistor 2310 (for example, a MOSFET).

在二次側同步整流器(SR)控制系統中，電晶體2310的接通延遲通常需要被最小化，以避免任何顯著的退磁電流流過電晶體2310的體二極體。電晶體2310的接通延遲的最小化通常對於高效和/或高功率密度的系統是非常重要的。另一方面，為了避免電晶體2310被雜訊或擾動無意接通，通常對於二次控制器2308非常重要的是在接通電晶體2310之前通過添加去抖動時間而濾除雜訊或擾動。 In a secondary-side synchronous rectifier (SR) control system, the turn-on delay of the transistor 2310 generally needs to be minimized to avoid any significant demagnetizing current flowing through the body diode of the transistor 2310. Minimization of the on-delay of transistor 2310 is often very important for efficient and / or high power density systems. On the other hand, in order to prevent the transistor 2310 from being unintentionally turned on by noise or disturbance, it is usually very important for the secondary controller 2308 to filter out noise or disturbance by adding a debounce time before turning on the transistor 2310.

二次側同步整流器(SR)控制器2308包括電壓感測器2320、邏輯控制器2322、以及驅動器2324。二次側同步整流器(SR)控制器2308感測指示電晶體2310的端子2364(例如，電晶體2310的汲極端子)處的電壓的電壓信號2362(例如，Vd)，並且提供決定電晶體2310的接通或關斷的驅動信號2366(例如，Vg)。最初，電晶體2310由於驅動信號2366(例如，電壓Vg)等於零或者電壓信號2362(例如，Vd)大於零而關斷。在正常操作下，當一次側脈衝寬度調變(PWM)控制器2302斷開(例如，關斷)功率開關2330(例如，電晶體)時，電壓信號2362(例如，Vd)迅速降低。在電壓信號2362(例如，Vd)變得小 於閾值電壓後，二次側同步整流器(SR)控制器2308通過將驅動電壓2366(例如，Vd)拉高來接通電晶體2310。通常，雜訊或擾動通過變壓器從AC線路耦合到電壓信號2362。 The secondary-side synchronous rectifier (SR) controller 2308 includes a voltage sensor 2320, a logic controller 2322, and a driver 2324. The secondary-side synchronous rectifier (SR) controller 2308 senses a voltage signal 2362 (eg, V d ) indicating a voltage at the terminal 2364 (eg, the drain terminal of the transistor 2310) of the transistor 2310, and provides a decision transistor Drive signal 2366 (eg, V g ) of 2310 on or off. Initially, the transistor 2310 is turned off because the driving signal 2366 (for example, the voltage V g ) is equal to zero or the voltage signal 2362 (for example, V d ) is greater than zero. Under normal operation, when the primary-side pulse width modulation (PWM) controller 2302 turns off (eg, turns off) the power switch 2330 (eg, a transistor), the voltage signal 2362 (eg, V d ) decreases rapidly. After the voltage signal 2362 (for example, V d ) becomes smaller than the threshold voltage, the secondary-side synchronous rectifier (SR) controller 2308 turns on the transistor 2310 by pulling the driving voltage 2366 (for example, V d ) high. Generally, noise or disturbance is coupled from the AC line to the voltage signal 2362 through a transformer.

因此，非常期望改善用於電源變換系統的整流和輸出感測的技術。 Therefore, it is highly desirable to improve the technology of rectification and output sensing for power conversion systems.

本發明涉及積體電路。更具體地，本發明提供了利用輸出感測和同步整流方案的系統和方法。僅通過示例，本發明已經應用於電源變換系統。但是將認識到，本發明具有更寬的應用範圍。 The invention relates to an integrated circuit. More specifically, the present invention provides systems and methods that utilize output sensing and synchronous rectification schemes. By way of example only, the present invention has been applied to a power conversion system. However, it will be recognized that the invention has a wider range of applications.

但應認識到，本發明具有更廣泛的適用範圍。 However, it should be recognized that the present invention has a wider scope of application.

根據一個實施例，用於調節電源變換系統的系統控制器包括第一控制器端子和第二控制器端子。該系統控制器被配置為在第一控制器端子接收至少輸入信號，並且基於至少與該輸入信號相關聯的資訊，在第二控制器端子生成閘極驅動信號，以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。該系統控制器還被配置為：如果輸入信號大於第一閾值，則生成處於第一邏輯位準的閘極驅動信號以關斷電晶體，而如果輸入信號從大於第二閾值的第一值變為小於第二閾值的第二值，則將閘極驅動信號從第一邏輯位準變為第二邏輯位準以接通電晶體。 According to one embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. The system controller is configured to receive at least an input signal at a first controller terminal and generate a gate drive signal at a second controller terminal based on information associated with at least the input signal to turn the transistor on or off This affects the current associated with the secondary winding of the power conversion system. The system controller is further configured to generate a gate driving signal at a first logic level to turn off the transistor if the input signal is greater than a first threshold, and change the input signal from a first value greater than a second threshold to change the input signal. If the second value is smaller than the second threshold, the gate driving signal is changed from the first logic level to the second logic level to turn on the transistor.

根據另一實施例，用於調節電源變換系統的系統控制器包括第一控制器端子和第二控制器端子。該系統控制器被配置為在第一控制器端子接收至少輸入信號，該輸入信號正比於與電源變換系統的二次繞組相關聯的輸出電壓，並且基於至少與輸入信號相關聯的資訊，在第二控制器端子生成閘極驅動信號，以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。該系統控制器還被配置為：只有輸入信號從大於第一閾值的第一值變為小於第一閾值的第二值時，才生成閘極驅動信號的脈衝以在與該脈衝相關聯的脈衝時段期間接通電晶體。 According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. The system controller is configured to receive at least an input signal at a first controller terminal, the input signal being proportional to an output voltage associated with a secondary winding of the power conversion system, and based on at least information associated with the input signal, at the first The two controller terminals generate a gate drive signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system. The system controller is further configured to generate a pulse of the gate drive signal only when the input signal changes from a first value greater than a first threshold value to a second value less than the first threshold value to a pulse associated with the pulse. The transistor is turned on during the period.

根據另一實施例，用於調節電源變換系統的系統控制器包括第一比較器、信號感測器和驅動元件。第一比較器被配置為接收輸入信號，並基於至少與輸入信號相關聯的資訊輸出第一比較信號。信號感測器被配置為接收輸入信號，並基於至少與輸入信號相關聯的資訊輸出第一感測信號。驅動元件被配置為基於至少與第一比較信號和第一感測信號相關聯的資訊輸出閘極驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。比較器還被配置為確定輸入信號是否大於第一閾值。信號感測器還被配置為確定輸入信號是否從大於第二閾值的第一值變為小於第二閾值的第二值。驅動元件還被配置為：如果第一比較信號指示輸入信號大於第一閾值，則生成處於第一邏輯位準的閘極驅動信號以關斷電晶體，而如果第一感測信號指示輸入信號從大於第二閾值的第一值變為小於第二閾值的第二值，則將閘極驅動信號從第一邏輯位準變為第二邏輯位準以接通電晶體。 According to another embodiment, a system controller for adjusting a power conversion system includes a first comparator, a signal sensor, and a driving element. The first comparator is configured to receive an input signal and output a first comparison signal based on information associated with at least the input signal. The signal sensor is configured to receive an input signal and output a first sensing signal based on at least information associated with the input signal. The driving element is configured to output the gate driving signal to turn on or off the transistor based on the information associated with at least the first comparison signal and the first sensing signal to affect the current associated with the secondary winding of the power conversion system. The comparator is further configured to determine whether the input signal is greater than a first threshold. The signal sensor is further configured to determine whether the input signal changes from a first value greater than a second threshold value to a second value less than the second threshold value. The driving element is further configured to: if the first comparison signal indicates that the input signal is greater than a first threshold value, generate a gate driving signal at a first logic level to turn off the transistor, and if the first sensing signal indicates that the input signal is from If the first value larger than the second threshold becomes the second value smaller than the second threshold, the gate driving signal is changed from the first logic level to the second logic level to turn on the transistor.

在一個實施例中，用於調節電源變換系統的系統控制器包括比較器、脈衝信號發生器和驅動元件。比較器被配置為接收輸入信號，並基於至少與輸入信號相關聯的資訊輸出比較信號。脈衝信號發生器被配置為接收至少比較信號，並基於至少與該比較信號相關聯的資訊生成脈衝信號。驅動元件被配置為接收脈衝信號，並基於至少與該脈衝信號相關聯的資訊生成閘極驅動信號，以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。比較器還被配置為確定輸入信號是大於還是小於閾值。脈衝信號發生器還被配置為：只有在比較信號指示輸入信號從大於閾值的第一值變為小於閾值的第二值時，才生成脈衝信號的第一脈衝。驅動元件還被配置為：回應於脈衝信號的第一脈衝，生成閘極驅動信號的第二脈衝以在與第二脈衝相關聯的脈衝時段中接通電晶體。 In one embodiment, a system controller for regulating a power conversion system includes a comparator, a pulse signal generator, and a driving element. The comparator is configured to receive an input signal and output a comparison signal based on information associated with at least the input signal. The pulse signal generator is configured to receive at least a comparison signal and generate a pulse signal based on at least information associated with the comparison signal. The driving element is configured to receive a pulse signal and generate a gate driving signal based on at least information associated with the pulse signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system. The comparator is also configured to determine whether the input signal is greater than or less than a threshold. The pulse signal generator is further configured to generate a first pulse of the pulse signal only when the comparison signal indicates that the input signal changes from a first value greater than a threshold value to a second value less than the threshold value. The driving element is further configured to generate a second pulse of the gate driving signal in response to the first pulse of the pulse signal to turn on the transistor in a pulse period associated with the second pulse.

在另一實施例中，用於調節電源變換系統的方法包括：接收至少輸入信號，處理與該輸入信號相關聯的資訊，並基於至少與該輸入信號相關聯的資訊生成閘極驅動信號，以接通或關斷電晶體從而影響與 電源變換系統的二次繞組相關聯的電流。基於至少與該輸入信號相關聯的資訊生成閘極驅動信號，以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流的過程包括：如果輸入信號大於第一閾值，則生成處於第一邏輯位準的閘極驅動信號以關斷電晶體，而如果輸入信號從大於第二閾值的第一值變為小於第二閾值的第二值，則將閘極驅動信號從第一邏輯位準變為第二邏輯位準以接通電晶體。 In another embodiment, a method for adjusting a power conversion system includes receiving at least an input signal, processing information associated with the input signal, and generating a gate driving signal based on the information associated with at least the input signal, to Turn the transistor on or off to affect the Current associated with the secondary winding of the power conversion system. The process of generating a gate driving signal based on at least information associated with the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: if the input signal is greater than a first threshold, A gate drive signal at a first logic level is generated to turn off the transistor, and if the input signal changes from a first value greater than a second threshold to a second value less than a second threshold, the gate drive signal is changed from The first logic level becomes the second logic level to turn on the transistor.

在另一實施例中，用於調節電源變換系統的方法包括：接收至少輸入信號，該輸入信號正比於與電源變換系統的二次繞組相關聯的輸出電壓，處理與該輸入信號相關聯的資訊，並基於至少與該輸入信號相關聯的資訊生成閘極驅動信號，以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。基於至少與該輸入信號相關聯的資訊生成閘極驅動信號，以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流的過程包括：只有在輸入信號從大於第一閾值的第一值變為小於第一閾值的第二值時，才生成閘極驅動信號的脈衝以在與該脈衝相關聯的脈衝時段期間接通電晶體。 In another embodiment, a method for adjusting a power conversion system includes: receiving at least an input signal that is proportional to an output voltage associated with a secondary winding of the power conversion system, and processing information associated with the input signal And generate a gate drive signal based on at least information associated with the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system. The process of generating a gate drive signal based on information associated with at least the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: only when the input signal changes from greater than the first When the first value of the threshold value becomes a second value less than the first threshold value, a pulse of the gate drive signal is generated to turn on the transistor during the pulse period associated with the pulse.

在另一實施例中，用於調節電源變換系統的方法包括：接收輸入信號，處理與輸入信號相關聯的資訊，並確定輸入信號是否大於第一閾值。該方法還包括：基於至少與輸入信號相關聯的資訊生成比較信號，確定輸入信號是否從大於第二閾值的第一值變為小於第二閾值的第二值，並基於至少與輸入信號相關聯的資訊生成感測信號。此外，該方法包括：基於至少與比較信號和感測信號相關聯的資訊輸出閘極驅動信號，以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。基於至少與比較信號和感測信號相關聯的資訊輸出閘極驅動信號，以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流的過程包括：如果比較信號指示輸入信號大於第一閾值，則生成處於第一邏輯位準的閘極驅動信號以關斷電晶體，而如果感測信號指示輸入信號從大於第二 閾值的第一值變為小於第二閾值的第二值，則將閘極驅動信號從第一邏輯位準變為第二邏輯位準以接通電晶體。 In another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and determining whether the input signal is greater than a first threshold. The method further includes generating a comparison signal based on at least information associated with the input signal, determining whether the input signal has changed from a first value greater than a second threshold value to a second value less than a second threshold value, and based on at least being associated with the input signal. Information generated by the sensor. In addition, the method includes outputting a gate drive signal based on information associated with at least the comparison signal and the sensing signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system. The process of outputting the gate drive signal based on the information associated with at least the comparison signal and the sensing signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: if the comparison signal indicates an input If the signal is greater than the first threshold, a gate driving signal at a first logic level is generated to turn off the transistor, and if the sensing signal indicates that the input signal is greater than a second When the first value of the threshold value becomes a second value smaller than the second threshold value, the gate driving signal is changed from the first logic level to the second logic level to turn on the transistor.

在另一實施例中，用於調節電源變換系統的方法包括：接收輸入信號，處理與輸入信號相關聯的資訊，並確定輸入信號是大於還是小於閾值。該方法還包括：基於至少與第一輸入信號相關聯的資訊生成比較信號，接收比較信號，並處理與比較信號相關聯的資訊。此外，該方法包括：基於至少與比較信號相關聯的資訊生成脈衝信號，接收脈衝信號，處理與該脈衝信號相關聯的資訊，並基於至少與該脈衝信號相關聯的資訊生成閘極驅動信號，以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。基於至少與比較信號相關聯的資訊生成脈衝信號的過程包括：只有比較信號指示輸入信號從大於閾值的第一值變為小於閾值的第二值時，才生成脈衝信號的第一脈衝。基於至少與該脈衝信號相關聯的資訊生成閘極驅動信號，以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流的過程包括：回應於脈衝信號的第一脈衝，生成閘極驅動信號的第二脈衝以在與第二脈衝相關聯的脈衝時段期間接通電晶體。 In another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and determining whether the input signal is greater than or less than a threshold. The method further includes generating a comparison signal based on information associated with at least the first input signal, receiving the comparison signal, and processing the information associated with the comparison signal. In addition, the method includes generating a pulse signal based on at least information associated with the comparison signal, receiving the pulse signal, processing the information associated with the pulse signal, and generating a gate driving signal based on at least information associated with the pulse signal, The transistor is turned on or off to affect the current associated with the secondary winding of the power conversion system. The process of generating a pulse signal based on at least information associated with the comparison signal includes generating a first pulse of the pulse signal only when the comparison signal indicates that the input signal changes from a first value greater than a threshold value to a second value less than the threshold value. The process of generating a gate drive signal based on information associated with at least the pulse signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: a first pulse in response to the pulse signal A second pulse of the gate drive signal is generated to turn on the transistor during a pulse period associated with the second pulse.

根據另一實施例，用於調節電源變換系統的系統控制器包括第一控制器端子和第二控制器端子。此外，該系統控制器被配置為在第一控制器端子接收輸入信號，並且至少部分基於該輸入信號，在第二控制器端子生成驅動信號，以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。此外，該系統控制器還被配置為：確定該輸入信號在第一時刻是否大於第一閾值；回應於該輸入信號被確定為在第一時刻大於第一閾值，確定該輸入信號在第二時刻是否小於第二閾值；並且回應於該輸入信號被確定為在第二時刻小於第二閾值，將第二控制器端子處的驅動信號從第一邏輯位準變為第二邏輯位準。此外，第二時刻在第一時刻之後。 According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. In addition, the system controller is configured to receive an input signal at a first controller terminal, and generate a drive signal at a second controller terminal based at least in part on the input signal to turn on or off the transistor to affect power conversion The current associated with the secondary winding of the system. In addition, the system controller is further configured to: determine whether the input signal is greater than a first threshold at a first moment; in response to the input signal being determined to be greater than a first threshold at a first moment, determine that the input signal is at a second moment Whether it is less than the second threshold; and in response to the input signal being determined to be less than the second threshold at the second moment, the driving signal at the second controller terminal is changed from the first logic level to the second logic level. In addition, the second time is after the first time.

根據另一實施例，用於調節電源變換系統的系統控制器包括第一控制器端子和第二控制器端子。此外，該系統控制器被配置為在第一控制器端子接收輸入信號，並且至少部分基於該輸入信號，在第二控制器端子生成驅動信號以接通或關斷電晶體，從而以影響與電源變換系統的二次繞組相關聯的電流。此外，該系統控制器還被配置為：確定該輸入信號是否在比預定持續時間更長的時間段內保持大於第一閾值，並且回應於該輸入信號被確定為在比預定持續時間更長的時間段內保持大於第一閾值，確定該輸入信號在該時間段之後的某時刻是否小於第二閾值。此外，該系統控制器還被配置為：回應於該輸入信號被確定為在該時刻小於第二閾值，將第二控制器端子處的驅動信號從第一邏輯位準變為第二邏輯位準。 According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. In addition, the system controller is configured to receive an input signal at the first controller terminal, and based at least in part on the input signal, generate a driving signal at the second controller terminal to turn the transistor on or off, thereby affecting the power supply Transform the current associated with the secondary winding of the system. In addition, the system controller is further configured to determine whether the input signal remains greater than the first threshold for a period of time longer than the predetermined duration, and in response to the input signal is determined to be longer than the predetermined duration It remains larger than the first threshold during the time period, and determines whether the input signal is less than the second threshold at a certain time after the time period. In addition, the system controller is further configured to: in response to the input signal being determined to be less than a second threshold at this time, change the driving signal at the terminal of the second controller from the first logic level to the second logic level .

根據另一實施例，用於調節電源變換系統的系統控制器包括第一控制器端子和第二控制器端子。此外，該系統控制器被配置為在第一控制器端子接收輸入信號，並且至少部分基於該輸入信號，在第二控制器端子生成驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。此外，該系統控制器還被配置為：確定從該輸入信號變得大於第一閾值的第一時刻到該輸入信號變得小於第二閾值的第二時刻的時間間隔是否比預定持續時間長，並且回應於該時間間隔被確定為比預定持續時間長，確定該輸入信號在該時間間隔之後的某時刻是否小於第三閾值。此外，該系統控制器還被配置為：回應於該輸入信號被確定為在該時刻小於第三閾值，將第二控制器端子處的驅動信號從第一邏輯位準變為第二邏輯位準。 According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. In addition, the system controller is configured to receive an input signal at the first controller terminal, and based at least in part on the input signal, generate a driving signal at the second controller terminal to turn on or off the transistor to affect the power conversion system Current associated with the secondary winding. In addition, the system controller is further configured to determine whether a time interval from a first moment when the input signal becomes greater than a first threshold to a second moment when the input signal becomes less than a second threshold is longer than a predetermined duration, And in response to the time interval being determined to be longer than a predetermined duration, it is determined whether the input signal is less than a third threshold at a certain time after the time interval. In addition, the system controller is further configured to: in response to the input signal being determined to be less than a third threshold at this time, change the driving signal at the second controller terminal from the first logic level to the second logic level .

根據另一實施例，用於調節電源變換系統的系統控制器包括第一控制器端子和第二控制器端子。此外，該系統控制器被配置為在第一控制器端子接收輸入信號，並且至少部分基於該輸入信號，在第二控制器端子生成驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。此外，該系統控制器還被配置為：確定該輸入信號 是否大於第一閾值；確定該輸入信號是否在比第一預定持續時間更長的時間段內保持大於第二閾值；並且確定從該輸入信號變得大於第三閾值的第一時刻到該輸入信號變得小於第四閾值的第二時刻的時間間隔是否比第二預定持續時間長。此外，該系統控制器還被配置為：回應於該輸入信號被確定為大於第一閾值、該輸入信號被確定為在比第一預定持續時間更長的時間段內保持大於第二閾值、或該時間間隔被確定為比第二預定持續時間長，確定該輸入信號是否小於第五閾值，並且回應於該輸入信號被確定為小於第五閾值，將第二控制器端子處的驅動信號從第一邏輯位準變為第二邏輯位準。 According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. In addition, the system controller is configured to receive an input signal at the first controller terminal, and based at least in part on the input signal, generate a driving signal at the second controller terminal to turn on or off the transistor to affect the power conversion system Current associated with the secondary winding. In addition, the system controller is configured to determine the input signal Whether it is greater than the first threshold; determining whether the input signal remains greater than the second threshold for a period of time longer than the first predetermined duration; and determining from the first moment when the input signal becomes greater than the third threshold to the input signal Whether the time interval of the second moment which becomes smaller than the fourth threshold is longer than the second predetermined duration. In addition, the system controller is further configured to: in response to the input signal being determined to be greater than the first threshold value, the input signal being determined to remain greater than the second threshold value for a time period longer than the first predetermined duration, or The time interval is determined to be longer than the second predetermined duration, it is determined whether the input signal is less than a fifth threshold, and in response to the input signal being determined to be less than a fifth threshold, the driving signal at the second controller terminal is removed from the first One logic level becomes the second logic level.

根據另一實施例，用於調節電源變換系統的方法包括：接收輸入信號，處理與該輸入信號相關聯的資訊，並至少部分基於該輸入信號生成驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。此外，處理與該輸入信號相關聯的資訊包括：確定該輸入信號在第一時刻是否大於第一閾值。此外，至少部分基於該輸入信號生成驅動信號，以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流包括：回應於該輸入信號被確定為在第一時刻大於第一閾值，確定該輸入信號在第二時刻是否小於第二閾值，並且回應於該輸入信號被確定為在第二時刻小於第二閾值，將驅動信號從第一邏輯位準變為第二邏輯位準。此外，第二時刻在第一時刻之後。 According to another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and generating a driving signal based on the input signal to turn on or off a transistor to affect The current associated with the secondary winding of the power conversion system. In addition, processing information associated with the input signal includes determining whether the input signal is greater than a first threshold at a first moment. In addition, generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: in response to the input signal being determined to be greater than the A threshold to determine whether the input signal is less than the second threshold at the second moment, and in response to the input signal being determined to be less than the second threshold at the second moment, the driving signal is changed from the first logic level to the second logic bit quasi. In addition, the second time is after the first time.

根據另一實施例，用於調節電源變換系統的方法包括：接收輸入信號，處理與該輸入信號相關聯的資訊，並至少部分基於該輸入信號生成驅動信號，以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。此外，處理與該輸入信號相關聯的資訊包括：確定該輸入信號是否在比預定持續時間更長的時間段內保持大於第一閾值。此外，至少部分基於該輸入信號生成驅動信號，以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流包括：回應於該輸入信號被確定為在比預定持續時間更長的時間段內保持大於第一閾值，確定該輸入信 號在該時間段之後的某時刻是否小於第二閾值，並且回應於該輸入信號被確定為在該時刻小於第二閾值，將驅動信號從第一邏輯位準變為第二邏輯位準。 According to another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and generating a driving signal based at least in part on the input signal to turn a transistor on or off to thereby Affects the current associated with the secondary winding of the power conversion system. In addition, processing information associated with the input signal includes determining whether the input signal remains greater than a first threshold for a period of time longer than a predetermined duration. In addition, generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: in response to the input signal being determined to be more than a predetermined duration Stays greater than the first threshold for a long period of time, determines the input message Whether the number is less than the second threshold at a certain time after the time period, and in response to the input signal being determined to be less than the second threshold at the time, the driving signal is changed from the first logic level to the second logic level.

根據另一實施例，用於調節電源變換系統的方法包括：接收輸入信號，處理與該輸入信號相關聯的資訊，並至少部分基於該輸入信號生成驅動信號，以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。此外，處理與該輸入信號相關聯的資訊包括：確定從該輸入信號變得大於第一閾值的第一時刻到該輸入信號變得小於第二閾值的第二時刻的時間間隔是否比預定持續時間長。此外，至少部分基於該輸入信號生成驅動信號，以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流包括：回應於該時間間隔被確定為比預定持續時間長，確定該輸入信號在該時間間隔之後的某時刻是否小於第三閾值，並且回應於該輸入信號被確定為在該時刻小於第三閾值，將驅動信號從第一邏輯位準變為第二邏輯位準。 According to another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and generating a driving signal based at least in part on the input signal to turn a transistor on or off to thereby Affects the current associated with the secondary winding of the power conversion system. In addition, processing information associated with the input signal includes determining whether a time interval from a first moment when the input signal becomes greater than a first threshold to a second moment when the input signal becomes less than a second threshold is longer than a predetermined duration long. In addition, generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: in response to the time interval being determined to be longer than a predetermined duration, Determine whether the input signal is less than the third threshold at a certain time after the time interval, and in response to the input signal being determined to be less than the third threshold at the time, change the driving signal from the first logic level to the second logic bit quasi.

根據另一實施例，用於調節電源變換系統的方法包括：接收輸入信號，處理與該輸入信號相關聯的資訊，並至少部分基於該輸入信號生成驅動信號，以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。此外，處理與該輸入信號相關聯的資訊包括：確定該輸入信號是否大於第一閾值；確定該輸入信號是否在比第一預定持續時間更長的時間段內保持大於第二閾值；以及確定從該輸入信號變得大於第三閾值的第一時刻到該輸入信號變得小於第四閾值的第二時刻的時間間隔是否比第二預定持續時間長。此外，至少部分基於該輸入信號生成驅動信號，以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流包括：回應於該輸入信號被確定為大於第一閾值，該輸入信號被確定為在比第一預定持續時間更長的時間段內保持大於第二閾值，或該時間間隔被確定為比第二預定持續時間長，確定該輸入信號是否小於第五閾值，並 且回應於該輸入信號被確定為小於第五閾值，將驅動信號從第一邏輯位準變為第二邏輯位準。 According to another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and generating a driving signal based at least in part on the input signal to turn a transistor on or off to thereby Affects the current associated with the secondary winding of the power conversion system. In addition, processing information associated with the input signal includes: determining whether the input signal is greater than a first threshold; determining whether the input signal remains greater than a second threshold for a period of time longer than a first predetermined duration; and determining from Whether the time interval from the first moment when the input signal becomes larger than the third threshold to the second moment when the input signal becomes smaller than the fourth threshold is longer than the second predetermined duration. In addition, generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: in response to the input signal being determined to be greater than a first threshold, the The input signal is determined to remain greater than the second threshold for a time period longer than the first predetermined duration, or the time interval is determined to be longer than the second predetermined duration, determining whether the input signal is less than a fifth threshold, and And in response to the input signal being determined to be smaller than the fifth threshold, the driving signal is changed from the first logic level to the second logic level.

根據另一實施例，用於調節電源變換器的系統控制器包括第一控制器端子和第二控制器端子。該系統控制器被配置為：在第一控制器端子處接收輸入信號，並至少部分基於輸入信號，在第二控制器端子處生成驅動信號，以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流。另外，系統控制器還被配置為：確定輸入信號在等於或長於第一預定持續時間的第一時段內是否保持大於第一閾值；並且回應於輸入信號未被確定為在等於或長於所述第一預定持續時間的第一時段內保持大於第一閾值，利用第一方案進行操作。另外，利用第一方案進行操作，該系統控制器還被配置為：確定輸入信號在等於或長於第二預定持續時間的第二時段內是否保持小於第二閾值；回應於輸入信號被確定為在等於或長於所述第二預定持續時間的第二時段內保持小於第二閾值，將第二控制器端子處的驅動信號從第一邏輯位準變為第二邏輯位準。第一預定持續時間大於零，並且第二預定持續時間大於零。 According to another embodiment, a system controller for regulating a power converter includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a drive signal at a second controller terminal based at least in part on the input signal to turn on or off the transistor to affect power conversion Current associated with the secondary winding of the converter. In addition, the system controller is further configured to determine whether the input signal remains greater than a first threshold for a first period equal to or longer than the first predetermined duration; and in response to the input signal not being determined to be equal to or longer than the first The first period of a predetermined duration remains greater than the first threshold, and the first scheme is used for operation. In addition, using the first scheme for operation, the system controller is further configured to determine whether the input signal remains less than a second threshold for a second period equal to or longer than a second predetermined duration; in response to the input signal being determined to be at The driving signal at the terminal of the second controller is changed from the first logic level to the second logic level within a second period equal to or longer than the second predetermined duration. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero.

根據另一實施例，用於調節電源變換器的系統控制器包括第一控制器端子和第二控制器端子。該系統控制器被配置為：在第一控制器端子處接收輸入信號，並且至少部分基於輸入信號，在第二控制器端子處生成驅動信號，以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流。另外，該系統控制器還被配置為：確定輸入信號在等於或長於第一預定持續時間的第一時段內是否保持小於或等於第一閾值且大於第二閾值，第二閾值小於第一閾值；並且回應於輸入信號未被確定為在等於或長於第一預定持續時間的第一時段內保持小於或等於第一閾值且大於第二閾值，利用第一方案進行操作。另外，利用第一方案進行操作，該系統控制器還被配置為：確定輸入信號在等於或長於第二預定持續時間的第二時段內是否保持小於第三閾值；回應於輸入信號被確定為在等於或長於第二預定持續時間的第二時段內保持小於第三閾值，將第二控制器端子 處的驅動信號從第一邏輯位準變為第二邏輯位準。第一預定持續時間大於零，並且第二預定持續時間大於零。 According to another embodiment, a system controller for regulating a power converter includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a driving signal at a second controller terminal based at least in part on the input signal to turn on or off the transistor to affect power conversion Current associated with the secondary winding of the converter. In addition, the system controller is further configured to determine whether the input signal remains less than or equal to the first threshold and greater than the second threshold during a first period equal to or longer than the first predetermined duration, and the second threshold is smaller than the first threshold; And in response to the input signal not being determined to remain less than or equal to the first threshold and greater than the second threshold for a first period of time equal to or longer than the first predetermined duration, the first scheme is used for operation. In addition, using the first scheme for operation, the system controller is further configured to determine whether the input signal remains less than a third threshold for a second period equal to or longer than the second predetermined duration; in response to the input signal being determined to be at Keeping the second controller terminal for a second period equal to or longer than the second predetermined duration to be less than the third threshold The driving signal at is changed from the first logic level to the second logic level. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero.

根據另一實施例，用於調節電源變換器的系統控制器包括第一控制器端子和第二控制器端子。該系統控制器被配置為：在第一控制器端子處接收輸入信號，並且至少部分基於輸入信號，在第二控制器端子處生成驅動信號，以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流。另外，系統控制器還被配置為：確定輸入信號在等於或長於第一預定持續時間的第一時段內是否保持大於第一閾值，並且確定輸入信號在等於或長於第二預定持續時間的第二時段內是否保持大於第二閾值。第二閾值小於第一閾值，第二預定持續時間長於第一預定持續時間。另外，該系統控制器還被配置為：回應於輸入信號未被確定為在等於或長於第一預定持續時間的第一時段內保持大於第一閾值，並且輸入信號未被確定為在等於或長於第二預定持續時間的第二時段內保持大於第二閾值，利用第一方案進行操作。另外，利用第一方案進行操作，該系統控制器還被配置為：確定輸入信號在等於或長於第三預定持續時間的第三時段內是否保持小於第三閾值；並且回應於輸入信號被確定為在等於或長於第三持續時間的第三時段內保持小於第三閾值，將第二控制器端子處的驅動信號從第一邏輯位準變為第二邏輯位準。第一預定持續時間大於零，第二預定持續時間大於零，並且第三預定持續時間大於零。 According to another embodiment, a system controller for regulating a power converter includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a driving signal at a second controller terminal based at least in part on the input signal to turn on or off the transistor to affect power conversion Current associated with the secondary winding of the converter. In addition, the system controller is further configured to determine whether the input signal remains greater than the first threshold for a first period of time equal to or longer than the first predetermined duration, and determine that the input signal is equal to or longer than the second predetermined duration for a second Whether it remains greater than the second threshold during the period. The second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration. In addition, the system controller is further configured to: in response to the input signal not being determined to remain greater than the first threshold for a first period equal to or longer than the first predetermined duration, and the input signal not determined to be equal to or longer than The second predetermined duration is kept greater than the second threshold within the second period, and the first scheme is used for operation. In addition, using the first scheme for operation, the system controller is further configured to: determine whether the input signal remains less than a third threshold in a third period equal to or longer than a third predetermined duration; and in response to the input signal being determined as The driving signal at the terminal of the second controller is changed from the first logic level to the second logic level within a third period equal to or longer than the third duration. The first predetermined duration is greater than zero, the second predetermined duration is greater than zero, and the third predetermined duration is greater than zero.

根據另一實施例，用於調節電源變換器的系統控制器包括第一控制器端子和第二控制器端子。該系統控制器被配置為：在第一控制器端子處接收輸入信號，並且至少部分基於輸入信號，在第二控制器端子處生成驅動信號，以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流。另外，該系統控制器還被配置為：確定輸入信號在等於或長於第一預定持續時間的第一時段內是否保持大於第一閾值，並且確定輸入信號在等於或長於第二預定持續時間的第二時段內是否保持大於第二閾值。另外，系統控制器還被配置為：回應於輸入信號未被確定為在等於 或長於第一預定持續時間的第一時段內保持大於第一閾值，並且輸入信號未被確定為在等於或長於第二預定持續時間的第二時段內保持大於第二閾值，利用第一方案進行操作。第二閾值小於第一閾值，並且第二預定持續時間長於第一預定持續時間。第一預定持續時間大於零，並且第二預定持續時間大於零。第一閾值在幅度上隨著輸入信號改變，第二閾值在幅度上隨著輸入信號改變。 According to another embodiment, a system controller for regulating a power converter includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a driving signal at a second controller terminal based at least in part on the input signal to turn on or off the transistor to affect power conversion Current associated with the secondary winding of the converter. In addition, the system controller is further configured to determine whether the input signal remains greater than the first threshold for a first period equal to or longer than the first predetermined duration, and determine that the input signal is equal to or longer than the second predetermined duration. Whether it remains greater than the second threshold in the two periods. In addition, the system controller is configured to: in response to the input signal not being determined to be equal to Or remains greater than the first threshold for a first period longer than the first predetermined duration, and the input signal is not determined to remain greater than the second threshold for a second period equal to or longer than the second predetermined duration, using the first scheme operating. The second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero. The first threshold value changes with the input signal in amplitude, and the second threshold value changes with the input signal in amplitude.

根據另一實施例，用於調節電源變換器的系統控制器包括第一控制器端子和第二控制器端子。該系統控制器被配置為：在第一控制器端子處接收輸入信號，並且至少部分基於輸入信號，在第二控制器端子處生成驅動信號，以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流。另外，該系統控制器還被配置為：確定輸入信號在等於或長於第一預定持續時間的第一時段內是否保持大於第一閾值，並且確定輸入信號在等於或長於第二預定持續時間的第二時段內是否保持大於第二閾值。另外，該系統控制器還被配置為：回應於輸入信號未被確定為在等於或長於第一預定持續時間的第一時段內保持大於第一閾值，並且輸入信號未被確定為在等於或長於第二預定持續時間的第二時段內保持大於第二閾值，利用第一方案進行操作。第二閾值小於第一閾值，並且第二預定持續時間長於第一預定持續時間。第一預定持續時間大於零，第二預定持續時間大於零，第一預定持續時間在幅度上隨著輸入信號改變，並且第二預定持續時間在幅度上隨著輸入信號改變。 According to another embodiment, a system controller for regulating a power converter includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a driving signal at a second controller terminal based at least in part on the input signal to turn on or off the transistor to affect power conversion Current associated with the secondary winding of the converter. In addition, the system controller is further configured to determine whether the input signal remains greater than the first threshold for a first period equal to or longer than the first predetermined duration, and determine that the input signal is equal to or longer than the second predetermined duration. Whether it remains greater than the second threshold in the two periods. In addition, the system controller is further configured to: in response to the input signal not being determined to remain greater than the first threshold for a first period equal to or longer than the first predetermined duration, and the input signal not determined to be equal to or longer than The second predetermined duration is kept greater than the second threshold within the second period, and the first scheme is used for operation. The second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration. The first predetermined duration is greater than zero, the second predetermined duration is greater than zero, the first predetermined duration changes in amplitude with the input signal, and the second predetermined duration changes in amplitude with the input signal.

根據另一實施例，用於調節電源變換器的方法包括：接收輸入信號；處理與輸入信號相關聯的資訊；以及至少部分基於輸入信號生成驅動信號，以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流。處理與輸入信號相關聯的資訊包括：確定輸入信號在等於或長於第一預定持續時間的第一時段內是否保持大於第一閾值；並且回應於輸入信號未被確定為在等於或長於第一預定持續時間的第一時段內保持大於第一閾值，利用第一方案進行操作。至少部分基於輸入信號生成驅動信 號，以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流包括：回應於利用第一方案進行操作，確定輸入信號在等於或長於第二預定持續時間的第二時段內是否保持小於第二閾值；並且回應於輸入信號被確定為在等於或長於第二預定持續時間的第二時段內保持小於第二閾值，將驅動信號從第一邏輯位準變為第二邏輯位準。第一預定持續時間大於零，並且第二預定持續時間大於零。 According to another embodiment, a method for adjusting a power converter includes: receiving an input signal; processing information associated with the input signal; and generating a driving signal based at least in part on the input signal to turn a transistor on or off to affect the Current associated with the secondary winding of the power converter. Processing the information associated with the input signal includes: determining whether the input signal remains greater than a first threshold for a first period of time equal to or longer than the first predetermined duration; and in response to the input signal not being determined to be equal to or longer than the first predetermined The first period of the duration remains greater than the first threshold, and the first scheme is used for operation. Generate drive signals based at least in part on input signals To switch on or off the transistor to affect the current associated with the secondary winding of the power converter includes: in response to operating with the first scheme, determining that the input signal is at a second equal to or longer than a second predetermined duration Whether it remains less than the second threshold during the period; and in response to the input signal being determined to remain less than the second threshold for a second period equal to or longer than the second predetermined duration, the driving signal is changed from the first logic level to the second Logic level. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero.

根據另一實施例，用於調節電源變換器的方法包括：接收輸入信號；處理與輸入信號相關聯的資訊；以及至少部分基於輸入信號生成驅動信號，以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流。處理與輸入信號相關聯的資訊包括：確定輸入信號在等於或長於第一預定持續時間的第一時段內是否保持小於或等於第一閾值且大於第二閾值，第二閾值小於第一閾值；並且回應於輸入信號未被確定為在等於或長於第一預定持續時間的第一時段內保持小於或等於第一閾值且大於第二閾值，利用第一方案進行操作。至少部分基於輸入信號生成驅動信號，以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流包括：回應於利用第一方案進行操作，確定輸入信號在等於或長於第二預定持續時間的第二時段內是否保持小於第三閾值；並且回應於輸入信號被確定為在等於或長於第二預定持續時間的第二時段內保持小於第三閾值，將驅動信號從第一邏輯位準變為第二邏輯位準。第一預定持續時間大於零，並且第二預定持續時間大於零。 According to another embodiment, a method for adjusting a power converter includes: receiving an input signal; processing information associated with the input signal; and generating a driving signal based at least in part on the input signal to turn a transistor on or off to affect the Current associated with the secondary winding of the power converter. Processing the information associated with the input signal includes: determining whether the input signal remains less than or equal to a first threshold value and greater than a second threshold value, and the second threshold value is less than the first threshold value within a first period equal to or longer than the first predetermined duration; and In response to the input signal not being determined to remain less than or equal to the first threshold and greater than the second threshold for a first period of time equal to or longer than the first predetermined duration, the first scheme is used for operation. Generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power converter includes: in response to operating with the first scheme, determining whether the input signal is equal to or longer than the first Whether the driving signal remains less than the third threshold in the second period of the second predetermined duration; and in response to the input signal being determined to remain less than the third threshold in the second period equal to or longer than the second predetermined duration, the driving signal is changed from the first The logic level becomes the second logic level. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero.

根據另一實施例，用於調節電源變換器的方法包括：接收輸入信號；處理與輸入信號相關聯的資訊；以及至少部分基於輸入信號生成驅動信號，以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流。處理與輸入信號相關聯的資訊包括：確定輸入信號在等於或長於第一預定持續時間的第一時段內是否保持大於第一閾值；確定輸入信號在等於或長於第二預定持續時間的第二時段內是否保持大於第二閾值，第二閾值小於第一閾值，第二預定持續時間長於第一預定持續時間；並且 回應於輸入信號未被確定為在等於或長於第一預定持續時間的第一時段內保持大於第一閾值，且輸入信號未被確定為在等於或長於第二預定持續時間的第二時段內保持大於第二閾值，利用第一方案進行操作。至少部分基於輸入信號生成驅動信號，以接通或關斷電晶體從而影響與電源變換器的二次繞組關聯的電流包括：回應於利用第一方案進行操作，確定所述輸入信號在等於或長於第三預定持續時間的第三時段內是否保持小於第三閾值；並且回應於輸入信號被確定為在等於或長於第三預定持續時間的第三時段內保持小於所述第三閾值，將驅動信號從第一邏輯位準變為第二邏輯位準。第一預定持續時間大於零，第二預定持續時間大於零，並且第三預定持續時間大於零。 According to another embodiment, a method for adjusting a power converter includes: receiving an input signal; processing information associated with the input signal; and generating a driving signal based at least in part on the input signal to turn a transistor on or off to affect the Current associated with the secondary winding of the power converter. Processing the information associated with the input signal includes: determining whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration; determining whether the input signal is in a second period equal to or longer than a second predetermined duration Whether it remains greater than the second threshold, the second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration; and In response to the input signal not being determined to remain greater than the first threshold for a first period equal to or longer than the first predetermined duration, and the input signal not being determined to remain for a second period equal to or longer than the second predetermined duration If it is larger than the second threshold, the first solution is used for operation. Generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power converter includes: in response to operating with the first scheme, determining that the input signal is equal to or longer than Whether the driving signal is kept smaller than the third threshold within a third period of the third predetermined duration; and in response to the input signal being determined to remain smaller than the third threshold within a third period equal to or longer than the third predetermined duration, the driving signal is driven Change from a first logic level to a second logic level. The first predetermined duration is greater than zero, the second predetermined duration is greater than zero, and the third predetermined duration is greater than zero.

根據另一實施例，用於調節電源變換器的方法包括：接收輸入信號；處理與輸入信號相關聯的資訊；以及至少部分基於輸入信號生成驅動信號，以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流。處理與輸入信號相關聯的資訊包括：確定輸入信號在等於或長於第一預定持續時間的第一時段內是否保持大於第一閾值；確定輸入信號在等於或長於第二預定持續時間的第二時段內是否保持大於第二閾值；並且回應於輸入信號未被確定為在等於或長於第一預定持續時間的第一時段內保持大於第一閾值，且輸入信號未被確定為在等於或長於第二預定持續時間的第二時段內保持大於第二閾值，利用第一方案進行操作。第二閾值小於第一閾值，第二預定持續時間長於第一預定持續時間。第一預定持續時間大於零，並且第二預定持續時間大於零。第一閾值在幅度上隨著輸入信號改變，並且第二閾值在幅度上隨著輸入信號改變。 According to another embodiment, a method for adjusting a power converter includes: receiving an input signal; processing information associated with the input signal; and generating a driving signal based at least in part on the input signal to turn a transistor on or off to affect the Current associated with the secondary winding of the power converter. Processing the information associated with the input signal includes: determining whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration; determining whether the input signal is in a second period equal to or longer than a second predetermined duration Whether or not remains greater than the second threshold; and in response to the input signal not being determined to remain greater than the first threshold for a first period of time equal to or longer than the first predetermined duration, and the input signal not determined to be equal to or longer than the second threshold The second period of the predetermined duration is kept greater than the second threshold, and the first scheme is used for operation. The second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero. The first threshold value changes with the input signal in amplitude, and the second threshold value changes with the input signal in amplitude.

根據另一實施例，用於調節電源變換器的方法包括：接收輸入信號；處理與輸入信號相關聯的資訊；以及至少部分基於輸入信號生成驅動信號，以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流。處理與輸入信號相關聯的資訊包括：確定輸入信號在等於或長於第一預定持續時間的第一時段內是否保持大於第一閾值；確定輸入信 號在等於或長於第二預定持續時間的第二時段內是否保持大於第二閾值；並且回應於輸入信號未被確定為在等於或長於第一預定持續時間的第一時段內保持大於第一閾值，且輸入信號未被確定為在等於或長於第二預定持續時間的第二時段內保持大於第二閾值，利用第一方案進行操作。第二閾值小於第一閾值，並且第二預定持續時間長於第一預定持續時間。第一預定持續時間大於零，第二預定持續時間大於零，第一預定持續時間在幅度上隨著輸入信號改變，且第二預定持續時間在幅度上隨著輸入信號改變。 According to another embodiment, a method for adjusting a power converter includes: receiving an input signal; processing information associated with the input signal; and generating a driving signal based at least in part on the input signal to turn a transistor on or off to affect the Current associated with the secondary winding of the power converter. Processing the information associated with the input signal includes: determining whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration; determining the input signal Whether the number remains greater than the second threshold for a second period equal to or longer than the second predetermined duration; and in response to the input signal not being determined to remain greater than the first threshold for a first period equal to or longer than the first predetermined duration And the input signal is not determined to remain greater than the second threshold for a second period equal to or longer than the second predetermined duration, the first scheme is used for operation. The second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration. The first predetermined duration is greater than zero, the second predetermined duration is greater than zero, the first predetermined duration changes in amplitude with the input signal, and the second predetermined duration changes in amplitude with the input signal.

取決於實施例，這些益處中的一個或多個益處可以被實現。參考下面的附圖和詳細描述將完全理解這些益處和本發明的各種附加的目標、特徵和優點。 Depending on the embodiment, one or more of these benefits may be realized. These benefits and various additional objects, features, and advantages of the present invention will be fully understood with reference to the following drawings and detailed description.

100、200、2300、300、400、3300‧‧‧電源變換系統 100, 200, 2300, 300, 400, 3300‧‧‧ Power Conversion System

102、302、402‧‧‧控制器 102, 302, 402‧‧‧ controller

104‧‧‧欠壓鎖定元件 104‧‧‧Undervoltage lockout element

106‧‧‧脈衝寬度調變發生器 106‧‧‧Pulse width modulation generator

108‧‧‧閘極驅動器 108‧‧‧Gate driver

110、210、2304、304、404、3304‧‧‧一次繞組 110, 210, 2304, 304, 404, 3304‧‧‧ primary winding

112、212、2306、306、406、3306‧‧‧二次繞組 112, 212, 2306, 306, 406, 3306‧‧‧ secondary winding

114、OCP‧‧‧過流保護元件 114. OCP‧‧‧Overcurrent protection element

116、LEB‧‧‧前沿消隱元件 116. LEB‧‧‧ leading edge blanking element

120、220、2330、330、430、3330‧‧‧功率開關 120, 220, 2330, 330, 430, 3330‧‧‧ power switches

122、230、328、428‧‧‧電流感測電阻器 122, 230, 328, 428‧‧‧ current sensing resistors

124、260、262‧‧‧整流二極體 124, 260, 262‧‧‧ rectified diodes

126、264、266、312、380、412、476、478‧‧‧電容器 126, 264, 266, 312, 380, 412, 476, 478‧‧‧ capacitors

128‧‧‧隔離回饋組件 128‧‧‧Isolated feedback components

130、Gate‧‧‧閘極驅動信號 130.Gate‧‧‧Gate driving signal

136、274、360、460‧‧‧回饋信號 136, 274, 360, 460‧‧‧ feedback signals

190‧‧‧AC輸入電壓 190‧‧‧AC input voltage

192、250、350、450‧‧‧輸出電壓 192, 250, 350, 450‧‧‧ output voltage

202‧‧‧系統控制器 202‧‧‧System Controller

214、324‧‧‧輔助繞組 214, 324‧‧‧Auxiliary winding

424‧‧‧第一輔助繞組 424‧‧‧The first auxiliary winding

425‧‧‧第二輔助繞組 425‧‧‧second auxiliary winding

254‧‧‧214的電壓 Voltage of 254‧‧‧214

272‧‧‧電流感測信號 272‧‧‧Current sensing signal

276‧‧‧一次電流 276‧‧‧ primary current

278、352、452、Isec‧‧‧二次電流 278, 352, 452, I sec ‧‧‧ secondary current

Ts‧‧‧預定時間段 Ts‧‧‧ scheduled time

TON‧‧‧接通時間段 T ON ‧‧‧ On time period

Toff‧‧‧關斷時間段 T off ‧‧‧ off time period

TDemag‧‧‧退磁時段 T Demag ‧‧‧ Demagnetization Period

2302、3302‧‧‧一次側脈衝寬度調製變控制器 2302, 3302‧‧‧ primary side pulse width modulation controller

2308、3308‧‧‧二次側同步整流器控制器 2308, 3308‧‧‧‧ Secondary-side synchronous rectifier controller

2310、MOSFET、310、410、3310‧‧‧電晶體 2310, MOSFET, 310, 410, 3310‧‧‧ transistor

2312、3312、CO‧‧‧輸出電容性負載 2312,3312, C O ‧‧‧ output capacitive load

2314、3314、RO‧‧‧輸出電阻性負載 2314, 3314, R O ‧‧‧ output resistive load

2320‧‧‧電壓感測器 2320‧‧‧Voltage Sensor

2322‧‧‧邏輯控制器 2322‧‧‧Logic Controller

2324、3850‧‧‧驅動器 2324, 3850‧‧‧Drive

2332、2366、3332、3366、Vg、Vg1‧‧‧驅動信號 2332, 2366, 3332, 3366, V g , V g1 ‧‧‧ drive signal

301、401‧‧‧整流電路 301, 401‧‧‧ rectifier circuit

308、408‧‧‧二次控制器 308, 408‧‧‧ secondary controller

320、420、474‧‧‧二極體 320, 420, 474‧‧‧ diodes

368‧‧‧溝道電流 368‧‧‧channel current

370‧‧‧體二極體電流 370‧‧‧body diode current

372‧‧‧地電壓 372‧‧‧ground voltage

528、828、928、1028、1109、Vth1‧‧‧第一閾值電壓 528, 828, 928, 1028, 1109, V th1 ‧‧‧ first threshold voltage

530、830、930、1030、1113、Vth2‧‧‧第二閾值電壓 530, 830, 930, 1030, 1113, V th2 ‧‧‧ second threshold voltage

Td‧‧‧延時 T d ‧‧‧ Delay

602、1102‧‧‧鉗位元元件 602, 1102‧‧‧clamp element

604、1104‧‧‧補償元件 604, 1104‧‧‧Compensation element

606、1106‧‧‧上升沿感測元件 606, 1106‧‧‧ rising edge sensing element

610、1110‧‧‧下降沿感測元件 610, 1110‧‧‧falling edge sensing element

612、1112‧‧‧時序控制器 612, 1112‧‧‧ timing controller

614、1114‧‧‧邏輯控制元件 614, 1114‧‧‧Logic control element

616、1116‧‧‧閘極驅動器 616, 1116‧‧‧Gate driver

618、1118‧‧‧輕載感測器 618, 1118‧‧‧‧light load sensor

620、1120‧‧‧信號發生器 620, 1120‧‧‧Signal generator

622、1122‧‧‧振盪器 622, 1122‧‧‧oscillator

626、1126‧‧‧參考信號發生器 626, 1126‧‧‧ reference signal generator

628、1128‧‧‧欠壓鎖定元件 628, 1128‧‧‧undervoltage lockout element

652、1180‧‧‧參考信號 652, 1180‧‧‧ reference signal

722、Vth3‧‧‧第三閾值電壓 722, V th3 ‧‧‧ third threshold voltage

724、Vth4‧‧‧第四閾值電壓 724, V th4 ‧‧‧ fourth threshold voltage

730‧‧‧脈衝 730‧‧‧pulse

829、1218、3490、Vref1‧‧‧第一參考電壓 829, 1218, 3490, V ref1 ‧‧‧ first reference voltage

929、1228、3590、Vref2‧‧‧第二參考電壓 929, 1228, 3590, V ref2 ‧‧‧ second reference voltage

1029、1238、Vref3‧‧‧第三參考電壓 1029,1238, V ref3 ‧‧‧ third reference voltage

1031、1248、Vref4‧‧‧第四參考電壓 1031,1248, V ref4 ‧‧‧ the fourth reference voltage

1250‧‧‧閘 1250‧‧‧Gate

1174‧‧‧時鐘信號 1174‧‧‧clock signal

1224、3820、3826‧‧‧消抖元件 1224, 3820, 3826‧‧‧ Debounce components

1234‧‧‧計時器元件 1234‧‧‧Timer element

3480‧‧‧閾值電壓 3480‧‧‧Threshold voltage

TA、TJ、TK‧‧‧持續時間 T A , T J , T K ‧‧‧ Duration

1300、3600‧‧‧方法 1300, 3600‧‧‧Method

3812、3818‧‧‧比較信號 3812, 3818‧‧‧Comparison signal

Tth1‧‧‧第一閾值時間段 T th1 ‧‧‧ first threshold time period

Tth2‧‧‧閾值持續時間 T th2 ‧‧‧threshold duration

3830‧‧‧接通方案控制器 3830‧‧‧ Connected to the solution controller

3836‧‧‧接通信號控制器 3836‧‧‧ On Signal Controller

3840‧‧‧關斷信號控制器 3840‧‧‧ Shutdown Signal Controller

3860‧‧‧鉗位元器 3860‧‧‧Clamp Device

3876‧‧‧閾值持續時間發生器 3876‧‧‧Threshold Duration Generator

3842‧‧‧關斷控制信號 3842‧‧‧ Shutdown control signal

532‧‧‧二次側退磁完畢 532‧‧‧ secondary demagnetization completed

R‧‧‧一次側脈衝寬度調變變控制器啟動電阻 R‧‧‧Primary Pulse Width Modulation Controller Startup Resistance

M‧‧‧功率開關 M‧‧‧Power Switch

C‧‧‧一次側脈衝寬度調變變控制器供電電源電容 C‧‧‧ Primary side pulse width modulation controller power supply capacitor

D‧‧‧同步整流開關漏端 D‧‧‧ Drain terminal of synchronous rectifier switch

VAC‧‧‧AC輸入電壓 V AC ‧‧‧AC input voltage

Rs‧‧‧變壓器一次側電流感測電阻器 R s ‧‧‧Transformer primary current sense resistor

R2‧‧‧系統輸出下分壓電阻 R2‧‧‧ System output voltage divider resistor

Lp‧‧‧變壓器一次側繞組感量 L p ‧‧‧Transformer primary winding inductance

Vth__oc‧‧‧過流保護閾值 V th _ oc ‧‧‧ overcurrent protection threshold

CS‧‧‧變壓器一次側電流檢測信號 CS‧‧‧Transformer primary current detection signal

VCC‧‧‧一次側脈衝寬度調變變控制器供電電源 VCC‧‧‧ Primary side pulse width modulation controller power supply

VDD‧‧‧二次側同步整流控制器供電電源 VDD‧‧‧ secondary side synchronous rectifier controller power supply

POR、UVLO‧‧‧欠壓保護致能信號 POR, UVLO‧‧‧ Undervoltage protection enable signal

FB‧‧‧隔離回饋控制信號 FB‧‧‧Isolated feedback control signal

GND、GND2‧‧‧接地腳 GND, GND2‧‧‧ ground pin

D1‧‧‧輸出電壓整流二極體 D1‧‧‧Output voltage rectified diode

D2‧‧‧二次側同步整流器控制器供電電源整流二極體 D2‧‧‧ secondary side synchronous rectifier controller power supply rectifier diode

D3‧‧‧一次側脈衝寬度調變變控制器供電電源整流二極體 D3‧‧‧ primary side pulse width modulation controller power supply rectifier diode

T1‧‧‧變壓器 T1‧‧‧Transformer

Naux‧‧‧變壓器輔助繞組匝數 N aux ‧‧‧ number of transformer auxiliary winding turns

Np‧‧‧變壓器一次側繞組匝數 N p ‧‧‧ number of turns of transformer primary winding

Vaux‧‧‧變壓器輔助繞組電壓 V aux ‧‧‧Transformer auxiliary winding voltage

Nsec‧‧‧變壓器二次側繞組匝數 N sec ‧‧‧Transformer secondary winding turns

Ipri‧‧‧變壓器二次側電流峰值 I pri ‧‧‧ peak current of secondary side of transformer

R1‧‧‧系統輸出上分壓電阻 R1‧‧‧ system output resistor

Np‧‧‧變壓器一次側繞組匝數 Np‧‧‧Transformer primary winding turns

NS‧‧‧變壓器二次側繞組匝數 N S ‧‧‧Transformer secondary winding turns

U1‧‧‧一次側脈衝寬度調變變控制器 U1‧‧‧Primary Pulse Width Modulation Controller

U2‧‧‧二次側同步整流器控制器 U2‧‧‧ secondary-side synchronous rectifier controller

Vbulk‧‧‧Bulk電容電壓 Vbulk‧‧‧Bulk capacitor voltage

M1‧‧‧同步整流開關 M1‧‧‧Synchronous Rectifier Switch

M2‧‧‧功率開關 M2‧‧‧Power Switch

1021‧‧‧二次側退磁完畢後諧振第三穀底 1021‧‧‧Resonant third valley bottom after secondary side demagnetization

CLK‧‧‧脈衝寬度調變變控制器時鐘信號 CLK‧‧‧Pulse Width Modulation Controller Clock Signal

V_D‧‧‧同步整流開關漏端信號 V_D‧‧‧Synchronous Rectifier Switch Drain Signal

V_FB‧‧‧PSR脈衝寬度調變變控制器回授信號 V_FB‧‧‧PSR Pulse Width Modulation Controller Feedback Signal

Vin、2316、2362、Vd、362、388、658、Vs、462、3316、3362‧‧‧電壓信號 V in , 2316, 2362, V d , 362, 388, 658, V s , 462, 3316, 3362‧‧‧ voltage signals

268、270、314、316、318、322、326、414、416、418、470、472‧‧‧電阻器 268, 270, 314, 316, 318, 322, 326, 414, 416, 418, 470, 472‧‧‧ resistors

608、624、1124、1210、1220、1230、1240、3810、3816‧‧‧比較器 608, 624, 1124, 1210, 1220, 1230, 1240, 3810, 3816‧‧‧ comparator

t0、t2、t3、t4、t5、t6、t7、t8、t9、t10、t11、t12、t13、t14、t15、t16、t17、t18、t24、t25、t30、t34、t35、t36、t37、t4o、t44、t45、t46、t47、t48、t50、t51、t101、t102、t111、t112、t113、t114、t115、t116‧‧‧時刻 t0, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15, t16, t17, t18, t24, t25, t30, t34, t35, t36, t37, t4o, t44, t45, t46, t47, t48, t50, t51, t101, t102, t111, t112, t113, t114, t115, t116

292、294、502、504、506、508、510、512、514、702、704、706、708、710、712、802、808、810、902、908、910、1002、1008、1010、3432、3462、3466、3532‧‧‧波形 292, 294, 502, 504, 506, 508, 510, 512, 514, 702, 704, 706, 708, 710, 712, 802, 808, 810, 902, 908, 910, 1002, 1008, 1010, 3432, 3462, 3466, 3532‧‧‧ waveform

296、268、516、518、520、522、524、525、526、529、534、714、716、718、720、726、728、818、819、826、827、918、919、926、927、1018、1019、1026、1027‧‧‧值 296, 268, 516, 518, 520, 522, 524, 525, 526, 529, 534, 714, 716, 718, 720, 726, 728, 818, 819, 826, 827, 918, 919, 926, 927, 1018, 1019, 1026, 1027‧‧‧ values

366、466、650、660、670、672、676、678、682、684、1107、1111、1115、1252、1172、1176、1178、1182、1184、1158、1216、1222、1226、1232、1236、1242、3822、3828、3874、3878、3832、3838‧‧‧信號 366, 466, 650, 660, 670, 672, 676, 678, 682, 684, 1107, 1111, 1115, 1252, 1172, 1176, 1178, 1182, 1184, 1158, 1216, 1222, 1226, 1232, 1236, 1242, 3822, 3828, 3874, 3878, 3832, 3838‧‧‧ signals

2364、2390、2392、2394、2396、390、392、394、396、398、364、G2、464、3364、3390、3392、3394、3396、DR‧‧‧端子 2364, 2390, 2392, 2394, 2396, 390, 392, 394, 396, 398, 364, G2, 464, 3364, 3390, 3392, 3394, 3396, DR‧‧‧ terminals

1310、1320、1322、1324、1340、3610、3620、3622、3630、3640、3710、3720、3721、3722、3723、3740‧‧‧過程 1310, 1320, 1322, 1324, 1340, 3610, 3620, 3622, 3630, 3640, 3710, 3720, 3721, 3722, 3723, 3740‧‧‧ process

第1圖是示出了傳統返馳式電源變換系統的簡化圖。 FIG. 1 is a simplified diagram showing a conventional flyback power conversion system.

第2A圖是示出了另一傳統返馳式電源變換系統的簡化圖。 FIG. 2A is a simplified diagram showing another conventional flyback power conversion system.

第2B圖是以斷續傳導模式(DCM)操作的、如第2A圖所示的返馳式電源變換系統的簡化傳統時序圖。 FIG. 2B is a simplified conventional timing diagram of the flyback power conversion system shown in FIG. 2A operated in discontinuous conduction mode (DCM).

第3圖是示出了具有二次側同步整流器(SR)的傳統電源變換系統的簡化圖。 FIG. 3 is a simplified diagram showing a conventional power conversion system having a secondary-side synchronous rectifier (SR).

第4A圖是根據本發明的實施例示出了具有整流電路的電源變換系統的簡化圖。 FIG. 4A is a simplified diagram showing a power conversion system having a rectifier circuit according to an embodiment of the present invention.

第4B圖是根據本發明的另一實施例示出了具有整流電路的電源變換系統的簡化圖。 FIG. 4B is a simplified diagram showing a power conversion system having a rectifier circuit according to another embodiment of the present invention.

第5圖是根據本發明的實施例，以斷續傳導模式(DCM)操作的、如第4A圖所示的電源變換系統的簡化時序圖。 FIG. 5 is a simplified timing diagram of the power conversion system shown in FIG. 4A operating in a discontinuous conduction mode (DCM) according to an embodiment of the present invention.

第6圖是根據本發明的實施例，示出了作為如第4A圖所示的電源變換系統的一部分的二次控制器的某些元件的簡化圖。 Fig. 6 is a simplified diagram showing certain elements of the secondary controller as part of the power conversion system as shown in Fig. 4A according to an embodiment of the present invention.

第7圖是根據本發明的實施例，包括如第6圖所示的二次控制器並且 以斷續傳導模式(DCM)進行操作的、如第4A圖所示的電源變換系統的簡化時序圖。 FIG. 7 is an embodiment according to the present invention, including a secondary controller as shown in FIG. 6 and A simplified timing diagram of a power conversion system operating in discontinuous conduction mode (DCM) as shown in FIG. 4A.

第8圖是根據本發明的另一實施例，以斷續傳導模式(DCM)操作的、如第4A圖所示的電源變換系統300的簡化時序圖。 FIG. 8 is a simplified timing diagram of the power conversion system 300 shown in FIG. 4A operating in a discontinuous conduction mode (DCM) according to another embodiment of the present invention.

第9圖是根據本發明的另一實施例，以斷續傳導模式(DCM)操作的、如第4A圖所示的電源變換系統300的簡化時序圖。 FIG. 9 is a simplified timing diagram of the power conversion system 300 shown in FIG. 4A operating in a discontinuous conduction mode (DCM) according to another embodiment of the present invention.

第10圖是根據本發明的另一實施例，以斷續傳導模式(DCM)操作的、如第4A圖所示的電源變換系統300的簡化時序圖。 FIG. 10 is a simplified timing diagram of the power conversion system 300 shown in FIG. 4A operating in a discontinuous conduction mode (DCM) according to another embodiment of the present invention.

第11圖是根據本發明的另一實施例，示出了作為電源變換系統300的一部分的二次控制器308的某些元件的簡化圖。 FIG. 11 is a simplified diagram showing certain elements of the secondary controller 308 as part of the power conversion system 300 according to another embodiment of the present invention.

第12圖是根據本發明的一個實施例，示出了用於致能作為電源變換系統300的一部分的二次控制器308的下降沿感測元件1110的方法的簡化圖。 FIG. 12 is a simplified diagram illustrating a method for enabling the falling edge sensing element 1110 of the secondary controller 308 as part of the power conversion system 300 according to one embodiment of the present invention.

第13圖是根據本發明的一個實施例，示出了具有二次側同步整流器(SR)的電源變換系統的簡化圖。 FIG. 13 is a simplified diagram showing a power conversion system having a secondary-side synchronous rectifier (SR) according to an embodiment of the present invention.

第14圖是根據本發明的一個實施例，示出了用於如第13圖中所示的二次側同步整流器(SR)控制器的接通方案從慢接通方案變為快接通方案的一個或多個預定條件的簡化圖。 FIG. 14 is a diagram illustrating a switching scheme for a secondary-side synchronous rectifier (SR) controller as shown in FIG. 13 from a slow-on scheme to a fast-on scheme according to an embodiment of the present invention A simplified diagram of one or more predetermined conditions.

第15圖是根據本發明的另一個實施例，示出了如第13圖中所示的二次側同步整流器(SR)控制器的接通方案從慢接通方案變為快接通方案的一個或多個預定條件的簡化圖。 FIG. 15 is a diagram illustrating a switching scheme of a secondary-side synchronous rectifier (SR) controller from a slow-switching scheme to a fast-switching scheme according to another embodiment of the present invention. Simplified graph of one or more predetermined conditions.

第16圖是根據本發明的一些實施例，示出了如第13圖中所示的二次側同步整流器(SR)控制器的確定接通方案的方法的簡化圖。 FIG. 16 is a simplified diagram illustrating a method of determining a switching scheme of a secondary-side synchronous rectifier (SR) controller as shown in FIG. 13 according to some embodiments of the present invention.

第17圖是根據本發明的某些實施例，示出了如第13圖中所示的二次側同步整流器(SR)控制器的確定接通方案的方法的簡化圖。 FIG. 17 is a simplified diagram illustrating a method of determining a switching scheme of a secondary-side synchronous rectifier (SR) controller as shown in FIG. 13 according to some embodiments of the present invention.

第18圖是根據本發明的一個實施例，示出了如第13圖中所示的電源變換系統的二次側同步整流器(SR)控制器的某些組件的簡化圖。 FIG. 18 is a simplified diagram showing certain components of a secondary-side synchronous rectifier (SR) controller of the power conversion system as shown in FIG. 13 according to an embodiment of the present invention.

本發明涉及積體電路。更具體地，本發明提供了利用輸出感測和同步整流方案的系統和方法。僅通過示例，本發明已經應用於電源變換系統。但是將認識到，本發明具有更寬的應用範圍。 The invention relates to an integrated circuit. More specifically, the present invention provides systems and methods that utilize output sensing and synchronous rectification schemes. By way of example only, the present invention has been applied to a power conversion system. However, it will be recognized that the invention has a wider range of applications.

第4A圖是根據本發明的實施例示出了具有整流電路的電源變換系統的簡化圖。該圖僅僅是示例，其不應該過度地限制申請專利範圍。本領域的普通技術人員將認識到許多變更、替換和修改。電源變換系統300包括：控制器302，一次繞組304，二次繞組306，輔助繞組324，整流電路301，二極體320，電流感測電阻器328，電容器312和380，電阻器314、316、322和326，以及功率開關330。整流電路301包括：二次控制器308、電阻器318和電晶體310。二次控制器308包括端子390、392、394、396和398。例如，電晶體310是MOSFET。在另一示例中，功率開關330是電晶體。 FIG. 4A is a simplified diagram showing a power conversion system having a rectifier circuit according to an embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. The power conversion system 300 includes: a controller 302, a primary winding 304, a secondary winding 306, an auxiliary winding 324, a rectifier circuit 301, a diode 320, a current sensing resistor 328, capacitors 312 and 380, resistors 314, 316, 322 and 326, and power switch 330. The rectifier circuit 301 includes a secondary controller 308, a resistor 318 and a transistor 310. The secondary controller 308 includes terminals 390, 392, 394, 396, and 398. For example, the transistor 310 is a MOSFET. In another example, the power switch 330 is a transistor.

根據一個實施例，當功率開關330閉合(例如，接通)時，能量被存儲在包括一次繞組304和二次繞組306的變壓器中。例如，當功率開關330斷開(例如，關斷)時，存儲的能量被轉移到二次側，並且輔助繞組324的電壓映射二次側上的輸出電壓350。在另一示例中，控制器302從包括電阻器322和326的分壓器接收用於輸出電壓調節的回饋信號360。在另一示例中，在能量轉移的過程(例如，退磁過程)中，電晶體310被接通，並且二次電流352的至少一部分流過電晶體310。在另一示例中，電晶體310的導通電阻非常小(例如，在幾十毫歐的範圍內)。在另一示例中，當導通時，電晶體310上的電壓下降遠遠小於整流二極體(例如，二極體124或二極體260)上的電壓下降，因此電源變換系統300的功率損耗與系統100或系統200相比大大降低。 According to one embodiment, when the power switch 330 is closed (eg, on), energy is stored in a transformer including a primary winding 304 and a secondary winding 306. For example, when the power switch 330 is turned off (eg, turned off), the stored energy is transferred to the secondary side, and the voltage of the auxiliary winding 324 is mapped to the output voltage 350 on the secondary side. In another example, the controller 302 receives a feedback signal 360 for output voltage adjustment from a voltage divider including resistors 322 and 326. In another example, during a process of energy transfer (eg, a demagnetization process), the transistor 310 is turned on, and at least a portion of the secondary current 352 flows through the transistor 310. In another example, the on-resistance of the transistor 310 is very small (for example, in the range of tens of milliohms). In another example, when turned on, the voltage drop across transistor 310 is much less than the voltage drop across the rectifier diode (eg, diode 124 or diode 260), so the power loss of the power conversion system 300 Compared to system 100 or system 200, it is greatly reduced.

根據另一實施例，在能量轉移過程(例如，退磁過程)的結束處，二次電流352具有低值(例如，幾乎為零)。例如，電晶體310被關斷以防止剩餘電流從輸出端351通過電晶體310流到地。在另一 示例中，當電晶體310接通時，功率開關330保持關斷(例如，斷開)。在另一示例中，二次控制器308接收指示電晶體310的端子364(例如，電晶體310的汲極端)處的電壓的電壓信號362(例如，VDR)，並且(例如，在端子G2處)提供信號366以驅動電晶體310。 According to another embodiment, at the end of the energy transfer process (eg, demagnetization process), the secondary current 352 has a low value (eg, almost zero). For example, the transistor 310 is turned off to prevent residual current from flowing from the output terminal 351 to the ground through the transistor 310. In another example, when the transistor 310 is on, the power switch 330 remains off (eg, off). In another example, the secondary controller 308 receives a voltage signal 362 (eg, V DR ) indicating a voltage at the terminal 364 (eg, the drain terminal of the transistor 310) of the transistor 310, and (eg, at the terminal G2 Where) a signal 366 is provided to drive the transistor 310.

如上面所討論的和在這裡進一步強調的那樣，第4A圖僅僅是示例，其不應該過度地限制申請專利範圍。本領域的普通技術人員將認識到許多變更、替換和修改。例如，控制器302和二次控制器308在不同的晶片上。在另一示例中，二次控制器308和電晶體310在不同的晶片上，該不同晶片是多晶片封裝的部分。在另一示例中，二次控制器308和電晶體310集成在同一晶片上。 As discussed above and further emphasized here, Figure 4A is merely an example, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, the controller 302 and the secondary controller 308 are on different wafers. In another example, the secondary controller 308 and the transistor 310 are on different wafers that are part of a multi-chip package. In another example, the secondary controller 308 and the transistor 310 are integrated on the same wafer.

第4B圖是根據本發明的另一實施例示出了具有整流電路的電源變換系統的簡化圖。該圖僅僅是示例，其不應該過度地限制申請專利範圍。本領域的普通技術人員將認識到許多變更、替換和修改。電源變換系統400包括：控制器402，一次繞組404，二次繞組406，第一輔助繞組424，第二輔助繞組425，整流電路401，二極體420和474，電容器412、476和478，電流感測電阻器428，電阻器414、416、470和472，以及功率開關430。整流電路401包括：二次控制器408、電阻器418和電晶體410。例如，電晶體410是MOSFET。在另一示例中，功率開關430是電晶體。在另一示例中，整流電路401與整流電路301相同。 FIG. 4B is a simplified diagram showing a power conversion system having a rectifier circuit according to another embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. The power conversion system 400 includes a controller 402, a primary winding 404, a secondary winding 406, a first auxiliary winding 424, a second auxiliary winding 425, a rectifier circuit 401, diodes 420 and 474, capacitors 412, 476, and 478, and a current Sense resistor 428, resistors 414, 416, 470, and 472, and power switch 430. The rectifying circuit 401 includes a secondary controller 408, a resistor 418, and a transistor 410. For example, the transistor 410 is a MOSFET. In another example, the power switch 430 is a transistor. In another example, the rectifying circuit 401 is the same as the rectifying circuit 301.

根據一個實施例，當功率開關430閉合(例如，接通)時，能量被存儲在包括一次繞組404和二次繞組406的變壓器中。例如，當功率開關430斷開(例如，關斷)時，存儲的能量被轉移到二次側，並且第二輔助繞組425的電壓映射二次側上的輸出電壓450。在另一示例中，控制器402從包括電阻器470和472的分壓器接收用於輸出電壓調節的回饋信號460。在另一示例中，在能量轉移的過程(例如，退磁過程)中，電晶體410被接通，並且二次電流452的至少一部分流過電晶體 410。在另一示例中，電晶體410的導通電阻非常小(例如，在幾十毫歐的範圍內)。 According to one embodiment, when the power switch 430 is closed (eg, on), energy is stored in a transformer including a primary winding 404 and a secondary winding 406. For example, when the power switch 430 is turned off (eg, turned off), the stored energy is transferred to the secondary side, and the voltage of the second auxiliary winding 425 is mapped to the output voltage 450 on the secondary side. In another example, the controller 402 receives a feedback signal 460 for output voltage adjustment from a voltage divider including resistors 470 and 472. In another example, during an energy transfer process (eg, a demagnetization process), the transistor 410 is turned on, and at least a portion of the secondary current 452 flows through the transistor 410. In another example, the on-resistance of the transistor 410 is very small (for example, in the range of tens of milliohms).

根據另一實施例，在能量轉移過程(例如，退磁過程)的結束處，二次電流452具有低值(例如，幾乎為零)。例如，電晶體410被關斷以防止反向電流從輸出端通過電晶體410流到地。在另一示例中，當電晶體410接通時，功率開關430保持關斷(例如，斷開)。在另一示例中，二次控制器408(例如，在端子DR處)接收指示電晶體410的端子464(例如，電晶體410的汲極端)處的電壓的電壓信號462，並且(例如，在端子G2處)提供信號466以驅動電晶體410。 According to another embodiment, at the end of the energy transfer process (eg, demagnetization process), the secondary current 452 has a low value (eg, almost zero). For example, the transistor 410 is turned off to prevent reverse current from flowing from the output terminal to the ground through the transistor 410. In another example, when the transistor 410 is on, the power switch 430 remains off (eg, off). In another example, the secondary controller 408 (e.g., at the terminal DR) receives a voltage signal 462 indicating a voltage at a terminal 464 (e.g., the drain terminal of the transistor 410) of the transistor 410, and (e.g., at A signal 466 is provided at terminal G2) to drive transistor 410.

如上面所討論的和在這裡進一步強調的那樣，第4B圖僅僅是示例，其不應該過度地限制申請專利範圍。本領域的普通技術人員將認識到許多變更、替換和修改。例如，控制器402和二次控制器408在不同的晶片上。在另一示例中，二次控制器408和電晶體410在不同的晶片上，該不同晶片是多晶片封裝的部分。在另一示例中，二次控制器408和電晶體410集成在同一晶片上。 As discussed above and further emphasized here, Figure 4B is merely an example, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, the controller 402 and the secondary controller 408 are on different wafers. In another example, the secondary controller 408 and the transistor 410 are on different wafers that are part of a multi-chip package. In another example, the secondary controller 408 and the transistor 410 are integrated on the same wafer.

第5圖是根據本發明的實施例，以斷續傳導模式(DCM)操作的、如第4A圖所示的電源變換系統300的簡化時序圖。該圖僅僅是示例，其不應該過度地限制申請專利範圍。本領域的普通技術人員將認識到許多變更、替換和修改。例如，波形502將功率開關330接通或關斷表示為時間函數，波形504將二次電流352表示為時間函數，而波形506將回饋信號360表示為時間函數。此外，波形508將電壓信號362(例如，在端子DR處)表示為時間函數，波形510將電壓信號366(例如，在端子G2處)表示為時間函數，波形512將流過電晶體310的溝道電流368表示為時間函數，而波形514將流過電晶體310的體二極體(例如，寄生二極體)的體二極體電流370表示為時間函數。 FIG. 5 is a simplified timing diagram of the power conversion system 300 shown in FIG. 4A operating in a discontinuous conduction mode (DCM) according to an embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, waveform 502 represents the power switch 330 on or off as a function of time, waveform 504 represents the secondary current 352 as a function of time, and waveform 506 represents the feedback signal 360 as a function of time. In addition, waveform 508 represents the voltage signal 362 (for example, at terminal DR) as a function of time, waveform 510 represents the voltage signal 366 (for example, at terminal G2) as a function of time, and waveform 512 will flow through the trench of transistor 310 The track current 368 is represented as a function of time, and the waveform 514 represents the body diode current 370 flowing through a body diode (eg, a parasitic diode) of the transistor 310 as a function of time.

例如，開關330的開關週期包括開關330閉合(例如，接通)的接通時間段和開關330斷開(例如，關斷)的關斷時間段。在另 一示例中，如第5圖所示，開關330的接通時間段(例如，Ton)開始於時刻t4，結束於時刻t5；開關330的關斷時間段(例如，Toff)開始於時刻t5，結束於時刻t9。與包括一次繞組304和二次繞組306相關聯的退磁時段(例如，Tdemag)開始於時刻t5，結束於時刻t8。在另一示例中，t4 t5 t6 t7 t8 t9。 For example, the switching period of the switch 330 includes an on period during which the switch 330 is closed (eg, on) and an off period during which the switch 330 is off (eg, off). In another example, as shown in FIG. 5, the on-time period of the switch 330 (eg, T on ) starts at time t 4 and ends at time t 5 ; the off-time period of the switch 330 (eg, T off ) Starts at time t 5 and ends at time t 9 . A demagnetization period (eg, T demag ) associated with including the primary winding 304 and the secondary winding 306 starts at time t 5 and ends at time t 8 . In another example, t 4 t 5 t 6 t 7 t 8 t 9 .

根據一個實施例，在接通時間段(例如，Ton)期間，開關330閉合(例如，接通)，如波形502所示，能量被存儲在包括一次繞組304和二次繞組306的變壓器中。例如，二次電流352具有低值516(例如，幾乎為零)，如波形504所示。在另一示例中，由二次控制器308接收的電壓信號362(例如，VDR)具有高於零的值518(例如，如波形508所示)。在另一示例中，信號366處於邏輯低位準(例如，如波形510所示)，並且電晶體310關斷。在另一示例中，在接通時間段(例如，Ton)期間，溝道電流368具有低值520(例如，幾乎為零，如波形512所示)，並且體二極體電流370具有低值522(例如，幾乎為零，如波形514所示)。 According to one embodiment, during the on-time period (eg, T on ), the switch 330 is closed (eg, on), as shown by the waveform 502, and energy is stored in a transformer including the primary winding 304 and the secondary winding 306 . For example, the secondary current 352 has a low value 516 (eg, almost zero), as shown by the waveform 504. In another example, the voltage signal 362 (eg, V DR ) received by the secondary controller 308 has a value 518 (eg, as shown by the waveform 508) above zero. In another example, signal 366 is at a logic low level (eg, as shown by waveform 510) and transistor 310 is turned off. In another example, during the on-time period (eg, T on ), the channel current 368 has a low value of 520 (eg, almost zero, as shown by waveform 512), and the body diode current 370 has a low Value 522 (for example, almost zero, as shown by waveform 514).

根據另一實施例，在接通時間段的結束處(例如，在t5處)，開關330斷開(例如，關斷)，如波形502所示，並且能量被轉移到二次側。例如，二次電流352從值516增大到值524(例如，在t5處)，如波形504所示。在另一示例中，電壓信號362(例如，VDR)從值518減小到值526(例如，如波形508所示)。在另一示例中，值526低於第一閾值電壓528(例如，Vth1)和第二閾值電壓530(例如，Vth2)二者。在另一示例中，第一閾值電壓528(例如，Vth1)和第二閾值電壓530(例如，Vth2)二者均低於地電壓372(例如，零伏)。在另一示例中，電晶體310的體二極體開始導通，並且體二極體電流370從值522增加到值529(例如，如波形514所示)。此後，信號366從邏輯低位準變為邏輯高位準(例如，在t6處，如波形510所示)，並且在某些實施例中，電晶體310被接通。例如，溝道電流368從值520增加到值525(例如，在t6 處，如波形512所示)。在另一示例中，在電壓信號362(例如，VDR)從值518減小到值526的時刻與信號366從邏輯低位準變為邏輯高位準的時刻之間存在延時(例如，Td)。在另一示例中，該(例如，Td)為零。 According to another embodiment, at the end of the on time period (e.g., at t 5), the switch 330 turned off (e.g., turned off), as shown in the waveform 502, and the energy is transferred to the secondary side. For example, the secondary current 352 increases from a value 516 to a value 524 (eg, at t 5 ), as shown by the waveform 504. In another example, the voltage signal 362 (eg, V DR ) is reduced from a value 518 to a value 526 (eg, as shown by the waveform 508). In another example, the value 526 is lower than both the first threshold voltage 528 (eg, V th1 ) and the second threshold voltage 530 (eg, V th2 ). In another example, both the first threshold voltage 528 (eg, V th1 ) and the second threshold voltage 530 (eg, V th2 ) are lower than the ground voltage 372 (eg, zero volts). In another example, the body diode of the transistor 310 begins to conduct, and the body diode current 370 increases from a value of 522 to a value of 529 (for example, as shown by waveform 514). Thereafter, the signal 366 changes from a logic low level to a logic high level (for example, at t 6 as shown by the waveform 510), and in some embodiments, the transistor 310 is turned on. For example, the channel current 368 increases from a value of 520 to a value of 525 (eg, at t 6 as shown by waveform 512). In another example, there is a delay (e.g., T d ) between the time when the voltage signal 362 (eg, V DR ) decreases from a value 518 to a value 526 and the time when the signal 366 changes from a logic low level to a logic high level . In another example, this (eg, T d ) is zero.

根據另一實施例，在退磁時段(例如，Tdemag)中，開關330保持斷開(例如，關斷)，如波形502所示。例如，二次電流352從值524下降，如波形504所示。在另一示例中，如果電壓信號362(例如，VDR)大於第一閾值電壓528(例如，在t7處，如波形508所示)，則信號366從邏輯高位準變為邏輯低位準(例如，如波形510所示)。在另一示例中，電壓信號362(例如，VDR)再次下降為變得低於第一閾值信號528(例如，在t8處，如波形508所示)。在另一示例中，電晶體310被關斷，並且溝道電流368減小到低值534(例如，幾乎為零，如波形512所示)。在另一示例中，體二極體電流370流過電晶體310的體二極體，並減小到低值(例如，在t9處幾乎為零，如波形514所示)。在另一示例中，退磁時段在時刻t9結束。在另一示例中，緊接時刻t9，電壓信號362增加，如波形508的上升沿所示，並且該上升沿即使被感測到也不會被用於確定電源變換系統300的開關頻率(例如，負載條件)。在另一示例中，二次電流352等於溝道電流368和體二極體電流370的和。因此，在某些實施例中，波形512(例如，在t5和t9之間)的一部分和波形514(例如，在t5和t9之間)的一部分的結合等於波形504(例如，在t5和t9之間)的一部分。 According to another embodiment, during a demagnetization period (eg, T demag ), the switch 330 remains off (eg, off), as shown by the waveform 502. For example, the secondary current 352 drops from the value 524 as shown by the waveform 504. In another example, if the voltage signal 362 (eg, V DR ) is greater than the first threshold voltage 528 (eg, at t 7 , as shown by waveform 508), the signal 366 changes from a logic high level to a logic low level ( (For example, as shown by waveform 510). In another example, the voltage signal 362 (eg, V DR ) drops again to become lower than the first threshold signal 528 (eg, at t 8 , as shown by waveform 508). In another example, the transistor 310 is turned off, and the channel current 368 is reduced to a low value 534 (eg, almost zero, as shown by the waveform 512). In another example, a body diode current 370 flows through the body diode of the transistor 310 and decreases to a low value (for example, almost zero at t 9 as shown by the waveform 514). In another example, the demagnetization period ends at time t 9 . In another example, immediately after time t 9 , the voltage signal 362 increases, as shown by the rising edge of the waveform 508, and even if the rising edge is sensed, it will not be used to determine the switching frequency of the power conversion system 300 ( (Eg load conditions). In another example, the secondary current 352 is equal to the sum of the channel current 368 and the body diode current 370. Thus, in some embodiments, waveform 512 (e.g., between t 5 and t 9) and a portion of a waveform 514 (e.g., between t 5 and t 9) bound a portion of the waveform is equal to 504 (e.g., Between t 5 and t 9 ).

根據本發明的另一實施例，第5圖是以斷續傳導模式(DCM)操作的示於第4B圖中的電源變換系統400的簡化時序圖。例如，波形502將功率開關430接通或關斷表示為時間函數，波形504將二次電流452表示為時間函數，而波形506將回饋信號460表示為時間函數。此外，波形508將電壓信號462(例如，在端子DR處)表示為時間函數，波形510將電壓信號466(例如，在端子G2處)表示為時間函數，波形512將流過電晶體410的溝道電流468表示為時間函數，而波形514 將流過電晶體410的體二極體(例如，寄生二極體)的體二極體電流480表示為時間函數。 According to another embodiment of the present invention, FIG. 5 is a simplified timing diagram of the power conversion system 400 shown in FIG. 4B operated in a discontinuous conduction mode (DCM). For example, waveform 502 represents the power switch 430 on or off as a function of time, waveform 504 represents the secondary current 452 as a function of time, and waveform 506 represents the feedback signal 460 as a function of time. In addition, waveform 508 represents the voltage signal 462 (eg, at terminal DR) as a function of time, waveform 510 represents the voltage signal 466 (eg, at terminal G2) as a function of time, and waveform 512 will flow through the trench of transistor 410 Track current 468 is expressed as a function of time, while waveform 514 The body diode current 480 flowing through a body diode (eg, a parasitic diode) of the transistor 410 is represented as a function of time.

如上面所討論的和在這裡進一步強調的那樣，第4A及4B圖僅僅是示例，其不應該過度地限制申請專利範圍。本領域的普通技術人員將認識到許多變更、替換和修改。例如，以其他模式(例如，准諧振模式)操作的、示於第4A圖中的電源變換系統300或示於第4B圖中的電源變換系統400也能夠實現第4A及4B圖所示的方案。 As discussed above and further emphasized here, Figures 4A and 4B are merely examples, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, the power conversion system 300 shown in FIG. 4A or the power conversion system 400 shown in FIG. 4B that operates in other modes (for example, a quasi-resonant mode) can also implement the solutions shown in FIGS. 4A and 4B. .

在某些實施例中，如第5圖所示的方案是以連續傳導模式實現的。例如，如果二次控制器308感測到信號362(例如，VDR)的下降沿，則二次控制器308改變信號366以接通電晶體310。在另一示例中，控制器302在退磁時段結束(例如，二次電流352大於零)之前接通電晶體310，並且作為回應，信號362(例如，VDR)增大。在另一示例中，二次控制器308感測到信號362的上升沿，並且改變信號366以關斷電晶體310。 In some embodiments, the scheme shown in Figure 5 is implemented in a continuous conduction mode. For example, if the secondary controller 308 senses a falling edge of the signal 362 (eg, V DR ), the secondary controller 308 changes the signal 366 to turn on the transistor 310. In another example, the controller 302 turns on the transistor 310 before the end of the demagnetization period (eg, the secondary current 352 is greater than zero), and in response, the signal 362 (eg, V DR ) increases. In another example, the secondary controller 308 senses the rising edge of the signal 362 and changes the signal 366 to turn off the transistor 310.

第6圖是根據本發明的實施例，示出了作為電源變換系統300的一部分的二次控制器308的某些元件的簡化圖。該圖僅僅是示例，其不應該過度地限制申請專利範圍。本領域的普通技術人員將認識到許多變更、替換和修改。二次控制器308包括：鉗位元元件602、補償元件(offset component)604、上升沿感測元件606、比較器608和624、下降沿感測元件610、時序控制器612、邏輯控制元件614、閘極驅動器616、輕載感測器618、信號發生器620、振盪器622、欠壓鎖定元件628、以及參考信號發生器626。例如，二次控制器308的一些元件被用於同步整流，包括：鉗位元元件602、補償元件604、上升沿感測元件606、比較器608、下降沿感測元件610、時序控制器612、邏輯控制元件614、以及閘極驅動器616。在另一示例中，二次控制器308的某些元件被用於輸出電壓感測和控制，包括：輕載感測器618、信號發生器620、振盪器622、參考信號發生器626、邏輯控制元件614、以及閘極驅動器616。在 另一示例中，二次控制器308中用於輸出電壓感測和控制的元件和二次控制器308中用於同步整流的元件被集成在同一晶片上。 FIG. 6 is a simplified diagram showing certain elements of the secondary controller 308 as part of the power conversion system 300 according to an embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. The secondary controller 308 includes: a clamp element 602, an offset component 604, a rising edge sensing element 606, comparators 608 and 624, a falling edge sensing element 610, a timing controller 612, and a logic control element 614 , A gate driver 616, a light load sensor 618, a signal generator 620, an oscillator 622, an undervoltage lockout element 628, and a reference signal generator 626. For example, some elements of the secondary controller 308 are used for synchronous rectification, including: clamp element 602, compensation element 604, rising edge sensing element 606, comparator 608, falling edge sensing element 610, and timing controller 612 , A logic control element 614, and a gate driver 616. In another example, certain elements of the secondary controller 308 are used for output voltage sensing and control, including: light load sensor 618, signal generator 620, oscillator 622, reference signal generator 626, logic The control element 614 and the gate driver 616. in In another example, the elements in the secondary controller 308 for output voltage sensing and control and the elements in the secondary controller 308 for synchronous rectification are integrated on the same chip.

第7圖是根據本發明的實施例，包括如第6圖所示的二次控制器308並且以斷續傳導模式(DCM)進行操作的電源變換系統300的簡化時序圖。該圖僅僅是示例，其不應該過度地限制申請專利範圍。本領域的普通技術人員將認識到許多變更、替換和修改。例如，波形702將功率開關330接通或關斷表示為時間函數，波形704將回饋信號360表示為時間函數，而波形706將電壓信號362(例如，在端子390處)表示為時間函數。此外，波形708將信號366(例如，在端子392處)表示為時間函數，波形710將流過電晶體310的溝道電流368表示為時間函數，而波形712將指示輸出電壓350的電壓信號388(例如，在端子398處)表示為時間函數。 FIG. 7 is a simplified timing diagram of a power conversion system 300 including a secondary controller 308 as shown in FIG. 6 and operating in a discontinuous conduction mode (DCM) according to an embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, waveform 702 represents the power switch 330 on or off as a function of time, waveform 704 represents the feedback signal 360 as a function of time, and waveform 706 represents a voltage signal 362 (eg, at terminal 390) as a function of time. In addition, waveform 708 represents signal 366 (eg, at terminal 392) as a function of time, waveform 710 represents channel current 368 flowing through transistor 310 as a function of time, and waveform 712 will indicate voltage signal 388 of output voltage 350 (For example, at terminal 398) is represented as a function of time.

根據一個實施例，鉗位元元件602從端子390(例如，端子DR)接收電壓信號362(例如，VDR)。例如，上升沿感測元件606、比較器608和下降沿感測元件610接收信號658，該信號658等於由補償元件604修改的電壓信號362。在另一示例中，上升沿感測元件606、比較器608和下降沿感測元件610基於至少與信號658相關聯的資訊分別輸出信號670、660和650。在另一示例中，時序控制器612接收信號670、660和650，並向邏輯控制器614輸出信號672以便驅動電晶體310。在一些實施例中，補償組件604被省去。 According to one embodiment, the clamp element 602 receives a voltage signal 362 (eg, V DR ) from a terminal 390 (eg, terminal DR ). For example, the rising edge sensing element 606, the comparator 608, and the falling edge sensing element 610 receive a signal 658 that is equal to the voltage signal 362 modified by the compensation element 604. In another example, rising-edge sensing element 606, comparator 608, and falling-edge sensing element 610 output signals 670, 660, and 650, respectively, based on information associated with at least signal 658. In another example, the timing controller 612 receives signals 670, 660, and 650 and outputs a signal 672 to the logic controller 614 to drive the transistor 310. In some embodiments, the compensation component 604 is omitted.

根據另一實施例，在時刻t16之前，電源變換系統300在無載/輕載條件下，並且系統300的開關頻率保持較低(例如，低於閾值)。例如，在接通時間段(例如，在時刻t11和時刻t12之間)中，開關330閉合(例如，接通)，如波形702所示，並且能量被存儲在包括一次繞組304和二次繞組306的變壓器中。在另一示例中，電壓信號362(例如，在端子DR處)具有值714(例如，如波形706所示)，並且被鉗位元元件602鉗位元。在另一示例中，信號366(例如，在端子G2處)處於 邏輯低位準(例如，如波形708所示)，並且電晶體310關斷。在另一示例中，在接通時間段(例如，Ton)中，溝道電流368具有低值716(例如，幾乎為零，如波形710所示)。在另一示例中，電壓信號388(例如，Vs)具有值718(例如，如波形712所示)。 According to another embodiment, before time t 16 , the power conversion system 300 is under no-load / light-load conditions, and the switching frequency of the system 300 remains low (eg, below a threshold). For example, during the on-time period (for example, between time t 11 and time t 12 ), the switch 330 is closed (for example, on) as shown by the waveform 702 and the energy is stored including the primary windings 304 and two Secondary transformer 306. In another example, the voltage signal 362 (eg, at the terminal DR) has a value 714 (eg, as shown by the waveform 706) and is clamped by the clamp element 602. In another example, the signal 366 (eg, at the terminal G2) is at a logic low level (eg, as shown by the waveform 708), and the transistor 310 is turned off. In another example, during the on-time period (eg, T on ), the channel current 368 has a low value of 716 (eg, almost zero, as shown by waveform 710). In another example, the voltage signal 388 (eg, V s ) has a value of 718 (eg, as shown by waveform 712).

根據另一實施例，在接通時間段的結束處(例如，在t12處)，開關330斷開(例如，關斷)，如波形702所示，並且能量被轉移到二次側。例如，電壓信號362從值714減小到值720(例如，如波形706所示)。在另一示例中，值720低於第三閾值電壓722(例如，Vth3)和第四閾值電壓724(例如，Vth4)二者。在另一示例中，第三閾值電壓722(例如，Vth3)和第四閾值電壓724(例如，Vth4)二者均低於地電壓372。在另一示例中，電晶體310的體二極體開始導通，並且體二極體電流370在大小上增加。此後，信號366從邏輯低位準變為邏輯高位準(例如，在t13處，如波形708所示)，並且在某些實施例中，電晶體310被接通。例如，第三閾值電壓722(例如，Vth3)和第四閾值電壓724(例如，Vth4)分別與第一閾值電壓528和第二閾值電壓530相同。 According to another embodiment, at the end of the on-time period (eg, at t 12 ), the switch 330 is turned off (eg, off), as shown by the waveform 702, and energy is transferred to the secondary side. For example, the voltage signal 362 decreases from a value 714 to a value 720 (eg, as shown by the waveform 706). In another example, the value 720 is lower than both the third threshold voltage 722 (eg, V th3 ) and the fourth threshold voltage 724 (eg, V th4 ). In another example, both the third threshold voltage 722 (eg, V th3 ) and the fourth threshold voltage 724 (eg, V th4 ) are lower than the ground voltage 372. In another example, the body diode of the transistor 310 starts to conduct, and the body diode current 370 increases in size. Thereafter, the signal 366 changes from a logic low level to a logic high level (eg, at t 13 as shown by the waveform 708), and in some embodiments, the transistor 310 is turned on. For example, the third threshold voltage 722 (for example, V th3 ) and the fourth threshold voltage 724 (for example, V th4 ) are the same as the first threshold voltage 528 and the second threshold voltage 530, respectively.

根據另一實施例，當電壓信號362從值714減小到值720(例如，如波形706所示)時，下降沿感測元件610感測到電壓信號362的下降，並且改變信號650以接通電晶體310。例如，作為回應，溝道電流368從值716增大到值726(例如，在t13處，如波形710所示)。在另一示例中，電晶體310的汲極端和源極端之間的電壓下降基於以下公式確定：V DS_M2=-I sec ×R ds_on (公式1) According to another embodiment, when the voltage signal 362 decreases from a value 714 to a value 720 (for example, as shown by the waveform 706), the falling edge sensing element 610 senses a drop in the voltage signal 362 and changes the signal 650 to connect Electricity crystal 310. For example, in response, the channel current 368 increases from a value of 716 to a value of 726 (eg, at t 13 as shown by waveform 710). In another example, the voltage between the drain terminal and the source terminal of transistor 310 drops is determined based on the formula: V DS_M 2 = - I sec × R ds_on ( Equation 1)

其中，VDS_M2表示電晶體310的汲極端和源極端之間的電壓下降，Isec表示二次電流352，而Rds_on表示電晶體310的導通電阻。 Among them, V DS_M2 indicates the voltage drop between the drain terminal and the source terminal of the transistor 310, I sec indicates the secondary current 352, and R ds_on indicates the on-resistance of the transistor 310.

根據某些實施例，因為電晶體310的導通電阻非常小，所以電晶體310的汲極端和源極端之間的電壓下降的大小遠遠小於整流二極體(例如，二極體124或二極體260)的正向電壓。例如，當二次電流 352變得很小(例如，接近零)時，電晶體310的汲極端和源極端之間的電壓下降在大小上變得非常小，並且電壓信號362在大小上非常小。在另一示例中，如果信號658在大小上大於參考信號652，則比較器608改變信號660以關斷電晶體310。在另一示例中，信號366從邏輯高位準變為邏輯低位準(例如，在t14處，如波形708所示)，並且電晶體310關斷。在另一示例中，電晶體310的體二極體再次開始導通，並且體二極體電流370在大小上減小(例如，最終在t15處達到幾乎為零)。因此，在一些實施例中，能量被完全傳遞到輸出。 According to some embodiments, because the on-resistance of transistor 310 is very small, the magnitude of the voltage drop between the drain and source terminals of transistor 310 is much smaller than that of a rectifying diode (e.g., diode 124 or diode) Body 260). For example, when the secondary current 352 becomes small (for example, near zero), the voltage drop between the drain terminal and the source terminal of the transistor 310 becomes very small in size, and the voltage signal 362 is very small in size . In another example, if the signal 658 is larger in size than the reference signal 652, the comparator 608 changes the signal 660 to turn off the transistor 310. In another example, the signal 366 changes from a logic high level to a logic low level (eg, at t 14 as shown by the waveform 708) and the transistor 310 is turned off. In another example, the body diode of the transistor 310 begins to conduct again, and the body diode current 370 decreases in size (eg, eventually reaches almost zero at t 15 ). Therefore, in some embodiments, energy is fully transferred to the output.

在一個實施例中，二次控制器308通過信號388(例如，Vs)連續監測輸出電壓350。例如，比較器624接收參考信號680和信號388(例如，Vs)，並且輸出信號682。在另一示例中，輕載感測器618從振盪器622接收時鐘信號並且從時序控制器612接收信號676。在另一示例中，信號676指示信號362中的某些開關事件(例如，上升沿或下降沿)。在另一示例中，輕載感測器618輸出指示電源變換系統300的開關頻率的信號678。在另一示例中，信號發生器620接收信號678和信號682，並向邏輯控制元件614輸出信號684以影響電晶體310的狀態。 In one embodiment, the secondary controller 308 continuously monitors the output voltage 350 through a signal 388 (eg, V s ). For example, the comparator 624 receives a reference signal 680 and a signal 388 (eg, V s ), and outputs a signal 682. In another example, the light load sensor 618 receives a clock signal from the oscillator 622 and a signal 676 from the timing controller 612. In another example, the signal 676 indicates certain switching events (eg, rising or falling edges) in the signal 362. In another example, the light load sensor 618 outputs a signal 678 indicating the switching frequency of the power conversion system 300. In another example, the signal generator 620 receives the signals 678 and 682 and outputs a signal 684 to the logic control element 614 to affect the state of the transistor 310.

在另一實施例中，如果輸出電壓350在任意條件下(例如，當輸出負載條件從無載/輕載條件變為滿載條件時(例如，在t16和t17之間))下降到低於閾值位準，則輸出電壓350減小(例如，低於閾值位準)。例如，如果信號388(例如，Vs)從在大小上大於參考信號680的第一值變為在大小上低於參考信號680的第二值(例如，在t16處，如波形712所示)，則比較器624在信號682中生成脈衝以便在短時間段內接通電晶體310。在一些實施例中，如果信號678指示電源變換系統300在無載/輕載條件下，則信號發生器620在信號684中輸出脈衝，並且作為回應，閘極驅動器616在信號366中生成脈衝730(例如，如波形708所示)。例如，信號362(例如，在端子DR處)減小到值728(例如，在t16和t17之間，如波形706所示)。在另一示例中，在與信號366中的脈衝 730相關聯的脈衝時段期間，電晶體310被接通，並且溝道電流368以不同方向(例如，從輸出電容器312通過電晶體310到地)流動，如波形710所示。在另一示例中，回饋信號360在大小上增加，並形成脈衝(例如，在t16和t17之間，如波形704所示)。根據某些實施例，控制器302感測到回饋信號360的脈衝，並且作為回應，增大一次繞組304的峰值電流和開關頻率以便向二次側傳遞更多的能量。例如，輸出電壓350和電壓信號388最終在大小上增加(例如，在t18處，如波形712所示)。 In another embodiment, if the output voltage 350 drops to low under any condition (for example, when the output load condition changes from no-load / light-load condition to full-load condition (for example, between t 16 and t 17 )) At the threshold level, the output voltage 350 decreases (eg, below the threshold level). For example, if the signal 388 (eg, V s ) changes from a first value that is larger in size than the reference signal 680 to a second value that is lower in size than the reference signal 680 (eg, at t 16 , as shown by waveform 712 ), The comparator 624 generates a pulse in the signal 682 to turn on the transistor 310 in a short period of time. In some embodiments, if signal 678 indicates that power conversion system 300 is under no-load / light-load conditions, signal generator 620 outputs a pulse in signal 684, and in response, gate driver 616 generates pulse 730 in signal 366 (For example, as shown by waveform 708). For example, the signal 362 (eg, at the terminal DR) is reduced to a value 728 (eg, between t 16 and t 17 as shown by the waveform 706). In another example, during the pulse period associated with pulse 730 in signal 366, transistor 310 is turned on and channel current 368 is in a different direction (e.g., from output capacitor 312 through transistor 310 to ground) Flow, as shown by waveform 710. In another example, the feedback signal 360 increases in size and forms a pulse (eg, between t 16 and t 17 as shown by waveform 704). According to some embodiments, the controller 302 senses the pulse of the feedback signal 360 and, in response, increases the peak current and switching frequency of the primary winding 304 in order to transfer more energy to the secondary side. For example, the output voltage 350 and the voltage signal 388 on the final size increases (e.g., at t 18, the waveform as shown in 712).

如上面所討論的和在這裡進一步強調的那樣，第6圖和第7圖僅僅是示例，其不應該過度地限制申請專利範圍。本領域的普通技術人員將認識到許多變更、替換和修改。例如，二次控制器408與第6圖所示的二次控制器308相同。 As discussed above and further emphasized here, Figures 6 and 7 are merely examples, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, the secondary controller 408 is the same as the secondary controller 308 shown in FIG. 6.

在某些實施例中，第7圖是包括二次控制器408並且以斷續傳導模式(DCM)進行操作的電源變換系統400的簡化時序圖。例如，波形702將功率開關430接通或關斷表示為時間函數，波形704將回饋信號460表示為時間函數，而波形706將電壓信號462表示為時間函數。此外，波形708將信號466表示為時間函數，波形710將流過電晶體410的溝道電流468表示為時間函數，而波形712將指示輸出電壓450的電壓信號488表示為時間函數。 In some embodiments, FIG. 7 is a simplified timing diagram of a power conversion system 400 including a secondary controller 408 and operating in a discontinuous conduction mode (DCM). For example, waveform 702 represents the power switch 430 on or off as a function of time, waveform 704 represents the feedback signal 460 as a function of time, and waveform 706 represents a voltage signal 462 as a function of time. In addition, waveform 708 represents the signal 466 as a function of time, waveform 710 represents the channel current 468 flowing through the transistor 410 as a function of time, and waveform 712 represents a voltage signal 488 indicating the output voltage 450 as a function of time.

在一些實施例中，以其他模式(例如，連續傳導模式和臨界傳導模式(例如，准諧振模式))操作的作為電源變換系統300的一部分的二次控制器308或作為電源變換系統400的一部分的二次控制器408也可實現如第6圖和第7圖所示的方案。 In some embodiments, the secondary controller 308 as part of the power conversion system 300 or as part of the power conversion system 400 operates in other modes (eg, continuous conduction mode and critical conduction mode (eg, quasi-resonant mode)). The secondary controller 408 can also implement the solutions shown in FIG. 6 and FIG. 7.

根據另一實施例，用於調節電源變換系統的系統控制器包括第一控制器端子和第二控制器端子。該系統控制器被配置為在第一控制器端子接收至少輸入信號，並且基於至少與該輸入信號相關聯的資訊，在第二控制器端子生成閘極驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。該系統控制器還被配置為：如果輸入 信號大於第一閾值，則生成處於第一邏輯位準的閘極驅動信號以關斷電晶體，而如果輸入信號從大於第二閾值的第一值變為小於第二閾值的第二值，則將閘極驅動信號從第一邏輯位準變為第二邏輯位準以接通電晶體。例如，該系統根據第4A圖、第4B圖、第5圖、第6圖、和/或第7圖實現。 According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. The system controller is configured to receive at least an input signal at a first controller terminal, and based on information associated with at least the input signal, generate a gate drive signal at a second controller terminal to turn a transistor on or off to thereby Affects the current associated with the secondary winding of the power conversion system. The system controller is also configured to: If the signal is greater than the first threshold, a gate driving signal at a first logic level is generated to turn off the transistor, and if the input signal changes from a first value greater than a second threshold to a second value less than the second threshold, then The gate driving signal is changed from the first logic level to the second logic level to turn on the transistor. For example, the system is implemented according to Figs. 4A, 4B, 5, 5, 6, and / or 7.

根據另一實施例，用於調節電源變換系統的系統控制器包括第一控制器端子和第二控制器端子。該系統控制器被配置為在第一控制器端子接收至少輸入信號，該輸入信號正比於與電源變換系統的二次繞組相關聯的輸出電壓，並且基於至少與輸入信號相關聯的資訊，在第二控制器端子生成閘極驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。該系統控制器還被配置為：只有輸入信號從大於第一閾值的第一值變為小於第一閾值的第二值時，才生成閘極驅動信號的脈衝以在與該脈衝相關聯的脈衝時段期間接通電晶體。例如，至少根據第4A圖、第4B圖、第6圖、和/或第7圖來實現該系統。 According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. The system controller is configured to receive at least an input signal at a first controller terminal, the input signal being proportional to an output voltage associated with a secondary winding of the power conversion system, and based on at least information associated with the input signal, at the first The two controller terminals generate a gate drive signal to turn on or off the transistor, thereby affecting the current associated with the secondary winding of the power conversion system. The system controller is further configured to generate a pulse of the gate drive signal only when the input signal changes from a first value greater than a first threshold value to a second value less than the first threshold value to a pulse associated with the pulse. The transistor is turned on during the period. For example, the system is implemented based on at least Figure 4A, Figure 4B, Figure 6, and / or Figure 7.

根據另一實施例，用於調節電源變換系統的系統控制器包括第一比較器、信號感測器和驅動元件。第一比較器被配置為接收輸入信號，並基於至少與輸入信號相關聯的資訊輸出第一比較信號。信號感測器被配置為接收輸入信號，並基於至少與輸入信號相關聯的資訊輸出第一感測信號。驅動元件被配置為基於至少與第一比較信號和第一感測信號相關聯的資訊輸出閘極驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。比較器還被配置為確定輸入信號是否大於第一閾值。信號感測器還被配置為確定輸入信號是否從大於第二閾值的第一值變為小於第二閾值的第二值。驅動元件還被配置為：如果第一比較信號指示輸入信號大於第一閾值，則生成處於第一邏輯位準的閘極驅動信號以關斷電晶體，而如果第一感測信號指示輸入信號從大於第二閾值的第一值變為小於第二閾值的第二值，則將閘極驅動信號從第一邏輯位準變為第二 邏輯位準以接通電晶體。例如，該系統根據第4A圖、第4B圖、第5圖、第6圖、和/或第7圖實現。 According to another embodiment, a system controller for adjusting a power conversion system includes a first comparator, a signal sensor, and a driving element. The first comparator is configured to receive an input signal and output a first comparison signal based on information associated with at least the input signal. The signal sensor is configured to receive an input signal and output a first sensing signal based on at least information associated with the input signal. The driving element is configured to output the gate driving signal to turn on or off the transistor based on the information associated with at least the first comparison signal and the first sensing signal to affect the current associated with the secondary winding of the power conversion system. The comparator is further configured to determine whether the input signal is greater than a first threshold. The signal sensor is further configured to determine whether the input signal changes from a first value greater than a second threshold value to a second value less than the second threshold value. The driving element is further configured to: if the first comparison signal indicates that the input signal is greater than a first threshold value, generate a gate driving signal at a first logic level to turn off the transistor, and if the first sensing signal indicates that the input signal is from If the first value greater than the second threshold becomes the second value smaller than the second threshold, the gate driving signal is changed from the first logic level to the second Logic level to turn on the transistor. For example, the system is implemented according to Figs. 4A, 4B, 5, 5, 6, and / or 7.

在一個實施例中，用於調節電源變換系統的系統控制器包括比較器、脈衝信號發生器和驅動元件。比較器被配置為接收輸入信號，並基於至少與輸入信號相關聯的資訊輸出比較信號。脈衝信號發生器被配置為接收至少比較信號，並基於至少與該比較信號相關聯的資訊生成脈衝信號。驅動元件被配置為接收脈衝信號，並基於至少與該脈衝信號相關聯的資訊生成閘極驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。比較器還被配置為確定輸入信號是大於還是小於閾值。脈衝信號發生器還被配置為：只有在比較信號指示輸入信號從大於閾值的第一值變為小於閾值的第二值時，才生成脈衝信號的第一脈衝。驅動元件還被配置為：回應於脈衝信號的第一脈衝，生成閘極驅動信號的第二脈衝以在與第二脈衝相關聯的脈衝時段中接通電晶體。例如，至少根據第4A圖、第4B圖、第6圖、和/或第7圖來實現該系統。 In one embodiment, a system controller for regulating a power conversion system includes a comparator, a pulse signal generator, and a driving element. The comparator is configured to receive an input signal and output a comparison signal based on information associated with at least the input signal. The pulse signal generator is configured to receive at least a comparison signal and generate a pulse signal based on at least information associated with the comparison signal. The driving element is configured to receive a pulse signal and generate a gate driving signal to turn on or off the transistor based on information associated with at least the pulse signal to affect the current associated with the secondary winding of the power conversion system. The comparator is also configured to determine whether the input signal is greater than or less than a threshold. The pulse signal generator is further configured to generate a first pulse of the pulse signal only when the comparison signal indicates that the input signal changes from a first value greater than a threshold value to a second value less than the threshold value. The driving element is further configured to generate a second pulse of the gate driving signal in response to the first pulse of the pulse signal to turn on the transistor in a pulse period associated with the second pulse. For example, the system is implemented based on at least Figure 4A, Figure 4B, Figure 6, and / or Figure 7.

在另一實施例中，用於調節電源變換系統的方法包括：接收至少輸入信號，處理與該輸入信號相關聯的資訊，並基於至少與該輸入信號相關聯的資訊生成閘極驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。基於至少與該輸入信號相關聯的資訊生成閘極驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流的過程包括：如果輸入信號大於第一閾值，則生成處於第一邏輯位準的閘極驅動信號以關斷電晶體，而如果輸入信號從大於第二閾值的第一值變為小於第二閾值的第二值，則將閘極驅動信號從第一邏輯位準變為第二邏輯位準以接通電晶體。例如，該方法根據第4A圖、第4B圖、第5圖、第6圖、和/或第7圖實現。 In another embodiment, a method for adjusting a power conversion system includes: receiving at least an input signal, processing information associated with the input signal, and generating a gate driving signal for receiving based on the information associated with at least the input signal. Turning the transistor on or off affects the current associated with the secondary winding of the power conversion system. The process of generating a gate drive signal to turn on or off a transistor based on information associated with at least the input signal to affect the current associated with the secondary winding of the power conversion system includes: if the input signal is greater than a first threshold, A gate drive signal at a first logic level is generated to turn off the transistor, and if the input signal changes from a first value greater than a second threshold value to a second value less than a second threshold value, the gate drive signal is changed from the first value A logic level becomes a second logic level to turn on the transistor. For example, the method is implemented according to FIG. 4A, FIG. 4B, FIG. 5, FIG. 6, and / or FIG.

在另一實施例中，用於調節電源變換系統的方法包括：接收至少輸入信號，該輸入信號正比於與電源變換系統的二次繞組相關聯的輸出電壓，處理與該輸入信號相關聯的資訊，並基於至少與該輸入信號 相關聯的資訊生成閘極驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。基於至少與該輸入信號相關聯的資訊生成閘極驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流的過程包括：只有在輸入信號從大於第一閾值的第一值變為小於第一閾值的第二值時，才生成閘極驅動信號的脈衝以在與該脈衝相關聯的脈衝時段期間接通電晶體。例如，至少根據第4A圖、第4B圖、第6圖、和/或第7圖來實現該方法。 In another embodiment, a method for adjusting a power conversion system includes: receiving at least an input signal that is proportional to an output voltage associated with a secondary winding of the power conversion system, and processing information associated with the input signal And based on at least the input signal The associated information generates a gate drive signal to turn the transistor on or off to affect the current associated with the secondary winding of the power conversion system. The process of generating a gate drive signal to turn on or off a transistor based on information associated with at least the input signal to affect the current associated with the secondary winding of the power conversion system includes: only when the input signal changes from greater than a first threshold A pulse of the gate drive signal is generated only when the first value of is changed to a second value that is less than the first threshold to turn on the transistor during the pulse period associated with the pulse. For example, the method is implemented based on at least Figure 4A, Figure 4B, Figure 6, and / or Figure 7.

在另一實施例中，用於調節電源變換系統的方法包括：接收輸入信號，處理與輸入信號相關聯的資訊，並確定輸入信號是否大於第一閾值。該方法還包括：基於至少與輸入信號相關聯的資訊生成比較信號，確定輸入信號是否從大於第二閾值的第一值變為小於第二閾值的第二值，並基於至少與輸入信號相關聯的資訊生成感測信號。此外，該方法包括：基於至少與比較信號和感測信號相關聯的資訊輸出閘極驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。基於至少與比較信號和感測信號相關聯的資訊輸出閘極驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流的過程包括：如果比較信號指示輸入信號大於第一閾值，則生成處於第一邏輯位準的閘極驅動信號以關斷電晶體，而如果感測信號指示輸入信號從大於第二閾值的第一值變為小於第二閾值的第二值，則將閘極驅動信號從第一邏輯位準變為第二邏輯位準以接通電晶體。例如，該方法根據第4A圖、第4B圖、第5圖、第6圖、和/或第7圖實現。 In another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and determining whether the input signal is greater than a first threshold. The method further includes generating a comparison signal based on at least information associated with the input signal, determining whether the input signal has changed from a first value greater than a second threshold value to a second value less than a second threshold value, and based on at least being associated with the input signal. Information generated by the sensor. In addition, the method includes outputting a gate driving signal to turn on or off the transistor based on information associated with at least the comparison signal and the sensing signal to affect the current associated with the secondary winding of the power conversion system. The process of outputting the gate drive signal to turn on or off the transistor based on the information associated with at least the comparison signal and the sensing signal to affect the current associated with the secondary winding of the power conversion system includes: if the comparison signal indicates an input signal Greater than the first threshold, a gate driving signal at a first logic level is generated to turn off the transistor, and if the sensing signal indicates that the input signal changes from a first value greater than a second threshold to a second less than the second threshold Value, the gate driving signal is changed from the first logic level to the second logic level to turn on the transistor. For example, the method is implemented according to FIG. 4A, FIG. 4B, FIG. 5, FIG. 6, and / or FIG.

在另一實施例中，用於調節電源變換系統的方法包括：接收輸入信號，處理與輸入信號相關聯的資訊，並確定輸入信號是大於還是小於閾值。該方法還包括：基於至少與第一輸入信號相關聯的資訊生成比較信號，接收比較信號，並處理與比較信號相關聯的資訊。此外，該方法包括：基於至少與比較信號相關聯的資訊生成脈衝信號，接收脈衝信號，處理與該脈衝信號相關聯的資訊，並基於至少與該脈衝信號相關聯的 資訊生成閘極驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。基於至少與比較信號相關聯的資訊生成脈衝信號的過程包括：只有比較信號指示輸入信號從大於閾值的第一值變為小於閾值的第二值時，才生成脈衝信號的第一脈衝。基於至少與該脈衝信號相關聯的資訊生成閘極驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流的過程包括：回應於脈衝信號的第一脈衝，生成閘極驅動信號的第二脈衝以在與第二脈衝相關聯的脈衝時段期間接通電晶體。例如，至少根據第4A圖、第4B圖、第6圖、和/或第7圖來實現該方法。 In another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and determining whether the input signal is greater than or less than a threshold. The method further includes generating a comparison signal based on information associated with at least the first input signal, receiving the comparison signal, and processing the information associated with the comparison signal. In addition, the method includes generating a pulse signal based on at least information associated with the comparison signal, receiving the pulse signal, processing the information associated with the pulse signal, and based on at least the pulse signal associated with the pulse signal. The information generates a gate drive signal to turn the transistor on or off, thereby affecting the current associated with the secondary winding of the power conversion system. The process of generating a pulse signal based on at least information associated with the comparison signal includes generating a first pulse of the pulse signal only when the comparison signal indicates that the input signal changes from a first value greater than a threshold value to a second value less than the threshold value. The process of generating a gate drive signal to turn on or off the transistor based on information associated with at least the pulse signal to affect the current associated with the secondary winding of the power conversion system includes: a first pulse in response to the pulse signal, A second pulse of the gate drive signal is generated to turn on the transistor during a pulse period associated with the second pulse. For example, the method is implemented based on at least Figure 4A, Figure 4B, Figure 6, and / or Figure 7.

第8圖是根據本發明的另一實施例，以斷續傳導模式(DCM)操作的、如第4A圖所示的電源變換系統300的簡化時序圖。該圖僅僅是示例，其不應該過度地限制申請專利範圍。本領域的普通技術人員將認識到許多變更、替換和修改。例如，波形802將功率開關330接通或關斷表示為時間函數，波形808將電壓信號362(例如，在端子DR處的VDR)表示為時間函數，而波形810將信號366(例如，在端子G2處)表示為時間函數。 FIG. 8 is a simplified timing diagram of the power conversion system 300 shown in FIG. 4A operating in a discontinuous conduction mode (DCM) according to another embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, waveform 802 represents power switch 330 on or off as a function of time, waveform 808 represents voltage signal 362 (e.g., V DR at terminal DR ) as a function of time, and waveform 810 represents signal 366 (e.g., at (At terminal G2) is shown as a function of time.

如第8圖所示，根據一些實施例，二次控制器308在端子390處接收電壓信號362(例如，VDR)，並確定電壓信號362是否超出第一參考電壓829(例如，Vref1)。例如，第一參考電壓829(例如，Vref1)高於第一閾值電壓828(例如，Vth1)，並且第一閾值電壓828(例如，Vth1)高於第二閾值電壓830(例如，Vth2)。在另一示例中，第一參考電壓829(例如，Vref1)高於地電壓372(例如，零伏)，並且第一閾值電壓828(例如，Vth1)和第二閾值電壓830(例如，Vth2)二者均低於地電壓372(例如，零伏)。在另一示例中，第一參考電壓829(例如，Vref1)大約等於15V。 As shown in FIG. 8, according to some embodiments, the secondary controller 308 receives the voltage signal 362 (eg, V DR ) at the terminal 390 and determines whether the voltage signal 362 exceeds the first reference voltage 829 (eg, V ref1 ) . For example, the first reference voltage 829 (for example, V ref1 ) is higher than the first threshold voltage 828 (for example, V th1 ), and the first threshold voltage 828 (for example, V th1 ) is higher than the second threshold voltage 830 (for example, V V th2 ). In another example, the first reference voltage 829 (eg, V ref1 ) is higher than the ground voltage 372 (eg, zero volts), and the first threshold voltage 828 (eg, V th1 ) and the second threshold voltage 830 (eg, V th1 ) V th2 ) Both are below ground voltage 372 (eg, zero volts). In another example, the first reference voltage 829 (eg, V ref1 ) is approximately equal to 15V.

在一個實施例中，如果電壓信號362被二次控制器308確定為超出第一參考電壓829，則二次控制器308回應於電壓信號362 (例如，VDR)從高於第一參考電壓829的值減小到低於第一閾值電壓828(例如，Vth1)和第二閾值電壓830(例如，Vth2)二者的值，將信號366從邏輯低位準變為邏輯高位準以便接通電晶體310。在另一實施例中，如果電壓信號362未被二次控制器308確定為超出第一參考電壓829，則即使電壓信號362(例如，VDR)減小到低於第一閾值電壓828(例如，Vth1)和第二閾值電壓830(例如，Vth2)二者的值，二次控制器308也不會將信號366從邏輯低位準變為邏輯高位準，從而電晶體310保持關斷。 In one embodiment, if the voltage signal 362 is determined by the secondary controller 308 to exceed the first reference voltage 829, the secondary controller 308 responds to the voltage signal 362 (eg, V DR ) from above the first reference voltage 829 Decreases to a value below both the first threshold voltage 828 (for example, V th1 ) and the second threshold voltage 830 (for example, V th2 ), changing the signal 366 from a logic low level to a logic high level for turning on Transistor 310. In another embodiment, if the voltage signal 362 is not determined by the secondary controller 308 to exceed the first reference voltage 829, then even if the voltage signal 362 (eg, V DR ) decreases below the first threshold voltage 828 (eg, V th1 ) and the second threshold voltage 830 (for example, V th2 ), the secondary controller 308 also does not change the signal 366 from a logic low level to a logic high level, so that the transistor 310 remains off.

例如，開關330的開關週期包括開關330閉合(例如，接通)期間的接通時間段和開關330斷開(例如，關斷)期間的關斷時間段。在另一示例中，如第8圖所示，開關330的接通時間段(例如，Ton)開始於時刻t24，結束於時刻t25；開關330的關斷時間段(例如，Toff)開始於時刻t25，結束於時刻t30。在另一示例中，與包括一次繞組304和二次繞組306的變壓器相關聯的退磁時段(例如，Tdemag)開始於時刻t25，結束於時刻t30或時刻t30之前。在另一示例中，t24 t25 t30。 For example, the switching period of the switch 330 includes an on period during which the switch 330 is closed (eg, on) and an off period during which the switch 330 is off (eg, off). In another example, as shown in FIG. 8, the on-time period (for example, T on ) of the switch 330 starts at time t 24 and ends at time t 25 ; the off-time period (for example, T off ) of the switch 330 ) Starts at time t 25 and ends at time t 30 . In another example, a demagnetization period (eg, T demag ) associated with a transformer including a primary winding 304 and a secondary winding 306 starts at time t 25 and ends at time t 30 or before time t 30 . In another example, t 24 t 25 t 30 .

在一個實施例中，在接通時間段(例如，Ton)中，開關330閉合(例如，接通)，如波形802所示，並且能量被存儲在包括一次繞組304和二次繞組306的變壓器中。例如，二次電流352具有低值(例如，幾乎為零)。在另一示例中，由二次控制器308接收的電壓信號362(例如，VDR)具有高於零的值818(例如，如波形808所示)。在另一示例中，信號366處於邏輯低位準(例如，如波形810所示)，並且電晶體310關斷。在另一示例中，在接通時間段(例如，Ton)中，電晶體310的溝道電流368具有低值(例如，幾乎為零)，並且電晶體310的體二極體電流370具有低值(例如，幾乎為零)。 In one embodiment, during the on-time period (eg, T on ), the switch 330 is closed (eg, on), as shown by the waveform 802, and the energy is stored in the primary winding 304 and the secondary winding 306. Transformer. For example, the secondary current 352 has a low value (for example, almost zero). In another example, the voltage signal 362 (eg, V DR ) received by the secondary controller 308 has a value 818 (eg, as shown by the waveform 808) above zero. In another example, the signal 366 is at a logic low level (eg, as shown by the waveform 810) and the transistor 310 is turned off. In another example, during the on-time period (eg, T on ), the channel current 368 of the transistor 310 has a low value (eg, almost zero), and the body diode current 370 of the transistor 310 has Low value (for example, almost zero).

在另一實施例中，在接通時間段的結束處(例如，在時刻t25處)，開關330斷開(例如，關斷)，如波形802所示，並且能量被轉移到二次側。例如，二次電流352增大(例如，在時刻t25處)。在另一示例中，電壓信號362(例如，VDR)從值818減小到值826(例如，如波 形808所示)。在另一示例中，值826低於第一閾值電壓828(例如，Vth1)和第二閾值電壓830(例如，Vth2)二者。在另一示例中，第一閾值電壓828(例如，Vth1)和第二閾值電壓830(例如，Vth2)二者均低於地電壓372(例如，零伏)。在另一示例中，第一閾值電壓828(例如，Vth1)大約等於300mV，並且第二閾值電壓830(例如，Vth2)大約等於10mV。在另一示例中，電晶體310的體二極體374開始導通，並且體二極體374的體二極體電流370增大。 In another embodiment, at the end of the on-time period (for example, at time t 25 ), the switch 330 is turned off (for example, turned off), as shown by the waveform 802, and energy is transferred to the secondary side . For example, the secondary current 352 increases (for example, at time t 25 ). In another example, the voltage signal 362 (eg, V DR ) is reduced from a value 818 to a value 826 (eg, as shown by the waveform 808). In another example, the value 826 is lower than both the first threshold voltage 828 (eg, V th1 ) and the second threshold voltage 830 (eg, V th2 ). In another example, both the first threshold voltage 828 (eg, V th1 ) and the second threshold voltage 830 (eg, V th2 ) are lower than the ground voltage 372 (eg, zero volts). In another example, the first threshold voltage 828 (eg, V th1 ) is approximately equal to 300 mV, and the second threshold voltage 830 (eg, V th2 ) is approximately equal to 10 mV. In another example, the body diode 374 of the transistor 310 starts to conduct, and the body diode current 370 of the body diode 374 increases.

根據某些實施例，二次控制器308在端子390處接收電壓信號362(例如，VDR)，並確定電壓信號362是否超出第一參考電壓829(例如，Vref1)。在一個實施例中，第一參考電壓829(例如，Vref1)高於第一閾值電壓828(例如，Vth1)，並且第一閾值電壓828(例如，Vth1)高於第二閾值電壓830(例如，Vth2)。例如，第一參考電壓829(例如，Vref1)大約等於15V。在另一實施例中，如果電壓信號362(例如，值818)已被確定為超出第一參考電壓829(例如，在時刻t24和時刻t25之間，如波形808所示)，則二次控制器308回應於電壓信號362(例如，VDR)從高於第一參考電壓829的值(例如，值818)減小到低於第一閾值電壓828(例如，Vth1)和第二閾值電壓830(例如，Vth2)二者的值(例如，值826)，將信號366從邏輯低位準變為邏輯高位準(例如，在時刻t25處，如波形810所示，或在時刻t25之後的時刻)以便接通電晶體310。在另一實施例中，如果電壓信號362(例如，值818)已被確定為超出第一參考電壓829(例如，在時刻t24和時刻t25之間，如波形808所示)，則二次控制器308回應於電壓信號362(例如，VDR)從高於第一參考電壓829的值(例如，值818)減小到低於第二閾值電壓830(例如，Vth2)的值(例如，值826)，將信號366從邏輯低位準變為邏輯高位準(例如，在時刻t25處，如波形810所示，或在時刻t25之後的時刻)以便接通電晶體310。 According to some embodiments, the secondary controller 308 receives the voltage signal 362 (eg, V DR ) at the terminal 390 and determines whether the voltage signal 362 exceeds the first reference voltage 829 (eg, V ref1 ). In one embodiment, the first reference voltage 829 (eg, V ref1 ) is higher than the first threshold voltage 828 (eg, V th1 ), and the first threshold voltage 828 (eg, V th1 ) is higher than the second threshold voltage 830 (For example, V th2 ). For example, the first reference voltage 829 (eg, V ref1 ) is approximately equal to 15V. In another embodiment, if the voltage signal 362 (eg, value 818) has been determined to exceed the first reference voltage 829 (eg, between time t 24 and time t 25 , as shown by waveform 808), then two The secondary controller 308 decreases in response to the voltage signal 362 (eg, V DR ) from a value (eg, value 818) above the first reference voltage 829 to below a first threshold voltage 828 (eg, V th1 ) and a second The value of both the threshold voltage 830 (for example, V th2 ) (for example, the value 826) changes the signal 366 from a logic low level to a logic high level (for example, at time t 25 , as shown in waveform 810, or at time t 25 ), so that the transistor 310 is turned on. In another embodiment, if the voltage signal 362 (eg, value 818) has been determined to exceed the first reference voltage 829 (eg, between time t 24 and time t 25 , as shown by waveform 808), then two The secondary controller 308 reduces the voltage signal 362 (eg, V DR ) from a value (eg, value 818) above the first reference voltage 829 to a value (eg, V th2 ) below the second threshold voltage 830 (eg, V th2 ). For example, the value 826) changes the signal 366 from a logic low level to a logic high level (eg, at time t 25 , as shown by waveform 810, or at a time after time t 25 ) to turn on transistor 310.

例如，在電壓信號362(例如，VDR)從值818減小到值826的時刻與信號366從邏輯低位準變為邏輯高位準的時刻之間存在延時(例如，Td)。在另一示例中，該延時(例如，Td)為零。在另一示例中，在電晶體310接通之後，電晶體310的溝道電流368增大。在另一示例中，二次電流352等於溝道電流368和體二極體電流370的和。 For example, there is a delay (eg, T d ) between the time when the voltage signal 362 (eg, V DR ) decreases from the value 818 to the value 826 and the time when the signal 366 changes from a logic low level to a logic high level. In another example, the delay (eg, T d ) is zero. In another example, after the transistor 310 is turned on, the channel current 368 of the transistor 310 increases. In another example, the secondary current 352 is equal to the sum of the channel current 368 and the body diode current 370.

在另一實施例中，如果電壓信號362未被確定為超出第一參考電壓829，則不管電壓信號362(例如，VDR)是否減小到低於第一閾值電壓828(例如，Vth1)和第二閾值電壓830(例如，Vth2)二者的值，二次控制器308都將信號366保持在邏輯低位準以保持電晶體310關斷。在另一實施例中，如果電壓信號362未被確定為超出第一參考電壓829，則不管電壓信號362(例如，VDR)是否減小到低於第二閾值電壓830(例如，Vth2)的值，二次控制器308都將信號366保持在邏輯低位準以保持電晶體310關斷。 In another embodiment, if the voltage signal 362 is not determined to exceed the first reference voltage 829, it does not matter whether the voltage signal 362 (for example, V DR ) is reduced below the first threshold voltage 828 (for example, V th1 ) And the value of both the second threshold voltage 830 (eg, V th2 ), the secondary controller 308 maintains the signal 366 at a logic low level to keep the transistor 310 off. In another embodiment, if the voltage signal 362 is not determined to exceed the first reference voltage 829, it does not matter whether the voltage signal 362 (eg, V DR ) is reduced below the second threshold voltage 830 (eg, V th2 ) The secondary controller 308 keeps the signal 366 at a logic low level to keep the transistor 310 off.

根據一個實施例，在退磁時段期間，開關330保持斷開(例如，關斷)，如波形802所示。例如，二次電流352減小。在另一示例中，如果電壓信號362(例如，VDR)變得大於第一閾值電壓828(例如，如波形808所示)，則信號366從邏輯高位準變為邏輯低位準(例如，如波形810所示)。在另一示例中，電晶體310被關斷，並且電晶體310的溝道電流368減小到低值(例如，幾乎為零)。在另一示例中，電晶體310的體二極體電流370流過電晶體310的體二極體374，然後減小到低值。在另一示例中，退磁時段在時刻t30之前結束。在另一示例中，緊接退磁時段的結束，電壓信號362增大到值819，如波形808的上升沿所示。 According to one embodiment, the switch 330 remains open (eg, off) during the demagnetization period, as shown by the waveform 802. For example, the secondary current 352 decreases. In another example, if the voltage signal 362 (e.g., V DR ) becomes greater than the first threshold voltage 828 (e.g., as shown by waveform 808), the signal 366 changes from a logic high level to a logic low level (e.g., as Waveform 810). In another example, the transistor 310 is turned off, and the channel current 368 of the transistor 310 is reduced to a low value (eg, almost zero). In another example, the body diode current 370 of the transistor 310 flows through the body diode 374 of the transistor 310 and then decreases to a low value. In another example, the demagnetization period ends before time t 30 . In another example, immediately after the end of the demagnetization period, the voltage signal 362 increases to a value of 819, as shown by the rising edge of the waveform 808.

根據一些實施例，二次控制器308在端子390處接收電壓信號362(例如，VDR)，並確定電壓信號362是否超出第一參考電壓829(例如，Vref1)。在一個實施例中，第一參考電壓829(例如，Vref1)高於第一閾值電壓828(例如，Vth1)，並且第一閾值電壓828(例如， Vth1)高於第二閾值電壓830(例如，Vth2)。例如，第一參考電壓829(例如，Vref1)大約等於15V。在另一實施例中，如果電壓信號362(例如，值819)未被確定為超出第一參考電壓829(例如，在時刻t25之後但在時刻t30之前，如波形808所示)，則即使電壓信號362(例如，VDR)減小到低於第一閾值電壓828(例如，Vth1)和第二閾值電壓830(例如，Vth2)二者的值(例如，82827)，二次控制器308也不會將信號366從邏輯低位準變為邏輯高位準，從而電晶體310保持關斷。 According to some embodiments, the secondary controller 308 receives the voltage signal 362 (eg, V DR ) at the terminal 390 and determines whether the voltage signal 362 exceeds the first reference voltage 829 (eg, V ref1 ). In one embodiment, the first reference voltage 829 (eg, V ref1 ) is higher than the first threshold voltage 828 (eg, V th1 ), and the first threshold voltage 828 (eg, V th1 ) is higher than the second threshold voltage 830 (For example, V th2 ). For example, the first reference voltage 829 (eg, V ref1 ) is approximately equal to 15V. In another embodiment, if the voltage signal 362 (eg, value 819) is not determined to exceed the first reference voltage 829 (eg, after time t 25 but before time t 30 , as shown by waveform 808), Even if the voltage signal 362 (for example, V DR ) decreases to a value (for example, 82827) lower than both the first threshold voltage 828 (for example, V th1 ) and the second threshold voltage 830 (for example, V th2 ), two times The controller 308 also does not change the signal 366 from a logic low level to a logic high level, so that the transistor 310 remains off.

根據本發明的另一實施例，第8圖是以斷續傳導模式(DCM)操作的如第4B圖所示的電源變換系統400的簡化時序圖。例如，波形802將功率開關430接通或關斷表示為時間函數，波形808將電壓信號462(例如，在端子DR處)表示為時間函數，而波形810將信號466(例如，在端子G2處)表示為時間函數。 According to another embodiment of the present invention, FIG. 8 is a simplified timing diagram of the power conversion system 400 shown in FIG. 4B operating in a discontinuous conduction mode (DCM). For example, waveform 802 represents power switch 430 on or off as a function of time, waveform 808 represents voltage signal 462 (eg, at terminal DR) as a function of time, and waveform 810 represents signal 466 (eg, at terminal G2) ) Is expressed as a function of time.

如先前討論的那樣，在一個實施例中，如果電壓信號362(例如，VDR)變得大於第一閾值電壓828(例如，如波形808所示)，則信號366從邏輯高位準變為邏輯低位準(例如，如波形810所示)，以便關斷電晶體310。例如，電晶體310這樣的硬關斷(hard turn-off)經常在電晶體310的汲極處產生振鈴(ringing)，因為包括一次繞組304和二次繞組306的變壓器中剩餘的能量通過電晶體310的寄生體二極體374散出，並與電晶體310的寄生電容器及變壓器的電感器產生共振。在另一示例中，這些共振振鈴(例如，如波形808所示在時刻t30之前的振鈴)可達到低於第一閾值電壓828(例如，Vth1)和第二閾值電壓830(例如，Vth2)二者的值(例如，值827)。 As previously discussed, in one embodiment, if the voltage signal 362 (eg, V DR ) becomes greater than the first threshold voltage 828 (eg, as shown by waveform 808), the signal 366 changes from a logic high level to a logic level Low level (eg, as shown by waveform 810) to turn off transistor 310. For example, a hard turn-off such as transistor 310 often causes ringing at the drain of transistor 310 because the remaining energy in the transformer including primary winding 304 and secondary winding 306 passes through the transistor The parasitic body diode 374 of 310 emits and resonates with the parasitic capacitor of the transistor 310 and the inductor of the transformer. In another example, the resonant ring (e.g., t as shown in the waveform 808 at a time before the ringing 30) reach lower than the first threshold voltage 828 (e.g., V ThI) and a second threshold voltage 830 (e.g., V th2 ) value of both (e.g., value 827).

同樣如先前討論的那樣，在另一實施例中，二次控制器308確定電壓信號362(例如，VDR)是否超出第一參考電壓829(例如，Vref1)，並基於該確定的結果，還決定是否回應於電壓信號362(例如，VDR)減小到低於第一閾值電壓828(例如，Vth1)和第二閾值電壓830(例如，Vth2)二者的值而關斷電晶體310。例如，如果一次側上的AC輸 入電壓具有大的振幅，則電壓信號362的值818高於電壓信號362的值819，如波形808所示；因此，第一參考電壓829(例如，Vref1)可被選擇為小於值818但大於值819，以便避免通過共振振鈴(例如，如波形808所示在時刻t30之前的振鈴)誤觸發二次控制器308。在另一示例中，該誤觸發可導致二次側整流器的不同步和輸出電壓350的不穩定性。 Also as previously discussed, in another embodiment, the secondary controller 308 determines whether the voltage signal 362 (eg, V DR ) exceeds the first reference voltage 829 (eg, V ref1 ), and based on the result of the determination, It is also determined whether to turn off the power in response to the voltage signal 362 (eg, V DR ) decreasing to a value below both the first threshold voltage 828 (eg, V th1 ) and the second threshold voltage 830 (eg, V th2 ) Crystal 310. For example, if the AC input voltage on the primary side has a large amplitude, the value 818 of the voltage signal 362 is higher than the value 819 of the voltage signal 362 as shown by the waveform 808; therefore, the first reference voltage 829 (eg, V ref1 ) It may be selected to be less than the value 818 but greater than the value 819 in order to avoid false triggering of the secondary controller 308 by resonant ringing (eg, ringing before time t 30 as shown by waveform 808). In another example, this false triggering may cause an out-of-synchronization of the secondary-side rectifier and an instability of the output voltage 350.

如上面所討論的和在這裡進一步強調的那樣，第8圖僅僅是示例，其不應該過度地限制申請專利範圍。本領域的普通技術人員將認識到許多變更、替換和修改。例如，以其他模式(例如，連續傳導模式和臨界傳導模式(例如，准諧振模式))操作的、如第4A圖所示的電源變換系統300或如第4B圖所示的電源變換系統400也可實現如第8圖所示的方案。 As discussed above and further emphasized here, Figure 8 is merely an example, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, a power conversion system 300 as shown in FIG. 4A or a power conversion system 400 as shown in FIG. 4B is also operated in other modes (for example, continuous conduction mode and critical conduction mode (for example, quasi-resonant mode)). The scheme shown in Figure 8 can be implemented.

根據某些實施例，如第8圖所示的方案在連續傳導模式下實現。在一個實施例中，如果電壓信號362被二次控制器308確定為超出第一參考電壓829，則二次控制器308回應於電壓信號362(例如，VDR)從高於第一參考電壓829的值減小到低於第一閾值電壓828(例如，Vth1)和第二閾值電壓830(例如，Vth2)二者的值，將信號366從邏輯低位準變為邏輯高位準以便接通電晶體310。在另一實施例中，如果電壓信號362未被二次控制器308確定為超出第一參考電壓829，則即使電壓信號362(例如，VDR)減小到低於第一閾值電壓828(例如，Vth1)和第二閾值電壓830(例如，Vth2)二者的值，二次控制器308也不會將信號366從邏輯低位準變為邏輯高位準，從而電晶體310保持關斷。在另一實施例中，控制器302在退磁時段結束之前接通電晶體310(例如，控制器302在二次電流352下降到零之前接通電晶體310)，並且作為回應，信號362(例如，VDR)增大。在另一示例中，二次控制器308感測到信號362的上升沿，並改變信號366以關斷電晶體310。 According to some embodiments, the scheme shown in Figure 8 is implemented in continuous conduction mode. In one embodiment, if the voltage signal 362 is determined by the secondary controller 308 to exceed the first reference voltage 829, the secondary controller 308 responds to the voltage signal 362 (eg, V DR ) from above the first reference voltage 829 Decreases to a value below both the first threshold voltage 828 (for example, V th1 ) and the second threshold voltage 830 (for example, V th2 ), changing the signal 366 from a logic low level to a logic high level for turning on Transistor 310. In another embodiment, if the voltage signal 362 is not determined by the secondary controller 308 to exceed the first reference voltage 829, then even if the voltage signal 362 (eg, V DR ) decreases below the first threshold voltage 828 (eg, V th1 ) and the second threshold voltage 830 (for example, V th2 ), the secondary controller 308 also does not change the signal 366 from a logic low level to a logic high level, so that the transistor 310 remains off. In another embodiment, the controller 302 turns on the transistor 310 before the end of the demagnetization period (eg, the controller 302 turns on the transistor 310 before the secondary current 352 drops to zero), and in response, the signal 362 (eg V DR ) increases. In another example, the secondary controller 308 senses the rising edge of the signal 362 and changes the signal 366 to turn off the transistor 310.

第9圖是根據本發明的另一實施例，以斷續傳導模式(DCM)操作的、如第4A圖所示的電源變換系統300的簡化時序圖。該 圖僅僅是示例，其不應該過度地限制申請專利範圍。本領域的普通技術人員將認識到許多變更、替換和修改。例如，波形902將功率開關330接通或關斷表示為時間函數，波形908將電壓信號362(例如，在端子DR處的VDR)表示為時間函數，而波形910將信號366(例如，在端子G2處)表示為時間函數。 FIG. 9 is a simplified timing diagram of the power conversion system 300 shown in FIG. 4A operating in a discontinuous conduction mode (DCM) according to another embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, waveform 902 represents power switch 330 on or off as a function of time, waveform 908 represents a voltage signal 362 (e.g., V DR at terminal DR ) as a function of time, and waveform 910 represents signal 366 (e.g., at (At terminal G2) is shown as a function of time.

如第9圖所示，根據一些實施例，二次控制器308在端子390處接收電壓信號362(例如，VDR)，並確定電壓信號362是否超出第二參考電壓929(例如，Vref2)。在一個實施例中，如果電壓信號362被確定為超出第二參考電壓929(例如，Vref2)，則二次控制器308進一步確定電壓信號362保持超出第二參考電壓929(例如，Vref2)的持續時間，並確定該持續時間是否比第一閾值時間段(例如，Tth1)長。例如，第二參考電壓929(例如，Vref2)低於第8圖所示的第一參考電壓829(例如，Vref1)。在另一示例中，第二參考電壓929(例如，Vref2)高於地電壓372(例如，零伏)，並且第一閾值電壓928(例如，Vth1)和第二閾值電壓930(例如，Vth2)二者均低於地電壓372(例如，零伏)。 As shown in FIG. 9, according to some embodiments, the secondary controller 308 receives the voltage signal 362 (for example, V DR ) at the terminal 390 and determines whether the voltage signal 362 exceeds the second reference voltage 929 (for example, V ref2 ) . In one embodiment, if the voltage signal 362 is determined to exceed the second reference voltage 929 (eg, V ref2 ), the secondary controller 308 further determines that the voltage signal 362 remains above the second reference voltage 929 (eg, V ref2 ) And determine whether the duration is longer than a first threshold time period (eg, T th1 ). For example, the second reference voltage 929 (for example, V ref2 ) is lower than the first reference voltage 829 (for example, V ref1 ) shown in FIG. 8. In another example, the second reference voltage 929 (eg, V ref2 ) is higher than the ground voltage 372 (eg, zero volts), and the first threshold voltage 928 (eg, V th1 ) and the second threshold voltage 930 (eg, V th1 ) V th2 ) Both are below ground voltage 372 (eg, zero volts).

在另一實施例中，如果電壓信號362保持超出第二參考電壓929(例如，Vref2)的持續時間被確定為比第一閾值時間段(例如，Tth1)長，則二次控制器308回應於電壓信號362(例如，VDR)從高於第二參考電壓929的值減小到低於第一閾值電壓928(例如，Vth1)和第二閾值電壓930(例如，Vth2)二者的值，將信號366從邏輯低位準變為邏輯高位準以接通電晶體310。在另一實施例中，如果電壓信號362保持超出第二參考電壓929(例如，Vref2)的持續時間未被確定為比第一閾值時間段(例如，Tth1)長，則即使電壓信號362(例如，VDR)減小到低於第一閾值電壓928(例如，Vth1)和第二閾值電壓930(例如，Vth2)二者的值，二次控制器308也不會將信號366從邏輯低位準變為邏輯高位準，從而電晶體310保持關斷。 In another embodiment, if the duration of the voltage signal 362 remaining beyond the second reference voltage 929 (eg, V ref2 ) is determined to be longer than the first threshold time period (eg, T th1 ), the secondary controller 308 In response to the voltage signal 362 (eg, V DR ) decreasing from a value above the second reference voltage 929 to a value below the first threshold voltage 928 (eg, V th1 ) and the second threshold voltage 930 (eg, V th2 ) This value changes the signal 366 from a logic low level to a logic high level to turn on the transistor 310. In another embodiment, if the duration of the voltage signal 362 remaining beyond the second reference voltage 929 (eg, V ref2 ) is not determined to be longer than the first threshold time period (eg, T th1 ), then even if the voltage signal 362 is (For example, V DR ) is reduced to a value lower than both the first threshold voltage 928 (for example, V th1 ) and the second threshold voltage 930 (for example, V th2 ). From logic low to logic high, transistor 310 remains off.

例如，開關330的開關週期包括開關330閉合(例如，接通)期間的接通時間段和開關330斷開(例如，關斷)期間的關斷時間段。在另一示例中，如第9圖所示，開關330的接通時間段(例如，Ton)開始於時刻t34，結束於時刻t35；開關330的關斷時間段(例如，Toff)開始於時刻t35，結束於時刻t40。在另一示例中，與包括一次繞組304和二次繞組306的變壓器相關聯的退磁時段(例如，Tdemag)開始於時刻t35，結束於時刻t40或時刻t40之前。在另一示例中，t34 t35 t40。 For example, the switching period of the switch 330 includes an on period during which the switch 330 is closed (eg, on) and an off period during which the switch 330 is off (eg, off). In another example, as shown in FIG. 9, the on-time period of the switch 330 (for example, T on ) starts at time t 34 and ends at the time t 35 ; the off-time period of the switch 330 (for example, T off ) Starts at time t 35 and ends at time t 40 . In another example, a demagnetization period (eg, T demag ) associated with a transformer including a primary winding 304 and a secondary winding 306 starts at time t 35 and ends at time t 40 or before time t 40 . In another example, t 34 t 35 t 40 .

在一個實施例中，在接通時間段(例如，Ton)期間，開關330閉合(例如，接通)，如波形902所示，並且能量被存儲在包括一次繞組304和二次繞組306的變壓器中。例如，二次電流352具有低值(例如，幾乎為零)。在另一示例中，由二次控制器308接收的電壓信號362(例如，VDR)具有高於零的值918(例如，如波形908所示)。在另一示例中，信號366處於邏輯低位準(例如，如波形910所示)，並且電晶體310關斷。在另一示例中，在接通時間段(例如，Ton)期間，電晶體310的溝道電流368具有低值(例如，幾乎為零)，並且電晶體310的體二極體電流370具有低值(例如，幾乎為零)。 In one embodiment, during the on time period (eg, T on ), the switch 330 is closed (eg, on) as shown by the waveform 902 and the energy is stored in the primary winding 304 and the secondary winding 306. Transformer. For example, the secondary current 352 has a low value (for example, almost zero). In another example, the voltage signal 362 (eg, V DR ) received by the secondary controller 308 has a value 918 (eg, as shown by the waveform 908) above zero. In another example, the signal 366 is at a logic low level (eg, as shown by the waveform 910) and the transistor 310 is turned off. In another example, during the on-time period (eg, T on ), the channel current 368 of the transistor 310 has a low value (eg, almost zero), and the body diode current 370 of the transistor 310 has Low value (for example, almost zero).

在另一實施例中，在接通時間段的結束處(例如，在時刻t35處)，開關330斷開(例如，關斷)，如波形902所示，並且能量被轉移到二次側。例如，二次電流352增大(例如，在時刻t35處)。在另一示例中，電壓信號362(例如，VDR)從值918減小到值926(例如，如波形908所示)。在另一示例中，值926低於第一閾值電壓928(例如，Vth1)和第二閾值電壓930(例如，Vth2)二者。在另一示例中，第一閾值電壓928(例如，Vth1)和第二閾值電壓930(例如，Vth2)二者均低於地電壓372(例如，零伏)。在另一示例中，第一閾值電壓928(例如，Vth1)大約等於-300mV，並且第二閾值電壓930(例如，Vth2)大約等於-10mV。在另一示例中，電晶體310的體二極體374開始導通，並且體二極體374的體二極體電流370增大。 In another embodiment, at the end of the on-time period (for example, at time t 35 ), the switch 330 is turned off (for example, turned off), as shown by the waveform 902, and energy is transferred to the secondary side . For example, the secondary current 352 increases (for example, at time t 35 ). In another example, the voltage signal 362 (eg, V DR ) is reduced from a value 918 to a value 926 (eg, as shown by the waveform 908). In another example, the value 926 is lower than both the first threshold voltage 928 (eg, V th1 ) and the second threshold voltage 930 (eg, V th2 ). In another example, both the first threshold voltage 928 (eg, V th1 ) and the second threshold voltage 930 (eg, V th2 ) are lower than the ground voltage 372 (eg, zero volts). In another example, the first threshold voltage 928 (eg, V th1 ) is approximately equal to -300 mV, and the second threshold voltage 930 (eg, V th2 ) is approximately equal to -10 mV. In another example, the body diode 374 of the transistor 310 starts to conduct, and the body diode current 370 of the body diode 374 increases.

根據某些實施例，二次控制器308在端子390處接收電壓信號362(例如，VDR)，並確定電壓信號362是否超出第二參考電壓929(例如，Vref2)。在一個實施例中，如果電壓信號362被確定為超出(例如，在時刻t34處)第二參考電壓929(例如，Vref2)，則二次控制器308進一步確定電壓信號362保持超出第二參考電壓929(例如，Vref2)期間的持續時間(例如，從時刻t34到時刻t35的持續時間TA)，並確定該持續時間(例如，持續時間TA)是否比第一閾值時間段(例如，Tth1)長。例如，第二參考電壓929(例如，Vref2)低於第8圖所示的第一參考電壓829(例如，Vref1)。在另一實施例中，如果該持續時間(例如，持續時間TA)被確定為比第一閾值時間段(例如，Tth1)長，則二次控制器308回應於電壓信號362(例如，VDR)從高於第二參考電壓929的值(例如，值918)減小到低於第一閾值電壓928(例如，Vth1)和第二閾值電壓930(例如，Vth2)二者的值(例如，值926)，將信號366從邏輯低位準變為邏輯高位準(例如，在時刻t35處，如波形910所示，或在t35之後的某個時刻)以便接通電晶體310。在另一實施例中，如果該持續時間(例如，持續時間TA)被確定為比第一閾值時間段(例如，Tth1)長，則二次控制器308回應於電壓信號362(例如，VDR)從高於第二參考電壓929的值(例如，值918)減小到低於第二閾值電壓930(例如，Vth2)的值(例如，值926)，將信號366從邏輯低位準變為邏輯高位準(例如，在時刻t35處，如波形910所示，或在t35之後的某個時刻)以便接通電晶體310。 According to some embodiments, the secondary controller 308 receives the voltage signal 362 (eg, V DR ) at the terminal 390 and determines whether the voltage signal 362 exceeds the second reference voltage 929 (eg, V ref2 ). In one embodiment, if the voltage signal 362 is determined to exceed (eg, at time t 34 ) the second reference voltage 929 (eg, V ref2 ), the secondary controller 308 further determines that the voltage signal 362 remains beyond the second Reference the duration of the voltage 929 (eg, V ref2 ) (eg, duration T A from time t 34 to time t 35 ) and determine if the duration (eg, duration T A ) is greater than the first threshold time The segment (for example, T th1 ) is long. For example, the second reference voltage 929 (for example, V ref2 ) is lower than the first reference voltage 829 (for example, V ref1 ) shown in FIG. 8. In another embodiment, if the duration (eg, duration T A ) is determined to be longer than the first threshold time period (eg, T th1 ), the secondary controller 308 responds to the voltage signal 362 (eg, V DR ) decreases from a value higher than the second reference voltage 929 (for example, the value 918) to a value lower than both the first threshold voltage 928 (for example, V th1 ) and the second threshold voltage 930 (for example, V th2 ). Value (e.g., value 926) to change signal 366 from a logic low level to a logic high level (e.g., at time t 35 , as shown by waveform 910, or some time after t 35 ) to turn on the transistor 310. In another embodiment, if the duration (eg, duration T A ) is determined to be longer than the first threshold time period (eg, T th1 ), the secondary controller 308 responds to the voltage signal 362 (eg, V DR ) decreases from a value higher than the second reference voltage 929 (for example, value 918) to a value lower than the second threshold voltage 930 (for example, V th2 ) (for example, value 926), and moves the signal 366 from a logic low The quasi-level becomes a logic high level (for example, at time t 35 , as shown by the waveform 910, or some time after t 35 ) in order to turn on the transistor 310.

例如，持續時間TA比第一閾值時間段Tth1長。在另一示例中，第一閾值電壓928(例如，Vth1)與第8圖所示的第一閾值電壓828(例如，Vth1)相同，並且第二閾值電壓930(例如，Vth2)與第8圖所示的第二閾值電壓830(例如，Vth2)相同。在另一示例中，在電壓信號362(例如，VDR)從值918減小到值926的時刻與信號366從邏輯低位準變為邏輯高位準的時刻之間存在延時(例如，Td)。在另一示例中，該延時(例如，Td)為零。 For example, the duration T A is longer than the first threshold period T th1 . In another example, the first threshold voltage 928 (for example, V th1 ) is the same as the first threshold voltage 828 (for example, V th1 ) shown in FIG. 8, and the second threshold voltage 930 (for example, V th2 ) is the same as The second threshold voltage 830 (for example, V th2 ) shown in FIG. 8 is the same. In another example, there is a delay between the time when the voltage signal 362 (eg, V DR ) decreases from the value 918 to the value 926 and the time when the signal 366 changes from a logic low level to a logic high level (eg, T d ) . In another example, the delay (eg, T d ) is zero.

在另一示例中，在電晶體310接通以後，電晶體310的溝道電流368增大。在另一實施例中，二次電流352等於溝道電流368和體二極體電流370的和。 In another example, after the transistor 310 is turned on, the channel current 368 of the transistor 310 increases. In another embodiment, the secondary current 352 is equal to the sum of the channel current 368 and the body diode current 370.

在另一實施例中，如果持續時間(例如，持續時間TA)未被確定為比第一閾值時間段(例如，Tth1)長，則不管電壓信號362(例如，VDR)是否減小到低於第一閾值電壓928(例如，Vth1)和第二閾值電壓930(例如，Vth2)二者的值，二次控制器308都將信號366保持在邏輯低位準以保持電晶體310關斷。在另一實施例中，如果持續時間(例如，持續時間TA)未被確定為比第一閾值時間段(例如，Tth1)長，則不管電壓信號362(例如，VDR)是否減小到低於第二閾值電壓930(例如，Vth2)的值，二次控制器308都將信號366保持在邏輯低位準以保持電晶體310關斷。 In another embodiment, if the duration (eg, duration T A ) is not determined to be longer than the first threshold time period (eg, T th1 ), regardless of whether the voltage signal 362 (eg, V DR ) decreases To values below both the first threshold voltage 928 (eg, V th1 ) and the second threshold voltage 930 (eg, V th2 ), the secondary controller 308 maintains the signal 366 at a logic low level to maintain the transistor 310 Shut down. In another embodiment, if the duration (eg, duration T A ) is not determined to be longer than the first threshold time period (eg, T th1 ), regardless of whether the voltage signal 362 (eg, V DR ) decreases To a value below the second threshold voltage 930 (eg, V th2 ), the secondary controller 308 keeps the signal 366 at a logic low level to keep the transistor 310 off.

根據一個實施例，在退磁時段期間，開關330保持斷開(例如，關斷)，如波形902所示。例如，二次電流352減小。在另一示例中，如果電壓信號362(例如，VDR)變為大於第一閾值電壓928(例如，如波形908所示)，則信號366從邏輯高位準變為邏輯低位準(例如，如波形910所示)。在另一示例中，電晶體310被關斷，並且電晶體310的溝道電流368減小到低值(例如，幾乎為零)。在另一示例中，電晶體310的體二極體電流370流過電晶體310的體二極體374，然後減小到低值。在另一示例中，退磁時段在時刻t40之前結束。在另一示例中，緊接退磁時段的結束，電壓信號362增大到值919，如波形908的上升沿所示。 According to one embodiment, the switch 330 remains open (eg, off) during the demagnetization period, as shown by the waveform 902. For example, the secondary current 352 decreases. In another example, if the voltage signal 362 (eg, V DR ) becomes greater than the first threshold voltage 928 (eg, as shown by waveform 908), the signal 366 changes from a logic high level to a logic low level (eg, as Waveform 910). In another example, the transistor 310 is turned off, and the channel current 368 of the transistor 310 is reduced to a low value (eg, almost zero). In another example, the body diode current 370 of the transistor 310 flows through the body diode 374 of the transistor 310 and then decreases to a low value. In another example, the demagnetization period ends before time t 40 . In another example, immediately after the end of the demagnetization period, the voltage signal 362 increases to a value 919, as shown by the rising edge of the waveform 908.

根據某些實施例，二次控制器308在端子390處接收電壓信號362(例如，VDR)，並確定電壓信號362是否超出第二參考電壓929(例如，Vref2)。在一個實施例中，如果電壓信號362被確定為超出(例如，在時刻t36處)第二參考電壓929(例如，Vref2)，則二次控制器308進一步確定電壓信號362保持超出第二參考電壓929(例如，Vref2)期 間的持續時間(例如，從時刻t36到時刻t37的持續時間TB)，並確定該持續時間(例如，持續時間TB)是否比第一閾值時間段(例如，Tth1)長。在另一實施例中，如果持續時間(例如，持續時間TB)未被確定為比第一閾值時間段(例如，Tth1)長，則即使電壓信號362(例如，VDR)減小到低於第一閾值電壓928(例如，Vth1)和第二閾值電壓930(例如，Vth2)二者的值(例如，值927)，二次控制器308也不會將信號366從邏輯低位準變為邏輯高位準，從而電晶體310保持關斷。例如，持續時間TB比第一閾值時間段Tth1短。 According to some embodiments, the secondary controller 308 receives the voltage signal 362 (eg, V DR ) at the terminal 390 and determines whether the voltage signal 362 exceeds the second reference voltage 929 (eg, V ref2 ). In one embodiment, if the voltage signal 362 is determined to exceed (eg, at time t 36 ) the second reference voltage 929 (eg, V ref2 ), the secondary controller 308 further determines that the voltage signal 362 remains beyond the second Reference the duration (eg, duration T B from time t 36 to time t 37 ) during the voltage 929 (eg, V ref2 ) and determine whether the duration (eg, duration T B ) is greater than the first threshold time The segment (for example, T th1 ) is long. In another embodiment, if the duration (eg, duration T B ) is not determined to be longer than the first threshold time period (eg, T th1 ), then even if the voltage signal 362 (eg, V DR ) decreases to Below the value of both the first threshold voltage 928 (eg, V th1 ) and the second threshold voltage 930 (eg, V th2 ) (eg, the value 927), the secondary controller 308 also does not move the signal 366 from a logic low The quasi becomes a logic high level, so that the transistor 310 remains off. For example, the duration T B is shorter than the first threshold time period T th1 .

根據本發明的另一實施例，第9圖是以斷續傳導模式(DCM)操作的如第4B圖所示的電源變換系統400的簡化時序圖。例如，波形902將功率開關430接通或關斷表示為時間函數，波形908將電壓信號462(例如，在端子DR處)表示為時間函數，而波形910將信號466(例如，在端子G2處)表示為時間函數。 According to another embodiment of the present invention, FIG. 9 is a simplified timing diagram of the power conversion system 400 shown in FIG. 4B operating in a discontinuous conduction mode (DCM). For example, waveform 902 represents power switch 430 on or off as a function of time, waveform 908 represents voltage signal 462 (eg, at terminal DR) as a function of time, and waveform 910 represents signal 466 (eg, at terminal G2) ) Is expressed as a function of time.

如先前討論的那樣，在一個實施例中，如果電壓信號362(例如，VDR)變得大於第一閾值電壓928(例如，如波形908所示)，則信號366從邏輯高位準變為邏輯低位準(例如，如波形910所示)，以便關斷電晶體310。例如，電晶體310這樣的硬關斷經常在電晶體310的汲極處產生振鈴，因為包括一次繞組304和二次繞組306的變壓器中剩餘的能量通過電晶體310的寄生體二極體374散出，並與電晶體310的寄生電容器及變壓器的電感器產生共振。在另一示例中，這些共振振鈴(例如，如波形908所示在時刻t40之前的振鈴)可達到低於第一閾值電壓928(例如，Vth1)和第二閾值電壓930(例如，Vth2)二者的值(例如，值927)。 As previously discussed, in one embodiment, if the voltage signal 362 (eg, V DR ) becomes greater than the first threshold voltage 928 (eg, as shown by waveform 908), the signal 366 changes from a logic high level to a logic level Low level (eg, as shown by waveform 910) to turn off transistor 310. For example, a hard shutdown such as transistor 310 often causes ringing at the drain of transistor 310 because the remaining energy in the transformer including primary winding 304 and secondary winding 306 is dissipated through parasitic diode 374 of transistor 310 And generate resonance with the parasitic capacitor of the transistor 310 and the inductor of the transformer. In another example, the resonant ring (e.g., as shown by the waveform 908 in the time t before the ringing 40) reach lower than the first threshold voltage 928 (e.g., V ThI) and a second threshold voltage 930 (e.g., V th2 ) value of both (e.g., value 927).

同樣如先前討論的那樣，在另一實施例中，二次控制器308確定電壓信號362保持超出第二參考電壓929(例如，Vref2)期間的持續時間是否比第一閾值時間段(例如，Tth1)長。例如，基於該確定的結果，二次控制器308還決定是否回應於電壓信號362(例如，VDR)減小到 低於第一閾值電壓928(例如，Vth1)和第二閾值電壓930(例如，Vth2)二者的值而關斷電晶體310。 Also as previously discussed, in another embodiment, the secondary controller 308 determines whether the duration during which the voltage signal 362 remains beyond the second reference voltage 929 (eg, V ref2 ) is greater than the first threshold time period (eg, T th1 ) is long. For example, based on the result of this determination, the secondary controller 308 also decides whether to respond to the voltage signal 362 (eg, V DR ) to decrease below the first threshold voltage 928 (eg, V th1 ) and the second threshold voltage 930 ( For example, V th2 ) and the transistor 310 is turned off.

在另一示例中，如果一次側上的AC輸入電壓具有小的振幅，則電壓信號362的值918和電壓信號362的值919近似相等，如波形908所示；因此，選擇小於值918但大於值919的第一參考電壓829(例如，Vref1)的值是困難的，但是第二參考電壓929(例如，Vref2)的值可被選擇為使得電壓信號362保持超出第二參考電壓929(例如，Vref2)的持續時間可被用於避免二次控制器308被共振振鈴(例如，如波形908所示在時刻t40之前的振鈴)誤觸發。在另一示例中，該誤觸發可導致二次側整流器的不同步和輸出電壓350的不穩定性。 In another example, if the AC input voltage on the primary side has a small amplitude, the value 918 of the voltage signal 362 and the value 919 of the voltage signal 362 are approximately equal, as shown by the waveform 908; therefore, a value less than the value 918 but greater than The value of the first reference voltage 829 (for example, V ref1 ) having a value of 919 is difficult, but the value of the second reference voltage 929 (for example, V ref2 ) may be selected such that the voltage signal 362 remains beyond the second reference voltage 929 ( For example, the duration of V ref2 ) may be used to prevent the secondary controller 308 from being triggered by resonance ringing (eg, ringing before time t 40 as shown in waveform 908) by mistake. In another example, this false triggering may cause an out-of-synchronization of the secondary-side rectifier and an instability of the output voltage 350.

如上面所討論的和在這裡進一步強調的那樣，第9圖僅僅是示例，其不應該過度地限制申請專利範圍。本領域的普通技術人員將認識到許多變更、替換和修改。例如，以其他模式(例如，連續傳導模式和臨界傳導模式(例如，准諧振模式))操作的、如第4A圖所示的電源變換系統300或如第4B圖所示的電源變換系統400也可實現如第9圖所示的方案。 As discussed above and further emphasized here, Figure 9 is merely an example, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, a power conversion system 300 as shown in FIG. 4A or a power conversion system 400 as shown in FIG. 4B is also operated in other modes (for example, continuous conduction mode and critical conduction mode (for example, quasi-resonant mode)). The scheme shown in Figure 9 can be implemented.

根據某些實施例，如第9圖所示的方案在連續傳導模式下實現。在一個實施例中，如果電壓信號362保持超出第二參考電壓929(例如，Vref2)的持續時間被確定為比第一閾值時間段(例如，Tth1)長，則二次控制器308回應於電壓信號362(例如，VDR)從高於第二參考電壓929的值減小到低於第一閾值電壓928(例如，Vth1)和第二閾值電壓930(例如，Vth2)二者的值，將信號366從邏輯低位準變為邏輯高位準以便接通電晶體310。在另一實施例中，如果電壓信號362保持超出第二參考電壓929(例如，Vref2)的持續時間未被確定為比第一閾值時間段(例如，Tth1)長，則即使電壓信號362(例如，VDR)減小到低於第一閾值電壓928(例如，Vth1)和第二閾值電壓930(例如，Vth2)二者的值，二次控制器308也不會將信號366從邏輯低位準變為邏輯高位準，從而電晶體 310保持關斷。在另一實施例中，控制器302在退磁時段結束之前接通電晶體310(例如，控制器302在二次電流352下降到零之前接通電晶體310)，並且作為回應，信號362(例如，VDR)增大。在另一示例中，二次控制器308感測到信號362的上升沿，並改變信號366以關斷電晶體310。 According to some embodiments, the scheme shown in Figure 9 is implemented in continuous conduction mode. In one embodiment, if the duration of the voltage signal 362 remaining beyond the second reference voltage 929 (eg, V ref2 ) is determined to be longer than the first threshold time period (eg, T th1 ), the secondary controller 308 responds The voltage signal 362 (for example, V DR ) decreases from a value higher than the second reference voltage 929 to both lower than the first threshold voltage 928 (for example, V th1 ) and the second threshold voltage 930 (for example, V th2 ) Value to change the signal 366 from a logic low level to a logic high level to turn on the transistor 310. In another embodiment, if the duration of the voltage signal 362 remaining beyond the second reference voltage 929 (eg, V ref2 ) is not determined to be longer than the first threshold time period (eg, T th1 ), then even if the voltage signal 362 is (For example, V DR ) is reduced to a value lower than both the first threshold voltage 928 (for example, V th1 ) and the second threshold voltage 930 (for example, V th2 ). From logic low to logic high, transistor 310 remains off. In another embodiment, the controller 302 turns on the transistor 310 before the end of the demagnetization period (eg, the controller 302 turns on the transistor 310 before the secondary current 352 drops to zero), and in response, the signal 362 (eg, V DR ) increases. In another example, the secondary controller 308 senses the rising edge of the signal 362 and changes the signal 366 to turn off the transistor 310.

根據一些實施例，如第9圖所示，二次控制器308在端子390處接收電壓信號362(例如，VDR)，並確定電壓信號362是否低於第一參考電壓829(例如，Vref1)但超出第二參考電壓929(例如，Vref2)。在一個實施例中，如果電壓信號362被確定為低於第一參考電壓829(例如，Vref1)但超出第二參考電壓929(例如，Vref2)，則二次控制器308進一步確定電壓信號362保持低於第一參考電壓829(例如，Vref1)但超出第二參考電壓929(例如，Vref2)的持續時間，並確定該持續時間是否比第一閾值時間段(例如，Tth1)長。在另一實施例中，如果電壓信號362保持低於第一參考電壓829(例如，Vref1)但超出第二參考電壓929(例如，Vref2)的持續時間被確定為比第一閾值時間段(例如，Tth1)長，則二次控制器308回應於電壓信號362(例如，VDR)從高於第二參考電壓929的值減小到低於第一閾值電壓928(例如，Vth1)和第二閾值電壓930(例如，Vth2)二者的值，將信號366從邏輯低位準變為邏輯高位準以便接通電晶體310。在另一實施例中，如果電壓信號362保持低於第一參考電壓829(例如，Vref1)但超出第二參考電壓929(例如，Vref2)的持續時間未被確定為比第一閾值時間段(例如，Tth1)長，則即使電壓信號362(例如，VDR)減小到低於第一閾值電壓928(例如，Vth1)和第二閾值電壓930(例如，Vth2)二者的值，二次控制器308也不會將信號366從邏輯低位準變為邏輯高位準，從而電晶體310保持關斷。 According to some embodiments, as shown in FIG. 9, the secondary controller 308 receives the voltage signal 362 (for example, V DR ) at the terminal 390 and determines whether the voltage signal 362 is lower than the first reference voltage 829 (for example, V ref1 ) But exceeds the second reference voltage 929 (eg, V ref2 ). In one embodiment, if the voltage signal 362 is determined to be lower than the first reference voltage 829 (eg, V ref1 ) but exceeds the second reference voltage 929 (eg, V ref2 ), the secondary controller 308 further determines the voltage signal 362 remains below the first reference voltage 829 (eg, V ref1 ) but exceeds the duration of the second reference voltage 929 (eg, V ref2 ) and determines whether the duration is longer than the first threshold time period (eg, T th1 ) long. In another embodiment, if the voltage signal 362 remains below the first reference voltage 829 (eg, V ref1 ) but exceeds the second reference voltage 929 (eg, V ref2 ), the duration is determined to be greater than the first threshold time period (For example, T th1 ) is long, the secondary controller 308 reduces the value of the secondary controller 308 (for example, V DR ) from a value higher than the second reference voltage 929 to a value lower than the first threshold voltage 928 (for example, V th1 ) And a second threshold voltage 930 (eg, V th2 ), changes the signal 366 from a logic low level to a logic high level to turn on the transistor 310. In another embodiment, if the voltage signal 362 remains below the first reference voltage 829 (eg, V ref1 ) but exceeds a second reference voltage 929 (eg, V ref2 ), the duration is not determined to be longer than the first threshold time The segment (for example, T th1 ) is long, even if the voltage signal 362 (for example, V DR ) decreases below both the first threshold voltage 928 (for example, V th1 ) and the second threshold voltage 930 (for example, V th2 ) Value, the secondary controller 308 also does not change the signal 366 from a logic low level to a logic high level, so that the transistor 310 remains off.

第10圖是根據本發明的另一實施例，以斷續傳導模式(DCM)操作的、如第4A圖所示的電源變換系統300的簡化時序圖。該圖僅僅是示例，其不應該過度地限制申請專利範圍。本領域的普通技術人 員將認識到許多變更、替換和修改。例如，波形1002將功率開關330接通或關斷表示為時間函數，波形1008將電壓信號362(例如，在端子DR處的VDR)表示為時間函數，而波形1010將信號366(例如，在端子G2處)表示為時間函數。 FIG. 10 is a simplified timing diagram of the power conversion system 300 shown in FIG. 4A operating in a discontinuous conduction mode (DCM) according to another embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, waveform 1002 represents the power switch 330 on or off as a function of time, waveform 1008 represents a voltage signal 362 (e.g., V DR at terminal DR ) as a function of time, and waveform 1010 represents signal 366 (e.g., at (At terminal G2) is shown as a function of time.

如第10圖所示，二次控制器308在端子390處接收電壓信號362(例如，VDR)，並確定從電壓信號362超出第三參考電壓1029(例如，Vref3)的時刻到電壓信號362下降到低於第四參考電壓1031(例如，Vref4)的時刻的持續時間，並進一步確定該持續時間是否比第二閾值時間段(例如，Tth2)長。在一個實施例中，如果該持續時間被確定為比第二閾值時間段(例如，Tth2)長，則二次控制器308回應於電壓信號362(例如，VDR)從高於第三參考電壓1029的值減小到低於第一閾值電壓1028(例如，Vth1)和第二閾值電壓1030(例如，Vth2)二者的值，將信號366從邏輯低位準變為邏輯高位準以便接通電晶體310。在另一實施例中，如果該持續時間未被確定為比第二閾值時間段(例如，Tth2)長，則即使電壓信號362(例如，VDR)減小到低於第一閾值電壓1028(例如，Vth1)和第二閾值電壓1030(例如，Vth2)二者的值，二次控制器308也不會將信號366從邏輯低位準變為邏輯高位準，從而電晶體310保持關斷。 As shown in FIG. 10, the secondary controller 308 receives the voltage signal 362 (for example, V DR ) at the terminal 390, and determines from the time when the voltage signal 362 exceeds the third reference voltage 1029 (for example, V ref3 ) to the voltage signal 362 drops to a duration that is lower than a fourth reference voltage 1031 (eg, V ref4 ), and further determines whether the duration is longer than a second threshold time period (eg, T th2 ). In one embodiment, if the duration is determined to be longer than a second threshold time period (eg, T th2 ), the secondary controller 308 responds to the voltage signal 362 (eg, V DR ) from above a third reference The value of voltage 1029 is reduced to a value below both the first threshold voltage 1028 (eg, V th1 ) and the second threshold voltage 1030 (eg, V th2 ), changing the signal 366 from a logic low level to a logic high level so that The transistor 310 is turned on. In another embodiment, if the duration is not determined to be longer than the second threshold time period (eg, T th2 ), then even if the voltage signal 362 (eg, V DR ) decreases below the first threshold voltage 1028 (For example, V th1 ) and the second threshold voltage 1030 (for example, V th2 ), the secondary controller 308 also does not change the signal 366 from a logic low level to a logic high level, so that the transistor 310 remains off Off.

例如，開關330的開關週期包括開關330閉合(例如，接通)的接通時間段和開關330斷開(例如，關斷)的關斷時間段。在另一示例中，如第10圖所示，開關330的接通時間段(例如，Ton)開始於時刻t44，結束於時刻t45，或開始於時刻t50，結束於時刻t51。在另一示例中，如第10圖所示，開關330的關斷時間段(例如，Toff)開始於時刻t45，結束於時刻t50。在另一示例中，與包括一次繞組304和二次繞組306的變壓器相關聯的退磁時段(例如，Tdemag)開始於時刻t45，結束於時刻t50或時刻t50之前。在另一示例中，t44 t45 t50 t51。 For example, the switching period of the switch 330 includes an on period during which the switch 330 is closed (eg, on) and an off period during which the switch 330 is off (eg, off). In another example, as shown in FIG. 10, the on-time period (eg, T on ) of the switch 330 starts at time t 44 , ends at time t 45 , or starts at time t 50 , and ends at time t 51 . In another example, as shown in FIG. 10, the off period (eg, T off ) of the switch 330 starts at time t 45 and ends at time t 50 . In another example, a demagnetization period (eg, T demag ) associated with a transformer including a primary winding 304 and a secondary winding 306 starts at time t 45 and ends at time t 50 or before time t 50 . In another example, t 44 t 45 t 50 t 51 .

在一個實施例中，在接通時間段(例如，Ton)期間，開關330閉合(例如，接通)，如波形1002所示，並且能量被存儲在包括 一次繞組304和二次繞組306的變壓器中。例如，二次電流352具有低值(例如，幾乎為零)。在另一示例中，由二次控制器308接收的電壓信號362(例如，VDR)具有高於零的值1018(例如，如波形1008所示)。在另一示例中，信號366處於邏輯低位準(例如，如波形1010所示)，並且電晶體310關斷。在另一示例中，在接通時間段(例如，Ton)期間，電晶體310的溝道電流368具有低值(例如，幾乎為零)，並且電晶體310的體二極體電流370具有低值(例如，幾乎為零)。 In one embodiment, during the on time period (eg, T on ), the switch 330 is closed (eg, on), as shown by the waveform 1002, and energy is stored in the primary winding 304 and the secondary winding 306. Transformer. For example, the secondary current 352 has a low value (for example, almost zero). In another example, the voltage signal 362 (eg, V DR ) received by the secondary controller 308 has a value 1018 (eg, as shown by waveform 1008) above zero. In another example, the signal 366 is at a logic low level (eg, as shown by the waveform 1010), and the transistor 310 is turned off. In another example, during the on-time period (eg, T on ), the channel current 368 of the transistor 310 has a low value (eg, almost zero), and the body diode current 370 of the transistor 310 has Low value (for example, almost zero).

在另一實施例中，在接通時間段的結束處(例如，在時刻t45處或在時刻t51處)，開關330斷開(例如，關斷)，如波形1002所示，並且能量被轉移到二次側。例如，二次電流352增大(例如，在時刻t45處或在時刻t51處)。在另一示例中，電壓信號362(例如，VDR)從值1018減小到值1026(例如，如波形1008所示)。在另一示例中，值1026低於第一閾值電壓1028(例如，Vth1)和第二閾值電壓1030(例如，Vth2)二者。在另一示例中，第一閾值電壓1028(例如，Vth1)和第二閾值電壓1030(例如，Vth2)二者均低於地電壓372(例如，零伏)。在另一示例中，第一閾值電壓1028(例如，Vth1)大約等於-300mV，並且第二閾值電壓1030(例如，Vth2)大約等於-10mV。在另一示例中，電晶體310的體二極體374開始導通，並且體二極體374的體二極體電流370增大。 In another embodiment, at the end of the on-time period (eg, at time t 45 or at time t 51 ), the switch 330 is turned off (eg, turned off), as shown in waveform 1002, and the energy It is transferred to the secondary side. For example, the secondary current 352 increases (for example, at time t 45 or at time t 51 ). In another example, the voltage signal 362 (eg, V DR ) is reduced from a value of 1018 to a value of 1026 (eg, as shown by waveform 1008). In another example, the value 1026 is lower than both the first threshold voltage 1028 (eg, V th1 ) and the second threshold voltage 1030 (eg, V th2 ). In another example, both the first threshold voltage 1028 (eg, V th1 ) and the second threshold voltage 1030 (eg, V th2 ) are lower than the ground voltage 372 (eg, zero volts). In another example, the first threshold voltage 1028 (eg, V th1 ) is approximately equal to -300 mV, and the second threshold voltage 1030 (eg, V th2 ) is approximately equal to -10 mV. In another example, the body diode 374 of the transistor 310 starts to conduct, and the body diode current 370 of the body diode 374 increases.

根據一些實施例，二次控制器308在端子390處接收電壓信號362(例如，VDR)，並確定從電壓信號362超出第三參考電壓1029(例如，Vref3)的時刻(例如，時刻t46)到電壓信號362下降到低於第四參考電壓1031(例如，Vref4)的時刻(例如，時刻t47)的持續時間(例如，持續時間TC)，並進一步確定該持續時間(例如，持續時間TC)是否比第二閾值時間段(例如，Tth2)長。例如，第四參考電壓1031(例如，Vref4)低於第三參考電壓1029(例如，Vref3)，第三參考電壓1029(例如，Vref3)低於第8圖所示的第一參考電壓829(例如，Vref1)，也低於第9圖所示的第二參考電壓929(例如，Vref2)。在另一示例中， 第三參考電壓1029(例如，Vref3)高於第四參考電壓1031(例如，Vref4)，第四參考電壓1031(例如，Vref4)高於第一閾值電壓1028(例如，Vth1)，而第一閾值電壓1028(例如，Vth1)高於第二閾值電壓1030(例如，Vth2)。在另一示例中，第三參考電壓1029(例如，Vref3)和第四參考電壓1031(例如，Vref4)二者均高於地電壓372(例如，零伏)，而第一閾值電壓1028(例如，Vth1)和第二閾值電壓1030(例如，Vth2)二者均低於地電壓372(例如，零伏)。在另一示例中，持續時間TC比第二閾值時間段Tth2短。 According to some embodiments, the secondary controller 308 receives the voltage signal 362 (eg, V DR ) at the terminal 390 and determines a time (eg, time t) from the voltage signal 362 to exceed the third reference voltage 1029 (eg, V ref3 ). 46 ) to the duration (e.g., duration T C ) of the time (e.g., time t 47 ) until the voltage signal 362 drops below the fourth reference voltage 1031 (e.g., V ref4 ), and further determine the duration (e.g., time T C ) , Whether the duration T C ) is longer than the second threshold time period (for example, T th2 ). For example, the fourth reference voltage 1031 (for example, V ref4 ) is lower than the third reference voltage 1029 (for example, V ref3 ), and the third reference voltage 1029 (for example, V ref3 ) is lower than the first reference voltage shown in FIG. 8 829 (for example, V ref1 ) is also lower than the second reference voltage 929 (for example, V ref2 ) shown in FIG. 9. In another example, the third reference voltage 1029 (eg, V ref3 ) is higher than the fourth reference voltage 1031 (eg, V ref4 ), and the fourth reference voltage 1031 (eg, V ref4 ) is higher than the first threshold voltage 1028 ( For example, V th1 ), and the first threshold voltage 1028 (for example, V th1 ) is higher than the second threshold voltage 1030 (for example, V th2 ). In another example, the third reference voltage 1029 (eg, V ref3 ) and the fourth reference voltage 1031 (eg, V ref4 ) are both higher than the ground voltage 372 (eg, zero volts), and the first threshold voltage 1028 (Eg, V th1 ) and the second threshold voltage 1030 (eg, V th2 ) are both lower than the ground voltage 372 (eg, zero volts). In another example, the duration T C is shorter than the second threshold time period T th2 .

在一個實施例中，如果持續時間(例如，持續時間TC)未被確定為比第二閾值時間段(例如，Tth2)長，則即使電壓信號362(例如，VDR)減小到低於第一閾值電壓1028(例如，Vth1)和第二閾值電壓1030(例如，Vth2)二者的值(例如，值1027)，二次控制器308也不會將信號366從邏輯低位準變為邏輯高位準，從而電晶體310保持關斷。例如，第一閾值電壓1028(例如，Vth1)與已經在第9圖中示出的第一閾值電壓928(例如，Vth1)相同，也與第7圖所示的第一閾值電壓828(例如，Vth1)相同。在另一示例中，第二閾值電壓1030(例如，Vth2)與第9圖所示的第二閾值電壓930(例如，Vth2)相同，也與第8圖所示的第二閾值電壓830(例如，Vth2)相同。 In one embodiment, if the duration (eg, duration T C ) is not determined to be longer than the second threshold time period (eg, T th2 ), then even if the voltage signal 362 (eg, V DR ) decreases to low Based on the value of the first threshold voltage 1028 (for example, V th1 ) and the second threshold voltage 1030 (for example, V th2 ) (for example, the value 1027), the secondary controller 308 also does not bring the signal 366 from a logic low level. Goes logic high, so transistor 310 remains off. For example, the first threshold voltage 1028 (for example, V th1 ) is the same as the first threshold voltage 928 (for example, V th1 ) already shown in FIG. 9, and is also the same as the first threshold voltage 828 (for example, V th1 ) shown in FIG. 7. For example, V th1 ) is the same. In another example, the second threshold voltage 1030 (for example, V th2 ) is the same as the second threshold voltage 930 (for example, V th2 ) shown in FIG. 9, and also the second threshold voltage 830 as shown in FIG. 8. (For example, V th2 ) is the same.

根據某些實施例，二次控制器308在端子390處接收電壓信號362(例如，VDR)，並確定從電壓信號362超出第三參考電壓1029(例如，Vref3)的時刻(例如，時刻t48)到電壓信號362下降到低於第四參考電壓1031(例如，Vref4)的時刻(例如，時刻t51)的持續時間(例如，持續時間TD)，並進一步確定該持續時間(例如，持續時間TD)是否比第二閾值時間段(例如，Tth2)長。在一個實施例中，如果持續時間(例如，持續時間TD)被確定為比第二閾值時間段(例如，Tth2)長，則二次控制器308回應於電壓信號362(例如，VDR)從高於第三參考電壓1029的值(例如，值1018)減小到低於第一閾值電壓1028(例如， Vth1)和第二閾值電壓1030(例如，Vth2)二者的值(例如，值1026)，將信號366從邏輯低位準變為邏輯高位準(例如，在時刻t51處，如波形1010所示，或在t51之後的某個時刻)以便接通電晶體310。在另一實施例中，如果持續時間(例如，持續時間TD)被確定為比第二閾值時間段(例如，Tth2)長，則二次控制器308回應於電壓信號362(例如，VDR)從高於第三參考電壓1029的值(例如，值1018)減小到低於第二閾值電壓1030(例如，Vth2)的值(例如，值1026)，將信號366從邏輯低位準變為邏輯高位準(例如，在時刻t51處，如波形1010所示，或在t51之後的某個時刻)以便接通電晶體310。 According to some embodiments, the secondary controller 308 receives the voltage signal 362 (eg, V DR ) at the terminal 390 and determines a time (eg, time) when the voltage signal 362 exceeds the third reference voltage 1029 (eg, V ref3 ) t 48) to the voltage signal 362 drops below the fourth reference voltage to time 1031 (e.g., V ref4) (e.g., time t 51) duration (e.g., the duration T D), and further determines the time duration ( For example, is the duration T D ) longer than a second threshold time period (for example, T th2 ). In one embodiment, if the duration (eg, duration T D ) is determined to be longer than the second threshold time period (eg, T th2 ), the secondary controller 308 responds to the voltage signal 362 (eg, V DR ) Decreases from a value higher than the third reference voltage 1029 (for example, the value 1018) to a value lower than both the first threshold voltage 1028 (for example, V th1 ) and the second threshold voltage 1030 (for example, V th2 ) ( For example, the value 1026) changes the signal 366 from a logic low level to a logic high level (for example, at time t 51 , as shown in waveform 1010, or some time after t 51 ) to turn on transistor 310. In another embodiment, if the duration (eg, duration T D ) is determined to be longer than the second threshold time period (eg, T th2 ), the secondary controller 308 responds to the voltage signal 362 (eg, V DR ) decreases from a value higher than the third reference voltage 1029 (e.g., value 1018) to a value lower than the second threshold voltage 1030 (e.g., Vth2 ) (e.g., the value 1026), and moves the signal 366 from a logic low level Go to a logic high level (for example, at time t 51 , as shown by waveform 1010, or some time after t 51 ) to turn on transistor 310.

例如，持續時間TD比第二閾值時間段Tth2長。在另一示例中，在電壓信號362(例如，VDR)從值1018減小到值1026的時刻與信號366從邏輯低位準變為邏輯高位準的時刻之間存在延時(例如，Td)。在另一示例中，該延時(例如，Td)為零。在另一實施例中，在電晶體310接通以後，電晶體310的溝道電流368增大。在另一實施例中，二次電流352等於溝道電流368和體二極體電流370的和。 For example, the duration T D is longer than the second threshold time period T th2 . In another example, there is a delay between the time when the voltage signal 362 (eg, V DR ) decreases from the value 1018 to the value 1026 and the time when the signal 366 changes from a logic low level to a logic high level (eg, T d ) . In another example, the delay (eg, T d ) is zero. In another embodiment, after the transistor 310 is turned on, the channel current 368 of the transistor 310 increases. In another embodiment, the secondary current 352 is equal to the sum of the channel current 368 and the body diode current 370.

在另一實施例中，如果持續時間(例如，持續時間TD)未被確定為比第二閾值時間段(例如，Tth2)長，則不管電壓信號362(例如，VDR)是否減小到低於第一閾值電壓1028(例如，Vth1)和第二閾值電壓1030(例如，Vth2)二者的值，二次控制器308都將信號366保持在邏輯低位準以保持電晶體310關斷。在另一實施例中，如果持續時間(例如，持續時間TD)未被確定為比第二閾值時間段(例如，Tth2)長，則不管電壓信號362(例如，VDR)是否減小到低於第二閾值電壓1030(例如，Vth2)的值，二次控制器308都將信號366保持在邏輯低位準以保持電晶體310關斷。 In another embodiment, if the duration (eg, duration T D ) is not determined to be longer than the second threshold time period (eg, T th2 ), then whether or not the voltage signal 362 (eg, V DR ) decreases To values below both the first threshold voltage 1028 (eg, V th1 ) and the second threshold voltage 1030 (eg, V th2 ), the secondary controller 308 maintains the signal 366 at a logic low level to maintain the transistor 310 Shut down. In another embodiment, if the duration (eg, duration T D ) is not determined to be longer than the second threshold time period (eg, T th2 ), then whether or not the voltage signal 362 (eg, V DR ) decreases To a value below the second threshold voltage 1030 (eg, V th2 ), the secondary controller 308 keeps the signal 366 at a logic low level to keep the transistor 310 off.

根據一個實施例，在退磁時段期間，開關330保持斷開(例如，關斷)，如波形1002所示。例如，二次電流352減小。在另一示例中，如果電壓信號362(例如，VDR)變得大於第一閾值電壓1028 (例如，如波形1008所示)，則信號366從邏輯高位準變為邏輯低位準(例如，如波形1010所示)。在另一示例中，電晶體310被關斷，並且電晶體310的溝道電流368減小到低值(例如，幾乎為零)。在另一示例中，電晶體310的體二極體電流370流過電晶體310的體二極體374，然後減小到低值。在另一示例中，退磁時段開始於時刻t45，而在時刻t50之前結束，或開始於時刻t51。在另一示例中，緊接退磁時段的結束，電壓信號362增大到值1019，如波形1008的上升沿所示。 According to one embodiment, the switch 330 remains open (eg, off) during the demagnetization period, as shown by the waveform 1002. For example, the secondary current 352 decreases. In another example, if the voltage signal 362 (e.g., V DR ) becomes greater than the first threshold voltage 1028 (e.g., as shown by waveform 1008), the signal 366 changes from a logic high level to a logic low level (e.g., as Waveform 1010). In another example, the transistor 310 is turned off, and the channel current 368 of the transistor 310 is reduced to a low value (eg, almost zero). In another example, the body diode current 370 of the transistor 310 flows through the body diode 374 of the transistor 310 and then decreases to a low value. In another example, the demagnetization period starts at time t 45 and ends before time t 50 or starts at time t 51 . In another example, immediately after the end of the demagnetization period, the voltage signal 362 increases to a value of 1019, as shown by the rising edge of the waveform 1008.

根據本發明的另一實施例，第10圖是以斷續傳導模式(DCM)操作的如第4B圖所示的電源變換系統400的簡化時序圖。例如，波形1002將功率開關430接通或關斷表示為時間函數，波形1008將電壓信號462(例如，在端子DR處)表示為時間函數，而波形1010將信號466(例如，在端子G2處)表示為時間函數。 According to another embodiment of the present invention, FIG. 10 is a simplified timing diagram of the power conversion system 400 shown in FIG. 4B operating in a discontinuous conduction mode (DCM). For example, waveform 1002 represents the power switch 430 on or off as a function of time, waveform 1008 represents the voltage signal 462 (for example, at terminal DR) as a function of time, and waveform 1010 represents signal 466 (for example, at terminal G2) ) Is expressed as a function of time.

如先前討論的那樣，在一個實施例中，如果電壓信號362(例如，VDR)變得大於第一閾值電壓1028(例如，如波形1008所示)，則信號366從邏輯高位準變為邏輯低位準(例如，如波形1010所示)從而關斷電晶體310。例如，電晶體310這樣的硬關斷經常在電晶體310的汲極處產生振鈴，因為包括一次繞組304和二次繞組306的變壓器中剩餘的能量通過電晶體310的寄生體二極體374散出，並與電晶體310的寄生電容器及變壓器的電感器產生共振。在另一示例中，這些共振振鈴(例如，如波形1008所示在時刻t50之前的振鈴)可達到低於第一閾值電壓1028(例如，Vth1)和第二閾值電壓1030(例如，Vth2)二者的值(例如，值1027)。 As previously discussed, in one embodiment, if the voltage signal 362 (eg, V DR ) becomes greater than the first threshold voltage 1028 (eg, as shown by waveform 1008), the signal 366 changes from a logic high level to a logic level A low level (eg, as shown by waveform 1010) to turn off transistor 310. For example, a hard shutdown such as transistor 310 often causes ringing at the drain of transistor 310 because the remaining energy in the transformer including primary winding 304 and secondary winding 306 is dissipated through parasitic diode 374 of transistor 310 And generate resonance with the parasitic capacitor of the transistor 310 and the inductor of the transformer. In another example, the resonant ring (e.g., t as before ringing waveform 50 at time 1008 shown) could be achieved at 1028 a first threshold voltage (e.g., V ThI) 1030 and a second threshold voltage (e.g., V th2 ) the value of both (for example, the value 1027).

同樣如先前討論的那樣，在另一實施例中，二次控制器308確定從電壓信號362超出第三參考電壓1029(例如，Vref3)的時刻到電壓信號362下降到低於第四參考電壓1031(例如，Vref4)的時刻的持續時間是否比第二閾值時間段(例如，Tth2)長。例如，基於該確定的結果，二次控制器308進一步決定是否回應於電壓信號362(例如，VDR)減 小到低於第一閾值電壓1028(例如，Vth1)和第二閾值電壓1030(例如，Vth2)二者的值而關斷電晶體310。在另一示例中，如果電源變換系統300處於輕載或無載條件下，則持續時間TA(例如，Ton)可變得比第一閾值時間段(例如，Tth1)短，從而導致錯過脈衝觸發(pulse firing)和/或不同步，但是這樣的共振振鈴模式可被感測，如第10圖所示。 Also as previously discussed, in another embodiment, the secondary controller 308 determines from the moment the voltage signal 362 exceeds the third reference voltage 1029 (eg, V ref3 ) until the voltage signal 362 drops below the fourth reference voltage Whether the duration of the time of 1031 (for example, V ref4 ) is longer than the second threshold time period (for example, T th2 ). For example, based on the result of this determination, the secondary controller 308 further decides whether to respond to the voltage signal 362 (eg, V DR ) to decrease below the first threshold voltage 1028 (eg, V th1 ) and the second threshold voltage 1030 ( For example, V th2 ) and the transistor 310 is turned off. In another example, if the power conversion system 300 is under a light load or no load condition, the duration T A (eg, T on ) may become shorter than the first threshold time period (eg, T th1 ), resulting in Missing pulse firing and / or out of sync, but such a resonant ringing pattern can be sensed, as shown in FIG. 10.

如上面所討論的和在這裡進一步強調的那樣，第10圖僅僅是示例，其不應該過度地限制申請專利範圍。本領域的普通技術人員將認識到許多變更、替換和修改。例如，以其他模式(例如，連續傳導模式和臨界傳導模式(例如，准諧振模式))操作的、如第4A圖所示的電源變換系統300或如第4B圖所示的電源變換系統400也可實現如第10圖所示的方案。 As discussed above and further emphasized here, Figure 10 is merely an example, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, a power conversion system 300 as shown in FIG. 4A or a power conversion system 400 as shown in FIG. 4B is also operated in other modes (for example, continuous conduction mode and critical conduction mode (for example, quasi-resonant mode)). The scheme shown in Figure 10 can be implemented.

根據某些實施例，如第10圖所示的方案在連續傳導模式下實現。在一個實施例中，如果從電壓信號362超出第三參考電壓1029(例如，Vref3)的時刻到電壓信號362下降到低於第四參考電壓1031(例如，Vref4)的時刻的持續時間被確定為比第二閾值時間段(例如，Tth2)長，則二次控制器308回應於電壓信號362(例如，VDR)從高於第三參考電壓1029的值減小到低於第一閾值電壓1028(例如，Vth1)和第二閾值電壓1030(例如，Vth2)二者的值，將信號366從邏輯低位準變為邏輯高位準以便接通電晶體310。在另一實施例中，如果從電壓信號362超出第三參考電壓1029(例如，Vref3)的時刻到電壓信號362下降到低於第四參考電壓1031(例如，Vref4)的時刻的持續時間未被確定為比第二閾值時間段(例如，Tth2)長，則即使電壓信號362(例如，VDR)減小到低於第一閾值電壓1028(例如，Vth1)和第二閾值電壓1030(例如，Vth2)二者的值，二次控制器308也不會將信號366從邏輯低位準變為邏輯高位準，從而電晶體310保持關斷。在另一實施例中，控制器302在退磁時段結束之前接通電晶體310(例如，控制器302在二次電流352下降到零之前接通電晶體310)，並且作為回應，信號362(例如，VDR)增大。在另一示例 中，二次控制器308感測到信號362的上升沿，並改變信號366以關斷電晶體310。 According to some embodiments, the scheme shown in Figure 10 is implemented in continuous conduction mode. In one embodiment, if the duration from the moment when the voltage signal 362 exceeds the third reference voltage 1029 (eg, V ref3 ) to the moment when the voltage signal 362 falls below the fourth reference voltage 1031 (eg, V ref4 ) is Determined to be longer than the second threshold time period (for example, T th2 ), the secondary controller 308 reduces the value of the second reference voltage 1029 from a value higher than the third reference voltage 1029 to a value lower than the first in response to the voltage signal 362 (for example, V DR ) The values of both the threshold voltage 1028 (eg, V th1 ) and the second threshold voltage 1030 (eg, V th2 ) change the signal 366 from a logic low level to a logic high level to turn on the transistor 310. In another embodiment, if the duration from the moment when the voltage signal 362 exceeds the third reference voltage 1029 (eg, V ref3 ) to the moment when the voltage signal 362 falls below the fourth reference voltage 1031 (eg, V ref4 ) Not determined to be longer than the second threshold time period (eg, T th2 ), even if the voltage signal 362 (eg, V DR ) decreases below the first threshold voltage 1028 (eg, V th1 ) and the second threshold voltage 1030 (for example, V th2 ), the secondary controller 308 also does not change the signal 366 from a logic low level to a logic high level, so that the transistor 310 remains off. In another embodiment, the controller 302 turns on the transistor 310 before the end of the demagnetization period (for example, the controller 302 turns on the transistor 310 before the secondary current 352 drops to zero), and in response, the signal 362 (for example V DR ) increases. In another example, the secondary controller 308 senses the rising edge of the signal 362 and changes the signal 366 to turn off the transistor 310.

根據某些實施例，如第10圖所示，二次控制器308在端子390處接收電壓信號362(例如，VDR)，確定從電壓信號362低於第一參考電壓829(例如，Vref1)和第二參考電壓929(例如，Vref1)二者但超出第三參考電壓1029(例如，Vref3)的時刻到電壓信號362下降到低於第四參考電壓1031(例如，Vref4)的時刻的持續時間，並進一步確定該持續時間是否比第二閾值時間段(例如，Tth2)長。例如，Vref1>Vref2>Vref3>Vref4。在一個實施例中，如果該持續時間被確定為比第二閾值時間段(例如，Tth2)長，則二次控制器308回應於電壓信號362(例如，VDR)從高於第三參考電壓1029的值減小到低於第一閾值電壓1028(例如，Vth1)和第二閾值電壓1030(例如，Vth2)二者的值，將信號366從邏輯低位準變為邏輯高位準以便接通電晶體310。在另一實施例中，如果該持續時間未被確定為比第二閾值時間段(例如，Tth2)長，則即使電壓信號362(例如，VDR)減小到低於第一閾值電壓1028(例如，Vth1)和第二閾值電壓1030(例如，Vth2)二者的值，二次控制器308也不會將信號366從邏輯低位準變為邏輯高位準，從而電晶體310保持關斷。 According to some embodiments, as shown in FIG. 10, the secondary controller 308 receives the voltage signal 362 (eg, V DR ) at the terminal 390 and determines that the slave voltage signal 362 is lower than the first reference voltage 829 (eg, V ref1 ) And the second reference voltage 929 (for example, V ref1 ) but exceeding the third reference voltage 1029 (for example, V ref3 ) until the voltage signal 362 drops below the fourth reference voltage 1031 (for example, V ref4 ) The duration of the time, and further determine whether the duration is longer than a second threshold time period (eg, T th2 ). For example, V ref1 > V ref2 > V ref3 > V ref4 . In one embodiment, if the duration is determined to be longer than a second threshold time period (eg, T th2 ), the secondary controller 308 responds to the voltage signal 362 (eg, V DR ) from above a third reference The value of voltage 1029 is reduced to a value below both the first threshold voltage 1028 (eg, V th1 ) and the second threshold voltage 1030 (eg, V th2 ), changing the signal 366 from a logic low level to a logic high level so that The transistor 310 is turned on. In another embodiment, if the duration is not determined to be longer than the second threshold time period (eg, T th2 ), then even if the voltage signal 362 (eg, V DR ) decreases below the first threshold voltage 1028 (For example, V th1 ) and the second threshold voltage 1030 (for example, V th2 ), the secondary controller 308 also does not change the signal 366 from a logic low level to a logic high level, so that the transistor 310 remains off Off.

第11圖是根據本發明的另一實施例，示出了作為電源變換系統300的一部分的二次控制器308的某些元件的簡化圖。該圖僅僅是示例，其不應該過度地限制申請專利範圍。本領域的普通技術人員將認識到許多變更、替換和修改。二次控制器308包括：鉗位元元件1102，補償元件1104，上升沿感測元件1106，比較器1124、1210、1220、1230和1240，下降沿感測元件1110，時序控制器1112，邏輯控制元件1114，閘極驅動器1116，輕載感測器1118，信號發生器1120，振盪器1122，欠壓鎖定元件1128，參考信號發生器1126，或閘1250，消抖元件1224，以及計時器元件1234。例如，二次控制器308的一些元件被用於同步整流，包括：鉗位元元件1102，補償元件1104，上升沿感測元件1106，比較器 1124、1210、1220、1230和1240，下降沿感測元件1110、時序控制器1112、邏輯控制元件1114、閘極驅動器1116，或閘1250，消抖元件1224，以及計時器元件1234。在另一示例中，二次控制器308的某些元件被用於輸出電壓感測和控制，包括：輕載感測器1118、信號發生器1120、振盪器1122、參考信號發生器1126、邏輯控制元件1114、以及閘極驅動器1116。在另一示例中，二次控制器308中用於同步整流的元件和二次控制器308中用於輸出電壓感測和控制的元件被集成在同一晶片上。 FIG. 11 is a simplified diagram showing certain elements of the secondary controller 308 as part of the power conversion system 300 according to another embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. Secondary controller 308 includes: clamp element 1102, compensation element 1104, rising edge sensing element 1106, comparators 1124, 1210, 1220, 1230, and 1240, falling edge sensing element 1110, timing controller 1112, logic control Element 1114, gate driver 1116, light load sensor 1118, signal generator 1120, oscillator 1122, undervoltage lockout element 1128, reference signal generator 1126, or gate 1250, debounce element 1224, and timer element 1234 . For example, some elements of the secondary controller 308 are used for synchronous rectification, including: clamp element 1102, compensation element 1104, rising edge sensing element 1106, comparator 1124, 1210, 1220, 1230, and 1240, falling edge sensing element 1110, timing controller 1112, logic control element 1114, gate driver 1116, or gate 1250, debounce element 1224, and timer element 1234. In another example, certain elements of the secondary controller 308 are used for output voltage sensing and control, including: light load sensor 1118, signal generator 1120, oscillator 1122, reference signal generator 1126, logic The control element 1114 and the gate driver 1116. In another example, the elements for synchronous rectification in the secondary controller 308 and the elements for output voltage sensing and control in the secondary controller 308 are integrated on the same wafer.

在一個實施例中，鉗位元元件1102從端子390(例如，端子DR)接收電壓信號362(例如，VDR)。例如，電壓信號362(例如，VDR)被鉗位元元件1102鉗位元。在另一示例中，鉗位元組件1102從二次控制器308中移除。在另一實施例中，上升沿感測元件1106，比較器1210、1220、1230和1240，以及下降沿感測元件1110接收信號1158，該信號1158等於由補償元件1104修改的電壓信號362。例如，補償元件604被省去，並且信號1158與信號362相同。在另一示例中，上升沿感測元件1106包括比較器，且下降沿感測元件1110包括比較器。 In one embodiment, the clamp element 1102 receives a voltage signal 362 (eg, V DR ) from a terminal 390 (eg, terminal DR ). For example, the voltage signal 362 (eg, V DR ) is clamped by the clamp element 1102. In another example, the clamp element 1102 is removed from the secondary controller 308. In another embodiment, the rising edge sensing element 1106, the comparators 1210, 1220, 1230, and 1240, and the falling edge sensing element 1110 receive a signal 1158 that is equal to the voltage signal 362 modified by the compensation element 1104. For example, the compensation element 604 is omitted, and the signal 1158 is the same as the signal 362. In another example, the rising edge sensing element 1106 includes a comparator, and the falling edge sensing element 1110 includes a comparator.

在另一實施例中，比較器1210接收信號1158和第一參考電壓1218(例如，第一參考電壓829)，並向或閘輸出信號1216。例如，如果信號1158大於第一參考電壓1218(例如，第一參考電壓829)，則信號1216處於邏輯高位準。在另一示例中，如果信號1158小於第一參考電壓1218(例如，第一參考電壓829)，則信號1216處於邏輯低位準。在另一實施例中，比較器1220接收信號1158和第二參考電壓1228(例如，第二參考電壓929)，並向消抖元件1224輸出信號1222。例如，如果信號1158大於第二參考電壓1228(例如，第二參考電壓929)，則信號1222處於邏輯高位準。在另一示例中，如果信號1158小於第二參考電壓1228(例如，第二參考電壓929)，則信號1222處於邏輯低位準。 In another embodiment, the comparator 1210 receives the signal 1158 and a first reference voltage 1218 (eg, the first reference voltage 829), and outputs a signal 1216 to the OR gate. For example, if the signal 1158 is greater than the first reference voltage 1218 (eg, the first reference voltage 829), the signal 1216 is at a logic high level. In another example, if the signal 1158 is less than the first reference voltage 1218 (eg, the first reference voltage 829), the signal 1216 is at a logic low level. In another embodiment, the comparator 1220 receives the signal 1158 and the second reference voltage 1228 (eg, the second reference voltage 929), and outputs a signal 1222 to the debouncer 1224. For example, if the signal 1158 is greater than the second reference voltage 1228 (eg, the second reference voltage 929), the signal 1222 is at a logic high level. In another example, if the signal 1158 is less than the second reference voltage 1228 (eg, the second reference voltage 929), the signal 1222 is at a logic low level.

在另一實施例中，比較器1230接收信號1158和第三參考電壓1238(例如，第三參考電壓1029)，並向計時器元件1234輸出信號1232。例如，如果信號1158大於第三參考電壓1238(例如，第三參考電壓1029)，則信號1232處於邏輯高位準。在另一示例中，如果信號1158小於第三參考電壓1238(例如，第三參考電壓1029)，則信號1232處於邏輯低位準。在另一實施例中，比較器1240接收信號1158和第四參考電壓1248(例如，第四參考電壓1031)，並向計時器元件1234輸出信號1242。例如，如果信號1158大於第四參考電壓1248(例如，第四參考電壓1031)，則信號1242處於邏輯高位準。在另一示例中，如果信號1158小於第四參考電壓1248(例如，第四參考電壓1031)，則信號1242處於邏輯低位準。 In another embodiment, the comparator 1230 receives the signal 1158 and the third reference voltage 1238 (eg, the third reference voltage 1029), and outputs a signal 1232 to the timer element 1234. For example, if the signal 1158 is greater than the third reference voltage 1238 (eg, the third reference voltage 1029), the signal 1232 is at a logic high level. In another example, if the signal 1158 is less than the third reference voltage 1238 (eg, the third reference voltage 1029), the signal 1232 is at a logic low level. In another embodiment, the comparator 1240 receives the signal 1158 and a fourth reference voltage 1248 (eg, the fourth reference voltage 1031), and outputs a signal 1242 to the timer element 1234. For example, if the signal 1158 is greater than the fourth reference voltage 1248 (eg, the fourth reference voltage 1031), the signal 1242 is at a logic high level. In another example, if the signal 1158 is less than the fourth reference voltage 1248 (eg, the fourth reference voltage 1031), the signal 1242 is at a logic low level.

根據一個實施例，消抖元件1224從比較器1220接收信號1222，確定信號1222是否指示信號1158在比第一閾值時間段(例如，Tth1)更長的持續時間內保持大於第二參考電壓1228(例如，第二參考電壓929)，並向或閘1250輸出信號1226。例如，如果消抖元件1224確定信號1222指示信號1158在比第一閾值時間段(例如，Tth1)更長的持續時間內保持大於第二參考電壓1228(例如，第二參考電壓929)，則消抖元件1224生成處於邏輯高位準的信號1226。在另一示例中，如果消抖元件1224確定信號1222未指示信號1158在比第一閾值時間段(例如，Tth1)更長的持續時間內保持大於第二參考電壓1228(例如，第二參考電壓929)，則消抖元件1224生成處於邏輯低位準的信號1226。 According to one embodiment, the debounce element 1224 receives the signal 1222 from the comparator 1220, and determines whether the signal 1222 indicates that the signal 1158 remains greater than the second reference voltage 1228 for a longer duration than the first threshold time period (e.g., T th1 ). (For example, the second reference voltage 929), and outputs a signal 1226 to the OR gate 1250. For example, if the anti-shake element 1224 determines that the signal 1222 indicates that the signal 1158 remains greater than the second reference voltage 1228 (eg, the second reference voltage 929) for a longer duration than the first threshold time period (eg, T th1 ), then The debounce element 1224 generates a signal 1226 at a logic high level. In another example, if the anti-shake element 1224 determines that the signal 1222 does not indicate that the signal 1158 remains greater than the second reference voltage 1228 (for example, the second reference) for a longer duration than the first threshold time period (for example, T th1 ) Voltage 929), the debounce element 1224 generates a signal 1226 at a logic low level.

根據另一實施例，計時器元件1234從比較器1230接收信號1232，以及從比較器1240接收信號1242，並向或閘1250輸出信號1236。例如，計時器元件1234確定從電壓信號1158超出第三參考電壓1238(例如，第三參考電壓1029)的時刻到電壓信號1158下降到低於第四參考電壓1248(例如，第四參考電壓1031)的時刻的持續時間。在另一示例中，如果所確定的持續時間比第二閾值時間段(例如，Tth2)長， 則計時器元件1234生成處於邏輯高位準的信號1236。在另一示例中，如果所確定的持續時間不比第二閾值時間段(例如，Tth2)長，則計時器元件1234生成處於邏輯低位準的信號1236。 According to another embodiment, the timer element 1234 receives a signal 1232 from the comparator 1230, and a signal 1242 from the comparator 1240, and outputs a signal 1236 to the OR gate 1250. For example, the timer element 1234 determines from the time when the voltage signal 1158 exceeds the third reference voltage 1238 (eg, the third reference voltage 1029) until the voltage signal 1158 drops below the fourth reference voltage 1248 (eg, the fourth reference voltage 1031) The duration of the moment. In another example, if the determined duration is longer than a second threshold time period (eg, T th2 ), the timer element 1234 generates a signal 1236 at a logic high level. In another example, if the determined duration is not longer than a second threshold time period (eg, T th2 ), the timer element 1234 generates a signal 1236 at a logic low level.

根據另一實施例，或閘1250分別從比較器1210、消抖元件1224和計時器元件1234接收信號1216、1226和1236，並向下降沿感測元件1110(例如，比較器)輸出信號1252。例如，如果信號1216、1226和1236中的任意一個處於邏輯高位準，則或閘生成處於邏輯高位準的信號1252。在另一示例中，如果信號1216、1226和1236都不處於邏輯高位準，則或閘生成處於邏輯低位準的信號1252。 According to another embodiment, OR gate 1250 receives signals 1216, 1226, and 1236 from comparator 1210, debounce element 1224, and timer element 1234, respectively, and outputs signal 1252 to falling edge sensing element 1110 (eg, a comparator). For example, if any of the signals 1216, 1226, and 1236 are at a logic high level, the OR gate generates a signal 1252 at a logic high level. In another example, if none of the signals 1216, 1226, and 1236 are at a logic high level, the OR gate generates a signal 1252 at a logic low level.

在一個實施例中，下降沿感測元件1110(例如，比較器)從或閘1250接收信號1252，並向時序控制器1112輸出信號1111。例如，如果信號1252處於邏輯高位準，則下降沿感測元件1110(例如，比較器)被致能用於下降沿感測；而如果信號1252處於邏輯低位準，則下降沿感測元件1110(例如，比較器)未被致能(例如，在待機中)用於下降沿感測。在另一示例中，如果下降沿感測元件1110(例如，比較器)被致能，則如果信號1158變得小於第二閾值電壓1113(例如，第二閾值電壓830、第二閾值電壓930、和/或第二閾值電壓1030)，那麼下降沿感測元件1110將信號1111從邏輯高位準變為邏輯低位準。在另一示例中，如果下降沿感測元件1110(例如，比較器)未被致能，則下降沿感測元件1110將信號1111保持在邏輯高位準而不管信號1158是否變得小於第二閾值電壓1113。 In one embodiment, the falling edge sensing element 1110 (eg, a comparator) receives a signal 1252 from the OR gate 1250 and outputs a signal 1111 to the timing controller 1112. For example, if the signal 1252 is at a logic high level, the falling edge sensing element 1110 (eg, a comparator) is enabled for falling edge sensing; and if the signal 1252 is at a logic low level, the falling edge sensing element 1110 ( For example, the comparator) is not enabled (e.g., in standby) for falling edge sensing. In another example, if the falling edge sensing element 1110 (eg, a comparator) is enabled, if the signal 1158 becomes less than the second threshold voltage 1113 (eg, the second threshold voltage 830, the second threshold voltage 930, And / or the second threshold voltage 1030), then the falling edge sensing element 1110 changes the signal 1111 from a logic high level to a logic low level. In another example, if the falling edge sensing element 1110 (eg, a comparator) is not enabled, the falling edge sensing element 1110 maintains the signal 1111 at a logic high level regardless of whether the signal 1158 becomes less than the second threshold The voltage is 1113.

在另一實施例中，上升沿感測元件1106(例如，比較器)向時序控制器1112輸出信號1107。例如，如果信號1158變得大於第一閾值電壓1109(例如，第一閾值電壓828、第一閾值電壓928、和/或第一閾值電壓1028)，則上升沿感測元件1106將信號1107從邏輯高位準變為邏輯低位準。在另一示例中，第一閾值電壓1109在大小上大於第二閾值電壓1113。 In another embodiment, the rising edge sensing element 1106 (eg, a comparator) outputs a signal 1107 to the timing controller 1112. For example, if the signal 1158 becomes greater than the first threshold voltage 1109 (eg, the first threshold voltage 828, the first threshold voltage 928, and / or the first threshold voltage 1028), the rising edge sensing element 1106 pulls the signal 1107 from the logic The high level becomes a logic low level. In another example, the first threshold voltage 1109 is larger in magnitude than the second threshold voltage 1113.

在另一實施例中，時序控制器1112接收信號1107和1111，並向邏輯控制器1114輸出信號1172。例如，邏輯控制器1114向閘極驅動器1116輸出信號1115。在另一示例中，閘極驅動器1116提供信號366(例如，在端子G2處)以驅動電晶體310。例如，響應於信號1107從邏輯高位準變為邏輯低位準，閘極驅動器1116將信號366從邏輯高位準變為邏輯低位準以關斷電晶體310。在另一示例中，如果信號1111從邏輯高位準變為邏輯低位準，則閘極驅動器1116將信號366從邏輯低位準變為邏輯高位準以接通電晶體310。 In another embodiment, the timing controller 1112 receives the signals 1107 and 1111 and outputs a signal 1172 to the logic controller 1114. For example, the logic controller 1114 outputs a signal 1115 to the gate driver 1116. In another example, the gate driver 1116 provides a signal 366 (eg, at the terminal G2) to drive the transistor 310. For example, in response to the signal 1107 changing from a logic high level to a logic low level, the gate driver 1116 changes the signal 366 from a logic high level to a logic low level to turn off the transistor 310. In another example, if the signal 1111 changes from a logic high level to a logic low level, the gate driver 1116 changes the signal 366 from a logic low level to a logic high level to turn on the transistor 310.

根據一個實施例，二次控制器308通過信號388(例如，Vs)連續監測輸出電壓350。例如，比較器1124接收參考信號1180和信號388(例如，Vs)，並且輸出信號1182。在另一示例中，輕載感測器1118從振盪器1122接收時鐘信號1174並且從時序控制器1112接收信號1176。在另一示例中，信號1176指示信號362中的某些開關事件(例如，上升沿或下降沿)。在另一示例中，輕載感測器1118輸出指示電源變換系統300的開關頻率的信號1178。在另一示例中，信號發生器1120接收信號1178和信號1182，並向邏輯控制元件1114輸出信號1184以影響電晶體310的狀態。 According to one embodiment, the secondary controller 308 continuously monitors the output voltage 350 through a signal 388 (eg, V s ). For example, the comparator 1124 receives a reference signal 1180 and a signal 388 (eg, V s ), and outputs a signal 1182. In another example, the light load sensor 1118 receives a clock signal 1174 from the oscillator 1122 and a signal 1176 from the timing controller 1112. In another example, the signal 1176 indicates certain switching events (eg, rising or falling edges) in the signal 362. In another example, the light load sensor 1118 outputs a signal 1178 indicating a switching frequency of the power conversion system 300. In another example, the signal generator 1120 receives the signal 1178 and the signal 1182, and outputs a signal 1184 to the logic control element 1114 to affect the state of the transistor 310.

在另一實施例中，如果輸出電壓350在任意條件下(例如，當輸出負載條件從無載/輕載條件變為滿載條件時)下降到低於某閾值位準，則輸出電壓350減小(例如，低於某閾值位準)。例如，如果信號388(例如，Vs)從在大小上大於參考信號1180的第一值變為在大小上低於參考信號1180的第二值，則信號發生器1120在信號1184中生成脈衝以便在短時間段內接通電晶體310。 In another embodiment, if the output voltage 350 drops below a certain threshold level under any condition (for example, when the output load condition changes from no-load / light-load condition to full-load condition), the output voltage 350 decreases (For example, below a certain threshold level). For example, if the signal 388 (eg, V s ) changes from a first value that is greater than the reference signal 1180 in size to a second value that is lower than the reference signal 1180 in size, the signal generator 1120 generates a pulse in the signal 1184 so that The transistor 310 is turned on in a short period of time.

根據一些實施例，如果信號1178指示電源變換系統300在無載/輕載條件下，則信號發生器620回應於信號388(例如，Vs)從在大小上大於參考信號1180的第一值變為在大小上低於參考信號1180的第二值，在信號1184中輸出脈衝。例如，響應於信號1184中的脈衝，閘極 驅動器1116在信號366中生成脈衝730。在另一示例中，在與信號366中的脈衝730相關聯的脈衝時段中，電晶體310被接通，並且溝道電流368以不同方向(例如，從輸出電容器312通過電晶體310到地)流動。在另一示例中，回饋信號360在大小上增大，並形成脈衝。根據某些實施例，控制器302感測到回饋信號360的脈衝，並且作為回應，增大一次繞組304的峰值電流和開關頻率以便向二次側傳遞更多的能量。例如，輸出電壓350和電壓信號388最終在大小上增加。 According to some embodiments, if the signal 1178 indicates that the power conversion system 300 is under no-load / light-load conditions, the signal generator 620 responds to the signal 388 (eg, V s ) from a first value that is larger in size than the reference signal 1180 To be lower in magnitude than the second value of the reference signal 1180, a pulse is output in a signal 1184. For example, in response to a pulse in the signal 1184, the gate driver 1116 generates a pulse 730 in the signal 366. In another example, during a pulse period associated with pulse 730 in signal 366, transistor 310 is turned on and channel current 368 is in a different direction (e.g., from output capacitor 312 through transistor 310 to ground) flow. In another example, the feedback signal 360 increases in size and forms a pulse. According to some embodiments, the controller 302 senses the pulse of the feedback signal 360 and, in response, increases the peak current and switching frequency of the primary winding 304 in order to transfer more energy to the secondary side. For example, the output voltage 350 and the voltage signal 388 eventually increase in size.

如上面所討論的和在這裡進一步強調的那樣，第11圖僅僅是示例，其不應該過度地限制申請專利範圍。本領域的普通技術人員將認識到許多變更、替換和修改。例如，比較器1230和1240以及計時器元件1234從二次控制器308中移除，並且或閘1250接收信號1216和1226並向下降沿感測元件1110(例如，比較器)輸出信號1252。在另一示例中，比較器1220和消抖元件1224從二次控制器308中移除，並且或閘1250接收信號1216和1236並向下降沿感測元件1110(例如，比較器)輸出信號1252。在另一示例中，比較器1210從二次控制器308中移除，並且或閘1250接收信號1226和1236並向下降沿感測元件1110(例如，比較器)輸出信號1252。 As discussed above and further emphasized here, Figure 11 is merely an example, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, comparators 1230 and 1240 and timer element 1234 are removed from secondary controller 308, and OR gate 1250 receives signals 1216 and 1226 and outputs signal 1252 to falling edge sensing element 1110 (eg, a comparator). In another example, the comparator 1220 and the debounce element 1224 are removed from the secondary controller 308, and the OR gate 1250 receives the signals 1216 and 1236 and outputs a signal 1252 to the falling edge sensing element 1110 (e.g., a comparator). . In another example, the comparator 1210 is removed from the secondary controller 308, and the OR gate 1250 receives signals 1226 and 1236 and outputs a signal 1252 to a falling edge sensing element 1110 (eg, a comparator).

在另一示例中，比較器1220、1230和1240，消抖元件1224，計時器元件1234，以及或閘1250從二次控制器308中移除，並且信號1216被用作信號1252並由下降沿感測元件1110(例如，比較器)接收。在另一示例中，比較器1210、1230和1240，計時器元件1234，以及或閘1250從二次控制器308中移除，並且信號1226被用作信號1252並由下降沿感測元件1110(例如，比較器)接收。在另一示例中，比較器1210和1220，消抖元件1224，以及或閘1250從二次控制器308中移除，並且信號1236被用作信號1252並由下降沿感測元件1110(例如，比較器)接收。 In another example, the comparators 1220, 1230, and 1240, the debounce element 1224, the timer element 1234, and the OR gate 1250 are removed from the secondary controller 308, and the signal 1216 is used as the signal 1252 and the falling edge A sensing element 1110 (eg, a comparator) receives. In another example, the comparators 1210, 1230, and 1240, the timer element 1234, and the OR gate 1250 are removed from the secondary controller 308, and the signal 1226 is used as the signal 1252 and is detected by the falling edge sensing element 1110 ( For example, a comparator) receives. In another example, the comparators 1210 and 1220, the debounce element 1224, and the OR gate 1250 are removed from the secondary controller 308, and the signal 1236 is used as the signal 1252 and the falling edge sensing element 1110 (for example, Comparator) receive.

第12圖是根據本發明的一個實施例，示出了用於致能作為電源變換系統300的一部分的二次控制器308的下降沿感測元件1110的方法的簡化圖。該圖僅僅是示例，其不應該過度地限制申請專利範圍。本領域的普通技術人員將認識到許多變更、替換和修改。方法1300包括：用於保持下降沿感測元件1110未致能的過程1310，用於確定條件A是否滿足的過程1320，用於確定條件B是否滿足的過程1322，用於確定條件C是否滿足的過程1324，用於確定條件A、條件B、或條件C中的至少一個是否滿足的過程1330，以及用於致能下降沿感測元件1110的過程1340。 FIG. 12 is a simplified diagram illustrating a method for enabling the falling edge sensing element 1110 of the secondary controller 308 as part of the power conversion system 300 according to one embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. The method 1300 includes a process 1310 for keeping the falling edge sensing element 1110 disabled, a process 1320 for determining whether the condition A is satisfied, a process 1322 for determining whether the condition B is satisfied, and a method 1322 for determining whether the condition C is satisfied. Process 1324, a process 1330 for determining whether at least one of the conditions A, B, or C is satisfied, and a process 1340 for enabling the falling edge sensing element 1110.

在過程1310，下降沿感測元件1110保持未致能(例如，保持待機)。例如，如果信號1252處於邏輯低位準，則下降沿感測元件1110(例如，比較器)不被致能(例如，在待機中)用於下降沿感測。在另一示例中，如果下降沿感測元件1110(例如，比較器)未被致能，則下降沿感測元件1110將信號1111保持在邏輯高位準而不管信號1158是否變為小於第二閾值電壓1113。 At process 1310, the falling edge sensing element 1110 remains disabled (eg, remains on standby). For example, if the signal 1252 is at a logic low level, the falling edge sensing element 1110 (eg, a comparator) is not enabled (eg, in standby) for falling edge sensing. In another example, if the falling edge sensing element 1110 (eg, a comparator) is not enabled, the falling edge sensing element 1110 maintains the signal 1111 at a logic high level regardless of whether the signal 1158 becomes less than the second threshold The voltage is 1113.

在過程1320，確定條件A是否滿足，其中條件A要求信號1158大於第一參考電壓1218(例如，第一參考電壓829)。例如，如果信號1158大於第一參考電壓1218(例如，第一參考電壓829)，則條件A被確定為滿足。在另一示例中，過程1320由比較器1210執行。 At process 1320, it is determined whether condition A is satisfied, where condition A requires signal 1158 to be greater than a first reference voltage 1218 (eg, first reference voltage 829). For example, if the signal 1158 is greater than the first reference voltage 1218 (eg, the first reference voltage 829), the condition A is determined to be satisfied. In another example, the process 1320 is performed by a comparator 1210.

在過程1322，確定條件B是否滿足，其中條件B要求信號1158在比第一閾值時間段(Tth1)更長的持續時間內保持大於第二參考電壓1228(例如，第一參考電壓929)。例如，如果信號1158在比第一閾值時間段(Tth1)更長的持續時間內保持大於第二參考電壓1228(例如，第二參考電壓929)，則條件B被確定為滿足。在另一示例中，過程1322由比較器1220和消抖元件1224執行。 In process 1322, it is determined whether condition B is satisfied, where condition B requires signal 1158 to remain greater than the second reference voltage 1228 (eg, first reference voltage 929) for a longer duration than the first threshold time period ( Tth1 ). For example, if the signal 1158 remains greater than the second reference voltage 1228 (eg, the second reference voltage 929) for a longer duration than the first threshold time period ( Tth1 ), then the condition B is determined to be satisfied. In another example, the process 1322 is performed by a comparator 1220 and a debounce element 1224.

在過程1324，確定條件C是否滿足，其中條件C要求從電壓信號1158超出第三參考電壓1238(例如，第三參考電壓1029)的時 刻到電壓信號1158下降到低於第四參考電壓1248(例如，第四參考電壓1031)的時刻的持續時間比第二閾值時間段(Tth2)長。例如，如果從電壓信號1158超出第三參考電壓1238(例如，第三參考電壓1029)的時刻到電壓信號1158下降到低於第四參考電壓1248(例如，第四參考電壓1031)的時刻的持續時間比第二閾值時間段(Tth2)長，則條件C被確定為滿足。在另一示例中，過程1324由比較器1230和1240以及計時器元件1234執行。 In process 1324, it is determined whether the condition C is satisfied, where the condition C requires that the voltage signal 1158 exceed the third reference voltage 1238 (for example, the third reference voltage 1029) until the voltage signal 1158 drops below the fourth reference voltage 1248 (for example The duration of the time of the fourth reference voltage 1031) is longer than the second threshold time period (T th2 ). For example, if the duration from the moment when the voltage signal 1158 exceeds the third reference voltage 1238 (eg, the third reference voltage 1029) to the moment when the voltage signal 1158 falls below the fourth reference voltage 1248 (eg, the fourth reference voltage 1031) If the time is longer than the second threshold time period (T th2 ), the condition C is determined to be satisfied. In another example, process 1324 is performed by comparators 1230 and 1240 and a timer element 1234.

根據某些實施例，第二參考電壓1228(例如，第二參考電壓929)小於第一參考電壓1218(例如，第一參考電壓829)，第三參考電壓1238(例如，第三參考電壓1029)小於第二參考電壓1228(例如，第二參考電壓929)，第四參考電壓1248(例如，第四參考電壓1031)小於第三參考電壓1238(例如，第三參考電壓1029)，並且第二閾值電壓1113(例如，第二閾值電壓830、第二閾值電壓930、和/或第二閾值電壓1030)小於第四參考電壓1248(例如，第四參考電壓1031)。根據一些實施例，第一參考電壓1218(例如，第一參考電壓829)、第二參考電壓1228(例如，第二參考電壓929)、第三參考電壓1238(例如，第三參考電壓1029)、第四參考電壓1248(例如，第四參考電壓1031)每個都大於零，並且第二閾值電壓1113(例如，第二閾值電壓830、第二閾值電壓930、和/或第二閾值電壓1030)小於零。 According to some embodiments, the second reference voltage 1228 (eg, the second reference voltage 929) is less than the first reference voltage 1218 (eg, the first reference voltage 829) and the third reference voltage 1238 (eg, the third reference voltage 1029) Is smaller than the second reference voltage 1228 (for example, the second reference voltage 929), the fourth reference voltage 1248 (for example, the fourth reference voltage 1031) is smaller than the third reference voltage 1238 (for example, the third reference voltage 1029), and the second threshold value The voltage 1113 (for example, the second threshold voltage 830, the second threshold voltage 930, and / or the second threshold voltage 1030) is smaller than the fourth reference voltage 1248 (for example, the fourth reference voltage 1031). According to some embodiments, the first reference voltage 1218 (eg, the first reference voltage 829), the second reference voltage 1228 (eg, the second reference voltage 929), the third reference voltage 1238 (eg, the third reference voltage 1029), The fourth reference voltages 1248 (eg, the fourth reference voltage 1031) are each greater than zero, and the second threshold voltage 1113 (eg, the second threshold voltage 830, the second threshold voltage 930, and / or the second threshold voltage 1030) Less than zero.

在過程1330，確定條件A、條件B、或條件C中的至少一個是否滿足。例如，如果條件A滿足，則條件A、條件B、或條件C中的至少一個滿足。在另一示例中，如果條件A和條件B滿足，則條件A、條件B、或條件C中的至少一個滿足。在另一示例中，過程1330由或閘1250執行。 At process 1330, it is determined whether at least one of condition A, condition B, or condition C is satisfied. For example, if condition A is satisfied, at least one of condition A, condition B, or condition C is satisfied. In another example, if condition A and condition B are satisfied, at least one of condition A, condition B, or condition C is satisfied. In another example, process 1330 is performed by OR gate 1250.

根據一個實施例，如果條件A、條件B、或條件C都不滿足，則執行過程1310，使得下降沿感測元件1110保持未致能(例如， 保持待機)。根據另一實施例，如果條件A、條件B、或條件C中的至少一個滿足，則執行過程1340。 According to one embodiment, if condition A, condition B, or condition C is not satisfied, process 1310 is performed, so that the falling edge sensing element 1110 remains unenabled (for example, (Standby). According to another embodiment, if at least one of condition A, condition B, or condition C is satisfied, process 1340 is performed.

例如，如果下降沿感測元件1110(例如，比較器)未被致能，則下降沿感測元件1110將信號1111保持在邏輯高位準而不管信號1158是否變為小於第二閾值電壓1113(例如，第二閾值電壓830、第二閾值電壓930、和/或第二閾值電壓1030)。在另一示例中，如果下降沿感測元件1110(例如，比較器)未被致能，則閘極驅動器1116將信號366保持在邏輯低位準從而保持電晶體310關斷而不管信號1158是否變為小於第二閾值電壓1113(例如，第二閾值電壓830、第二閾值電壓930、和/或第二閾值電壓1030)。 For example, if the falling edge sensing element 1110 (eg, a comparator) is not enabled, the falling edge sensing element 1110 maintains the signal 1111 at a logic high level regardless of whether the signal 1158 becomes less than the second threshold voltage 1113 (eg (The second threshold voltage 830, the second threshold voltage 930, and / or the second threshold voltage 1030). In another example, if the falling edge sensing element 1110 (eg, a comparator) is not enabled, the gate driver 1116 maintains the signal 366 at a logic low level to keep the transistor 310 off regardless of whether the signal 1158 is changed Is less than the second threshold voltage 1113 (eg, the second threshold voltage 830, the second threshold voltage 930, and / or the second threshold voltage 1030).

在步驟1340，下降沿感測元件1110被致能。例如，如果下降沿感測元件1110(例如，比較器)被致能，則如果信號1158變得小於第二閾值電壓1113(例如，第二閾值電壓830、第二閾值電壓930、和/或第二閾值電壓1030)，那麼下降沿感測元件1110將信號1111從邏輯高位準變為邏輯低位準。在另一示例中，如果信號1111從邏輯高位準變為邏輯低位準，則閘極驅動器1116將信號366從邏輯低位準變為邏輯高位準，以接通電晶體310。在另一示例中，如果下降沿感測元件1110(例如，比較器)被致能且如果信號1158變得小於第二閾值電壓1113(例如，第二閾值電壓830、第二閾值電壓930、和/或第二閾值電壓1030)，則閘極驅動器1116將信號366從邏輯低位準變為邏輯高位準，以接通電晶體310。 At step 1340, the falling edge sensing element 1110 is enabled. For example, if the falling edge sensing element 1110 (eg, a comparator) is enabled, if the signal 1158 becomes less than the second threshold voltage 1113 (eg, the second threshold voltage 830, the second threshold voltage 930, and / or the first Two threshold voltages 1030), then the falling edge sensing element 1110 changes the signal 1111 from a logic high level to a logic low level. In another example, if the signal 1111 changes from a logic high level to a logic low level, the gate driver 1116 changes the signal 366 from a logic low level to a logic high level to turn on the transistor 310. In another example, if the falling edge sensing element 1110 (eg, a comparator) is enabled and if the signal 1158 becomes less than the second threshold voltage 1113 (eg, the second threshold voltage 830, the second threshold voltage 930, and (Or the second threshold voltage 1030), the gate driver 1116 changes the signal 366 from a logic low level to a logic high level to turn on the transistor 310.

如上面所討論的和在這裡進一步強調的那樣，第12圖僅僅是示例，其不應該過度地限制申請專利範圍。本領域的普通技術人員將認識到許多變更、替換和修改。例如，如果下降沿感測元件1110在過程1340被致能，則在下降沿感測元件1110感測到信號1158變為小於第二閾值電壓1113之後，下降沿感測元件1110再次變為未致能，從而重複過程1310。在另一示例中，信號1158與信號362相同。 As discussed above and further emphasized here, Figure 12 is merely an example, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, if the falling edge sensing element 1110 is enabled in the process 1340, after the falling edge sensing element 1110 senses that the signal 1158 becomes smaller than the second threshold voltage 1113, the falling edge sensing element 1110 becomes inactive again. If so, process 1310 is repeated. In another example, the signal 1158 is the same as the signal 362.

在一個實施例中，二次控制器408與第11圖所示的二次控制器308相同。在另一實施例中，第12圖是示出了用於致能作為電源變換系統400的一部分的二次控制器408的下降沿感測元件1110的方法的簡化圖。 In one embodiment, the secondary controller 408 is the same as the secondary controller 308 shown in FIG. 11. In another embodiment, FIG. 12 is a simplified diagram illustrating a method for enabling the falling edge sensing element 1110 of the secondary controller 408 as part of the power conversion system 400.

根據一些實施例，以其他模式(例如，連續傳導模式和臨界傳導模式(例如，准諧振模式))操作的、作為電源變換系統300的一部分的二次控制器308或作為電源變換系統400的一部分的二次控制器408也可實現如第11圖和第12圖所示的方案。 According to some embodiments, the secondary controller 308 that is part of the power conversion system 300 or that is part of the power conversion system 400 that operates in other modes (eg, continuous conduction mode and critical conduction mode (eg, quasi-resonant mode)) The secondary controller 408 can also implement the solutions shown in FIG. 11 and FIG. 12.

本發明的某些實施例提供了可避免由於寄生電容器和變壓器電感引起的共振振盪而導致開關脈衝的錯誤觸發的整流電路。例如，開關脈衝的錯誤觸發可引起二次側開關控制和一次側開關控制之間的不同步。在另一示例中，該不同步可引起可能導致電源變換系統損壞的可靠性問題。本發明的一些實施例提供了提高二次側開關與一次側開關的同步性並且也提高電源變換系統的可靠性的系統和方法。例如，本發明的二次控制器可識別負脈衝是真的接通信號還是只是共振振鈴或毛刺。 Certain embodiments of the present invention provide a rectifier circuit that can avoid false triggering of switching pulses due to resonance oscillations caused by parasitic capacitors and transformer inductance. For example, a false triggering of a switching pulse may cause a non-synchronization between the secondary-side switching control and the primary-side switching control. In another example, this out of sync can cause reliability issues that can cause damage to the power conversion system. Some embodiments of the present invention provide systems and methods that improve the synchronization between the secondary-side switch and the primary-side switch and also improve the reliability of the power conversion system. For example, the secondary controller of the present invention can identify whether a negative pulse is really a turn-on signal or only a resonant ringing or glitch.

根據另一實施例，用於調節電源變換系統的系統控制器包括第一控制器端子和第二控制器端子。此外，該系統控制器被配置為在第一控制器端子接收輸入信號，並且至少部分基於該輸入信號，在第二控制器端子生成驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。此外，該系統控制器還被配置為：確定該輸入信號在第一時刻是否大於第一閾值；回應於該輸入信號被確定為在第一時刻大於第一閾值，確定該輸入信號在第二時刻是否小於第二閾值；並且回應於該輸入信號被確定為在第二時刻小於第二閾值，將第二控制器端子處的驅動信號從第一邏輯位準變為第二邏輯位準。此外，第二時刻在第一時刻之後。例如，至少根據第8圖和/或第11圖來實現該系統控制器。 According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. In addition, the system controller is configured to receive an input signal at the first controller terminal, and based at least in part on the input signal, generate a driving signal at the second controller terminal to turn on or off the transistor to affect the power conversion system Current associated with the secondary winding. In addition, the system controller is further configured to: determine whether the input signal is greater than a first threshold at a first moment; in response to the input signal being determined to be greater than a first threshold at a first moment, determine that the input signal is at a second moment Whether it is less than the second threshold; and in response to the input signal being determined to be less than the second threshold at the second moment, the driving signal at the second controller terminal is changed from the first logic level to the second logic level. In addition, the second time is after the first time. For example, the system controller is implemented according to at least FIG. 8 and / or FIG. 11.

根據另一實施例，用於調節電源變換系統的系統控制器包括第一控制器端子和第二控制器端子。此外，該系統控制器被配置為在 第一控制器端子接收輸入信號，並且至少部分基於該輸入信號，在第二控制器端子生成驅動信號以接通或關斷電晶體，以影響與電源變換系統的二次繞組相關聯的電流。此外，該系統控制器還被配置為：確定該輸入信號是否在比預定持續時間更長的時間段內保持大於第一閾值，並且回應於該輸入信號被確定為在比預定持續時間更長的時間段內保持大於第一閾值，確定該輸入信號在該時間段之後的某時刻是否小於第二閾值。此外，該系統控制器還被配置為：回應於該輸入信號被確定為在該時刻小於第二閾值，將第二控制器端子處的驅動信號從第一邏輯位準變為第二邏輯位準。例如，至少根據第9圖和/或第11圖來實現該系統控制器。 According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. In addition, the system controller is configured to The first controller terminal receives an input signal, and based at least in part on the input signal, generates a drive signal at the second controller terminal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system. In addition, the system controller is further configured to determine whether the input signal remains greater than the first threshold for a period of time longer than the predetermined duration, and in response to the input signal is determined to be longer than the predetermined duration It remains larger than the first threshold during the time period, and determines whether the input signal is less than the second threshold at a certain time after the time period. In addition, the system controller is further configured to: in response to the input signal being determined to be less than a second threshold at this time, change the driving signal at the terminal of the second controller from the first logic level to the second logic level . For example, the system controller is implemented according to at least FIG. 9 and / or FIG. 11.

根據另一實施例，用於調節電源變換系統的系統控制器包括第一控制器端子和第二控制器端子。此外，該系統控制器被配置為在第一控制器端子接收輸入信號，並且至少部分基於該輸入信號，在第二控制器端子生成驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。此外，該系統控制器還被配置為：確定從該輸入信號變得大於第一閾值的第一時刻到該輸入信號變得小於第二閾值的第二時刻的時間間隔是否比預定持續時間長，並且回應於該時間間隔被確定為比預定持續時間長，確定該輸入信號在該時間間隔之後的某時刻是否小於第三閾值。此外，該系統控制器還被配置為：回應於該輸入信號被確定為在該時刻小於第三閾值，將第二控制器端子處的驅動信號從第一邏輯位準變為第二邏輯位準。例如，至少根據第10圖和/或第11圖來實現該系統控制器。 According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. In addition, the system controller is configured to receive an input signal at the first controller terminal, and based at least in part on the input signal, generate a driving signal at the second controller terminal to turn on or off the transistor to affect the power conversion system Current associated with the secondary winding. In addition, the system controller is further configured to determine whether a time interval from a first moment when the input signal becomes greater than a first threshold to a second moment when the input signal becomes less than a second threshold is longer than a predetermined duration, And in response to the time interval being determined to be longer than a predetermined duration, it is determined whether the input signal is less than a third threshold at a certain time after the time interval. In addition, the system controller is further configured to: in response to the input signal being determined to be less than a third threshold at this time, change the driving signal at the second controller terminal from the first logic level to the second logic level . For example, the system controller is implemented according to at least FIG. 10 and / or FIG. 11.

根據另一實施例，用於調節電源變換系統的系統控制器包括第一控制器端子和第二控制器端子。此外，該系統控制器被配置為在第一控制器端子接收輸入信號，並且至少部分基於該輸入信號，在第二控制器端子生成驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。此外，該系統控制器還被配置為：確定該輸入信號是否大於第一閾值；確定該輸入信號是否在比第一預定持續時間更長的時 間段內保持大於第二閾值；並且確定從該輸入信號變得大於第三閾值的第一時刻到該輸入信號變得小於第四閾值的第二時刻的時間間隔是否比第二預定持續時間長。此外，該系統控制器還被配置為：回應於該輸入信號被確定為大於第一閾值、該輸入信號被確定為在比第一預定持續時間更長的時間段內保持大於第二閾值、或該時間間隔被確定為比第二預定持續時間長，確定該輸入信號是否小於第五閾值，並且回應於該輸入信號被確定為小於第五閾值，將第二控制器端子處的驅動信號從第一邏輯位準變為第二邏輯位準。例如，至少根據第11圖和/或第12圖來實現該系統控制器。 According to another embodiment, a system controller for adjusting a power conversion system includes a first controller terminal and a second controller terminal. In addition, the system controller is configured to receive an input signal at the first controller terminal, and based at least in part on the input signal, generate a driving signal at the second controller terminal to turn on or off the transistor to affect the power conversion system Current associated with the secondary winding. In addition, the system controller is further configured to: determine whether the input signal is greater than a first threshold; determine whether the input signal is longer than a first predetermined duration Remain within the interval greater than the second threshold; and determine whether the time interval from the first moment when the input signal becomes greater than the third threshold to the second moment when the input signal becomes less than the fourth threshold is longer than the second predetermined duration . In addition, the system controller is further configured to: in response to the input signal being determined to be greater than the first threshold value, the input signal being determined to remain greater than the second threshold value for a time period longer than the first predetermined duration, or The time interval is determined to be longer than the second predetermined duration, it is determined whether the input signal is less than a fifth threshold, and in response to the input signal being determined to be less than a fifth threshold, the driving signal at the second controller terminal is removed from the first One logic level becomes the second logic level. For example, the system controller is implemented according to at least FIG. 11 and / or FIG. 12.

根據另一實施例，用於調節電源變換系統的方法包括：接收輸入信號，處理與該輸入信號相關聯的資訊，並至少部分基於該輸入信號生成驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。此外，處理與該輸入信號相關聯的資訊包括：確定該輸入信號在第一時刻是否大於第一閾值。此外，至少部分基於該輸入信號生成驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流包括：回應於該輸入信號被確定為在第一時刻大於第一閾值，確定該輸入信號在第二時刻是否小於第二閾值，並且回應於該輸入信號被確定為在第二時刻小於第二閾值，將驅動信號從第一邏輯位準變為第二邏輯位準。此外，第二時刻在第一時刻之後。例如，至少根據第8圖和/或第11圖來實現該方法。 According to another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and generating a driving signal based on the input signal to turn on or off a transistor to affect The current associated with the secondary winding of the power conversion system. In addition, processing information associated with the input signal includes determining whether the input signal is greater than a first threshold at a first moment. In addition, generating a driving signal based on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: in response to the input signal being determined to be greater than the first at a first moment Threshold, determining whether the input signal is less than the second threshold at the second moment, and in response to the input signal being determined to be less than the second threshold at the second moment, changing the driving signal from the first logic level to the second logic level . In addition, the second time is after the first time. For example, the method is implemented according to at least FIG. 8 and / or FIG. 11.

根據另一實施例，用於調節電源變換系統的方法包括：接收輸入信號，處理與該輸入信號相關聯的資訊，並至少部分基於該輸入信號生成驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。此外，處理與該輸入信號相關聯的資訊包括：確定該輸入信號是否在比預定持續時間更長的時間段內保持大於第一閾值。此外，至少部分基於該輸入信號生成驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流包括：回應於該輸入信號被確定為在比預定持續時間更長的時間段內保持大於第一閾值，確定該輸入信號在該 時間段之後的某時刻是否小於第二閾值，並且回應於該輸入信號被確定為在該時刻小於第二閾值，將驅動信號從第一邏輯位準變為第二邏輯位準。例如，至少根據第9圖和/或第11圖來實現該方法。 According to another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and generating a driving signal based on the input signal to turn on or off a transistor to affect The current associated with the secondary winding of the power conversion system. In addition, processing information associated with the input signal includes determining whether the input signal remains greater than a first threshold for a period of time longer than a predetermined duration. In addition, generating a drive signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: in response to the input signal being determined to be longer than a predetermined duration Remains greater than the first threshold for a period of time, determines that the input signal is within the Whether a certain time after the time period is less than the second threshold, and in response to the input signal being determined to be less than the second threshold at that time, the driving signal is changed from the first logic level to the second logic level. For example, the method is implemented according to at least FIG. 9 and / or FIG. 11.

根據另一實施例，用於調節電源變換系統的方法包括：接收輸入信號，處理與該輸入信號相關聯的資訊，並至少部分基於該輸入信號生成驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。此外，處理與該輸入信號相關聯的資訊包括：確定從該輸入信號變得大於第一閾值的第一時刻到該輸入信號變得小於第二閾值的第二時刻的時間間隔是否比預定持續時間長。此外，至少部分基於該輸入信號生成驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流包括：回應於該時間間隔被確定為比預定持續時間長，確定該輸入信號在該時間間隔之後的某時刻是否小於第三閾值，並且回應於該輸入信號被確定為在該時刻小於第三閾值，將驅動信號從第一邏輯位準變為第二邏輯位準。例如，至少根據第10圖和/或第11圖來實現該方法。 According to another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and generating a driving signal based on the input signal to turn on or off a transistor to affect The current associated with the secondary winding of the power conversion system. In addition, processing information associated with the input signal includes determining whether a time interval from a first moment when the input signal becomes greater than a first threshold to a second moment when the input signal becomes less than a second threshold is longer than a predetermined duration long. In addition, generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: in response to the time interval being determined to be longer than a predetermined duration, determining Whether the input signal is less than the third threshold at a time after the time interval, and in response to the input signal being determined to be less than the third threshold at the time, changing the driving signal from the first logic level to the second logic level . For example, the method is implemented according to at least FIG. 10 and / or FIG. 11.

根據另一實施例，用於調節電源變換系統的方法包括：接收輸入信號，處理與該輸入信號相關聯的資訊，並至少部分基於該輸入信號生成驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流。此外，處理與該輸入信號相關聯的資訊包括：確定該輸入信號是否大於第一閾值；確定該輸入信號是否在比第一預定持續時間更長的時間段內保持大於第二閾值；以及確定從該輸入信號變得大於第三閾值的第一時刻到該輸入信號變得小於第四閾值的第二時刻的時間間隔是否比第二預定持續時間長。此外，至少部分基於該輸入信號生成驅動信號以接通或關斷電晶體從而影響與電源變換系統的二次繞組相關聯的電流包括：回應於該輸入信號被確定為大於第一閾值，該輸入信號被確定為在比第一預定持續時間更長的時間段內保持大於第二閾值，或該時間間隔被確定為比第二預定持續時間長，確定該輸入信號是否小於第五閾值，並且回 應於該輸入信號被確定為小於第五閾值，將驅動信號從第一邏輯位準變為第二邏輯位準。例如，至少根據第11圖和/或第12圖來實現該方法。 According to another embodiment, a method for adjusting a power conversion system includes receiving an input signal, processing information associated with the input signal, and generating a driving signal based on the input signal to turn on or off a transistor to affect The current associated with the secondary winding of the power conversion system. In addition, processing information associated with the input signal includes: determining whether the input signal is greater than a first threshold; determining whether the input signal remains greater than a second threshold for a period of time longer than a first predetermined duration; and determining from Whether the time interval from the first moment when the input signal becomes larger than the third threshold to the second moment when the input signal becomes smaller than the fourth threshold is longer than the second predetermined duration. In addition, generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power conversion system includes: in response to the input signal being determined to be greater than a first threshold, the input The signal is determined to remain greater than the second threshold for a time period longer than the first predetermined duration, or the time interval is determined to be longer than the second predetermined duration, determines whether the input signal is less than a fifth threshold, and returns When the input signal is determined to be smaller than the fifth threshold, the driving signal is changed from the first logic level to the second logic level. For example, the method is implemented according to at least FIG. 11 and / or FIG. 12.

第13圖是根據本發明的一個實施例，示出了具有二次側同步整流器(SR)的電源變換系統的簡化圖。該圖僅僅是示例，其不應該過度地限制申請專利範圍。本領域的普通技術人員將認識到許多變更、替換和修改。電源變換系統3300(例如，返馳式電源變換器)包括一次側脈衝寬度調變(PWM)控制器3302，一次繞組3304，二次繞組3306，二次側同步整流器(SR)控制器3308，電晶體3310(例如，MOSFET)，輸出電容性負載3312，輸出電阻性負載3314，以及功率開關3330(例如，電晶體)。二次側同步整流器(SR)控制器3308包括端子3390、3392、3394和3396。 FIG. 13 is a simplified diagram showing a power conversion system having a secondary-side synchronous rectifier (SR) according to an embodiment of the present invention. This figure is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. The power conversion system 3300 (eg, a flyback power converter) includes a primary-side pulse width modulation (PWM) controller 3302, a primary winding 3304, a secondary winding 3306, a secondary-side synchronous rectifier (SR) controller 3308, A crystal 3310 (eg, a MOSFET), an output capacitive load 3312, an output resistive load 3314, and a power switch 3330 (eg, a transistor). The secondary-side synchronous rectifier (SR) controller 3308 includes terminals 3390, 3392, 3394, and 3396.

在一個實施例中，端子3390接收指示電晶體3310的端子3364(例如，電晶體3310的汲極端)處的電壓的電壓信號3362，並且端子3392輸出驅動信號3366到電晶體3310(例如，MOSFET)。在另一實施例中，端子3394接收指示輸出電容性負載3312和輸出電容性負載3314接收到的輸出電壓的電壓信號3316。在又一實施例中，端子3396被偏置到二次側地。 In one embodiment, the terminal 3390 receives a voltage signal 3362 indicating the voltage at the terminal 3364 (eg, the drain terminal of the transistor 3310) of the transistor 3310, and the terminal 3392 outputs a drive signal 3366 to the transistor 3310 (eg, a MOSFET) . In another embodiment, the terminal 3394 receives a voltage signal 3316 indicating the output voltage received by the output capacitive load 3312 and the output capacitive load 3314. In yet another embodiment, the terminal 3396 is biased to the secondary ground.

根據一些實施例，一次側脈衝寬度調變(PWM)控制器3302生成驅動信號3332並且向功率開關3330(例如，電晶體)輸出驅動信號3332，二次側同步整流器(SR)控制器3308生成驅動信號3366並且向電晶體3310(例如，MOSFET)輸出驅動信號3366。 According to some embodiments, the primary-side pulse width modulation (PWM) controller 3302 generates a drive signal 3332 and outputs the drive signal 3332 to a power switch 3330 (eg, a transistor), and the secondary-side synchronous rectifier (SR) controller 3308 generates a drive The signal 3366 also outputs a driving signal 3366 to the transistor 3310 (for example, a MOSFET).

在一個實施例中，二次側同步整流器(SR)控制器3308感測指示電晶體3310的端子3364(例如，電晶體3310的樓極端)處的電壓的電壓信號3362，並且提供決定電晶體3310的接通或關斷的驅動信號3366。在另一實施例中，二次側同步整流器(SR)控制器3308確定使用慢接通方案還是快接通方案。 In one embodiment, the secondary-side synchronous rectifier (SR) controller 3308 senses a voltage signal 3362 indicating a voltage at a terminal 3364 of the transistor 3310 (eg, a building terminal of the transistor 3310), and provides a decision transistor 3310 The driving signal 3366 is turned on or off. In another embodiment, the secondary-side synchronous rectifier (SR) controller 3308 determines whether to use a slow-on scheme or a fast-on scheme.

根據一個實施例，如果二次側同步整流器(SR)控制器3308確定使用快接通方案，則二次側同步整流器(SR)控制器3308感測電壓信號3362是否變得小於閾值電壓(例如，Vth)。例如，在快接通方案中，如果二次側同步整流器(SR)控制器3308感測到電壓信號3362變得小於閾值電壓(例如，Vth)，則二次側同步整流器(SR)控制器3308立即將驅動信號3366從邏輯低位準變為邏輯高位準；如果二次側同步整流器(SR)控制器3308感測到電壓信號3362沒有變得小於閾值電壓(例如，Vth)，則二次側同步整流器(SR)控制器3308不將驅動信號3366從邏輯低位準變為邏輯高位準。在另一示例中，如果驅動信號3366在快接通方案中沒有從邏輯低位準變為邏輯高位準，則用於二次側同步整流器(SR)控制器3308的接通方案保持為快接通方案，直到回應於驅動信號3366在快接通方案中從邏輯低位準變為邏輯高位準，用於二次側同步整流器(SR)控制器3308的接通方案從快接通方案變為慢接通方案。在又一示例中，如果驅動信號3366在快接通方案中從邏輯低位準變為邏輯高位準，則用於二次側同步整流器(SR)控制器3308的接通方案從快接通方案變回到慢接通方案，直到響應於一個或多個預定條件被滿足(例如，如第14圖、第15圖、和/或第16圖所示)，用於二次側同步整流器(SR)控制器3308的接通方案從慢接通方案變為快接通方案。 According to one embodiment, if the secondary-side synchronous rectifier (SR) controller 3308 determines to use a fast-on scheme, the secondary-side synchronous rectifier (SR) controller 3308 senses whether the voltage signal 3362 becomes less than a threshold voltage (eg, V th ). For example, in the fast-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V th ), the secondary-side synchronous rectifier (SR) controller 3308 immediately changes the driving signal 3366 from a logic low level to a logic high level; if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 does not become less than a threshold voltage (for example, V th ), the secondary The side synchronous rectifier (SR) controller 3308 does not change the driving signal 3366 from a logic low level to a logic high level. In another example, if the driving signal 3366 does not change from a logic low level to a logic high level in the fast turn-on scheme, the turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 remains fast turn-on Solution until the response signal 3366 changes from a logic low level to a logic high level in the fast turn-on scheme, and the turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 changes from the fast turn-on scheme to the slow turn-on Link scheme. In yet another example, if the driving signal 3366 changes from a logic low level to a logic high level in the fast turn-on scheme, the turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 changes from the fast turn-on scheme Return to the slow-on scheme until one or more predetermined conditions are met (for example, as shown in Figure 14, Figure 15, and / or Figure 16) for a secondary-side synchronous rectifier (SR) The connection scheme of the controller 3308 is changed from a slow connection scheme to a fast connection scheme.

根據另一實施例，如果二次側同步整流器(SR)控制器3308確定使用慢接通方案，則二次側同步整流器(SR)控制器3308感測電壓信號3362是否變得小於閾值電壓(例如，Vth)。例如，在慢接通方案中，如果二次側同步整流器(SR)控制器3308感測到電壓信號3362變得小於閾值電壓(例如，Vth)，則二次側同步整流器(SR)控制器3308不立即將驅動信號3366從邏輯低位準變為邏輯高位準。在另一示例中，在慢接通方案中，如果二次側同步整流器(SR)控制器3308感測到電壓信號3362變得小於閾值電壓(例如，Vth)，則二次側同步整流器(SR)控制器3308感測電壓信號3362在等於或大於預定時間段的持續時間內是 否保持小於閾值電壓(例如，Vth)，並且如果電壓信號3362在等於或大於預定時間段的持續時間內保持小於預定電壓(例如，Vth)，則二次側同步整流器(SR)控制器3308將驅動信號3366從邏輯低位準變為邏輯高位準。在另一示例中，在慢接通方案中，如果二次側同步整流器(SR)控制器3308感測到電壓信號3362在等於或大於預定時間段的持續時間內沒有保持小於閾值電壓(例如，Vth)，則二次側同步整流器(SR)控制器3308不將驅動信號3366從邏輯低位準變為邏輯高位準。在又一示例中，不管驅動信號3366在慢接通方案中是否從邏輯低位準變為邏輯高位準，用於二次側同步整流器(SR)控制器3308的接通方案保持作為默認接通方案的慢接通方案，直到回應於一個或多個預定條件被滿足(例如，如第14圖、第15圖、和/或第16圖所示)，用於二次側同步整流器(SR)控制器3308的接通方案從慢接通方案變為快接通方案。 According to another embodiment, if the secondary-side synchronous rectifier (SR) controller 3308 determines to use a slow-on scheme, the secondary-side synchronous rectifier (SR) controller 3308 senses whether the voltage signal 3362 becomes less than a threshold voltage (e.g., , V th ). For example, in the slow-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V th ), the secondary-side synchronous rectifier (SR) controller 3308 does not immediately change the driving signal 3366 from a logic low level to a logic high level. In another example, in the slow-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V th ), the secondary-side synchronous rectifier ( (SR) The controller 3308 senses whether the voltage signal 3362 remains less than a threshold voltage (for example, V th ) for a duration equal to or greater than a predetermined period of time, and if the voltage signal 3362 remains for a duration equal to or greater than a predetermined period of time If it is less than a predetermined voltage (for example, V th ), the secondary-side synchronous rectifier (SR) controller 3308 changes the driving signal 3366 from a logic low level to a logic high level. In another example, in the slow-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 has not remained below a threshold voltage for a duration equal to or greater than a predetermined time period (for example, V th ), the secondary-side synchronous rectifier (SR) controller 3308 does not change the driving signal 3366 from a logic low level to a logic high level. In yet another example, the switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 remains as the default switching scheme regardless of whether the driving signal 3366 changes from a logic low level to a logic high level in the slow switching scheme. Slow-on scheme until responding to one or more predetermined conditions are met (eg, as shown in Figure 14, Figure 15, and / or Figure 16) for secondary-side synchronous rectifier (SR) control The connection scheme of the switch 3308 is changed from a slow-connection scheme to a fast-connection scheme.

根據一些實施例，在快接通方案中，如果二次側同步整流器(SR)控制器3308感測到電壓信號3362變得小於閾值電壓(例如，Vth)，則二次側同步整流器(SR)控制器3308立即將驅動信號3366從邏輯低位準變為邏輯高位準。例如，在二次側同步整流器(SR)控制器3308在快接通方案中將驅動信號3366從邏輯低位準變為邏輯高位準之後，二次側同步整流器(SR)控制器3308將驅動信號3366保持在邏輯高位準，然後將驅動信號3366從邏輯高位準變為邏輯低位準。例如，在連續傳導模式(CCM)下，二次側同步整流器(SR)控制器3308預測將驅動信號3366從邏輯高位準變回邏輯低位準的時間。在另一示例中，在斷續傳導模式(DCM)下，二次側同步整流器(SR)控制器3308在流過電晶體3310的源極端與電晶體3310的汲極端之間的電流的大小達到零時將驅動信號3366從邏輯高位準變回邏輯低位準。 According to some embodiments, in the fast-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V th ), the secondary-side synchronous rectifier (SR The controller 3308 immediately changes the driving signal 3366 from a logic low level to a logic high level. For example, after the secondary-side synchronous rectifier (SR) controller 3308 changes the drive signal 3366 from a logic low level to a logic high level in the fast-on scheme, the secondary-side synchronous rectifier (SR) controller 3308 changes the drive signal 3366 Keep at the logic high level, and then change the driving signal 3366 from the logic high level to the logic low level. For example, in continuous conduction mode (CCM), the secondary-side synchronous rectifier (SR) controller 3308 predicts the time to change the drive signal 3366 from a logic high level to a logic low level. In another example, in the discontinuous conduction mode (DCM), the magnitude of the current between the secondary side synchronous rectifier (SR) controller 3308 between the source terminal of the transistor 3310 and the drain terminal of the transistor 3310 reaches At zero, the driving signal 3366 is changed from a logic high level to a logic low level.

根據一些實施例，在慢接通方案中，如果二次側同步整流器(SR)控制器3308感測到電壓信號3362變得小於閾值電壓(例如，Vth)，則二次側同步整流器(SR)控制器3308感測電壓信號3362在等於 或長於預定時間段的持續時間內是否保持小於閾值電壓(例如，Vth)，並且如果電壓信號3362在等於或者長於預定時間段的持續時間內保持小於閾值電壓(例如，Vth)，則二次側同步整流器(SR)控制器3308將驅動信號3366從邏輯低位準變為邏輯高位準。例如，在二次側同步整流器(SR)控制器3308在慢接通方案中將驅動信號3366從邏輯低位準變為邏輯高位準之後，二次側同步整流器(SR)控制器3308將驅動信號3366保持在邏輯高位準，然後將驅動信號3366從邏輯高位準變回邏輯低位準。例如，在連續傳導模式(CCM)下，二次側同步整流器(SR)控制器3308預測驅動信號3366從邏輯高位準變回邏輯低位準的時間。在另一示例中，在斷續傳導模式(DCM)下，二次側同步整流器(SR)控制器3308在流過電晶體3310的源極端與電晶體3310的汲極端之間的電流的大小達到零時將驅動信號3366從邏輯高位準變為邏輯低位準。 According to some embodiments, in the slow-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V th ), the secondary-side synchronous rectifier (SR The controller 3308 senses whether the voltage signal 3362 remains less than a threshold voltage (eg, V th ) for a duration equal to or longer than a predetermined period of time, and if the voltage signal 3362 remains less than a duration equal to or longer than a predetermined period of time The threshold voltage (for example, V th ), the secondary-side synchronous rectifier (SR) controller 3308 changes the driving signal 3366 from a logic low level to a logic high level. For example, after the secondary-side synchronous rectifier (SR) controller 3308 changes the drive signal 3366 from a logic low level to a logic high level in the slow-on scheme, the secondary-side synchronous rectifier (SR) controller 3308 changes the drive signal 3366 Keep at the logic high level, and then change the drive signal 3366 from the logic high level to the logic low level. For example, in continuous conduction mode (CCM), the secondary-side synchronous rectifier (SR) controller 3308 predicts the time at which the drive signal 3366 will change from a logic high level to a logic low level. In another example, in the discontinuous conduction mode (DCM), the magnitude of the current between the secondary side synchronous rectifier (SR) controller 3308 between the source terminal of the transistor 3310 and the drain terminal of the transistor 3310 reaches At zero, the driving signal 3366 is changed from a logic high level to a logic low level.

根據某些實施例，用於二次側同步整流器(SR)控制器3308的默認接通方案是慢接通方案。在一個實施例中，如果一個或多個預定條件被滿足(例如，如第14圖、第15圖、和/或第16圖所示)，則用於二次側同步整流器(SR)控制器3308的接通方案從慢接通方案變為快接通方案。例如，在快接通方案中，如果二次側同步整流器(SR)控制器3308感測到電壓信號3362變得小於閾值電壓(例如，Vth)，則二次側同步整流器(SR)控制器3308無延時地生成接通電晶體3310的驅動信號3366。在另一示例中，如果在快接通方案中生成接通電晶體3310的驅動信號3366，則用於二次側同步整流器(SR)控制器3308的接通方案從快接通方案變回慢接通方案，並且保持作為默認接通方案的慢接通方案，直到回應於一個或多個預定條件被滿足(例如，如第14圖、第15圖、和/或第16圖所示)，用於二次側同步整流器(SR)控制器3308的接通方案從慢接通方案變為快接通方案。 According to some embodiments, the default on scheme for the secondary-side synchronous rectifier (SR) controller 3308 is a slow on scheme. In one embodiment, if one or more predetermined conditions are met (e.g., as shown in Figure 14, Figure 15, and / or Figure 16), it is used for a secondary-side synchronous rectifier (SR) controller The 3308 connection scheme changed from a slow connection scheme to a fast connection scheme. For example, in the fast-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V th ), the secondary-side synchronous rectifier (SR) controller 3308 generates a drive signal 3366 for turning on the transistor 3310 without delay. In another example, if the driving signal 3366 for turning on the transistor 3310 is generated in the fast-on scheme, the turning-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 becomes slower from the fast-on scheme Turn-on scheme, and maintain the slow-on scheme as the default turn-on scheme until one or more predetermined conditions are met (for example, as shown in FIG. 14, FIG. 15, and / or FIG. 16), The switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 is changed from a slow switching scheme to a fast switching scheme.

在另一實施例中，在慢接通方案中，如果二次側同步整流器(SR)控制器3308感測到電壓信號3362變得小於閾值電壓(例如， Vth)，則二次側同步整流器(SR)控制器3308進一步感測電壓信號3362是否至少在消抖持續時間(例如，400ns)內保持小於閾值電壓，如果電壓信號3362至少在消抖持續時間(例如，400ns)內保持小於閾值電壓，則二次側同步整流器(SR)控制器3308生成接通電晶體3310的驅動信號3366。例如，如果電壓信號3362沒有至少在消抖持續時間(例如，400ns)內保持小於閾值電壓(例如，Vth)，則二次側同步整流器(SR)控制器3308不生成接通電晶體3310的驅動信號3366。在另一示例中，不管在慢接通方案中是否生成接通電晶體3310的驅動信號3366，用於二次側同步整流器(SR)控制器3308的接通方案保持作為默認接通方案的慢接通方案，直到回應於一個或多個預定條件被滿足(例如，如第14圖、第15圖、和/或第16圖所示)，用於二次側同步整流器(SR)控制器3308的接通方案從慢接通方案變為快接通方案。在又一示例中，慢接通方案被用來濾出電壓信號3362的雜訊干擾。 In another embodiment, in the slow-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V th ), the secondary-side synchronous rectifier (SR) The controller 3308 further senses whether the voltage signal 3362 remains less than the threshold voltage for at least the debounce duration (for example, 400ns), and if the voltage signal 3362 remains less than the threshold voltage for at least the debounce duration (for example, 400ns) Then, the secondary-side synchronous rectifier (SR) controller 3308 generates a driving signal 3366 for turning on the transistor 3310. For example, if the voltage signal 3362 does not remain less than a threshold voltage (for example, V th ) for at least the debounce duration (for example, 400 ns), the secondary-side synchronous rectifier (SR) controller 3308 does not generate Driving signal 3366. In another example, regardless of whether the driving signal 3366 for turning on the transistor 3310 is generated in the slow-on scheme, the switching-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 remains slow as the default switching scheme. The scheme is switched on in response to one or more predetermined conditions being met (for example, as shown in FIG. 14, FIG. 15, and / or FIG. 16) for a secondary-side synchronous rectifier (SR) controller 3308 The connection scheme changed from a slow connection scheme to a fast connection scheme. In yet another example, a slow-on scheme is used to filter out noise interference from the voltage signal 3362.

根據一些實施例，當二次側同步整流器(SR)控制器3308上電時，接通方案在上電過程開始時被設置為作為其默認接通方案的慢接通方案。在一個實施例中，如果如第14圖中所示的一個或多個預定條件被滿足，則用於二次側同步整流器(SR)控制器3308的接通方案從慢接通方案變為快接通方案，然後在快接通方案中生成接通電晶體3310的驅動信號3366之後，用於二次側同步整流器(SR)控制器3308的接通方案從快接通方案變回作為其默認方案的慢接通方案。在另一實施例中，如果第15圖中所示的一個或多個預定條件被滿足，則用於二次側同步整流器(SR)控制器3308的接通方案從慢接通方案變為快接通方案，然後在快接通方案中生成接通電晶體3310的驅動信號3366之後，用於二次側同步整流器(SR)控制器3308的接通方案從快接通方案變回作為其默認方案的慢接通方案。在又一實施例中，如果如第16圖中所示的一個或多個預定條件被滿足時，用於二次側同步整流器(SR)控制器3308的接通方案從慢接通方案變為快接通方案，然後在快接通方案中生成接通電晶體 3310的驅動信號3366之後，用於二次側同步整流器(SR)控制器3308的接通方案從快接通方案變回作為其默認方案的慢接通方案。 According to some embodiments, when the secondary-side synchronous rectifier (SR) controller 3308 is powered on, the turn-on scheme is set at the beginning of the power-up process as a slow-on scheme as its default turn-on scheme. In one embodiment, if one or more predetermined conditions as shown in FIG. 14 are satisfied, the switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 is changed from a slow switching scheme to a fast switching scheme. After the switching-on scheme, and then generating the driving signal 3366 for turning on the transistor 3310 in the quick-switching scheme, the switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 is changed from the quick-switching scheme back to its default The scheme's slow-on scheme. In another embodiment, if one or more predetermined conditions shown in FIG. 15 are satisfied, the switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 is changed from a slow switching scheme to a fast switching scheme. After the switching-on scheme, and then generating the driving signal 3366 for turning on the transistor 3310 in the quick-switching scheme, the switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 is changed from the quick-switching scheme back to its default The scheme's slow-on scheme. In yet another embodiment, if one or more predetermined conditions as shown in FIG. 16 are satisfied, the switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 is changed from a slow switching scheme to Quick-on scheme, and then turn on the transistor in the quick-on scheme After the driving signal 3366 of 3310, the switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 is changed from the fast switching scheme to the slow switching scheme as its default scheme.

第14圖是根據本發明的一個實施例，示出如第13圖中所示的二次側同步整流器(SR)控制器3308的接通方案從慢接通方案變為快接通方案的一個或多個預定條件的簡化圖。該圖僅僅是示例，其不應該過度限制申請專利範圍。本領域普通技術人員將認識到很多變形、替代和修改。波形3432將驅動信號3332表示為時間函數，波形3462電壓信號3362表示為時間函數，波形3466將驅動信號3366表示為時間函數。 FIG. 14 is a diagram illustrating a switching scheme of the secondary-side synchronous rectifier (SR) controller 3308 shown in FIG. 13 from a slow-on scheme to a fast-on scheme according to an embodiment of the present invention. A simplified diagram of one or more predetermined conditions. This figure is only an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and modifications. Waveform 3432 represents the driving signal 3332 as a function of time, waveform 3462 voltage signal 3362 represents a function of time, and waveform 3466 represents the driving signal 3366 as function of time.

在一個實施例中，二次側同步整流器(SR)控制器3308感測到電壓信號3362在時刻t101處變得大於參考電壓3490(例如，Vref1)，在時刻t102之前保持大於參考電壓3490，並且在時刻t102處變得小於參考電壓3490(例如，Vref1)。例如，如果從時刻t101到時刻t102的持續時間(例如，TA)等於或者大於閾值持續時間Tth1，則用於二次側同步整流器(SR)控制器3308的接通方案從慢接通方案變為快接通方案。在另一示例中，閾值持續時間Tth1表示一次側控制系統的前沿消抖時間(例如，300ns)。 In one embodiment, the secondary-side synchronous rectifier (SR) controller 3308 senses the voltage signal at a 3362 t 101 3490 becomes greater than the reference voltage (e.g., V ref1) at time t at time 102 remains greater than the reference voltage before 3490 and becomes less than the reference voltage 3490 (for example, V ref1 ) at time t 102 . For example, if the duration (for example, T A ) from time t 101 to time t 102 is equal to or greater than the threshold duration T th1 , the turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 is connected slowly The communication scheme is changed to the quick connection scheme. In another example, the threshold duration T th1 represents the leading edge debounce time (eg, 300 ns) of the primary control system.

在另一實施例中，在快接通方案中，二次側同步整流器(SR)控制器3308感測到電壓信號3362在時刻t102處變得小於閾值電壓3480(例如，Vth)，二次側同步整流器(SR)控制器3308在時刻t102處將驅動信號3366從邏輯低位準變為邏輯高位準。例如，閾值電壓3480(例如，Vth)小於參考電壓3490(例如，Vref1)。在另一示例中，在驅動信號3366在快接通方案中在時刻t102處從邏輯低位準變為邏輯高位準之後，用於二次側同步整流器(SR)控制器3308的接通方案從快接通方案變回作為其默認方案的慢接通方案。 In another embodiment, in the fast-on scheme, the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 has become less than the threshold voltage 3480 (for example, V th ) at time t 102 , two The secondary-side synchronous rectifier (SR) controller 3308 changes the driving signal 3366 from a logic low level to a logic high level at time t 102 . For example, the threshold voltage 3480 (eg, V th ) is less than the reference voltage 3490 (eg, V ref1 ). In another example, after the driving signal 3366 is changed from a logic low level to a logic high level at time t 102 in the fast turn-on scheme, the turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 starts from The fast-on scheme changes back to the slow-on scheme as its default scheme.

在又一實施例中，在二次側同步整流器(SR)控制器3308在時刻t102處將驅動信號3366從邏輯低位準變為邏輯高位準之後，二次側同步整流器(SR)控制器3308將驅動信號3366保持在邏輯高位準， 然後將驅動信號3366從邏輯高位準變回邏輯低位準。例如，在連續傳導模式(CCM)下，二次側同步整流器(SR)控制器3308預測將驅動信號3366從邏輯高位準變回邏輯低位準的時間。在另一示例中，在斷續傳導模式(DCM)下，二次側同步整流器(SR)控制器3308在流過電晶體3310的源極端與電晶體3310的汲極端之間的電流的大小達到零時將驅動信號3366從邏輯高位準變回邏輯低位準。 In yet another embodiment, after the secondary-side synchronous rectifier (SR) controller 3308 changes the driving signal 3366 from a logic low level to a logic high level at time t 102 , the secondary-side synchronous rectifier (SR) controller 3308 The driving signal 3366 is maintained at a logic high level, and then the driving signal 3366 is changed from a logic high level to a logic low level. For example, in continuous conduction mode (CCM), the secondary-side synchronous rectifier (SR) controller 3308 predicts the time to change the drive signal 3366 from a logic high level to a logic low level. In another example, in the discontinuous conduction mode (DCM), the magnitude of the current between the secondary side synchronous rectifier (SR) controller 3308 between the source terminal of the transistor 3310 and the drain terminal of the transistor 3310 reaches At zero, the driving signal 3366 is changed from a logic high level to a logic low level.

第15圖是根據本發明的另一實施例，如第13圖中所示的二次側同步整流器(SR)控制器3308的接通方案從慢接通方案變為快接通方案的一個或多個預定條件的簡化圖。該圖僅僅是示例，其不應該過度限制申請專利範圍。本領域普通技術人員將認識到很多變形、替代和修改。波形3532將驅動信號3332表示為時間函數，波形3562將電壓信號3362表示為時間函數，波形3566將驅動信號3366表示為時間函數。 FIG. 15 is one or more of the switching scheme of the secondary-side synchronous rectifier (SR) controller 3308 shown in FIG. 13 from the slow-switching scheme to the fast-switching scheme according to another embodiment of the present invention. Simplified graph of multiple predetermined conditions. This figure is only an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and modifications. Waveform 3532 represents the drive signal 3332 as a function of time, waveform 3562 represents the voltage signal 3362 as a function of time, and waveform 3566 represents the drive signal 3366 as a function of time.

在一個實施例中，二次側同步整流器(SR)控制器3308感測到電壓信號3362在時刻t111變得大於參考電壓3590(例如，Vref2)，在時刻t112之前保持大於參考電壓3590(例如，Vref2)，並且在時刻t112處變得小於參考電壓3590(例如，Vref2)。例如，參考電壓3590(例如，Vref2)小於參考電壓3490(例如，Vref1)。在另一示例中，如果從時刻t111到時刻t112的持續時間(例如，TJ)等於或大於閾值持續時間Tth2，則用於二次側同步整流器(SR)控制器3308的接通方案從慢接通方案變為快接通方案。在又一示例中，閾值持續時間Tth2比閾值持續時間Tth1更長。 In one embodiment, the secondary-side synchronous rectifier (SR) controller 3308 senses the voltage signal 3362 at time t 111 3590 becomes greater than the reference voltage (e.g., V ref2), before the time t 112 3590 remains greater than the reference voltage (For example, V ref2 ), and becomes smaller than the reference voltage 3590 (for example, V ref2 ) at time t 112 . For example, the reference voltage 3590 (eg, V ref2 ) is less than the reference voltage 3490 (eg, V ref1 ). In another example, if the duration (eg, T J ) from time t 111 to time t 112 is equal to or greater than the threshold duration Tth2, a turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 From a slow-on scheme to a fast-on scheme. In yet another example, the threshold duration Tth2 is longer than the threshold duration Tth1.

在另一實施例中，在快接通方案中，二次側同步整流器(SR)控制器3308感測到電壓信號3362在時刻t112處變得小於閾值電壓3480(例如，Vth)，二次側同步整流器(SR)控制器3308在時刻t112處將驅動信號3366從邏輯低位準變為邏輯高位準。例如，閾值電壓3480(例如，Vth)小於參考電壓3490(例如，Vref1)和參考電壓3590(例如，Vref2)。在另一示例中，在驅動信號3366在快接通方案中在時刻t112 處從邏輯低位準變為邏輯高位準之後，用於二次側同步整流器(SR)控制器3308的接通方案從快接通方案變回作為其默認方案的慢接通方案。 In another embodiment, in the fast turn-on scheme, the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than the threshold voltage 3480 (eg, V th ) at time t 112 , two The secondary-side synchronous rectifier (SR) controller 3308 changes the driving signal 3366 from a logic low level to a logic high level at time t 112 . For example, the threshold voltage 3480 (eg, Vth) is less than the reference voltage 3490 (eg, V ref1 ) and the reference voltage 3590 (eg, V ref2 ). In another example, after the driving signal 3366 changes from a logic low level to a logic high level at time t 112 in the fast turn-on scheme, the turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 starts from The fast-on scheme changes back to the slow-on scheme as its default scheme.

在又一實施例中，在二次側同步整流器(SR)控制器3308在時刻t112處將驅動信號3366從邏輯低位準比哪位元邏輯高位準之後，二次側同步整流器(SR)控制器3308將驅動信號3366保持在邏輯高位準，隨後將驅動信號3366從邏輯高位準變回邏輯低位準。例如，在連續傳導模式(CCM)下，二次側同步整流器(SR)控制器3308預測將驅動信號3366從邏輯高位準變回邏輯低位準的時間。在另一示例中，在斷續傳導模式(DCM)下，二次側同步整流器(SR)控制器3308在流過電晶體3310的源極端與電晶體3310的汲極端之間的電流的大小達到零時將驅動信號3366從邏輯高位準變回邏輯低位準。 In yet another embodiment, after the secondary-side synchronous rectifier (SR) controller 3308 drives the driving signal 3366 from a logic low level to a logic high level at time t 112 , the secondary-side synchronous rectifier (SR) controls The driver 3308 maintains the driving signal 3366 at a logic high level, and then changes the driving signal 3366 from a logic high level to a logic low level. For example, in continuous conduction mode (CCM), the secondary-side synchronous rectifier (SR) controller 3308 predicts the time to change the drive signal 3366 from a logic high level to a logic low level. In another example, in the discontinuous conduction mode (DCM), the magnitude of the current between the secondary side synchronous rectifier (SR) controller 3308 between the source terminal of the transistor 3310 and the drain terminal of the transistor 3310 reaches At zero, the driving signal 3366 is changed from a logic high level to a logic low level.

根據一個實施例，二次側同步整流器(SR)控制器3308感測到電壓信號3362在時刻t113處變得大於參考電壓3590(例如，Vref2)，在時刻t114之前保持大於參考電壓3590(例如，Vref2)，並且在時刻t114處變得小於參考電壓3590(例如，Vref2)。例如，如果從時刻t113到時刻t114的持續時間(例如，TK)小於閾值持續時間Tth2，則用於二次側同步整流器(SR)控制器3308的接通方案保持慢接通方案。 According to one embodiment, the secondary-side synchronous rectifier (SR) controller 3308 senses the voltage signal becomes at a time t 113 3362 3590 than the reference voltage (e.g., V ref2), the time t is greater than the reference voltage 114 remains before 3590 (For example, V ref2 ), and becomes smaller than the reference voltage 3590 (for example, V ref2 ) at time t 114 . For example, if the duration (for example, T K ) from time t 113 to time t 114 is less than the threshold duration T th2 , the turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 maintains a slow turn-on scheme .

根據另一實施例，在慢接通方案中，二次側同步整流器(SR)控制器3308感測到電壓信號3362在時刻t115處變得小於閾值電壓3480(例如，Vth)，二次側同步整流器(SR)控制器3308在時刻115處不將驅動信號3366從邏輯低位準變為邏輯高位準。例如，在慢接通方案中，二次側同步整流器(SR)控制器3308確定電壓信號3362是否在等於或大於預定時間段(例如，Ts)的持續時間內保持小於閾值電壓3480(例如，Vth)。在另一示例中，預定時間段(例如，Ts)大於零，閾值持續時間Tth1大於零，並且閾值持續時間Tth2大於零。在又一示例中，如第15圖中所示，二次側同步整流器(SR)控制器3308感測到電壓信號3362在時刻t116處變得大於閾值電壓3480(例如，Vth)，並且確定從時刻t115到t116 的持續時間比預定時間段(例如，Ts)短，二次側同步整流器(SR)控制器3308將驅動信號3366保持在邏輯低位準。 According to another embodiment, in the slow-on scheme, the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than the threshold voltage 3480 (eg, V th ) at time t 115 , and the secondary The side synchronous rectifier (SR) controller 3308 does not change the driving signal 3366 from a logic low level to a logic high level at time 115. For example, in the slow-on scheme, the secondary-side synchronous rectifier (SR) controller 3308 determines whether the voltage signal 3362 remains less than a threshold voltage 3480 (for example, for a duration equal to or greater than a predetermined time period (for example, T s ) V th ). In another example, the predetermined time period (eg, T s ) is greater than zero, the threshold duration T th1 is greater than zero, and the threshold duration T th2 is greater than zero. In yet another example, as shown in FIG. 15, the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 has become greater than the threshold voltage 3480 (for example, V th ) at time t 116 , and It is determined that the duration from time t 115 to t 116 is shorter than a predetermined time period (for example, T s ), and the secondary-side synchronous rectifier (SR) controller 3308 maintains the driving signal 3366 at a logic low level.

如前所述以及在這裡進一步強調的，第15圖僅僅是示例，其不應該過度限制申請專利範圍。本領域普通技術人員將認識到很多變形、替代、和修改。例如，二次側同步整流器(SR)控制器3308感測到電壓信號3362在時刻t111處變得小於參考電壓3490(例如，Vref1)但是大於參考電壓3590(例如，Vref2)，在時刻t112之前保持小於參考電壓3490(例如，Vref1)但是大於參考電壓3590(例如，Vref2)，並且在時刻t112處變得小於參考電壓3590(例如，Vref2)。在另一示例中，如果從時刻t111到時刻t112的持續時間(例如，TJ)等於或大於閾值持續時間Tth2，則用於二次側同步整流器(SR)控制器3308的接通方案從慢接通方案變為快接通方案。 As mentioned earlier and further emphasized here, Figure 15 is merely an example, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. For example, the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes smaller than the reference voltage 3490 (for example, V ref1 ) but greater than the reference voltage 3590 (for example, V ref2 ) at time t 111 at time t Before t 112, it remains less than the reference voltage 3490 (eg, V ref1 ) but is greater than the reference voltage 3590 (eg, V ref2 ), and becomes less than the reference voltage 3590 (eg, V ref2 ) at time t 112 . In another example, if the duration (for example, T J ) from time t 111 to time t 112 is equal to or greater than the threshold duration T th2 , for the turn-on of the secondary-side synchronous rectifier (SR) controller 3308 The scheme changed from a slow-on scheme to a fast-on scheme.

第16圖是根據本發明的一些實施例，示出了如第13圖中所示的二次側同步整流器(SR)控制器3308確定接通方案的方法的簡化圖。該圖僅僅是示例，並且其不應該過度限制申請專利範圍。本領域普通技術人員將認識到很多變形、替代、和修改。方法3600包括用於確定接通方案為慢接通方案的過程3610，用於確定條件P是否滿足的過程3620，用於確定條件Q是否滿足的過程3622，用於確定條件P或條件Q中的至少一個是否滿足的過程3630，以及用於確定接通方案為快接通方案的過程3640。 FIG. 16 is a simplified diagram illustrating a method of determining a turn-on scheme by a secondary-side synchronous rectifier (SR) controller 3308 as shown in FIG. 13 according to some embodiments of the present invention. This figure is only an example, and it should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. The method 3600 includes a process 3610 for determining that the connection scheme is a slow connection scheme, a process 3620 for determining whether the condition P is satisfied, a process 3622 for determining whether the condition Q is satisfied, and a method for determining the condition P or the condition Q. At least one of the processes 3630 is satisfied, and the process 3640 for determining that the connection scheme is a fast connection scheme.

在過程3610，二次側同步整流器(SR)控制器3308確定接通方案為作為默認接通方案的慢接通方案。例如，當二次側同步整流器(SR)控制器3308上電時，接通方案在上電過程開始時是作為其默認接通方案的慢接通方案。 At process 3610, the secondary-side synchronous rectifier (SR) controller 3308 determines the turn-on scheme as a slow-on scheme as a default turn-on scheme. For example, when the secondary-side synchronous rectifier (SR) controller 3308 is powered on, the turn-on scheme is a slow turn-on scheme as its default turn-on scheme at the beginning of the power-up process.

在過程3620，確定條件P是否滿足。例如，條件P是電壓信號3362變得大於參考電壓3490(例如，Vref1)，並且在等於或大於閾值持續時間Tth1的持續時間(例如，TA)內保持大於參考電壓3490(例 如，Vref1)。在另一示例中，如果電壓信號3362變得大於參考電壓3490(例如，Vref1)並且在等於或大於閾值持續時間Tth1的持續時間(例如，TA)內保持大於參考電壓3490(例如，Vref1)，則確定滿足條件P。 In process 3620, it is determined whether the condition P is satisfied. For example, the condition P is that the voltage signal 3362 becomes greater than the reference voltage 3490 (for example, V ref1 ), and remains greater than the reference voltage 3490 (for example, V for a duration equal to or greater than the threshold duration T th1 (for example, T A )). ref1 ). In another example, if the voltage signal 3362 becomes greater than the reference voltage 3490 (eg, V ref1 ) and remains greater than the reference voltage 3490 (eg, T A ) for a duration equal to or greater than the threshold duration T th1 (eg, T A ) V ref1 ), it is determined that the condition P is satisfied.

在過程3622，確定條件Q是否滿足。例如，條件Q是電壓信號3362變得大於參考電壓3590(例如，Vref2)，並且在等於或大於閾值持續時間Tth2的持續時間(例如，TJ)內保持大於參考電壓3590(例如，Vref2)。在另一示例中，如果電壓信號3362變得大於參考電壓3590(例如，)並且在等於或大於閾值持續時間Tth2的持續時間(例如，TJ)內保持大於參考電壓3590(例如，Vref2)，則確定滿足條件Q。在又一示例中，參考電壓3590(例如，Vref2)小於參考電壓3490(例如，Vref1)，並且閾值持續時間Tth2比閾值持續時間Tth1長。 In process 3622, it is determined whether the condition Q is satisfied. For example, the condition Q is that the voltage signal 3362 becomes greater than the reference voltage 3590 (for example, V ref2 ) and remains greater than the reference voltage 3590 (for example, V for a duration equal to or greater than the threshold duration T th2 (for example, T J ) ref2 ). In another example, if the voltage signal 3362 becomes greater than the reference voltage 3590 (e.g.,) and equal to or greater than the duration threshold duration T th2 (e.g., T J) 3590 remains greater than the reference voltage (e.g., V ref2 ), It is determined that the condition Q is satisfied. In yet another example, the reference voltage 3590 (eg, V ref2 ) is less than the reference voltage 3490 (eg, V ref1 ), and the threshold duration T th2 is longer than the threshold duration T th1 .

在過程3630，確定條件P或條件Q中的至少一個滿足。例如，如果條件P滿足，則條件P或條件Q中的至少一個滿足。在另一示例中，如果條件Q滿足，則條件P或條件Q中的至少一個滿足。在又一示例中，如果條件P和條件Q滿足，則條件P或條件Q中的至少一個滿足。 At process 3630, it is determined that at least one of condition P or condition Q is satisfied. For example, if the condition P is satisfied, at least one of the condition P or the condition Q is satisfied. In another example, if the condition Q is satisfied, at least one of the condition P or the condition Q is satisfied. In yet another example, if the condition P and the condition Q are satisfied, at least one of the condition P or the condition Q is satisfied.

根據一個實施例，如果條件P和條件Q都不滿足，則過程3610被執行，使得二次側同步整流器(SR)控制器3308的接通方案保持作為默認接通方案的慢接通方案。根據另一實施例，如果條件P或條件Q中的至少一個滿足，則過程3640被執行。 According to one embodiment, if neither the condition P nor the condition Q is satisfied, the process 3610 is executed so that the turn-on scheme of the secondary-side synchronous rectifier (SR) controller 3308 remains as the slow-on scheme of the default turn-on scheme. According to another embodiment, if at least one of the condition P or the condition Q is satisfied, the process 3640 is performed.

在過程3640，二次側同步整流器(SR)控制器3308確定接通方案為快接通方案。例如，用於二次側同步整流器(SR)控制器3308的接通方案從慢接通方案變為快接通方案。 At process 3640, the secondary-side synchronous rectifier (SR) controller 3308 determines that the turn-on scheme is a fast turn-on scheme. For example, the turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 changes from a slow-on scheme to a fast-on scheme.

在一個實施例中，在接通方案下，如果二次側同步整流器(SR)控制器3308感測到電壓信號3362變得小於閾值電壓(例如，Vth)，則二次側同步整流器(SR)控制器3308進一步感測電壓信號3362是否至少在消抖持續時間期間(例如，400ns)保持小於閾值電壓，如果電壓信號3362至少在消抖持續時間期間(例如，400ns)保持小於閾值電 壓，則二次側同步整流器(SR)控制器3308生成接通電晶體3310的驅動信號3366。例如，如果電壓信號3362沒有至少在消抖持續時間(例如，400ns)期間保持小於閾值電壓(例如，Vth)，則二次側同步整流器(SR)控制器3308不生成接通電晶體3310的驅動信號3366。在另一示例中，不管在慢接通方案下是否生成接通電晶體3310的驅動信號3366，用於二次側同步整流器(SR)控制器3308的接通方案保持為作為默認接通方案的慢接通方案，如過程3610所示。 In one embodiment, under the turn-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V th ), the secondary-side synchronous rectifier (SR The controller 3308 further senses whether the voltage signal 3362 remains less than the threshold voltage at least during the debounce duration (eg, 400ns), and if the voltage signal 3362 remains less than the threshold voltage at least during the debounce duration (eg, 400ns), then The secondary-side synchronous rectifier (SR) controller 3308 generates a driving signal 3366 that turns on the transistor 3310. For example, if the voltage signal 3362 does not remain less than a threshold voltage (for example, Vth) for at least the duration of the debounce duration (for example, 400ns), the secondary-side synchronous rectifier (SR) controller 3308 does not generate a drive to turn on the transistor 3310 Signal 3366. In another example, regardless of whether the driving signal 3366 for turning on the transistor 3310 is generated under the slow-on scheme, the switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 remains as the default switching scheme A slow-on scheme, as shown in process 3610.

在另一實施例中，在快接通方案下，如果二次側同步整流器(SR)控制器3308感測到電壓信號3362變得小於閾值電壓(例如，Vth)，則二次側同步整流器(SR)控制器3308無時延地生成接通電晶體3310的驅動信號3366。在另一示例中，在快接通方案下生成接通電晶體3310的驅動信號3366之後，用於二次側同步整流器(SR)控制器3308的接通方案從快接通方案變回慢接通方案，如過程3610所示。 In another embodiment, under the fast-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, Vth), the secondary-side synchronous rectifier ( (SR) The controller 3308 generates a drive signal 3366 for turning on the transistor 3310 without delay. In another example, after the driving signal 3366 for turning on the transistor 3310 is generated under the fast-on scheme, the switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 is changed from the fast-on scheme to the slow-on scheme. Communication scheme, as shown in process 3610.

如上面討論的和這裡進一步強調的，第16圖僅僅是示例，其不應該過度限制申請專利範圍。本領域普通技術人員將認識到很多變形、替代和修改。例如，條件P是電壓信號3362變得等於或大於參考電壓3490(例如，Vref1)並且在等於或大於閾值持續時間Tth1的持續時間(例如，TA)內保持等於或大於參考電壓3490(例如，Vref1)，條件Q是電壓信號3362變得等於或大於參考電壓3590(例如，Vref2)並且在等於或大於閾值持續時間Tth2的持續時間(例如，TJ)內保持等於或大於參考電壓3590(例如，Vref2)。在另一示例中，條件P是參考電壓3362變得等於或大於參考電壓3490(例如，Vref1)，並且在大於閾值持續時間Tth1的持續時間(例如，TA)內保持等於或大於參考電壓3490(例如，Vref1)，條件Q是電壓信號3362變得等於或大於參考電壓3590(例如，Vref2)，並且在大於閾值持續時間Tth2的持續時間(例如，TJ)內保持等於或大於參考電壓3590(例如，Vref2)。在又一示例中，條件P是參考電壓3362變得大於參考電壓3490(例如，Vref1)，並且在大於閾值持續時 間Tth1的持續時間(例如，TA)內保持大於參考電壓3490(例如，Vref1)，條件Q是電壓信號3362變得大於參考電壓3590(例如，Vref2)，並且在大於閾值持續時間Tth2的持續時間(例如，TJ)內保持大於參考電壓3590(例如，Vref2)。 As discussed above and further emphasized here, Figure 16 is merely an example, which should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and modifications. For example, the condition P is that the voltage signal 3362 becomes equal to or greater than the reference voltage 3490 (for example, V ref1 ) and remains equal to or greater than the reference voltage 3490 (for example, T A ) for a duration equal to or greater than the threshold duration T th1 (for example, T A ) For example, V ref1 ), the condition Q is that the voltage signal 3362 becomes equal to or greater than the reference voltage 3590 (eg, V ref2 ) and remains equal to or greater than a duration equal to or greater than the threshold duration T th2 (eg, T J ) Reference voltage 3590 (for example, V ref2 ). In another example, the condition P is that the reference voltage 3362 becomes equal to or greater than the reference voltage 3490 (for example, V ref1 ), and remains equal to or greater than the reference for a duration (for example, T A ) that is greater than the threshold duration T th1 . Voltage 3490 (eg, V ref1 ), condition Q is that the voltage signal 3362 becomes equal to or greater than the reference voltage 3590 (eg, V ref2 ), and remains equal to a duration (eg, T J ) that is greater than a threshold duration T th2 Or greater than the reference voltage 3590 (for example, V ref2 ). In yet another example, the condition P is that the reference voltage 3362 becomes greater than the reference voltage 3490 (eg, V ref1 ) and remains greater than the reference voltage 3490 (eg, T A ) for a duration (eg, T A ) that is greater than the threshold duration T th1 . , V ref1 ), condition Q is that the voltage signal 3362 becomes greater than the reference voltage 3590 (for example, V ref2 ), and remains greater than the reference voltage 3590 (for example, T J ) for a duration greater than the threshold duration T th2 (for example, T J ) V ref2 ).

第17圖是根據本發明的某些實施例，示出了如第13圖中所示的二次側同步整流器(SR)控制器3308確定接通方案的方法的簡化圖。該圖僅僅是示例，並且其不應該過度限制申請專利範圍。本領域普通技術人員將認識到很多變形、替代、和修改。方法3600包括用於確定接通方案為慢接通方案的過程3710，用於確定電壓信號3362是否變得大於參考電壓3490(例如，Vref1)的過程3720，用於確定電壓信號3362是否在等於或大於閾值持續時間Tth1的持續時間內保持大於參考電壓3490(例如，Vref1)的過程3721，用於確定電壓信號3362是否變的大於參考電壓3590(例如，Vref2)的過程3722，用於確定電壓信號3362是否在等於或大於閾值持續時間Tth2的持續時間內保持大於參考電壓3590(例如，Vref2)的過程3723，以及用於確定接通方案為快接通方案的過程3740。 FIG. 17 is a simplified diagram illustrating a method of determining a turn-on scheme by a secondary-side synchronous rectifier (SR) controller 3308 as shown in FIG. 13 according to some embodiments of the present invention. This figure is only an example, and it should not unduly limit the scope of patent applications. Those of ordinary skill in the art will recognize many variations, substitutions, and alterations. The method 3600 includes a process 3710 for determining that the turn-on scheme is a slow-on scheme, a process 3720 for determining whether the voltage signal 3362 becomes greater than a reference voltage 3490 (eg, V ref1 ), and a process for determining whether the voltage signal 3362 is Or a process 3721 that remains greater than a reference voltage 3490 (for example, V ref1 ) for a duration that is greater than a threshold duration T th1 , a process 3722 for determining whether the voltage signal 3362 becomes greater than a reference voltage 3590 (for example, V ref2 ), with A process 3723 for determining whether the voltage signal 3362 remains greater than a reference voltage 3590 (eg, V ref2 ) for a duration equal to or greater than the threshold duration T th2 , and a process 3740 for determining that the turn-on scheme is a quick-on scheme.

在過程3710，二次側同步整流器(SR)控制器3308確定接通方案為作為默認接通方案的慢接通方案。例如，當二次側同步整流器(SR)控制器3308上電時，接通方案在上電過程開始時是作為其默認接通方案的慢接通方案。 At process 3710, the secondary-side synchronous rectifier (SR) controller 3308 determines the turn-on scheme as a slow-on scheme as a default turn-on scheme. For example, when the secondary-side synchronous rectifier (SR) controller 3308 is powered on, the turn-on scheme is a slow turn-on scheme as its default turn-on scheme at the beginning of the power-up process.

在過程3720，確定電壓信號3362是否變得大於參考電壓3490(例如，Vref1)。例如，如果在過程3720確定電壓信號3362沒有變得大於參考電壓3490(例如，Vref1)，則過程3722被執行。在另一示例中，如果在過程3720確定電壓信號3362變得大於參考電壓3490(例如，Vref1)，則過程3721被執行。 At process 3720, it is determined whether the voltage signal 3362 becomes greater than a reference voltage 3490 (eg, V ref1 ). For example, if it is determined at process 3720 that the voltage signal 3362 has not become greater than the reference voltage 3490 (eg, V ref1 ), then the process 3722 is performed. In another example, if it is determined in process 3720 that the voltage signal 3362 becomes greater than the reference voltage 3490 (eg, V ref1 ), then the process 3721 is performed.

在過程3721，確定電壓信號3362是否在等於或大於閾值持續時間Tth1的持續時間內保持大於參考電壓3490(例如，Vref1)。例如，如果在過程3721確定電壓信號3362沒有在等於或大於閾值持續時間 Tth1的持續時間內保持大於參考電壓3490(例如，Vref1)，則過程3722被執行。在另一示例中，如果在過程3721確定電壓信號3362在等於或大於閾值持續時間Tth1的持續時間內保持大於參考電壓3490(例如，Vref1)，則過程3740被執行。 In process 3721, it is determined whether the voltage signal 3362 remains greater than the reference voltage 3490 (eg, V ref1 ) for a duration equal to or greater than the threshold duration T th1 . For example, if it is determined in process 3721 that the voltage signal 3362 has not remained greater than the reference voltage 3490 (eg, V ref1 ) for a duration equal to or greater than the threshold duration T th1 , then process 3722 is performed. In another example, if it is determined in process 3721 that the voltage signal 3362 remains greater than the reference voltage 3490 (eg, V ref1 ) for a duration equal to or greater than the threshold duration T th1 , the process 3740 is performed.

在過程3722，確定電壓信號3362是否變得大於參考電壓3590(例如，Vref2)。例如，參考電壓3590(例如，Vref2)小於參考電壓3490(例如，Vref1)在另一示例中，如果在過程3722確定電壓信號3362沒有變得大於參考電壓3590(例如，Vref2)，則過程3710被執行。在另一示例中，如果在過程3722確定電壓信號3362變得大於參考電壓3590(例如，Vref2)，則過程3723被執行。 At process 3722, it is determined whether the voltage signal 3362 has become greater than a reference voltage 3590 (eg, V ref2 ). For example, the reference voltage 3590 (eg, V ref2 ) is less than the reference voltage 3490 (eg, V ref1 ). In another example, if it is determined in process 3722 that the voltage signal 3362 has not become greater than the reference voltage 3590 (eg, V ref2 ), then Process 3710 is performed. In another example, if it is determined in process 3722 that the voltage signal 3362 becomes greater than a reference voltage 3590 (eg, V ref2 ), then process 3723 is performed.

在過程3723，確定電壓信號3362是否在等於或大於閾值持續時間Tth2的持續時間內保持大於參考電壓3590(例如，Vref2)。例如，如果在過程3723確定電壓信號3362沒有在等於或大於閾值持續時間Tth2的持續時間內保持大於參考電壓3590(例如，Vref2)，則過程3710被執行。在另一示例中，如果在過程3723確定電壓信號3362在等於或大於閾值持續時間Tth2的持續時間內保持大於參考電壓3590(例如，Vref2)，則過程3740被執行。 In process 3723, it is determined whether the voltage signal 3362 remains greater than the reference voltage 3590 (eg, V ref2 ) for a duration equal to or greater than the threshold duration T th2 . For example, if it is determined in process 3723 that the voltage signal 3362 has not remained greater than the reference voltage 3590 (eg, V ref2 ) for a duration equal to or greater than the threshold duration T th2 , then process 3710 is performed. In another example, if it is determined in process 3723 that the voltage signal 3362 remains greater than the reference voltage 3590 (eg, V ref2 ) for a duration equal to or greater than the threshold duration T th2 , the process 3740 is performed.

在過程3740，二次側同步整流器(SR)控制器3308確定接通方案為快接通方案。例如，用於二次側同步整流器(SR)控制器3308的接通方案從慢接通方案變為快接通方案。 At process 3740, the secondary-side synchronous rectifier (SR) controller 3308 determines that the turn-on scheme is a fast turn-on scheme. For example, the turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 changes from a slow-on scheme to a fast-on scheme.

在一個實施例中，在慢接通方案下，如果二次側同步整流器(SR)控制器3308感測到電壓信號3362變得小於閾值電壓(例如，Vth)，則二次側同步整流器(SR)控制器3308進一步感測電壓信號3362是否至少在消抖持續時間(例如，400ns)期間保持小於閾值電壓，如果電壓信號3362至少在消抖持續時間(例如，400ns)期間保持小於閾值電壓，則二次側同步整流器(SR)控制器3308生成接通電晶體3310的驅動信號3366。另外，如果電壓信號3362沒有至少在消抖持續時間(例如， 400ns)期間保持小於閾值電壓(例如，Vth)，則二次側同步整流器(SR)控制器3308不生成接通電晶體3310的驅動信號3366。在另一示例中，不管是否在慢接通方案下生成了接通電晶體3310的驅動信號3366，用於二次側同步整流器(SR)控制器3308的接通方案保持為作為默認接通方案的慢接通方案，如過程3610所示。 In one embodiment, under the slow-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V th ), the secondary-side synchronous rectifier ( (SR) The controller 3308 further senses whether the voltage signal 3362 remains less than the threshold voltage at least during the debounce duration (for example, 400ns), and if the voltage signal 3362 remains less than the threshold voltage for at least the debounce duration (for example, 400ns), Then, the secondary-side synchronous rectifier (SR) controller 3308 generates a driving signal 3366 for turning on the transistor 3310. In addition, if the voltage signal 3362 does not remain less than a threshold voltage (for example, V th ) at least during the debounce duration (for example, 400 ns), the secondary-side synchronous rectifier (SR) controller 3308 does not generate Driving signal 3366. In another example, regardless of whether a drive signal 3366 for turning on the transistor 3310 is generated under the slow turn-on scheme, the turn-on scheme for the secondary-side synchronous rectifier (SR) controller 3308 remains as the default turn-on scheme The slow-on scheme is shown in process 3610.

在另一實施例中，在快接通方案下，如果二次側同步整流器(SR)控制器3308感測到電壓信號3362變得小於閾值電壓(例如，Vth)，則二次側同步整流器(SR)控制器3308無延時地生成接通電晶體3310的驅動信號3366，而不管電壓信號3362是否至少在消抖持續時間(例如，400ns)期間保持小於閾值電壓(例如，Vth)。在另一示例中，在快接通方案下生成接通電晶體3310的驅動信號3366之後，用於二次側同步整流器(SR)控制器3308的接通方案從快接通方案變回慢接通方案，如過程3610所示。 In another embodiment, under the fast-on scheme, if the secondary-side synchronous rectifier (SR) controller 3308 senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V th ), the secondary-side synchronous rectifier The (SR) controller 3308 generates the drive signal 3366 that turns on the transistor 3310 without delay, regardless of whether the voltage signal 3362 remains less than a threshold voltage (for example, V th ) at least during the debounce duration (for example, 400 ns). In another example, after the driving signal 3366 for turning on the transistor 3310 is generated under the fast-on scheme, the switching scheme for the secondary-side synchronous rectifier (SR) controller 3308 is changed from the fast-on scheme to the slow-on scheme. Communication scheme, as shown in process 3610.

如上面討論的和這裡進一步強調的，第17圖僅僅是示例，其不應該過度限制申請專利範圍。本領域普通技術人員將認識到很多變形、替代和修改。例如，在過程3722，確定電壓信號3362是否變得小於參考電壓3490(例如，Vref1)但大於參考電壓3590(例如，Vref2)，如果在過程3722確定電壓信號3362變得小於參考電壓3490(例如，Vref1)但大於參考電壓3590(例如，Vref2)，則過程3723被執行。在另一示例中，在過程3723，確定電壓信號3362是否在等於或大於閾值持續時間Tth2的持續時間內保持小於參考電壓3490(例如，Vref1)但大於參考電壓3590(例如，Vref2)，如果在過程3723確定電壓信號3362在等於或大於閾值持續時間Tth2的持續時間內保持小於參考電壓3490(例如，Vref1)但大於參考電壓3590(例如，Vref2)，則過程3740被執行。 As discussed above and further emphasized here, Figure 17 is merely an example, which should not unduly limit the scope of patent application. Those of ordinary skill in the art will recognize many variations, substitutions, and modifications. For example, in process 3722, it is determined whether the voltage signal 3362 becomes less than the reference voltage 3490 (for example, V ref1 ) but is greater than the reference voltage 3590 (for example, V ref2 ). If it is determined in process 3722 that the voltage signal 3362 becomes less than the reference voltage 3490 ( For example, V ref1 ) but greater than the reference voltage 3590 (eg, V ref2 ), the process 3723 is performed. In another example, in process 3723, it is determined whether the voltage signal 3362 remains less than the reference voltage 3490 (e.g., V ref1 ) but greater than the reference voltage 3590 (e.g., V ref2 ) for a duration equal to or greater than the threshold duration Tth2, If it is determined in process 3723 that the voltage signal 3362 remains less than the reference voltage 3490 (eg, V ref1 ) but greater than the reference voltage 3590 (eg, V ref2 ) for a duration equal to or greater than the threshold duration T th2 , then the process 3740 is performed.

第18圖是根據本發明的一個實施例，示出了如第13圖中所示的電源變換系統3300的二次側同步整流器(SR)控制器3308的某些組件的簡化圖。該圖僅僅是示例，其不應該過度限制申請專利範圍。本 領域普通技術人員將認識到很多變形、替代和修改。二次側同步整流器(SR)控制器3308包括端子3390、3392、3394和3396。另外，二次側同步整流器(SR)控制器3308包括比較器3810和3816，消抖元件3820和3826，接通方案控制器3830，接通信號控制器3836，關斷信號控制器3840，驅動器3850，鉗位元器3860，參考電壓發生器3870，以及閾值持續時間發生器3876。 FIG. 18 is a simplified diagram showing certain components of the secondary-side synchronous rectifier (SR) controller 3308 of the power conversion system 3300 as shown in FIG. 13 according to an embodiment of the present invention. This figure is only an example, which should not unduly limit the scope of patent application. this Those of ordinary skill in the art will recognize many variations, substitutions, and modifications. The secondary-side synchronous rectifier (SR) controller 3308 includes terminals 3390, 3392, 3394, and 3396. In addition, the secondary-side synchronous rectifier (SR) controller 3308 includes comparators 3810 and 3816, debouncing elements 3820 and 3826, a solution controller 3830, a signal controller 3836, a signal controller 3840, and a driver 3850. , Clamp unit 3860, reference voltage generator 3870, and threshold duration generator 3876.

在一個實施例中，參考電壓發生器3870接收電壓信號3316，並且至少部分地基於電壓信號3316生成參考電壓3490(例如，Vref1)和參考電壓3590(例如，Vref2)。例如，分別根據以下等式確定參考電壓3490(例如，Vref1)和參考電壓3590(例如，Vref2)：V ref1=V ref_inｉ +α×V in (等式2) In one embodiment, the reference voltage generator 3870 receives the voltage signal 3316 and generates a reference voltage 3490 (eg, V ref1 ) and a reference voltage 3590 (eg, V ref2 ) based at least in part on the voltage signal 3316. For example, the reference voltage 3490 (for example, V ref1 ) and the reference voltage 3590 (for example, V ref2 ) are determined according to the following equations: V ref 1 = V ref_ini + α × V in (Equation 2)

V ref2=V ref_ini +β×V in (等式3) V ref 2 = V ref_ini + β × V in (Equation 3)

其中，Vref1表示參考電壓3490，Vref2表示參考電壓3590。此外，Vin表示電壓信號3316。Vref_ini表示預定電壓大小。另外，α表示預定常數，β表示另一預定常數。 Among them, V ref1 represents the reference voltage 3490, and V ref2 represents the reference voltage 3590. In addition, V in represents a voltage signal 3316. V ref_ini represents a predetermined voltage magnitude. In addition, α represents a predetermined constant, and β represents another predetermined constant.

在另一示例中，參考電壓3490(例如，Vref1)比參考電壓3590(例如，Vref2)大。在另一示例中，等式2中的預定常數α大於零，等式3中的預定常數β大於零，並且等式2中的預定常數α大於等式3中的預定常數β。在又一示例中，參考電壓3490(例如，Vref1)隨著電壓信號3316(例如，Vin)線性增大，並且參考電壓3590(例如，Vref2)隨著電壓信號3316(例如，Vin)線性增大。 In another example, the reference voltage 3490 (eg, V ref1 ) is greater than the reference voltage 3590 (eg, V ref2 ). In another example, the predetermined constant α in Equation 2 is greater than zero, the predetermined constant β in Equation 3 is greater than zero, and the predetermined constant α in Equation 2 is greater than the predetermined constant β in Equation 3. In yet another example, the reference voltage 3490 (eg, V ref1 ) increases linearly with the voltage signal 3316 (eg, V in ), and the reference voltage 3590 (eg, V ref2 ) increases with the voltage signal 3316 (eg, V in ) Increases linearly.

在另一實施例中，閾值持續時間發生器3876接收電壓信號3316，並且至少部分地基於電壓信號3316生成表示閾值時間段Tth1的信號3874和表示閾值時間段Tth2的信號3878。例如，分別根據以下等式確定閾值持續時間Tth1和閾值持續時間Tth2：T th1=T th_ini +γ×V in (等式4) In another embodiment, the duration of the threshold voltage generator 3876 receives signal 3316, and 3316 at least in part generated based on the voltage signal representing a threshold time period T th1 and the signal 3874 represents the threshold time period T th2 signal 3878. For example, the threshold duration Tth1 and the threshold duration T th2 are respectively determined according to the following equations: T th 1 = T th_ini + γ × V in (Equation 4)

T th2=T th_ini +δ×V in (等式5) T th 2 = T th_ini + δ × V in (Equation 5)

其中，Tth1表示閾值持續時間Tth1，Tth2表示閾值持續時間Tth2。另外，Vin表示電壓信號3316。Tth_ini表示預定電壓大小。此外，γ表示預定常數，δ表示另一預定常數。在另一示例中，閾值持續時間Tth2比閾值持續時間Tth1長。在又一示例中，參考電壓3590(例如，Vref2)小於參考電壓3490(例如，Vref1)，並且閾值持續時間Tth2比閾值持續時間Tth1長。 T th1 represents the threshold duration Tth1, and Tth2 represents the threshold duration T th2 . In addition, V in represents a voltage signal 3316. T th_ini represents a predetermined voltage magnitude. In addition, γ represents a predetermined constant, and δ represents another predetermined constant. In another example, Tth2 threshold duration longer than the duration threshold value T th1. In yet another example, the reference voltage 3590 (eg, V ref2 ) is less than the reference voltage 3490 (eg, V ref1 ), and the threshold duration T th2 is longer than the threshold duration T th1 .

在又一示例中，等式4中的預定常數γ大於零，等式5中的預定常數δ大於零，並且等式4中的預定常數γ小於等式5中的預定常數δ。在又一示例中，閾值持續時間Tth1隨著電壓信號3316(例如，Vin)線性增大，並且閾值持續時間Tth2隨著電壓信號3316(例如，Vin)線性增大。 In yet another example, the predetermined constant γ in Equation 4 is greater than zero, the predetermined constant δ in Equation 5 is greater than zero, and the predetermined constant γ in Equation 4 is less than the predetermined constant δ in Equation 5. In yet another example, the threshold duration T th1 increases linearly with the voltage signal 3316 (eg, V in ), and the threshold duration T th2 increases linearly with the voltage signal 3316 (eg, V in ).

根據一個實施例，比較器3810接收電壓信號3362和參考電壓3590(例如，Vref2)，並且生成比較信號3812。例如，如果電壓信號3362變得大於參考電壓3590(例如，Vref2)，則比較信號3812從邏輯低位準變為邏輯高位準。在另一示例中，比較信號3812由消抖元件3820接收。根據另一實施例，消抖元件3820接收比較信號3812和表示閾值時間段Tth2的信號3878。例如，消抖元件3820確定電壓信號3362是否在等於或長於閾值持續時間Tth2的持續時間內保持大於參考電壓3590(例如，Vth2)(例如，比較信號3812是否保持處於邏輯高位準)。在另一示例中，消抖元件3820生成信號3822，該信號指示電壓信號3362是否在等於或長於閾值持續時間Tth2的持續時間內保持大於參考電壓3590(例如，Vref2)(例如，比較信號3812是否保持處於邏輯高位準)。 According to one embodiment, the comparator 3810 receives a voltage signal 3362 and a reference voltage 3590 (eg, V ref2 ), and generates a comparison signal 3812. For example, if the voltage signal 3362 becomes greater than the reference voltage 3590 (eg, V ref2 ), the comparison signal 3812 changes from a logic low level to a logic high level. In another example, the comparison signal 3812 is received by a debouncer element 3820. According to another embodiment, the debouncer element 3820 receives a comparison signal 3812 and a signal 3878 representing a threshold time period Tth2 . For example, the debounce element 3820 determines whether the voltage signal 3362 remains greater than the reference voltage 3590 (eg, V th2 ) for a duration equal to or longer than the threshold duration T th2 (eg, whether the comparison signal 3812 remains at a logic high level). In another example, the debounce element 3820 generates a signal 3822 that indicates whether the voltage signal 3362 remains greater than the reference voltage 3590 (eg, V ref2 ) for a duration equal to or longer than the threshold duration T th2 (eg, a comparison signal 3812 remains at a logic high level).

根據另一實施例，比較器3816接收電壓信號3362和參考電壓3490(例如，Vref1)，並且生成比較信號3818。例如，如果電壓信號3362變得大於參考電壓3490(例如，Vref1)，則比較信號3818從邏輯低位準變為邏輯高位準。在另一示例中，比較信號3818由消抖元件3826接收。根據另一實施例，消抖元件3826接收比較信號3818和表示閾值時 間段Tth1的信號3874。例如，消抖元件3826確定電壓信號3362是否在等於或長於閾值持續時間Tth1的持續時間內保持大於參考電壓3490(例如，Vref1)(例如，比較信號3818是否保持處於邏輯高位準)。在另一示例中，消抖元件3826生成信號3828，該信號指示電壓信號3362是否在等於或者長於閾值持續時間Tth1的持續時間內保持大於參考電壓3490(例如，Vref1)(例如，比較信號3818是否保持處於邏輯高位準)。 According to another embodiment, the comparator 3816 receives the voltage signal 3362 and a reference voltage 3490 (eg, V ref1 ), and generates a comparison signal 3818. For example, if the voltage signal 3362 becomes greater than the reference voltage 3490 (eg, V ref1 ), the comparison signal 3818 changes from a logic low level to a logic high level. In another example, the comparison signal 3818 is received by a debounce element 3826. According to another embodiment, the debouncer element 3826 receives the comparison signal 3818 and a signal 3874 representing a threshold time period T th1 . For example, the debounce element 3826 determines whether the voltage signal 3362 remains greater than the reference voltage 3490 (eg, V ref1 ) for a duration equal to or longer than the threshold duration T th1 (eg, whether the comparison signal 3818 remains at a logic high level). In another example, the debounce element 3826 generates a signal 3828 that indicates whether the voltage signal 3362 remains greater than the reference voltage 3490 (eg, V ref1 ) (eg, a comparison signal) for a duration equal to or longer than the threshold duration T th1 . 3818 remains at a logic high level).

在另一實施例中，接通方案控制器3830接收信號3822和3828，並且作為回應，生成指示接通方案是快接通方案還是慢接通方案的信號3832。例如，如果信號3822指示電壓信號3362在等於或者長於閾值持續時間Tth2的持續時間內保持大於參考電壓3590(例如，Vref2)，和/或信號3828指示電壓信號3362在等於或者長於閾值持續時間Tth1的持續時間內保持大於參考電壓3490(例如，Vref1)，則接通方案控制器3830確定接通方案為快接通方案並且生成指示接通方案為快接通方案的信號3832。在另一示例中，如果信號3822不指示電壓信號3362在等於或者長於閾值持續時間Tth2的持續時間內保持大於參考電壓3590(例如，Vref2)，並且信號3828不指示電壓信號3362在等於或者長於閾值持續時間Tth1的持續時間內保持大於參考電壓3490(例如，Vref1)，則接通方案控制器3830確定接通方案為慢接通方案並且生成指示接通方案為慢接通方案的信號3832。 In another embodiment, the connection plan controller 3830 receives the signals 3822 and 3828 and, in response, generates a signal 3832 indicating whether the connection plan is a fast connection plan or a slow connection plan. For example, if the signal 3822 indicates that the voltage signal 3362 remains greater than the reference voltage 3590 (eg, V ref2 ) for a duration equal to or longer than the threshold duration T th2 , and / or the signal 3828 indicates that the voltage signal 3362 is equal to or longer than the threshold duration The duration of Tth1 remains greater than the reference voltage 3490 (for example, V ref1 ), then the connection plan controller 3830 determines that the connection plan is a fast-on plan and generates a signal 3832 indicating that the connection plan is a fast-on plan. In another example, if the signal 3822 does not indicate that the voltage signal 3362 remains greater than the reference voltage 3590 (eg, V ref2 ) for a duration equal to or longer than the threshold duration T th2 , and the signal 3828 does not indicate that the voltage signal 3362 is equal to or The duration longer than the threshold duration Tth1 remains greater than the reference voltage 3490 (for example, V ref1 ), then the connection scheme controller 3830 determines that the connection scheme is a slow connection scheme and generates a signal indicating that the connection scheme is a slow connection scheme 3832.

在另一示例中，如第16圖中所示，如果條件P或條件Q中的至少一個條件被滿足，則接通方案控制器3830確定接通方案為快接通方案，並且生成指示接通方案為快接通方案的信號3832。在又一示例中，如第16圖中所示，如果條件P和條件Q均沒有滿足，則接通方案控制器3830確定接通方案為慢接通方案，並且生成指示接通方案為慢接通方案的信號3832。 In another example, as shown in FIG. 16, if at least one of the condition P or the condition Q is satisfied, the connection plan controller 3830 determines that the connection plan is a quick connection plan, and generates an indication that the connection is on. The scheme is the signal 3832 of the quick-connect scheme. In another example, as shown in FIG. 16, if neither the condition P nor the condition Q is satisfied, the connection plan controller 3830 determines that the connection plan is a slow connection plan, and generates an indication that the connection plan is a slow connection.通 programme signal 3832.

根據一些實施例，接通信號控制器接收信號3832和電壓信號3362，並且生成信號3838。在一個實施例中，如果信號3832指示接 通方案為快接通方案，則當接通信號控制器感測到電壓信號3362變得小於閾值電壓(例如，Vth)時，接通信號控制器無延時地輸出信號3838，信號3838如果被驅動器3850接收則指示驅動器3850生成接通電晶體3310(例如，MOSFET)的驅動信號3366。例如，驅動器3850接收信號3838，並且作為回應，生成接通電晶體3310(例如，MOSFET)的驅動信號3366。在另一實施例匯總，信號3838被接通方案控制器3830接收。例如，信號3838在被驅動器3850接收的情況下，指示驅動器3850生成接通電晶體3310(例如，MOSFET)的驅動信號3366，並且作為回應，接通方案控制器3830將接通方案從快接通方案變為慢接通方案，並且生成指示接通方案為慢接通方案的信號3832。 According to some embodiments, the on-signal controller receives a signal 3832 and a voltage signal 3362 and generates a signal 3838. In one embodiment, if the signal 3832 indicates that the turn-on scheme is a fast turn-on scheme, the turn-on signal controller is turned on when the turn-on signal controller senses that the voltage signal 3362 has become less than a threshold voltage (eg, V th ). The signal 3838 is output without delay. If the signal 3838 is received by the driver 3850, the driver 3850 instructs the driver 3850 to generate a driving signal 3366 that turns on the transistor 3310 (for example, a MOSFET). For example, the driver 3850 receives the signal 3838 and, in response, generates a driving signal 3366 that turns on the transistor 3310 (eg, a MOSFET). In another embodiment, the signal 3838 is received by the on-scheme controller 3830. For example, if the signal 3838 is received by the driver 3850, the driver 3850 instructs the driver 3850 to generate a driving signal 3366 for turning on the transistor 3310 (for example, a MOSFET), and in response, the switching scheme controller 3830 switches the switching scheme from the quick switching on. The scheme becomes a slow-on scheme, and a signal 3832 indicating that the on-scheme is a slow-on scheme is generated.

在又一實施例中，如果信號3832指示接通方案為快接通方案，則當接通信號控制器沒有感測到電壓信號3362變得小於閾值電壓(例如，Vth)時，接通信號控制器不輸出信號3838，信號3838如果被驅動器3850接收將指示驅動器3850生成接通鏡頭感3310(例如，MOSFET)的驅動信號3366。例如，驅動器3850接收信號3838，並且作為回應，不生成接通電晶體3310(例如，MOSFET)的驅動信號3366。在另一實施例中，信號3838被接通方案控制器3830接收。例如，信號3838在被驅動器3850接收的情況下，不指示驅動器3850生成接通電晶體3310(例如，MOSFET)的驅動信號3366，並且作為回應，接通方案控制器3830保持接通方案為快接通方案，並且生成指示接通方案為快接通方案的信號3832。 In yet another embodiment, if the signal 3832 indicates that the turn-on scheme is a fast turn-on scheme, when the turn-on signal controller does not sense that the voltage signal 3362 becomes less than a threshold voltage (eg, V th ), the turn-on signal The controller does not output a signal 3838. If the signal 3838 is received by the driver 3850, it will instruct the driver 3850 to generate a driving signal 3366 that turns on the lens sense 3310 (for example, a MOSFET). For example, the driver 3850 receives the signal 3838 and, in response, does not generate a driving signal 3366 that turns on the transistor 3310 (eg, a MOSFET). In another embodiment, the signal 3838 is received by the on-scheme controller 3830. For example, when the signal 3838 is received by the driver 3850, the driver 3850 does not instruct the driver 3850 to generate a driving signal 3366 for turning on the transistor 3310 (for example, a MOSFET), and in response, the switching scheme controller 3830 keeps the switching scheme as a fast connection. And the signal 3832 is generated to indicate that the connection scheme is a fast connection scheme.

在又一實施例中，如果信號3832指示接通方案為慢接通方案，則當接通信號控制器感測到電壓信號3362變得小於閾值電壓(例如，Vth)並且感測到電壓信號3362至少在消抖持續時間(例如，400ns)期間保持小於閾值電壓，則接通信號控制器輸出信號3838，信號3838在被驅動器3850接收的情況下指示驅動器3850生成接通電晶體3310(例如，MOSFET)的驅動信號3366。例如，驅動器3850接收信號3838，並 且作為回應，生成接通電晶體3310(例如，MOSFET)的驅動信號3366。在另一實施例中，信號3838被接通方案控制器3830接收，並且作為回應，保持接通方案為慢接通方案並且生成指示接通方案為慢接通方案的信號3832。 In yet another embodiment, if the signal 3832 indicates that the on scheme is a slow on scheme, when the on signal controller senses that the voltage signal 3362 becomes less than a threshold voltage (eg, V th ) and senses the voltage signal If 3362 remains less than the threshold voltage at least during the debounce duration (for example, 400ns), the on-signal controller outputs a signal 3838, and the signal 3838 instructs the driver 3850 to generate an on-transistor 3310 (for example, MOSFET) driving signal 3366. For example, the driver 3850 receives the signal 3838 and, in response, generates a driving signal 3366 that turns on the transistor 3310 (eg, a MOSFET). In another embodiment, the signal 3838 is received by the on-scheme controller 3830, and in response, the keep-on scheme is a slow-on scheme and a signal 3832 is generated indicating that the on-scheme is a slow-on scheme.

在又一實施例中，如果信號3832指示接通方案為慢接通方案，則當接通信號控制器沒有感測到電壓信號3362變得小於閾值電壓(例如，Vth)或者沒有感測到電壓信號3362至少在消抖持續時間(例如，400ns)期間保持小於閾值電壓，則接通信號控制器不輸出信號3838，信號3838在被驅動器3850接收的情況下指示驅動器3850生成接通電晶體3310(例如，MOSFET)的驅動信號3366。例如，驅動器3850接收信號3838，並且作為回應，不生成接通電晶體3310(例如，MOSFET)的驅動信號3366。在另一示例中，信號3838被接通方案控制器3830接收，作為回應，接通方案控制器3830保持接通方案為慢接通方案並且生成接通方案為慢接通方案的信號3832。 In yet another embodiment, if the signal 3832 indicates that the turn-on scheme is a slow-on scheme, when the on-signal controller does not sense that the voltage signal 3362 becomes less than a threshold voltage (eg, V th ) or does not sense it The voltage signal 3362 remains less than the threshold voltage at least during the debounce duration (for example, 400ns), then the on-signal controller does not output a signal 3838, and the signal 3838 instructs the driver 3850 to generate a switching transistor 3310 when it is received by the driver 3850 (Eg, MOSFET) drive signal 3366. For example, the driver 3850 receives the signal 3838 and, in response, does not generate a driving signal 3366 that turns on the transistor 3310 (eg, a MOSFET). In another example, the signal 3838 is received by the connection plan controller 3830. In response, the connection plan controller 3830 maintains the connection plan as a slow connection plan and generates a signal 3832 that the connection plan is a slow connection plan.

在又一實施例中，鉗位元器3860接收電壓信號3362。例如，電壓信號3362包括一個或多個高電壓毛刺。在另一示例中，鉗位器被用來鉗位元電壓信號3362，以保護二次側同步整流器(SR)控制器3308的一個或多個內部電路。 In yet another embodiment, the clamper 3860 receives the voltage signal 3362. For example, the voltage signal 3362 includes one or more high-voltage glitches. In another example, a clamp is used to clamp the element voltage signal 3362 to protect one or more internal circuits of the secondary-side synchronous rectifier (SR) controller 3308.

本發明的某些實施例提供了這樣的二次側同步整流器(SR)控制器，其選擇快接通方案或慢接通方案以便提供效率和可靠性之間的期望折衷。 Certain embodiments of the present invention provide such a secondary-side synchronous rectifier (SR) controller that selects a fast-on scheme or a slow-on scheme in order to provide a desired compromise between efficiency and reliability.

根據另一實施例，用於調節電源變換器的系統控制器包括第一控制器端子和第二控制器端子。系統控制器被配置為在第一控制器端子接收輸入信號，並且至少部分地基於輸入信號在第二控制器端子處生成驅動信號以接通或關斷電晶體，從而影響與電源變換器的二次繞組相關聯的電流。另外，系統控制器進一步被配置為確定輸入信號是否在等於或者長於第一預定持續時間的第一時段內保持大於第一閾值，並且回應於輸 入信號未被確定為在等於或者長於第一預定持續時間的第一時段內大於第一閾值，利用第一方案進行操作。另外，利用第一方案進行操作，系統控制器進一步被配置為確定輸入信號在等於或者長於第二預定持續時間的第二時段內保持小於第二閾值，並且回應於輸入信號在等於或者長於第二預定持續時間的第二時段內保持小於第二閾值，將第二控制器端子處的驅動信號從第一邏輯位準變為第二邏輯位準。第一預定持續時間大於零，第二預定持續時間大於零。例如，該系統控制器至少根據第13圖和/或第14圖實現。 According to another embodiment, a system controller for regulating a power converter includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a driving signal at a second controller terminal based on the input signal to turn the transistor on or off, thereby affecting the second The current associated with the secondary winding. In addition, the system controller is further configured to determine whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration, and is responsive to the input The incoming signal is not determined to be greater than a first threshold within a first period of time equal to or longer than a first predetermined duration, and the first scheme is used for operation. In addition, using the first scheme for operation, the system controller is further configured to determine that the input signal remains less than the second threshold for a second period equal to or longer than the second predetermined duration, and in response to the input signal is equal to or longer than the second threshold The second duration of the predetermined duration is kept smaller than the second threshold, and the driving signal at the second controller terminal is changed from the first logic level to the second logic level. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero. For example, the system controller is implemented according to at least FIG. 13 and / or FIG. 14.

根據又一實施例，用於調節電源變換器的系統控制器包括第一控制器端子和第二控制器端子。系統控制器被配置為在第一控制器端子接收輸入信號，並且至少部分地基於輸入信號在第二控制器端子處生成驅動信號以接通或關斷電晶體，從而影響與電源變換器的二次繞組相關聯的電流。另外，系統控制器進一步被配置為確定輸入信號是否在等於或者長於第一預定持續時間的第一時段內保持小於或者等於第一閾值且大於第二閾值，第二閾值小於第一閾值，並且回應於輸入信號未被確定為在等於或者長於第一預定持續時間的第一時段內保持等於或者小於第一閾值且大於第二閾值，利用第一方案進行操作。另外，利用第一方案進行操作，系統控制器進一步被配置為確定輸入信號是否在等於或者長於第二預定持續時間的第二時段內保持小於第三閾值，並且回應於輸入信號被確定為在等於或者長於第二預定持續時間的第二時段內保持小於第三閾值，將第二控制器端子處的驅動信號從第一邏輯位準變為第二邏輯位準。第一預定持續時間大於零，第二預定持續時間大於零。例如，系統控制器至少根據第13圖和/或第15圖實現。 According to yet another embodiment, a system controller for regulating a power converter includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a driving signal at a second controller terminal based on the input signal to turn the transistor on or off, thereby affecting the second The current associated with the secondary winding. In addition, the system controller is further configured to determine whether the input signal remains less than or equal to a first threshold value and greater than a second threshold value within a first period of time equal to or longer than the first predetermined duration, the second threshold value is less than the first threshold value, and responds When the input signal is not determined to remain equal to or smaller than the first threshold and greater than the second threshold within a first period equal to or longer than the first predetermined duration, the first scheme is used for operation. In addition, using the first scheme for operation, the system controller is further configured to determine whether the input signal remains less than a third threshold for a second period equal to or longer than the second predetermined duration, and in response to the input signal being determined to be equal to Alternatively, the driving signal at the terminal of the second controller is changed from the first logic level to the second logic level within a second period longer than the second predetermined duration. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero. For example, the system controller is implemented according to at least FIG. 13 and / or FIG. 15.

根據又一實施例，用於調節電源變換器的系統控制器包括第一控制器端子和第二控制器端子。系統控制器被配置為在第一控制器端子接收輸入信號，並且至少部分地基於輸入信號在第二控制器端子處生成驅動信號以接通或關斷電晶體，從而影響與電源變換器的二次繞組相關 聯的電流。另外，系統控制器進一步被配置為確定輸入信號是否在等於或者長於第一預定持續時間的第一時段內保持大於第一閾值，並且確定輸入信號是否在等於或者長於第二預定持續時間的第二時段內保持大於第二閾值。第二閾值比第一閾值小，第二預定持續時間比第一預定持續時間長。另外，系統控制器進一步被配置為，回應於輸入信號未被確定為在等於或者長於第一預定持續時間的第一時段內保持大於第一閾值並且輸入信號未被確定為在等於或者長於第二預定持續時間的第二時段內保持大於第二閾值，利用第一方案進行操作。另外，利用第一方案進行操作，系統控制器進一步被配置為確定輸入信號是否在等於或者長於第三預定持續時間的第三時段內保持小於第三閾值，並且回應於輸入信號被確定為在等於或者長於第三預定持續時間的第三時段內保持小於第三閾值，將第二控制器端子處的驅動信號從第一邏輯位準變為第二邏輯位準。第一預定持續時間大於零，第二預定持續時間大於零，並且第三預定持續時間大於零。例如，系統控制器至少根據第13圖、第16圖、第17圖、和/或第18圖實現。 According to yet another embodiment, a system controller for regulating a power converter includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a driving signal at a second controller terminal based on the input signal to turn the transistor on or off, thereby affecting the second Secondary winding related Associated current. In addition, the system controller is further configured to determine whether the input signal remains greater than a first threshold for a first period equal to or longer than the first predetermined duration, and determine whether the input signal is equal to or longer than a second predetermined duration It remains greater than the second threshold during the period. The second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration. In addition, the system controller is further configured to respond to the input signal not being determined to remain greater than the first threshold for a first period equal to or longer than the first predetermined duration and the input signal not determined to be equal to or longer than the second The second period of the predetermined duration is kept greater than the second threshold, and the first scheme is used for operation. In addition, using the first scheme for operation, the system controller is further configured to determine whether the input signal remains less than a third threshold for a third period equal to or longer than a third predetermined duration, and in response to the input signal being determined to be equal to Alternatively, the driving signal at the terminal of the second controller is changed from the first logic level to the second logic level within a third period longer than the third predetermined duration. The first predetermined duration is greater than zero, the second predetermined duration is greater than zero, and the third predetermined duration is greater than zero. For example, the system controller is implemented based on at least Figure 13, Figure 16, Figure 17, and / or Figure 18.

根據又一實施例，用於調節電源變換器的系統控制器包括第一控制器端子和第二控制器端子。系統控制器被配置為在第一控制器端子接收輸入信號，並且至少部分地基於輸入信號在第二控制器端子處生成驅動信號以接通或關斷電晶體，從而影響與電源變換器的二次繞組相關聯的電流。另外，系統控制器進一步被配置為確定輸入信號是否在等於或者長於第一預定持續時間的第一時段內保持大於第一閾值，並且確定輸入信號是否在等於或者長於第二預定持續時間的第二時段內保持大於第二閾值。另外，系統控制器進一步被配置為，回應於輸入信號未被確定為在等於或者長於第一預定持續時間的第一時段內保持大於第一閾值並且輸入信號未被確定為在等於或者長於第二預定持續時間的第二時段內保持大於第二閾值，利用第一方案進行操作。第二閾值小於第一閾值，並且第二預定持續時間長於第一預定持續時間。第一預定持續時間大於零，並且第二預定持續時間大於零。第一閾值在大小上隨著輸入信號改變，第二閾值在大 小上隨著輸入信號改變，例如，系統控制器至少根據第13圖、第16圖、第17圖、和/或第18圖實現。 According to yet another embodiment, a system controller for regulating a power converter includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a driving signal at a second controller terminal based on the input signal to turn the transistor on or off, thereby affecting the second The current associated with the secondary winding. In addition, the system controller is further configured to determine whether the input signal remains greater than a first threshold for a first period equal to or longer than the first predetermined duration, and determine whether the input signal is equal to or longer than a second predetermined duration It remains greater than the second threshold during the period. In addition, the system controller is further configured to respond to the input signal not being determined to remain greater than the first threshold for a first period equal to or longer than the first predetermined duration and the input signal not determined to be equal to or longer than the second The second period of the predetermined duration is kept greater than the second threshold, and the first scheme is used for operation. The second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero. The first threshold changes in size with the input signal, and the second threshold is large Xiao Shang changes with the input signal, for example, the system controller is implemented based on at least Figure 13, Figure 16, Figure 17, and / or Figure 18.

根據又一實施例，用於調節電源變換器的系統控制器包括第一控制器端子和第二控制器端子。系統控制器被配置為在第一控制器端子接收輸入信號，並且至少部分地基於輸入信號在第二控制器端子處生成驅動信號以接通或關斷電晶體，從而影響與電源變換器的二次繞組相關聯的電流。另外，系統控制器進一步被配置為確定輸入信號是否在等於或者長於第一預定持續時間的第一時段內保持大於第一閾值，並且確定輸入信號是否在等於或者長於第二持續時間的第二時段內保持大於第二閾值。另外，系統控制器進一步被配置為，回應於輸入信號未被確定為在等於或者長於第一預定持續時間的第一時段內保持大於第一閾值並且輸入信號未被確定為在等於或者長於第二預定持續時間的第二時段內保持大於第二閾值，利用第一方案進行操作。第二閾值小於第一閾值，並且第二預定持續時間長於第一預定持續時間。第一預定持續時間大於零，第二預定持續時間大於零，第一預定持續時間在大小上隨著輸入信號改變，並且第二預定持續時間在大小上隨著輸入信號改變。例如，系統控制器至少根據第13圖、第16圖、第17圖、和/或第18圖實現。 According to yet another embodiment, a system controller for regulating a power converter includes a first controller terminal and a second controller terminal. The system controller is configured to receive an input signal at a first controller terminal, and generate a driving signal at a second controller terminal based on the input signal to turn the transistor on or off, thereby affecting the second The current associated with the secondary winding. In addition, the system controller is further configured to determine whether the input signal remains greater than the first threshold for a first period equal to or longer than the first predetermined duration, and determine whether the input signal is for a second period equal to or longer than the second duration Is kept greater than the second threshold. In addition, the system controller is further configured to respond to the input signal not being determined to remain greater than the first threshold for a first period equal to or longer than the first predetermined duration and the input signal not determined to be equal to or longer than the second The second period of the predetermined duration is kept greater than the second threshold, and the first scheme is used for operation. The second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration. The first predetermined duration is greater than zero, the second predetermined duration is greater than zero, the first predetermined duration changes in size with the input signal, and the second predetermined duration changes in size with the input signal. For example, the system controller is implemented based on at least Figure 13, Figure 16, Figure 17, and / or Figure 18.

根據又一實施例，用於調節電源變換器的方法包括：接收輸入信號，處於與輸入信號相關聯的資訊，並且至少部分地基於輸入信號生成驅動信號以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流。處理與輸入信號相關聯的資訊包括：確定輸入信號是否在等於或者長於第一預定持續時間的第一時段內保持大於第一閾值；回應於輸入信號未被確定為在等於或者長於第一預定持續時間的第一時段內保持大於第一閾值，利用第一方案進行操作。至少部分地基於輸入信號生成驅動信號以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流包括：回應於利用第一方案進行操作，確定輸入信號是否在等於或者長於第二預定持續時間的第二時段內保持小於第二閾值；並且回應於輸入信號 被確定為在等於或者長於第二預定持續時間的第二時段內保持小於第二閾值，將驅動信號從第一邏輯位準變為第二邏輯位準。第一預定持續時間大於零，並且第二預定持續時間大於零。例如，該方法至少根據第13圖和/或第14圖實現。 According to yet another embodiment, a method for adjusting a power converter includes: receiving an input signal, in information associated with the input signal, and generating a drive signal based at least in part on the input signal to turn a transistor on or off to affect the Current associated with the secondary winding of the power converter. Processing the information associated with the input signal includes: determining whether the input signal remains greater than a first threshold for a first period of time equal to or longer than the first predetermined duration; in response to the input signal not being determined to be equal to or longer than the first predetermined duration The first period of time remains greater than the first threshold, and the first scheme is used for operation. Generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power converter includes: in response to operating with the first scheme, determining whether the input signal is equal to or longer than Remain less than a second threshold for a second period of a second predetermined duration; and in response to an input signal It is determined to remain less than a second threshold for a second period of time equal to or longer than the second predetermined duration to change the driving signal from the first logic level to the second logic level. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero. For example, the method is implemented according to at least FIG. 13 and / or FIG. 14.

根據又一實施例，用於調節電源變換器的方法包括：接收輸入信號，處於與輸入信號相關聯的資訊，並且至少部分地基於輸入信號生成驅動信號以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流。處理與輸入信號相關聯的資訊包括：確定輸入信號是否在等於或者長於第一預定持續時間的第一時段內保持小於或者等於第一閾值且大於第二閾值，第二閾值小於第一閾值；並且回應於輸入信號未被確定為在等於或者長於第一預定持續時間的第一時段內保持小於或者等於第一閾值且大於第二閾值，利用第一方案進行操作。至少部分地基於輸入信號生成驅動信號以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流包括：回應於利用第一方案進行操作，確定輸入信號是否在等於或者長於第二預定持續時間的第二時段內保持小於第三閾值；並且回應於輸入信號被確定為在等於或者長於第二預定持續時間的第二時段內保持小於第三閾值，將驅動信號從第一邏輯位準變為第二邏輯位準。第一預定持續時間大於零，並且第二預定持續時間大於零。例如，該方法至少根據第13圖和/或第15圖實現。 According to yet another embodiment, a method for adjusting a power converter includes: receiving an input signal, in information associated with the input signal, and generating a drive signal based at least in part on the input signal to turn a transistor on or off to affect the Current associated with the secondary winding of the power converter. Processing the information associated with the input signal includes: determining whether the input signal remains less than or equal to a first threshold and greater than a second threshold for a first period of time equal to or longer than a first predetermined duration, and the second threshold is less than the first threshold; and In response to the input signal not being determined to remain less than or equal to the first threshold and greater than the second threshold for a first period of time equal to or longer than the first predetermined duration, the first scheme is used for operation. Generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power converter includes: in response to operating with the first scheme, determining whether the input signal is equal to or longer than The driving signal is kept from the first threshold in the second period of the second predetermined duration to be less than the third threshold; and in response to the input signal being determined to remain less than the third threshold in the second period equal to or longer than the second predetermined duration The logic level becomes the second logic level. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero. For example, the method is implemented according to at least FIG. 13 and / or FIG. 15.

根據又一實施例，用於調節電源變換器的方法包括：接收輸入信號，處於與輸入信號相關聯的資訊，並且至少部分地基於輸入信號生成驅動信號以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流。處理與輸入信號相關聯的資訊包括：確定輸入信號是否在等於或者長於第一預定持續時間的第一時段內保持大於第一閾值；確定輸入信號在等於或者長於第二預定持續時間的第二時段內保持大於第二閾值，第二閾值小於第一閾值，第二預定持續時間長於第一預定持續時間；並且回應於輸入信號未被確定為在等於或者長於第一預定持續時間的第一時段 內保持大於第一閾值並且輸入信號未被確定為在等於或者長於第二預定持續時間的第二時段內保持大於第二閾值，利用第一方案進行操作。至少部分地基於輸入信號生成驅動信號以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流包括：回應於利用第一方案進行操作，確定輸入信號是否在等於或者長於第三預定持續時間的第三時段內保持小於第三閾值；並且回應於輸入信號被確定為在等於或者長於第三預定持續時間的第三時段內保持小於第三閾值，將驅動信號從第一邏輯位準變為第二邏輯位準。第一預定持續時間大於零，第二預定持續時間大於零，並且第三預定持續時間大於零。例如，該方法至少根據第13圖、第16圖、第17圖、和/或第18圖實現。 According to yet another embodiment, a method for adjusting a power converter includes: receiving an input signal, in information associated with the input signal, and generating a drive signal based at least in part on the input signal to turn a transistor on or off to affect the Current associated with the secondary winding of the power converter. Processing the information associated with the input signal includes: determining whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration; determining whether the input signal is in a second period equal to or longer than a second predetermined duration Is maintained greater than the second threshold, the second threshold is smaller than the first threshold, the second predetermined duration is longer than the first predetermined duration; and in response to the input signal not being determined to be in a first period equal to or longer than the first predetermined duration The internal retention is greater than the first threshold and the input signal is not determined to remain greater than the second threshold for a second period that is equal to or longer than the second predetermined duration, and is operated using the first scheme. Generating a driving signal based at least in part on the input signal to turn on or off the transistor to affect the current associated with the secondary winding of the power converter includes: in response to operating with the first scheme, determining whether the input signal is equal to or longer than The driving signal is kept from the first threshold in the third period of the third predetermined duration to be less than the third threshold; and in response to the input signal being determined to remain less than the third threshold in the third period of time equal to or longer than the third predetermined duration The logic level becomes the second logic level. The first predetermined duration is greater than zero, the second predetermined duration is greater than zero, and the third predetermined duration is greater than zero. For example, the method is implemented based on at least Figure 13, Figure 16, Figure 17, and / or Figure 18.

根據又一實施例，用於調節電源變換器的方法包括：接收輸入信號，處於與輸入信號相關聯的資訊，並且至少部分地基於輸入信號生成驅動信號以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流。處理與輸入信號相關聯的資訊包括：確定輸入信號是否在等於或者長於第一預定持續時間的第一時段內保持大於第一閾值；確定輸入信號在等於或者長於第二預定持續時間的第二時段內保持大於第二閾值；回應於輸入信號未被確定為在等於或者長於第一預定持續時間的第一時段內保持大於第一閾值並且輸入信號未被確定為在等於或者長於第二預定持續時間的第二時段內保持大於第二閾值，利用第一方案進行操作。第二閾值小於第一閾值，並且第二預定持續時間長於第一預定持續時間。第一預定持續時間大於零，第二預定持續時間大於零。第一閾值在大小上隨著輸入信號改變，並且第二閾值在大小上隨著輸入信號改變。例如，該方法至少根據第13圖、第16圖、第17圖、和/或第18圖實現。 According to yet another embodiment, a method for adjusting a power converter includes: receiving an input signal, in information associated with the input signal, and generating a drive signal based at least in part on the input signal to turn a transistor on or off to affect the Current associated with the secondary winding of the power converter. Processing the information associated with the input signal includes: determining whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration; determining whether the input signal is in a second period equal to or longer than a second predetermined duration Within the first threshold; in response to the input signal not being determined to remain greater than the first threshold for a first period equal to or longer than the first predetermined duration and the input signal not determined to be equal to or longer than the second predetermined duration The second period of time remains greater than the second threshold, and the first scheme is used for operation. The second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero. The first threshold changes in size with the input signal, and the second threshold changes in size with the input signal. For example, the method is implemented based on at least Figure 13, Figure 16, Figure 17, and / or Figure 18.

根據又一實施例，用於調節電源變換器的方法包括：接收輸入信號，處於與輸入信號相關聯的資訊，並且至少部分地基於輸入信號生成驅動信號以接通或關斷電晶體從而影響與電源變換器的二次繞組相關聯的電流。處理與輸入信號相關聯的資訊包括：確定輸入信號是否在等 於或者長於第一預定持續時間的第一時段內保持大於第一閾值；確定輸入信號在等於或者長於第二預定持續時間的第二時段內保持大於第二閾值；回應於輸入信號未被確定為在等於或者長於第一預定持續時間的第一時段內保持大於第一閾值並且輸入信號未被確定為在等於或者長於第二預定持續時間的第二時段內保持大於第二閾值，利用第一方案進行操作。第二閾值小於第一閾值，並且第二預定持續時間長於第一預定持續時間。第一預定持續時間大於零，第二預定持續時間大於零。第一預定持續時間在大小上隨著輸入信號改變，並且第二預定持續時間在大小上隨著輸入信號改變。例如，該方法至少根據第13圖、第16圖、第17圖、和/或第18圖實現。 According to yet another embodiment, a method for adjusting a power converter includes: receiving an input signal, in information associated with the input signal, and generating a drive signal based at least in part on the input signal to turn a transistor on or off to affect the Current associated with the secondary winding of the power converter. Processing information associated with the input signal includes: determining if the input signal is waiting Remains greater than the first threshold for a first period of time that is longer than or longer than the first predetermined duration; determines that the input signal remains greater than the second threshold for a second period that is equal to or longer than the second predetermined duration; in response to the input signal not being determined as The first scheme is used to keep greater than the first threshold for a first period equal to or longer than the first predetermined duration and the input signal is not determined to remain greater than the second threshold for a second period equal to or longer than the second predetermined duration, using the first scheme Do it. The second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration. The first predetermined duration is greater than zero and the second predetermined duration is greater than zero. The first predetermined duration changes in size with the input signal, and the second predetermined duration changes in size with the input signal. For example, the method is implemented based on at least Figure 13, Figure 16, Figure 17, and / or Figure 18.

例如，本發明的各種實施例的一些或全部元件每個都通過使用一個或多個軟體元件、一個或多個硬體元件和/或軟體和硬體元件的一個或多個組合，單獨地和/或與至少另一組件相結合地實現。在另一示例中，本發明的各種實施例的一些或全部元件每個都單獨地和/或與至少另一元件相結合地實現在一個或多個電路中，該一個或多個電路例如是一個或多個類比電路和/或一個或多個數位電路。在又一個示例中，能夠組合本發明的各種實施例和/或示例。 For example, some or all of the elements of the various embodiments of the present invention are each individually and individually using one or more software elements, one or more hardware elements, and / or one or more combinations of software and hardware elements. And / or implemented in combination with at least one other component. In another example, some or all of the elements of the various embodiments of the present invention are each implemented individually and / or in combination with at least one other element in one or more circuits, such as One or more analog circuits and / or one or more digital circuits. In yet another example, various embodiments and / or examples of the invention can be combined.

儘管已經對本發明的具體實施例進行了描述，但是本領域的技術人員應該理解，存在與所描述的實施例等同的其它實施例。因此，應當理解的是，本發明不由具體圖示的實施例來限制，而是僅由所附申請專利範圍來限制。 Although specific embodiments of the invention have been described, those skilled in the art will understand that there are other embodiments equivalent to the described embodiments. Therefore, it should be understood that the present invention is not limited by the specifically illustrated embodiments, but is limited only by the scope of the appended patent applications.

Claims (79)

一種用於調節電源變換器的系統控制器，所述系統控制器包括：第一控制器端子；以及第二控制器端子；其中，所述系統控制器被配置為：在所述第一控制器端子處接收輸入信號；並且至少部分基於所述輸入信號，在所述第二控制器端子處生成驅動信號，以接通或關斷電晶體從而影響與所述電源變換器的二次繞組相關聯的電流；其中，所述系統控制器還被配置為：確定所述輸入信號在等於或長於第一預定持續時間的第一時段內是否保持大於第一閾值；並且回應於所述輸入信號未被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，利用第一方案進行操作；其中，利用所述第一方案進行操作，所述系統控制器還被配置為：確定所述輸入信號在等於或長於第二預定持續時間的第二時段內是否保持小於第二閾值；回應於所述輸入信號被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持小於所述第二閾值，將所述第二控制器端子處的所述驅動信號從第一邏輯位準變為第二邏輯位準；其中：所述第一預定持續時間大於零；並且所述第二預定持續時間大於零。A system controller for adjusting a power converter, the system controller includes: a first controller terminal; and a second controller terminal; wherein the system controller is configured to: Receiving an input signal at a terminal; and based at least in part on the input signal, generating a driving signal at the second controller terminal to turn on or off a transistor to affect the secondary winding associated with the power converter Wherein the system controller is further configured to: determine whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration; and in response to the input signal being not It is determined to remain greater than the first threshold within the first period of time equal to or longer than the first predetermined duration, and the operation is performed using a first scheme; wherein the operation is performed using the first scheme, and the system controls The controller is further configured to determine whether the input signal remains less than a second threshold for a second period equal to or longer than a second predetermined duration; in response to The input signal is determined to remain less than the second threshold for the second period equal to or longer than the second predetermined duration, and the drive signal at the second controller terminal is removed from the first logic The level becomes a second logical level; wherein: the first predetermined duration is greater than zero; and the second predetermined duration is greater than zero. 如申請專利範圍第1項所述的系統控制器，其中：所述系統控制器還被配置為：回應於所述輸入信號被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，利 用第二方案進行操作；並且利用所述第二方案進行操作，所述系統控制器還被配置為：確定所述輸入信號是否變得小於所述第二閾值；以及回應於所述輸入信號被確定為變得小於所述第二閾值，將所述第二控制器端子處的所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，而不管所述輸入信號在等於或長於所述第二預定持續時間的所述第二時段內是否保持小於所述第二閾值。The system controller according to item 1 of the scope of patent application, wherein the system controller is further configured to: in response to the input signal being determined to be equal to or longer than the first predetermined duration For a period of time that remains greater than the first threshold and operates using the second scheme; and operating with the second scheme, the system controller is further configured to determine whether the input signal becomes less than the first scheme Two thresholds; and in response to the input signal being determined to become smaller than the second threshold, changing the drive signal at the second controller terminal from the first logic level to the second A logic level regardless of whether the input signal remains less than the second threshold during the second period equal to or longer than the second predetermined duration. 如申請專利範圍第2項所述的系統控制器，其中，所述系統控制器還被配置為：在回應於所述輸入信號被確定為變得小於所述第二閾值，將所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，而不管所述輸入信號在等於或長於所述第二預定持續時間的所述第二時段內是否保持小於所述第二閾值之後，利用所述第一方案進行操作。The system controller according to item 2 of the scope of patent application, wherein the system controller is further configured to: in response to the input signal being determined to become smaller than the second threshold, the driving signal Changing from the first logic level to the second logic level, regardless of whether the input signal remains less than the second threshold in the second period equal to or longer than the second predetermined duration After that, the first scheme is used for operation. 如申請專利範圍第2項所述的系統控制器，其中：所述第一方案是慢接通方案；並且所述第二方案是快接通方案。The system controller according to item 2 of the patent application scope, wherein: the first scheme is a slow-on scheme; and the second scheme is a fast-on scheme. 如申請專利範圍第1項所述的系統控制器，其中：所述第一邏輯位準是邏輯低位準；並且所述第二邏輯位準是邏輯高位準。The system controller according to item 1 of the scope of patent application, wherein: the first logic level is a logic low level; and the second logic level is a logic high level. 如申請專利範圍第1項所述的系統控制器，其中，所述系統控制器還被配置為：響應於將所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，接通所述電晶體。The system controller according to item 1 of the patent application scope, wherein the system controller is further configured to: in response to changing the driving signal from the first logic level to the second logic level To switch on the transistor. 如申請專利範圍第1項所述的系統控制器，其中，所述第二閾值小於所述第一閾值。The system controller according to item 1 of the scope of patent application, wherein the second threshold value is smaller than the first threshold value. 一種用於調節電源變換器的系統控制器，所述系統控制器包括：第一控制器端子；以及第二控制器端子；其中，所述系統控制器被配置為： 在所述第一控制器端子處接收輸入信號；並且至少部分基於所述輸入信號，在所述第二控制器端子處生成驅動信號，以接通或關斷電晶體從而影響與所述電源變換器的二次繞組相關聯的電流；其中，所述系統控制器還被配置為：確定所述輸入信號在等於或長於第一預定持續時間的第一時段內是否保持小於或等於第一閾值且大於第二閾值，所述第二閾值小於所述第一閾值；並且回應於所述輸入信號未被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持小於或等於所述第一閾值且大於所述第二閾值，利用第一方案進行操作；其中，利用所述第一方案進行操作，所述系統控制器還被配置為：確定所述輸入信號在等於或長於第二預定持續時間的第二時段內是否保持小於第三閾值；回應於所述輸入信號被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持小於所述第三閾值，將所述第二控制器端子處的所述驅動信號從第一邏輯位準變為第二邏輯位準；其中：所述第一預定持續時間大於零；並且所述第二預定持續時間大於零。A system controller for adjusting a power converter, the system controller includes: a first controller terminal; and a second controller terminal; wherein the system controller is configured to: Receiving an input signal at a terminal; and based at least in part on the input signal, generating a driving signal at the second controller terminal to turn on or off a transistor to affect the secondary winding associated with the power converter Wherein the system controller is further configured to determine whether the input signal remains less than or equal to a first threshold and greater than a second threshold within a first period of time equal to or longer than a first predetermined duration, the A second threshold value is less than the first threshold value; and in response to the input signal not being determined to remain less than or equal to the first threshold value and greater than the first time period equal to or longer than the first predetermined duration The second threshold is operated using the first scheme; wherein, the system controller is further configured to determine the output using the first scheme to operate. Whether an incoming signal remains less than a third threshold for a second period equal to or longer than a second predetermined duration; in response to the input signal being determined to be within the second period equal to or longer than the second predetermined duration Keeping it less than the third threshold, changing the driving signal at the second controller terminal from a first logic level to a second logic level; wherein: the first predetermined duration is greater than zero; and all The second predetermined duration is greater than zero. 如申請專利範圍第8項所述的系統控制器，其中：所述系統控制器還被配置為：回應於所述輸入信號被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持小於或等於所述第一閾值且大於所述第二閾值，利用第二方案進行操作；並且利用所述第二方案進行操作，所述系統控制器還被配置為：確定所述輸入信號是否變得小於所述第三閾值；並且回應於所述輸入信號被確定為變得小於所述第三閾值，將所述第二控 制器端子處的所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，而不管所述輸入信號在等於或長於所述第二預定持續時間的所述第二時段內是否保持小於所述第三閾值。The system controller according to item 8 of the scope of patent application, wherein the system controller is further configured to: in response to the input signal being determined to be equal to or longer than the first predetermined duration For a period of time remaining less than or equal to the first threshold value and greater than the second threshold value, and operating with a second scheme; and operating with the second scheme, the system controller is further configured to determine the Whether the input signal becomes smaller than the third threshold; and in response to the input signal being determined to become smaller than the third threshold, the driving signal at the second controller terminal is removed from the first The logic level becomes the second logic level regardless of whether the input signal remains less than the third threshold for the second period of time equal to or longer than the second predetermined duration. 如申請專利範圍第9項所述的系統控制器，其中，所述系統控制器還被配置為：在回應於所述輸入信號被確定為變得小於所述第三閾值，將所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，而不管所述輸入信號在等於或長於所述第二預定持續時間的所述第二時段內是否保持小於所述第三閾值之後，利用所述第一方案進行操作。The system controller according to item 9 of the scope of patent application, wherein the system controller is further configured to: in response to the input signal being determined to become smaller than the third threshold, the driving signal Changing from the first logic level to the second logic level, regardless of whether the input signal remains less than the third threshold in the second period equal to or longer than the second predetermined duration After that, the first scheme is used for operation. 如申請專利範圍第9項所述的系統控制器，其中：所述第一方案是慢接通方案；並且所述第二方案是快接通方案。The system controller according to item 9 of the scope of patent application, wherein: the first scheme is a slow-on scheme; and the second scheme is a fast-on scheme. 如申請專利範圍第8項所述的系統控制器，其中：所述第一邏輯位準是邏輯低位準；並且所述第二邏輯位準是邏輯高位準。The system controller according to item 8 of the scope of patent application, wherein: the first logic level is a logic low level; and the second logic level is a logic high level. 如申請專利範圍第8項所述的系統控制器，其中，所述系統控制器還被配置為：響應於將所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，接通所述電晶體。The system controller according to item 8 of the scope of patent application, wherein the system controller is further configured to: in response to changing the driving signal from the first logic level to the second logic level To switch on the transistor. 如申請專利範圍第8項所述的系統控制器，其中：所述第三閾值小於所述第一閾值；並且所述第三閾值小於所述第二閾值。The system controller according to item 8 of the scope of patent application, wherein: the third threshold is smaller than the first threshold; and the third threshold is smaller than the second threshold. 一種用於調節電源變換器的系統控制器，所述系統控制器包括：第一控制器端子；以及第二控制器端子；其中，所述系統控制器被配置為：在所述第一控制器端子處接收輸入信號；並且至少部分基於所述輸入信號，在所述第二控制器端子處生成驅動信號，以接通或關斷電晶體從而影響與所述電源變換器的二次繞組相關聯的 電流；其中，所述系統控制器還被配置為：確定所述輸入信號在等於或長於第一預定持續時間的第一時段內是否保持大於第一閾值；並且確定所述輸入信號在等於或長於第二預定持續時間的第二時段內是否保持大於第二閾值，所述第二閾值小於所述第一閾值，所述第二預定持續時間長於所述第一預定持續時間；其中，所述系統控制器還被配置為：回應於所述輸入信號未被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，並且所述輸入信號未被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值，利用第一方案進行操作；其中，利用所述第一方案進行操作，所述系統控制器還被配置為：確定所述輸入信號在等於或長於第三預定持續時間的第三時段內是否保持小於第三閾值；並且回應於所述輸入信號被確定為在等於或長於所述第三持續時間的所述第三時段內保持小於所述第三閾值，將所述第二控制器端子處的所述驅動信號從第一邏輯位準變為第二邏輯位準；其中：所述第一預定持續時間大於零；所述第二預定持續時間大於零；並且所述第三預定持續時間大於零。A system controller for adjusting a power converter, the system controller includes: a first controller terminal; and a second controller terminal; wherein the system controller is configured to: Receiving an input signal at a terminal; and based at least in part on the input signal, generating a driving signal at the second controller terminal to turn on or off a transistor to affect the secondary winding associated with the power converter Wherein the system controller is further configured to: determine whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration; and determine that the input signal is equal to or greater than Whether it remains greater than a second threshold within a second period longer than a second predetermined duration, the second threshold is smaller than the first threshold, and the second predetermined duration is longer than the first predetermined duration; wherein, the The system controller is further configured in response to the input signal not being determined to be within the first period of time equal to or longer than the first predetermined duration. Remain greater than the first threshold, and the input signal is not determined to remain greater than the second threshold for the second period of time equal to or longer than the second predetermined duration, and operate using the first scheme; Wherein, using the first scheme for operation, the system controller is further configured to: determine whether the input signal remains less than a third threshold within a third period equal to or longer than a third predetermined duration; and responding to The input signal is determined to remain less than the third threshold for the third period equal to or longer than the third duration, and the drive signal at the second controller terminal is removed from the first logic The level becomes a second logical level; wherein: the first predetermined duration is greater than zero; the second predetermined duration is greater than zero; and the third predetermined duration is greater than zero. 如申請專利範圍第15項所述的系統控制器，其中：所述系統控制器還被配置為：回應於所述輸入信號被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，或者所述輸入信號被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值，利用第二方案進行操作；並且 利用所述第二方案進行操作，所述系統控制器還被配置為：確定所述輸入信號是否變得小於所述第三閾值；並且回應於所述輸入信號被確定為變得小於所述第三閾值，將所述第二控制器端子處的所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，而不管所述輸入信號在等於或長於所述第三預定持續時間的所述第三時段內是否保持小於所述第三閾值。The system controller according to item 15 of the scope of patent application, wherein the system controller is further configured to: in response to the input signal being determined to be equal to or longer than the first predetermined duration Remains greater than the first threshold for a period of time, or the input signal is determined to remain greater than the second threshold for the second period of time equal to or longer than the second predetermined duration, using a second scheme to perform And operating with the second scheme, the system controller is further configured to: determine whether the input signal becomes less than the third threshold; and determine that the input signal becomes less than in response to the input signal The third threshold value changes the driving signal at the second controller terminal from the first logic level to the second logic level, regardless of whether the input signal is equal to or longer than the input signal Whether the third predetermined period of time remains smaller than the third threshold. 如申請專利範圍第16項所述的系統控制器，其中，所述系統控制器還被配置為：回應於所述輸入信號被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，並且所述輸入信號被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值，利用所述第二方案進行操作。The system controller according to item 16 of the scope of patent application, wherein the system controller is further configured to: in response to the input signal being determined to be equal to or longer than the first predetermined duration Remains greater than the first threshold for a period, and the input signal is determined to remain greater than the second threshold for the second period equal to or longer than the second predetermined duration, using the second Program to operate. 如申請專利範圍第16項所述的系統控制器，其中，所述系統控制器還被配置為：在回應於所述輸入信號被確定為變得小於所述第三閾值，將所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，而不管所述輸入信號在等於或長於所述第三預定持續時間的所述第三時段內是否保持小於所述第三閾值之後，利用所述第一方案進行操作。The system controller according to item 16 of the scope of patent application, wherein the system controller is further configured to: in response to the input signal being determined to become smaller than the third threshold, the driving signal Changing from the first logic level to the second logic level, regardless of whether the input signal remains less than the third threshold in the third period equal to or longer than the third predetermined duration After that, the first scheme is used for operation. 如申請專利範圍第16項所述的系統控制器，其中：所述第一方案是慢接通方案；並且所述第二方案是快接通方案。The system controller according to item 16 of the scope of patent application, wherein: the first scheme is a slow-on scheme; and the second scheme is a fast-on scheme. 如申請專利範圍第15項所述的系統控制器，其中：所述第一邏輯位準是邏輯低位準；並且所述第二邏輯位準是邏輯高位準。The system controller according to item 15 of the scope of patent application, wherein: the first logic level is a logic low level; and the second logic level is a logic high level. 如申請專利範圍第15項所述的系統控制器，其中，所述系統控制器還被配置為：響應於將所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，接通所述電晶體。The system controller according to item 15 of the scope of patent application, wherein the system controller is further configured to: in response to changing the driving signal from the first logic level to the second logic level To switch on the transistor. 如申請專利範圍第15項所述的系統控制器，其中：所述第三閾值小於所述第一閾值；並且 所述第三閾值小於所述第二閾值。The system controller according to item 15 of the scope of patent application, wherein: the third threshold is smaller than the first threshold; and the third threshold is smaller than the second threshold. 一種用於調節電源變換器的系統控制器，所述系統控制器包括：第一控制器端子；以及第二控制器端子；其中，所述系統控制器被配置為：在所述第一控制器端子處接收輸入信號；並且至少部分基於所述輸入信號，在所述第二控制器端子處生成驅動信號，以接通或關斷電晶體從而影響與所述電源變換器的二次繞組相關聯的電流；其中，所述系統控制器還被配置為：確定所述輸入信號在等於或長於第一預定持續時間的第一時段內是否保持大於第一閾值；並且確定所述輸入信號在等於或長於第二預定持續時間的第二時段內是否保持大於第二閾值；其中，所述系統控制器還被配置為：回應於所述輸入信號未被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，並且所述輸入信號未被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值，利用第一方案進行操作；其中：所述第二閾值小於所述第一閾值；並且所述第二預定持續時間長於所述第一預定持續時間；其中：所述第一預定持續時間大於零；並且所述第二預定持續時間大於零；其中：所述第一閾值在幅度上隨著所述輸入信號改變； 所述第二閾值在幅度上隨著所述輸入信號改變。A system controller for adjusting a power converter, the system controller includes: a first controller terminal; and a second controller terminal; wherein the system controller is configured to: Receiving an input signal at a terminal; and based at least in part on the input signal, generating a driving signal at the second controller terminal to turn on or off a transistor to affect the secondary winding associated with the power converter Wherein the system controller is further configured to: determine whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration; and determine that the input signal is equal to or greater than Whether it remains greater than a second threshold for a second period longer than a second predetermined duration; wherein the system controller is further configured to: in response to the input signal not being determined to be equal to or longer than the first predetermined duration Remains greater than the first threshold for the first period of time, and the input signal is not determined to be equal to or longer than the second predetermined duration Within the second period of time remaining greater than the second threshold, using the first scheme to operate; wherein: the second threshold is smaller than the first threshold; and the second predetermined duration is longer than the first A predetermined duration; wherein: the first predetermined duration is greater than zero; and the second predetermined duration is greater than zero; wherein: the first threshold value changes in amplitude with the input signal; the second threshold value Changes in amplitude with the input signal. 如申請專利範圍第23項所述的系統控制器，其中：所述第一閾值在幅度上隨著所述輸入信號增大；並且所述第二閾值在幅度上隨著所述輸入信號增大。The system controller according to item 23 of the patent application scope, wherein: the first threshold value increases with the input signal in amplitude; and the second threshold value increases with the input signal in amplitude . 如申請專利範圍第24項所述的系統控制器，其中：所述第一閾值在幅度上隨著所述輸入信號線性增大；並且所述第二閾值在幅度上隨著所述輸入信號線性增大。The system controller according to claim 24, wherein: the first threshold increases linearly with the input signal in amplitude; and the second threshold linearly increases with the input signal in amplitude Increase. 如申請專利範圍第23項所述的系統控制器，其中：所述系統控制器還被配置為：回應於所述輸入信號被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，或者所述輸入信號被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值，利用第二方案進行操作；並且所述第二方案不同於所述第一方案。The system controller according to item 23 of the scope of patent application, wherein the system controller is further configured to: in response to the input signal being determined to be equal to or longer than the first predetermined duration Remains greater than the first threshold for a period of time, or the input signal is determined to remain greater than the second threshold for the second period of time equal to or longer than the second predetermined duration, using a second scheme to perform Operation; and the second scheme is different from the first scheme. 如申請專利範圍第26項所述的系統控制器，其中，所述系統控制器還被配置為：回應於所述輸入信號被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，並且所述輸入信號被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值，利用所述第二方案進行操作。The system controller according to item 26 of the scope of patent application, wherein the system controller is further configured to: in response to the input signal being determined to be equal to or longer than the first predetermined duration Remains greater than the first threshold for a period, and the input signal is determined to remain greater than the second threshold for the second period equal to or longer than the second predetermined duration, using the second Program to operate. 如申請專利範圍第26項所述的系統控制器，其中：所述第一方案是慢接通方案；並且所述第二方案是快接通方案。The system controller as described in claim 26, wherein: the first scheme is a slow-on scheme; and the second scheme is a fast-on scheme. 如申請專利範圍第23項所述的系統控制器，其中：利用所述第一方案進行操作，所述系統控制器還被配置為：確定所述輸入信號在等於或長於第三預定持續時間的第三時段內是否保持小於第三閾值，所述第三預定持續時間大於零；並且回應於所述輸入信號被確定為在等於或長於所述第三持續時間的所述第三時段內保持小於所述第三閾值，將所述第二控制器端子處的所述驅動 信號從第一邏輯位準變為第二邏輯位準。The system controller according to item 23 of the scope of patent application, wherein: using the first scheme for operation, the system controller is further configured to determine that the input signal is equal to or longer than a third predetermined duration Whether it remains less than a third threshold within a third period, the third predetermined duration is greater than zero; and in response to the input signal being determined to remain less than the third period equal to or longer than the third duration The third threshold changes the driving signal at the second controller terminal from a first logic level to a second logic level. 如申請專利範圍第29項所述的系統控制器，其中：所述第一邏輯位準是邏輯低位準；並且所述第二邏輯位準是邏輯高位準。The system controller according to item 29 of the scope of patent application, wherein: the first logic level is a logic low level; and the second logic level is a logic high level. 如申請專利範圍第29項所述的系統控制器，其中，所述系統控制器還被配置為：響應於將所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，接通所述電晶體。The system controller of claim 29, wherein the system controller is further configured to: in response to changing the driving signal from the first logic level to the second logic level To switch on the transistor. 如申請專利範圍第23項所述的系統控制器，其中：所述第三閾值小於所述第一閾值；並且所述第三閾值小於所述第二閾值。The system controller according to item 23 of the scope of patent application, wherein: the third threshold is smaller than the first threshold; and the third threshold is smaller than the second threshold. 一種用於調節電源變換器的系統控制器，所述系統控制器包括：第一控制器端子；以及第二控制器端子；其中，所述系統控制器被配置為：在所述第一控制器端子處接收輸入信號；並且至少部分基於所述輸入信號，在所述第二控制器端子處生成驅動信號，以接通或關斷電晶體從而影響與所述電源變換器的二次繞組相關聯的電流；其中，所述系統控制器還被配置為：確定所述輸入信號在等於或長於第一預定持續時間的第一時段內是否保持大於第一閾值；並且確定所述輸入信號在等於或長於第二預定持續時間的第二時段內是否保持大於第二閾值；其中，所述系統控制器還被配置為：回應於所述輸入信號未被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，並且所述輸入信號未被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值，利用第一方案進行操作； 其中：所述第二閾值小於所述第一閾值；並且所述第二預定持續時間長於所述第一預定持續時間；其中：所述第一預定持續時間大於零；所述第二預定持續時間大於零；所述第一預定持續時間在幅度上隨著所述輸入信號改變；並且所述第二預定持續時間在幅度上隨著所述輸入信號改變。A system controller for adjusting a power converter, the system controller includes: a first controller terminal; and a second controller terminal; wherein the system controller is configured to: Receiving an input signal at a terminal; and based at least in part on the input signal, generating a driving signal at the second controller terminal to turn on or off a transistor to affect the secondary winding associated with the power converter Wherein the system controller is further configured to: determine whether the input signal remains greater than a first threshold for a first period of time equal to or longer than a first predetermined duration; and determine that the input signal is equal to or greater than Whether it remains greater than a second threshold for a second period longer than a second predetermined duration; wherein the system controller is further configured to: in response to the input signal not being determined to be equal to or longer than the first predetermined duration Remains greater than the first threshold for the first period of time, and the input signal is not determined to be equal to or longer than the second predetermined duration The second period of time remains larger than the second threshold, and the first scheme is used for operation; wherein: the second threshold is smaller than the first threshold; and the second predetermined duration is longer than the first A predetermined duration; wherein: the first predetermined duration is greater than zero; the second predetermined duration is greater than zero; the first predetermined duration changes in amplitude with the input signal; and the second predetermined duration The duration varies in magnitude with the input signal. 如申請專利範圍第33項所述的系統控制器，其中：所述第一預定持續時間在幅度上隨著所述輸入信號增大；並且所述第二預定持續時間在幅度上隨著所述輸入信號增大。The system controller according to item 33 of the scope of patent application, wherein: the first predetermined duration increases in amplitude with the input signal; and the second predetermined duration increases in amplitude with the input signal The input signal increases. 如申請專利範圍第34項所述的系統控制器，其中：所述第一預定持續時間在幅度上隨著所述輸入信號線性增大；並且所述第二預定持續時間在幅度上隨著所述輸入信號線性增大。The system controller according to item 34 of the patent application scope, wherein: the first predetermined duration increases linearly with the input signal in amplitude; and the second predetermined duration increases in amplitude with the The input signal increases linearly. 如申請專利範圍第33項所述的系統控制器，其中：所述系統控制器還被配置為：回應於所述輸入信號被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，或者所述輸入信號被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值，利用第二方案進行操作；並且所述第二方案不同於所述第一方案。The system controller according to item 33 of the scope of patent application, wherein the system controller is further configured to: in response to the input signal being determined to be equal to or longer than the first predetermined duration Remains greater than the first threshold for a period of time, or the input signal is determined to remain greater than the second threshold for the second period of time equal to or longer than the second predetermined duration, using a second scheme to perform Operation; and the second scheme is different from the first scheme. 如申請專利範圍第36項所述的系統控制器，其中，所述系統控制器還被配置為：回應於所述輸入信號被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，並且所述輸入信號被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值，利用所述第二方案進行操作。The system controller of claim 36, wherein the system controller is further configured to: in response to the input signal being determined to be equal to or longer than the first predetermined duration Remains greater than the first threshold for a period, and the input signal is determined to remain greater than the second threshold for the second period equal to or longer than the second predetermined duration, using the second Program to operate. 如申請專利範圍第36項所述的系統控制器，其中：所述第一方案是慢接通方案；並且 所述第二方案是快接通方案。The system controller according to claim 36, wherein: the first scheme is a slow-on scheme; and the second scheme is a fast-on scheme. 如申請專利範圍第33項所述的系統控制器，其中：利用所述第一方案進行操作，所述系統控制器還被配置為：確定所述輸入信號在等於或長於第三預定持續時間的第三時段內是否保持小於第三閾值，所述第三預定持續時間大於零；並且回應於所述輸入信號被確定為在等於或長於所述第三持續時間的所述第三時段內保持小於所述第三閾值，將所述第二控制器端子處的所述驅動信號從第一邏輯位準變為第二邏輯位準。The system controller according to item 33 of the scope of patent application, wherein: using the first scheme for operation, the system controller is further configured to determine that the input signal is equal to or longer than a third predetermined duration Whether it remains less than a third threshold within a third period, the third predetermined duration is greater than zero; and in response to the input signal being determined to remain less than the third period equal to or longer than the third duration The third threshold changes the driving signal at the second controller terminal from a first logic level to a second logic level. 如申請專利範圍第39項所述的系統控制器，其中：所述第一邏輯位準是邏輯低位準；並且所述第二邏輯位準是邏輯高位準。The system controller according to item 39 of the scope of patent application, wherein: the first logic level is a logic low level; and the second logic level is a logic high level. 如申請專利範圍第39項所述的系統控制器，其中，所述系統控制器還被配置為：響應於將所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，接通所述電晶體。The system controller according to claim 39, wherein the system controller is further configured to: in response to changing the driving signal from the first logic level to the second logic level To switch on the transistor. 如申請專利範圍第33項所述的系統控制器，其中：所述第三閾值小於所述第一閾值；並且所述第三閾值小於所述第二閾值。The system controller according to item 33 of the patent application scope, wherein: the third threshold is smaller than the first threshold; and the third threshold is smaller than the second threshold. 一種用於調節電源變換器的方法，所述方法包括：接收輸入信號；處理與所述輸入信號相關聯的資訊；以及至少部分基於所述輸入信號生成驅動信號，以接通或關斷電晶體從而影響與所述電源變換器的二次繞組相關聯的電流；其中，處理與所述輸入信號相關聯的資訊包括：確定所述輸入信號在等於或長於第一預定持續時間的第一時段內是否保持大於第一閾值；並且回應於所述輸入信號未被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，利用第一方案進行操作； 其中，至少部分基於所述輸入信號生成驅動信號，以接通或關斷電晶體從而影響與所述電源變換器的二次繞組相關聯的電流包括：回應於利用所述第一方案進行操作，確定所述輸入信號在等於或長於第二預定持續時間的第二時段內是否保持小於第二閾值；並且回應於所述輸入信號被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持小於所述第二閾值，將所述驅動信號從第一邏輯位準變為第二邏輯位準；其中：所述第一預定持續時間大於零；並且所述第二預定持續時間大於零。A method for adjusting a power converter, the method comprising: receiving an input signal; processing information associated with the input signal; and generating a driving signal based at least in part on the input signal to turn a transistor on or off Thereby affecting the current associated with the secondary winding of the power converter; wherein processing information associated with the input signal includes determining that the input signal is within a first period of time equal to or longer than a first predetermined duration Whether to remain greater than a first threshold; and in response to the input signal not being determined to remain greater than the first threshold for the first period of time equal to or longer than the first predetermined duration, operate using a first scheme Generating a driving signal based at least in part on the input signal to turn on or off a transistor to affect a current associated with a secondary winding of the power converter includes: responding to operation using the first scheme To determine whether the input signal remains less than a second threshold for a second period equal to or longer than a second predetermined duration; And in response to the input signal being determined to remain less than the second threshold for the second period equal to or longer than the second predetermined duration, the driving signal is changed from a first logic level to a Two logic levels; wherein: the first predetermined duration is greater than zero; and the second predetermined duration is greater than zero. 如申請專利範圍第43項所述的方法，其中：處理與所述輸入信號相關聯的資訊還包括：回應於所述輸入信號被確定為在等於或大於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，利用第二方案進行操作；至少部分地基於所述輸入信號生成驅動信號，以接通或關斷電晶體從而影響與所述電源變換器的二次繞組相關聯的電流還包括：回應於利用所述第二方案進行操作，確定所述輸入信號是否變得小於所述第二閾值；並且回應於所述輸入信號被確定為變得小於所述第二閾值，將所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，而不管所述輸入信號在等於或長於所述第二預定持續時間的所述第二時段內是否保持小於所述第二閾值。The method of claim 43, wherein processing information associated with the input signal further comprises: in response to the input signal being determined to be equal to or greater than the first predetermined duration Remain greater than the first threshold for the first period of time, and operate using the second scheme; generating a drive signal based at least in part on the input signal to turn on or off the transistor to affect the secondary connection with the power converter The winding-associated current further includes: determining whether the input signal becomes smaller than the second threshold in response to operating with the second scheme; and in response to the input signal being determined to become smaller than the first threshold Two thresholds to change the driving signal from the first logic level to the second logic level, regardless of whether the input signal is within the second period equal to or longer than the second predetermined duration Whether to keep it smaller than the second threshold. 如申請專利範圍第44項所述的方法，其中，處理與所述輸入信號相關聯的資訊還包括：在回應於所述輸入信號被確定為變得小於所述第二閾值，將所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，而不管所述輸入信號在等於或長於所述第二預定持續時間的所述第二時段內是 否保持小於所述第二閾值之後，利用所述第一方案進行操作。The method of claim 44, wherein processing the information associated with the input signal further comprises: in response to the input signal being determined to become less than the second threshold, driving the driver The signal changes from the first logic level to the second logic level, regardless of whether the input signal remains less than the second within the second period equal to or longer than the second predetermined duration After the threshold, the first scheme is used for operation. 如申請專利範圍第44項所述的方法，其中：所述第一方案是慢接通方案；並且所述第二方案是快接通方案。The method according to item 44 of the scope of patent application, wherein: the first scheme is a slow-on scheme; and the second scheme is a fast-on scheme. 如申請專利範圍第43項所述的方法，還包括：響應於將所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，接通所述電晶體。The method of claim 43, further comprising: turning on the transistor in response to changing the driving signal from the first logic level to the second logic level. 如申請專利範圍第43項所述的方法，其中，所述第二閾值小於所述第一閾值。The method of claim 43, wherein the second threshold is smaller than the first threshold. 一種用於調節電源變換器的方法，所述方法包括：接收輸入信號；處理與所述輸入信號相關聯的資訊；以及至少部分基於所述輸入信號生成驅動信號，以接通或關斷電晶體從而影響與所述電源變換器的二次繞組相關聯的電流；其中，處理與所述輸入信號相關聯的資訊包括：確定所述輸入信號在等於或長於第一預定持續時間的第一時段內是否保持小於或等於第一閾值且大於第二閾值，所述第二閾值小於所述第一閾值；並且回應於所述輸入信號未被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持小於或等於所述第一閾值且大於所述第二閾值，利用第一方案進行操作；其中，至少部分基於所述輸入信號生成驅動信號，以接通或關斷電晶體從而影響與所述電源變換器的二次繞組相關聯的電流包括：回應於利用所述第一方案進行操作，確定所述輸入信號在等於或長於第二預定持續時間的第二時段內是否保持小於第三閾值；並且回應於所述輸入信號被確定為在等於或長於所述第二預定持續時間的 所述第二時段內保持小於所述第三閾值，將所述驅動信號從第一邏輯位準變為第二邏輯位準；其中：所述第一預定持續時間大於零；並且所述第二預定持續時間大於零。A method for adjusting a power converter, the method comprising: receiving an input signal; processing information associated with the input signal; and generating a driving signal based at least in part on the input signal to turn a transistor on or off Thereby affecting the current associated with the secondary winding of the power converter; wherein processing information associated with the input signal includes determining that the input signal is within a first period of time equal to or longer than a first predetermined duration Whether to remain less than or equal to a first threshold value and greater than a second threshold value, the second threshold value being less than the first threshold value; and in response to the input signal not being determined to be equal to or longer than the first predetermined duration The first period of time remains less than or equal to the first threshold value and is greater than the second threshold value, and is operated using the first scheme; wherein a driving signal is generated based at least in part on the input signal to turn on or off the transistor Thus affecting the current associated with the secondary winding of the power converter includes: in response to operating with the first scheme, determining Whether the input signal remains less than a third threshold for a second period equal to or longer than a second predetermined duration; and in response to the input signal being determined to be at the second equal to or longer than the second predetermined duration Staying less than the third threshold for a period of time, changing the driving signal from a first logic level to a second logic level; wherein: the first predetermined duration is greater than zero; and the second predetermined duration is greater than zero. 如申請專利範圍第49項所述的方法，其中：處理與所述輸入信號相關聯的資訊還包括：回應於所述輸入信號被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持小於或等於所述第一閾值且大於所述第二閾值，利用第二方案進行操作；其中，至少部分地基於所述輸入信號生成驅動信號，以接通或關斷電晶體從而影響與所述電源變換器的二次繞組相關聯的電流還包括：回應於利用所述第二方案進行操作，確定所述輸入信號是否變得小於所述第三閾值；並且回應於所述輸入信號被確定為變得小於所述第三閾值，將所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，而不管所述輸入信號在等於或長於所述第二預定持續時間的所述第二時段內是否保持小於所述第三閾值。The method of claim 49, wherein processing the information associated with the input signal further comprises: in response to the input signal being determined to be equal to or longer than the first predetermined duration Remain within the first period less than or equal to the first threshold and greater than the second threshold, and operate using a second scheme; wherein a driving signal is generated based at least in part on the input signal to turn the transistor on or off Thus affecting the current associated with the secondary winding of the power converter further includes: determining whether the input signal becomes less than the third threshold in response to operating with the second scheme; and responding to the The input signal is determined to become smaller than the third threshold, and the driving signal is changed from the first logic level to the second logic level, regardless of whether the input signal is equal to or longer than the first logic level. Whether the second predetermined period of time remains smaller than the third threshold. 如申請專利範圍第50項所述的方法，其中，處理與所述輸入信號相關聯的資訊還包括：在回應於所述輸入信號被確定為變得小於所述第三閾值，將所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，而不管所述輸入信號在等於或長於所述第二預定持續時間的所述第二時段內是否保持小於所述第三閾值之後，利用所述第一方案進行操作。The method of claim 50, wherein processing the information associated with the input signal further comprises: in response to the input signal being determined to become less than the third threshold, driving the driver The signal changes from the first logic level to the second logic level, regardless of whether the input signal remains less than the third within the second period equal to or longer than the second predetermined duration After the threshold, the first scheme is used for operation. 如申請專利範圍第50項所述的方法，其中：所述第一方案是慢接通方案；並且所述第二方案是快接通方案。The method of claim 50, wherein: the first scheme is a slow-on scheme; and the second scheme is a fast-on scheme. 如申請專利範圍第49項所述的方法，還包括： 響應於將所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，接通所述電晶體。The method of claim 49, further comprising: in response to changing the driving signal from the first logic level to the second logic level, turning on the transistor. 如申請專利範圍第49項所述的方法，其中：所述第三閾值小於所述第一閾值；並且所述第三閾值小於所述第二閾值。The method of claim 49, wherein: the third threshold is smaller than the first threshold; and the third threshold is smaller than the second threshold. 一種用於調節電源變換器的方法，所述方法包括：接收輸入信號；處理與所述輸入信號相關聯的資訊；以及至少部分基於所述輸入信號生成驅動信號，以接通或關斷電晶體從而影響與所述電源變換器的二次繞組相關聯的電流；其中，處理與所述輸入信號相關聯的資訊包括：確定所述輸入信號在等於或長於第一預定持續時間的第一時段內是否保持大於第一閾值；確定所述輸入信號在等於或長於第二預定持續時間的第二時段內是否保持大於第二閾值，所述第二閾值小於所述第一閾值，所述第二預定持續時間長於所述第一預定持續時間；並且回應於所述輸入信號未被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，且所述輸入信號未被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值，利用第一方案進行操作；其中，至少部分基於所述輸入信號生成驅動信號，以接通或關斷電晶體從而影響與所述電源變換器的二次繞組相關聯的電流包括：回應於利用所述第一方案進行操作，確定所述輸入信號在等於或長於第三預定持續時間的第三時段內是否保持小於第三閾值；並且回應於所述輸入信號被確定為在等於或長於所述第三預定持續時間的所述第三時段內保持小於所述第三閾值，將所述驅動信號從第一邏輯位準 變為第二邏輯位準；其中：所述第一預定持續時間大於零；所述第二預定持續時間大於零；並且所述第三預定持續時間大於零。A method for adjusting a power converter, the method comprising: receiving an input signal; processing information associated with the input signal; and generating a driving signal based at least in part on the input signal to turn a transistor on or off Thereby affecting the current associated with the secondary winding of the power converter; wherein processing information associated with the input signal includes determining that the input signal is within a first period of time equal to or longer than a first predetermined duration Whether to remain greater than a first threshold; determine whether the input signal remains greater than a second threshold for a second period equal to or longer than a second predetermined duration, the second threshold being less than the first threshold, and the second predetermined The duration is longer than the first predetermined duration; and in response to the input signal not being determined to remain greater than the first threshold for the first period of time equal to or longer than the first predetermined duration, and The input signal is not determined to remain greater than the second threshold for the second period that is equal to or longer than the second predetermined duration Use the first scheme to operate; wherein generating a driving signal based at least in part on the input signal to turn on or off a transistor to affect the current associated with the secondary winding of the power converter includes: The first solution is operated to determine whether the input signal remains less than a third threshold for a third period equal to or longer than a third predetermined duration; and in response to the input signal being determined to be equal to or longer than the first threshold The third period of three predetermined durations is kept smaller than the third threshold, and the driving signal is changed from a first logic level to a second logic level; wherein: the first predetermined duration is greater than zero; The second predetermined duration is greater than zero; and the third predetermined duration is greater than zero. 如申請專利範圍第55項所述的方法，其中：處理與所述輸入信號相關聯的資訊還包括：回應於所述輸入信號被確定為在等於或大於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，或者所述輸入信號被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值，利用第二方案進行操作；至少部分地基於所述輸入信號生成驅動信號，以接通或關斷電晶體從而影響與所述電源變換器的二次繞組相關聯的電流還包括：回應於利用所述第二方案進行操作，確定所述輸入信號是否變得小於所述第三閾值；並且回應於所述輸入信號被確定為變得小於所述第三閾值，將所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，而不管所述輸入信號在等於或長於所述第三預定持續時間的所述第三時段內是否保持小於所述第三閾值。The method of claim 55, wherein processing the information associated with the input signal further comprises: in response to the input signal being determined to be equal to or greater than the first predetermined duration Remains greater than the first threshold for the first period, or the input signal is determined to remain greater than the second threshold for the second period equal to or longer than the second predetermined duration, using a second solution Performing an operation; generating a driving signal based at least in part on the input signal to turn on or off a transistor to affect a current associated with a secondary winding of the power converter further includes: responding to using the second scheme Performing an operation to determine whether the input signal becomes less than the third threshold; and in response to the input signal being determined to become less than the third threshold, driving the drive signal from the first logic level Becomes the second logic level regardless of whether the input signal remains smaller than the third period in the third period equal to or longer than the third predetermined duration Value. 如申請專利範圍第56項所述的方法，其中，回應於所述輸入信號被確定為在等於或大於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，或者所述輸入信號被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值，利用第二方案進行操作包括：回應於所述輸入信號被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，且所述輸入信號被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值， 利用第二方案進行操作。The method of claim 56, wherein in response to the input signal being determined to remain greater than the first threshold for the first period of time equal to or greater than the first predetermined duration, or The input signal is determined to remain greater than the second threshold for the second period of time equal to or longer than the second predetermined duration, and the operation using the second scheme includes: in response to the input signal being determined as Remains greater than the first threshold for the first time period equal to or longer than the first predetermined duration, and the input signal is determined to be the second time equal to or longer than the second predetermined duration It remains larger than the second threshold for a period of time, and is operated by using a second solution. 如申請專利範圍第56項所述的方法，其中，處理與所述輸入信號相關聯的資訊還包括：在回應於所述輸入信號被確定為變得小於所述第三閾值，將所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，而不管所述輸入信號在等於或長於所述第三預定持續時間的所述第三時段內是否保持小於所述第三閾值之後，利用所述第一方案進行操作。The method of claim 56, wherein processing information associated with the input signal further comprises: in response to the input signal being determined to become less than the third threshold, driving the driver The signal changes from the first logic level to the second logic level, regardless of whether the input signal remains less than the third period in the third period equal to or longer than the third predetermined duration After the threshold, the first scheme is used for operation. 如申請專利範圍第56項所述的方法，其中：所述第一方案是慢接通方案；並且所述第二方案是快接通方案。The method according to item 56 of the scope of patent application, wherein: the first scheme is a slow-on scheme; and the second scheme is a fast-on scheme. 如申請專利範圍第55項所述的方法，還包括：響應於將所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，接通所述電晶體。The method of claim 55, further comprising: turning on the transistor in response to changing the driving signal from the first logic level to the second logic level. 如申請專利範圍第55項所述的方法，其中：所述第三閾值小於所述第一閾值；並且所述第三閾值小於所述第二閾值。The method of claim 55, wherein: the third threshold is smaller than the first threshold; and the third threshold is smaller than the second threshold. 一種用於調節電源變換器的方法，所述方法包括：接收輸入信號；處理與所述輸入信號相關聯的資訊；以及至少部分基於所述輸入信號生成驅動信號，以接通或關斷電晶體從而影響與所述電源變換器的二次繞組相關聯的電流；其中，處理與所述輸入信號相關聯的資訊包括：確定所述輸入信號在等於或長於第一預定持續時間的第一時段內是否保持大於第一閾值；確定所述輸入信號在等於或長於第二預定持續時間的第二時段內是否保持大於第二閾值；並且回應於所述輸入信號未被確定為在等於或長於所述第一預定持續時間 的所述第一時段內保持大於所述第一閾值，且所述輸入信號未被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值，利用第一方案進行操作；其中：所述第二閾值小於所述第一閾值；並且所述第二預定持續時間長於所述第一預定持續時間；其中：所述第一預定持續時間大於零；並且所述第二預定持續時間大於零；其中：所述第一閾值在幅度上隨著所述輸入信號改變；並且所述第二閾值在幅度上隨著所述輸入信號改變。A method for adjusting a power converter, the method comprising: receiving an input signal; processing information associated with the input signal; and generating a driving signal based at least in part on the input signal to turn a transistor on or off Thereby affecting the current associated with the secondary winding of the power converter; wherein processing information associated with the input signal includes determining that the input signal is within a first period of time equal to or longer than a first predetermined duration Whether to remain greater than a first threshold; determine whether the input signal remains greater than a second threshold for a second period equal to or longer than a second predetermined duration; and in response to the input signal not being determined to be equal to or longer than the The first predetermined duration is maintained greater than the first threshold for the first time period, and the input signal is not determined to remain greater than the first time period for the second time period that is equal to or longer than the second predetermined time duration. The second threshold is operated by using the first scheme; wherein: the second threshold is smaller than the first threshold; and the second predetermined The duration is longer than the first predetermined duration; wherein: the first predetermined duration is greater than zero; and the second predetermined duration is greater than zero; wherein: the first threshold value follows the input signal in amplitude And the second threshold changes in amplitude with the input signal. 如申請專利範圍第62項所述的方法，其中：所述第一閾值在幅度上隨著所述輸入信號增大；並且所述第二閾值在幅度上隨著所述輸入信號增大。The method of claim 62, wherein: the first threshold value increases with the input signal in amplitude; and the second threshold value increases with the input signal in amplitude. 如申請專利範圍第63項所述的方法，其中：所述第一閾值在幅度上隨著所述輸入信號線性增大；並且所述第二閾值在幅度上隨著所述輸入信號線性增大。The method of claim 63, wherein: the first threshold increases linearly with the input signal in amplitude; and the second threshold increases linearly with the input signal in amplitude . 如申請專利範圍第62項所述的方法，其中：處理與所述輸入信號相關聯的資訊還包括：回應於所述輸入信號被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，或者所述輸入信號被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值，利用第二方案進行操作；並且所述第二方案不同於所述第一方案。The method of claim 62, wherein processing the information associated with the input signal further comprises: in response to the input signal being determined to be equal to or longer than the first predetermined duration Remains greater than the first threshold for the first period, or the input signal is determined to remain greater than the second threshold for the second period equal to or longer than the second predetermined duration, using a second solution And the second scheme is different from the first scheme. 如申請專利範圍第65項所述的方法，其中，回應於所述輸入信號被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於 所述第一閾值，或者所述輸入信號被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值，利用第二方案進行操作包括：回應於所述輸入信號被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，並且所述輸入信號被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值，利用所述第二方案進行操作。The method of claim 65, wherein in response to the input signal being determined to remain greater than the first threshold for the first period of time equal to or longer than the first predetermined duration, or The input signal is determined to remain greater than the second threshold for the second period of time equal to or longer than the second predetermined duration, and the operation using the second scheme includes: in response to the input signal being determined as Remains greater than the first threshold for the first time period equal to or longer than the first predetermined duration, and the input signal is determined to be the second time equal to or longer than the second predetermined duration It remains larger than the second threshold for a period of time, and is operated by using the second scheme. 如申請專利範圍第65項所述的方法，其中：所述第一方案是慢接通方案；並且所述第二方案是快接通方案。The method of claim 65, wherein: the first scheme is a slow-on scheme; and the second scheme is a fast-on scheme. 如申請專利範圍第62項所述的方法，其中，至少部分基於所述輸入信號生成驅動信號，以接通或關斷電晶體從而影響與所述電源變換器的二次繞組相關聯的電流包括：回應於利用所述第一方案進行操作，確定所述輸入信號在等於或長於第三預定持續時間的第三時段內是否保持小於第三閾值，所述第三預定持續時間大於零；並且回應於所述輸入信號被確定為在等於或長於所述第三持續時間的所述第三時段內保持小於所述第三閾值，將所述驅動信號從第一邏輯位準變為第二邏輯位準。The method of claim 62, wherein generating a driving signal based at least in part on the input signal to turn on or off a transistor to affect a current associated with a secondary winding of the power converter includes : In response to operating with the first scheme, determining whether the input signal remains less than a third threshold within a third period equal to or longer than a third predetermined duration, the third predetermined duration being greater than zero; and responding After the input signal is determined to remain less than the third threshold for the third period equal to or longer than the third duration, the driving signal is changed from a first logic level to a second logic bit quasi. 如申請專利範圍第68項所述的方法，還包括：響應於將所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準，接通所述電晶體。The method of claim 68, further comprising: turning on the transistor in response to changing the driving signal from the first logic level to the second logic level. 如申請專利範圍第68項所述的方法，其中：所述第三閾值小於所述第一閾值；並且所述第三閾值小於所述第二閾值。The method of claim 68, wherein: the third threshold is smaller than the first threshold; and the third threshold is smaller than the second threshold. 一種用於調節電源變換器的方法，所述方法包括：接收輸入信號；處理與所述輸入信號相關聯的資訊；以及 至少部分基於所述輸入信號生成驅動信號，以接通或關斷電晶體從而影響與所述電源變換器的二次繞組相關聯的電流；其中，處理與所述輸入信號相關聯的資訊包括：確定所述輸入信號在等於或長於第一預定持續時間的第一時段內是否保持大於第一閾值；確定所述輸入信號在等於或長於第二預定持續時間的第二時段內是否保持大於第二閾值；並且回應於所述輸入信號未被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，且所述輸入信號未被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值，利用第一方案進行操作；其中：所述第二閾值小於所述第一閾值；並且所述第二預定持續時間長於所述第一預定持續時間；其中：所述第一預定持續時間大於零；所述第二預定持續時間大於零；所述第一預定持續時間在幅度上隨著所述輸入信號改變；並且所述第二預定持續時間在幅度上隨著所述輸入信號改變。A method for adjusting a power converter, the method comprising: receiving an input signal; processing information associated with the input signal; and generating a driving signal based at least in part on the input signal to turn a transistor on or off Thereby affecting the current associated with the secondary winding of the power converter; wherein processing information associated with the input signal includes determining that the input signal is within a first period of time equal to or longer than a first predetermined duration Whether to remain greater than a first threshold; determine whether the input signal remains greater than a second threshold for a second period equal to or longer than a second predetermined duration; and in response to the input signal not being determined to be equal to or longer than the The first predetermined duration is maintained greater than the first threshold for the first time period, and the input signal is not determined to remain greater than the first time period for the second time period that is equal to or longer than the second predetermined time duration. The second threshold is operated by using the first scheme; wherein: the second threshold is smaller than the first threshold; and the second predetermined The duration is longer than the first predetermined duration; wherein: the first predetermined duration is greater than zero; the second predetermined duration is greater than zero; the first predetermined duration changes in amplitude with the input signal ; And the second predetermined duration changes in amplitude with the input signal. 如申請專利範圍第71項所述的方法，其中：所述第一預定持續時間在幅度上隨著所述輸入信號增大；並且所述第二預定持續時間在幅度上隨著所述輸入信號增大。The method of claim 71, wherein: the first predetermined duration increases with the input signal in amplitude; and the second predetermined duration increases with the input signal in amplitude Increase. 如申請專利範圍第72項所述的方法，其中：所述第一預定持續時間在幅度上隨著所述輸入信號線性增大；並且所述第二預定持續時間在幅度上隨著所述輸入信號線性增大。The method of claim 72, wherein: the first predetermined duration increases linearly with the input signal in amplitude; and the second predetermined duration increases in amplitude with the input The signal increases linearly. 如申請專利範圍第71項所述的方法，其中：處理與所述輸入信號相關聯的資訊還包括： 回應於所述輸入信號被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，或者所述輸入信號被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值，利用第二方案進行操作；並且所述第二方案不同於所述第一方案。The method of claim 71, wherein processing information associated with the input signal further comprises: in response to the input signal being determined to be equal to or longer than the first predetermined duration Remains greater than the first threshold for the first period, or the input signal is determined to remain greater than the second threshold for the second period equal to or longer than the second predetermined duration, using a second solution And the second scheme is different from the first scheme. 如申請專利範圍第74項所述的方法，其中，回應於所述輸入信號被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，或者所述輸入信號被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值，利用第二方案進行操作包括：回應於所述輸入信號被確定為在等於或長於所述第一預定持續時間的所述第一時段內保持大於所述第一閾值，並且所述輸入信號被確定為在等於或長於所述第二預定持續時間的所述第二時段內保持大於所述第二閾值，利用所述第二方案進行操作。The method of claim 74, wherein in response to the input signal being determined to remain greater than the first threshold for the first period of time equal to or longer than the first predetermined duration, or The input signal is determined to remain greater than the second threshold for the second period of time equal to or longer than the second predetermined duration, and the operation using the second scheme includes: in response to the input signal being determined as Remains greater than the first threshold for the first time period equal to or longer than the first predetermined duration, and the input signal is determined to be the second time equal to or longer than the second predetermined duration It remains larger than the second threshold for a period of time, and is operated by using the second scheme. 如申請專利範圍第74項所述的方法，其中：所述第一方案是慢接通方案；並且所述第二方案是快接通方案。The method of claim 74, wherein: the first scheme is a slow-on scheme; and the second scheme is a fast-on scheme. 如申請專利範圍第71項所述的方法，其中，至少部分基於所述輸入信號生成驅動信號，以接通或關斷電晶體從而影響與所述電源變換器的二次繞組相關聯的電流包括：回應於利用所述第一方案進行操作，確定所述輸入信號在等於或長於第三預定持續時間的第三時段內是否保持小於第三閾值，所述第三預定持續時間大於零；並且回應於所述輸入信號被確定為在等於或長於所述第三持續時間的所述第三時段內保持小於所述第三閾值，將所述驅動信號從第一邏輯位準變為第二邏輯位準。The method of claim 71, wherein generating a driving signal based at least in part on the input signal to turn on or off a transistor to affect a current associated with a secondary winding of the power converter includes : In response to operating with the first scheme, determining whether the input signal remains less than a third threshold within a third period equal to or longer than a third predetermined duration, the third predetermined duration being greater than zero; and responding After the input signal is determined to remain less than the third threshold for the third period equal to or longer than the third duration, the driving signal is changed from a first logic level to a second logic bit quasi. 如申請專利範圍第77項所述的方法，還包括：響應於將所述驅動信號從所述第一邏輯位準變為所述第二邏輯位準， 接通所述電晶體。The method of claim 77, further comprising: turning on the transistor in response to changing the driving signal from the first logic level to the second logic level. 如申請專利範圍第77項所述的方法，其中：所述第三閾值小於所述第一閾值；並且所述第三閾值小於所述第二閾值。The method of claim 77, wherein: the third threshold is smaller than the first threshold; and the third threshold is smaller than the second threshold.
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