TWI663601B - Semiconductor device - Google Patents

Abstract

本發明利用新的方法提供一種具有產生固有資料的功能的半導體裝置。本發明的NAND型快閃記憶體具有：記憶胞陣列、分頁緩衝器/感測電路、在記憶胞陣列的虛擬陣列被讀出時檢測出虛擬陣列的位元線對的電位差的差動感測放大器，其中NAND型快閃記憶體會根據差動感測放大器的檢出結果而輸出半導體裝置的固有資料。The present invention uses a new method to provide a semiconductor device having a function of generating unique data. The NAND-type flash memory of the present invention includes a memory cell array, a page buffer / sensing circuit, and a differential sensing amplifier that detects the potential difference of the bit line pairs of the virtual array when the virtual array of the memory cell array is read out. The NAND-type flash memory outputs the inherent data of the semiconductor device according to the detection result of the differential sense amplifier.

Description

半導體裝置Semiconductor device

本發明係有關於具備產生固有資訊功能的半導體裝置，且特別有關於利用NAND型快閃記憶體的固有資訊的產生。 The present invention relates to a semiconductor device having a function of generating unique information, and more particularly to the generation of unique information using a NAND flash memory.

伴隨著電子裝置或電子裝置的安全性的強化，為了防止實體安裝於上述裝置的半導體裝置的偽造或仿冒，需要有對應方案。某一個方法中，給予半導體裝置固有資訊並驗證了固有資訊的情況下，可將該半導體裝置視為正品而允許使用。固有資訊例如能夠儲存於半導體裝置的非揮發性記憶體等，但是這種方法會有解析半導體裝置使得固有資訊被讀取，或者是從外部不正當存取半導體裝置使得固有資訊被讀取的風險。 With the enhancement of the security of electronic devices or electronic devices, in order to prevent counterfeiting or counterfeiting of semiconductor devices physically mounted on the devices, corresponding solutions are required. In a certain method, when the inherent information is given to the semiconductor device and the inherent information is verified, the semiconductor device may be regarded as a genuine product and allowed to be used. The inherent information can be stored in the non-volatile memory of the semiconductor device, but this method has the risk of analyzing the semiconductor device so that the inherent information is read, or the semiconductor device is accessed improperly from the outside, so that the inherent information is read. .

近年來，物理上無法複製的PUF(Physical Unclonable Function)相當受到注目。PUF是將不能夠預測，隱匿性高且具有恆久性的物理資訊做為固有資料使用的技術。例如，有使用仲裁器電路的PUF、使用環形振盪器的PUF、使用SRAM的PUF等的提案。又，NAND型快閃記憶體中，揭露了使用擦除驗證的PUF(專利文獻1)、或者是使用電壓調整單元的PUF(專利文獻2)等。 In recent years, PUF (Physical Unclonable Function) which cannot be physically copied has attracted considerable attention. PUF is a technology that uses unpredictable, highly concealed, and permanent physical information as inherent data. For example, there are proposals for a PUF using an arbiter circuit, a PUF using a ring oscillator, and a PUF using SRAM. Moreover, a NAND-type flash memory has disclosed a PUF (Patent Document 1) using erasure verification, or a PUF (Patent Document 2) using a voltage adjustment unit.

先行技術文獻 Advance technical literature

專利文獻1：美國專利公開2015/0007337A1號公報 Patent Document 1: U.S. Patent Publication No. 2015 / 0007337A1

專利文獻2：美國專利公開2015/0055417A1號公報 Patent Document 2: U.S. Patent Publication No. 2015 / 0055417A1

半導體裝置的設計/製造中，藉由抑制電路元件或配線等的不均一(變動)，或者是將不均一最小化，提供了重現性、信賴信高的半導體裝置。另一方面，使電路元件或配線等的不均一最小化，會為電路元件或配線帶來均一性，有可能造成PUF或固有資料的隨機性(非預測性)降低。因此，會希望有一種PUF技術能夠一邊維持重現性、信賴性，一邊確保固有資料的隨機性。 In designing and manufacturing a semiconductor device, by suppressing or minimizing non-uniformity (variation) of circuit elements, wiring, and the like, it is possible to provide a reproducible and reliable semiconductor device. On the other hand, minimizing the unevenness of circuit elements or wiring will bring uniformity to the circuit elements or wiring, which may cause the randomness (unpredictability) of the PUF or the inherent data to decrease. Therefore, it is desirable to have a PUF technology that can maintain the reproducibility and reliability while ensuring the randomness of the inherent data.

本發明的目的是透過新的方法來提供一種具有產生固有資料功能的半導體裝置。 An object of the present invention is to provide a semiconductor device having a function of generating unique data by a new method.

本發明的半導體裝置，包括：記憶體陣列，包括NAND型串列；選擇構件，選擇該記憶體陣列的特定區域；讀出構件，讀出該選擇構件所選擇的特定的區域；檢出構件，檢測出該讀出構件所讀出的特定的區域的位元線對的電位差；以及產生構件，根據該檢出構件的檢出結果產生半導體裝置的固有資料。 The semiconductor device of the present invention includes: a memory array including a NAND-type string; a selection component, which selects a specific area of the memory array; a reading component, which reads out a specific area selected by the selection component; a detection component, Detecting a potential difference of a bit line pair in a specific area read by the reading means; and generating means, and generating specific data of the semiconductor device based on a detection result of the detecting means.

根據本發明，從記憶胞陣列中讀出的特定的區域的位元線對的電位差，根據該檢出結果輸出固有資料，因此能夠一邊保持半導體裝置的再現性或信賴性，一邊能夠保持固有資料的隨機性。 According to the present invention, since the potential difference between the bit line pairs of a specific region read out from the memory cell array and the unique data are output based on the detection result, the unique data can be maintained while maintaining the reproducibility or reliability of the semiconductor device. Randomness.

100‧‧‧快閃記憶體 100‧‧‧Flash memory

110‧‧‧記憶胞陣列 110‧‧‧Memory Cell Array

120‧‧‧輸出入緩衝器 120‧‧‧I / O buffer

130‧‧‧位址暫存器 130‧‧‧Address Register

140‧‧‧控制器 140‧‧‧controller

150‧‧‧字元線選擇電路 150‧‧‧word line selection circuit

160‧‧‧分頁緩衝器/感測電路 160‧‧‧Page buffer / sensing circuit

170‧‧‧行選擇電路 170‧‧‧row selection circuit

180‧‧‧內部電壓產生電路 180‧‧‧ Internal voltage generating circuit

200‧‧‧位元線選擇電路 200‧‧‧bit line selection circuit

300‧‧‧固有資料產生電路 300‧‧‧ inherent data generating circuit

310‧‧‧差動感測放大器 310‧‧‧ Differential Sense Amplifier

320‧‧‧計算電路 320‧‧‧Calculation Circuit

BLK‧‧‧記憶體塊 BLK‧‧‧Memory Block

BLS‧‧‧位元線選擇電晶體 BLS‧‧‧Bit line selection transistor

BLCD‧‧‧電晶體 BLCD‧‧‧Transistor

BLCLAMP‧‧‧電晶體 BLCLAMP‧‧‧Transistor

BLPRE‧‧‧電晶體 BLPRE‧‧‧Transistor

Dout_i‧‧‧固有資料 Dout_i‧‧‧ inherent information

GBL_e‧‧‧偶數位元線 GBL_e‧‧‧even bit line

GBL_o‧‧‧奇數位元線 GBL_o‧‧‧odd bit line

MCi‧‧‧記憶胞 MCi‧‧‧Memory Cell

SEL_e‧‧‧偶數選擇電晶體 SEL_e‧‧‧ Even Selection Transistor

SEL_o‧‧‧奇數選擇電晶體 SEL_o‧‧‧Odd number selection transistor

LAT‧‧‧拴鎖電路 LAT‧‧‧ Latching Circuit

NU‧‧‧NAND串列 NU‧‧‧NAND Serial

PB_i‧‧‧分頁緩衝器 PB_i‧‧‧Paged Buffer

SGD‧‧‧選擇閘極線 SGD‧‧‧Select gate line

SGS‧‧‧選擇閘極線 SGS‧‧‧Select gate line

SNS‧‧‧感測節點 SNS‧‧‧sensing node

SL‧‧‧源極線 SL‧‧‧Source Line

VPRE‧‧‧假想電位 VPRE‧‧‧imaginary potential

TR1‧‧‧汲極側的位元線選擇電晶體 TR1‧‧‧Bit line selection transistor on drain side

TR2‧‧‧源極側的位元線選擇電晶體 TR2‧‧‧Bit line selection transistor on source side

WLi‧‧‧字元線 WLi‧‧‧Character Line

YSEL_e‧‧‧偶數偏壓選擇電晶體 YSEL_e‧‧‧even bias selection transistor

YSEL_o‧‧‧奇數偏壓選擇電晶體 YSEL_o‧‧‧odd bias selection transistor

第1圖顯示本發明的實施例的NAND型快閃記憶體的構造。 FIG. 1 shows a structure of a NAND-type flash memory according to an embodiment of the present invention.

第2圖顯示本發明的實施例的記憶體胞陣列的NAND型字串的架構。 FIG. 2 shows the architecture of a NAND string of a memory cell array according to an embodiment of the present invention.

第3圖顯示本發明的實施例的位元線選擇電路的一例。 FIG. 3 shows an example of a bit line selection circuit according to an embodiment of the present invention.

第4圖顯示本發明的實施例的分頁緩衝器/感測電路的一例。 FIG. 4 shows an example of a page buffer / sensing circuit according to an embodiment of the present invention.

第5圖顯示本發明的實施例的固有資料產生電路的一例。 FIG. 5 shows an example of a unique data generating circuit according to an embodiment of the present invention.

第6圖係顯示NAND型快閃記憶體動作時所施加的偏壓電壓的表格。 FIG. 6 is a table showing a bias voltage applied when a NAND-type flash memory operates.

第7圖係說明本發明的實施例的固有資料產生的動作的流程圖。 Fig. 7 is a flowchart illustrating an operation of generating unique data in the embodiment of the present invention.

第8圖係說明本發明的實施例的虛擬陣列的選擇例。 FIG. 8 illustrates an example of selecting a virtual array according to the embodiment of the present invention.

第9圖係說明施加於虛擬陣列的字元線電壓的例子。 FIG. 9 illustrates an example of a word line voltage applied to the dummy array.

第10圖係說明本發明的變形例。 Fig. 10 illustrates a modification of the present invention.

接著，參照圖式說明本發明的實施型態。本發明的半導體裝置具有產生半導體裝置所固有的固有資料，並且將其輸出到外部的功能。在某個實施型態中，本發明的半導體裝置包含NAND型快閃記憶體，利用NAND型快閃記憶體產生來固有資料，並將其輸出至外部。本發明的半導體裝置也可以是NAND型快閃記憶體本身，也可以是具有除此之外的功能的半導體電路。 Next, embodiments of the present invention will be described with reference to the drawings. The semiconductor device of the present invention has a function of generating unique data inherent to the semiconductor device and outputting it to the outside. In a certain embodiment, the semiconductor device of the present invention includes a NAND-type flash memory, and uses the NAND-type flash memory to generate unique data and output it to the outside. The semiconductor device of the present invention may be a NAND-type flash memory itself, or a semiconductor circuit having other functions.

[實施例] [Example]

第1圖顯示本發明實施例的NAND型快閃記憶體的構造。本實施例的快閃記憶體100包括：記憶胞陣列110，由配置成行列狀的複數記憶胞所形成；輸出入緩衝器120，連接至外部輸出入端子 I/O並保持輸出入資料；位址暫存器130，接收來自輸出入緩衝器120的位址資料；控制器140，根據來自輸出入緩衝器120的指令資料和外部的控制信號(CLE、ALE等)來供給控制各部；字元線選擇電路150，根據來自位址暫存器130的列位址資訊Ax來進行塊的選擇以及頁的選擇等；分頁緩衝器/感測器160，保持從選擇的頁所讀出的資料以及保持要程式化到被選擇的頁的資料；行選擇電路170，根據來自位址暫存器130的行位址資訊Ay來進行分頁緩衝器/感測電路160內的資料的選擇；內部電壓產生電路180，產生資料的讀出、程式化、抹除等所需要的電壓(寫入電壓Vpgm、通過電壓Vpass、抹除電壓Vers、讀出電壓Vread等)。 FIG. 1 shows a structure of a NAND flash memory according to an embodiment of the present invention. The flash memory 100 in this embodiment includes: a memory cell array 110 formed by a plurality of rows and columns of memory cells; an input / output buffer 120 connected to an external input / output terminal I / O and hold input / output data; address register 130 receives address data from input / output buffer 120; controller 140, according to instruction data from input / output buffer 120 and external control signals (CLE, ALE, etc.) to supply and control each unit; the character line selection circuit 150 performs block selection and page selection based on the column address information Ax from the address register 130; the page buffer / sensor 160 holds The data read from the selected page and the data to be programmed to the selected page are maintained; the row selection circuit 170 performs a page buffer / sensing circuit based on the row address information Ay from the address register 130 Selection of data in 160; internal voltage generation circuit 180 generates voltages required for data reading, programming, erasing (write voltage Vpgm, pass voltage Vpass, erase voltage Vers, read voltage Vread, etc.) .

記憶胞陣列110在行方向具有m個記憶體塊BLK(0)、BLK(1)、…、BLK(m-1)，一個記憶體塊如第2圖所示形成有複數的NAND串列。一個NAND串列包括串聯的複數個記憶胞MCi(i=0、1、…、62、63)、連接於記憶胞MC63的汲極側的位元線選擇電晶體TR1、以及連接於記憶胞MC0的源極側的源極線選擇電晶體TR2。記憶胞MCi的控制閘連接到對應的字元線WLi，位元線側選擇電晶體TR1的閘極連接到選擇閘極線SGD，源極線側選擇電晶體TR2的閘極連接到選擇閘極線SGS。字元線選擇電路150在各動作狀態時，根據列位址Ax透過選擇閘極信號SGD、SGS，選擇地驅動選擇閘極電晶體TR1、TR2。 The memory cell array 110 has m memory blocks BLK (0), BLK (1),... BLK (m-1) in the row direction, and one memory block is formed with a plurality of NAND strings as shown in FIG. 2. A NAND string includes a plurality of memory cells MCi (i = 0, 1, ..., 62, 63) connected in series, a bit line selection transistor TR1 connected to the drain side of the memory cell MC63, and a memory cell MC0 The source line on the source side selects the transistor TR2. The control gate of the memory cell MCi is connected to the corresponding word line WLi, the gate of the bit line selection transistor TR1 is connected to the selection gate line SGD, and the gate of the source line selection transistor TR2 is connected to the selection gate Line SGS. In each operating state, the word line selection circuit 150 selectively drives the selection gate transistors TR1 and TR2 through the selection gate signals SGD and SGS according to the column address Ax.

NAND字串可以是形成於基板表面的2次元陣列狀，也可以是利用形成於基板表面上的半導體層的3次元陣列狀。又，一個記 憶胞可以是儲存一個位元(2值資料)的SLC形式，也可以是儲存多個位元的MLC形式。 The NAND string may be in a two-dimensional array shape formed on the substrate surface, or may be a three-dimensional array shape using a semiconductor layer formed on the substrate surface. Again, a note The memory cell can be in the form of SLC that stores one bit (binary data), or in the form of MLC that stores multiple bits.

各個塊的各個NAND字串會透過位元線選擇電晶體TR1連接到通用位元線GBL0、GBL1、…GBLn，通用位元線GBL0、GBL1、…GBLn連接到分頁緩衝器/感測電路160。各通用位元線例如由金屬配線構成，從記憶胞陣列110的塊(0)朝向塊(m-1)延伸。 Each NAND string of each block is connected to the general bit lines GBL0, GBL1, ... GBLn through the bit line selection transistor TR1, and the general bit lines GBL0, GBL1, ... GBLn are connected to the paging buffer / sensing circuit 160. Each general-purpose bit line is made of, for example, a metal wiring, and extends from the block (0) to the block (m-1) of the memory cell array 110.

接著，說明分頁緩衝器160。分頁緩衝器160如第3圖所示，包括選擇偶數通用位元線或奇數通用位元線用的位元線選擇電路200。第3圖顯示包括連接到一個NAND串列NU的偶數位元線GBL_e與連接到一個NAND串列NU的奇數位元線GBL_o的一對的通用位元線。位元線選擇電路200在讀出時或程式化時，選擇偶數位元線GBL_e或者是奇數位元線GBL_o，將選擇的偶數位元線GBL_e或者是奇數位元線GBL_o電性連接到分頁緩衝器/感測電路160的感測電路(感測節點SNS)。也就是說，分頁緩衝器/感測電路160雖然對應一頁的量，但一個分頁緩衝器/感測電路160會被一對的偶數位元線GBL_e及奇數位元線GBL_o所共用。 Next, the page buffer 160 will be described. As shown in FIG. 3, the page buffer 160 includes a bit line selection circuit 200 for selecting even-numbered general-purpose bit lines or odd-numbered general-purpose bit lines. FIG. 3 shows a pair of general-purpose bit lines including an even bit line GBL_e connected to one NAND string NU and an odd bit line GBL_o connected to one NAND string NU. The bit line selection circuit 200 selects the even bit line GBL_e or the odd bit line GBL_o during reading or programming, and electrically connects the selected even bit line GBL_e or the odd bit line GBL_o to the paging buffer. Sensor / sensing circuit 160 (sensing node SNS). That is, although the page buffer / sensing circuit 160 corresponds to the amount of one page, one page buffer / sensing circuit 160 is shared by a pair of even bit lines GBL_e and odd bit lines GBL_o.

位元線選擇電路200包括：位元線選擇電晶體BLS，在讀出時電性連接到感測節點SNS；偶數選擇電晶體SEL_e，串聯連接到位元線選擇電晶體BLS的節點N1與偶數位元線GBL_e之間；奇數選擇電晶體SEL_o，串聯連接到位元線選擇電晶體BLS的節點N1與奇數位元線GBL_o之間；偶數偏壓選擇電晶體YSEL_e，連接於偶數位元 線GBL_e與假想電位VPRE之間；以及奇數偏壓選擇電晶體YSEL_o，連接於奇數位元線GBL_o與假想電位VPRE之間。 The bit line selection circuit 200 includes: a bit line selection transistor BLS, which is electrically connected to the sensing node SNS during reading; an even-numbered selection transistor SEL_e, which is connected in series to the node N1 of the bit-line selection transistor BLS and the even bits Between the element lines GBL_e; the odd selection transistor SEL_o is connected in series between the node N1 of the bit line selection transistor BLS and the odd bit line GBL_o; the even bias selection transistor YSEL_e is connected to the even bits The line GBL_e and the virtual potential VPRE; and the odd bias selection transistor YSEL_o are connected between the odd bit line GBL_o and the virtual potential VPRE.

位元線選擇電晶體BLS、偶數選擇電晶體SEL_e、奇數選擇電晶體SEL_o、偶數偏壓選擇電晶體YSEL_e、奇數偏壓選擇電晶體YSEL_o是由NMOS電晶體構成，各個閘極會被施加來自連接器140的控制信號。又，假想電位VPRE會因為控制器140的控制，而被內部電壓產生電路180供給因應動作狀態的各種偏壓電壓或預充電壓。 The bit line selection transistor BLS, the even selection transistor SEL_e, the odd selection transistor SEL_o, the even bias selection transistor YSEL_e, and the odd bias selection transistor YSEL_o are composed of NMOS transistors, and each gate is applied from the connection Control signal of the controller 140. In addition, due to the control of the controller 140, the virtual potential VPRE is supplied with various bias voltages or precharge voltages according to the operating state by the internal voltage generating circuit 180.

例如，在讀出動作中，進行偶數頁的讀出時，偶數選擇電晶體SEL_e、位元線選擇電晶體BLS導通，奇數選擇電晶體SEL_o非導通，偶數位元線GBL_e被選擇，奇數位元線GBL_o不被選擇。又，偶數偏壓選擇電晶體YSEL_e非導通，奇數偏壓選擇電晶體YSEL_o導通，不被選擇的奇數位元線GBL_o會被從供給假想電位VPRE供給GND。另一方面，進行奇數頁的讀出時，奇數選擇電晶體SEL_o、位元線選擇電晶體BLS導通，偶數選擇電晶體SEL_e非導通，奇數位元線GBL_o被選擇，偶數位元線GBL_e不被選擇。又，奇數偏壓選擇電晶體YSEL_o非導通，偶數偏壓選擇電晶體YSEL_e導通，不被選擇的偶數位元線GBL_e會被從供給假想電位VPRE供給GND。這樣一來，進行偶數頁及奇數頁的位元線屏蔽讀出。 For example, in the read operation, when reading even pages, the even selection transistor SEL_e and the bit line selection transistor BLS are turned on, the odd selection transistor SEL_o is not turned on, the even bit line GBL_e is selected, and the odd bits The line GBL_o is not selected. Also, the even-numbered bias selection transistor YSEL_e is non-conductive, the odd-numbered bias selection transistor YSEL_o is conductive, and the unselected odd-numbered bit line GBL_o is supplied from the supply virtual potential VPRE to GND. On the other hand, when reading an odd page, the odd selection transistor SEL_o and the bit line selection transistor BLS are turned on, the even selection transistor SEL_e is not turned on, the odd bit line GBL_o is selected, and the even bit line GBL_e is not turned on. select. In addition, the odd bias selection transistor YSEL_o is non-conductive, the even bias selection transistor YSEL_e is conductive, and the unselected even bit line GBL_e is supplied from the virtual potential VPRE to GND. In this way, the bit line mask reading of even pages and odd pages is performed.

又，程式化時，會交互地進行偶數頁與奇數頁的程式化，不被選擇的頁會被假想電位VPRE供給用來抑制程式化干擾的電壓。 In programming, programming of even pages and odd pages is performed interactively, and pages that are not selected are supplied with voltages for suppressing programmatic interference by the virtual potential VPRE.

第4圖係一個分頁緩衝器/感測電路160的一例。分頁緩衝器/感測電路160的構造包括：電晶體BLPRE，用以將電壓供給部V1供給的電壓預充到位元線；電晶體BLCLAMP，用來箝制位元線；感測節點SNS；電晶體BLCD，傳送感測節點SNS與拴鎖節點N2之間的電荷；拴鎖電路，連接到拴鎖節點N2。電晶體BLCLAMP連接到位元線選擇電路200的位元線選擇電路200的位元線選擇電晶體BLS。 FIG. 4 is an example of a paging buffer / sensing circuit 160. The structure of the paging buffer / sensing circuit 160 includes: a transistor BLPRE to precharge the voltage supplied by the voltage supply unit V1 to the bit line; a transistor BLCLAMP to clamp the bit line; a sensing node SNS; a transistor The BLCD transmits the charge between the sensing node SNS and the latch node N2; the latch circuit is connected to the latch node N2. The transistor BLCLAMP is connected to the bit line selection circuit 200 of the bit line selection circuit 200 of the bit line selection circuit 200.

讀出動作時，從電壓供給部V1供給的預充電壓會透過電晶體BLPRE、BLCLAMP施加給被位元線選擇電路200選擇的偶數位元線GBL_e或者是奇數位元線GBL_o。之後，選擇字元線被施加讀出電壓，不被選擇的字元線被施加讀出通過電壓，選擇字元線的記憶胞開啟的話，通用位元線的預充電壓會放電到源極線SL，感測節點SNS成為GND位準。記憶胞關閉的話，通用位元線會與源極線SL隔離，感測節點SNS被保持在預充電壓。感測節點SNS的電荷透過電晶體BLCD被傳送到節點N2，拴鎖電路LAT藉由節點N2的電位而保持H或L位準。 During the read operation, the precharge voltage supplied from the voltage supply unit V1 is applied to the even bit line GBL_e or the odd bit line GBL_o selected by the bit line selection circuit 200 through the transistors BLPRE and BLCLAMP. After that, a read voltage is applied to the selected word line, and a read pass voltage is applied to the unselected word line. When the memory cell of the selected word line is turned on, the precharge voltage of the general-purpose bit line is discharged to the source line. SL, the sensing node SNS becomes the GND level. When the memory cell is closed, the universal bit line is isolated from the source line SL, and the sensing node SNS is maintained at a precharge voltage. The charge of the sensing node SNS is transmitted to the node N2 through the transistor BLCD, and the latch circuit LAT maintains the H or L level by the potential of the node N2.

第5圖係顯示本實施例的固有資料產生電路的一例。固有資料產生電路300會連接到分頁緩衝器/感測電路160，當記憶胞陣列110的特定的區域被讀出時，檢測出連接到鄰接的一對的通用位元線的感測節點的電位差，利用這個檢測結果產生固有資料並將其輸出。 Fig. 5 shows an example of a unique data generating circuit of this embodiment. The inherent data generating circuit 300 is connected to the paging buffer / sensing circuit 160. When a specific area of the memory cell array 110 is read out, the potential difference of the sensing nodes connected to the adjacent pair of universal bit lines is detected. Use this test result to generate inherent data and output it.

具體來說，固有資料產生電路300包括連接到鄰接的分頁緩衝器PB_0、PB_1的差動感測放大器310_0、連接到鄰接的分頁緩衝器PB_2、PB_3的差動感測放大器310_1、…、連接到鄰接的分 頁緩衝器PB_n-1、PB_n的差動感測放大器310_n-1/2(總稱差動放大器時為差動放大器310)。分頁緩衝器/感測電路160的數目是一頁的話，差動感測放大器310的數目是1/2頁。 Specifically, the inherent data generating circuit 300 includes a differential sense amplifier 310_0 connected to adjacent page buffers PB_0, PB_1, a differential sense amplifier 310_1, ... connected to adjacent page buffers PB_2, PB_3, ... Minute Differential sense amplifiers 310_n-1 / 2 of the page buffers PB_n-1 and PB_n (differential amplifier 310 when the differential amplifier is collectively referred to). If the number of page buffers / sensing circuits 160 is one page, the number of differential sense amplifiers 310 is 1/2 page.

差動感測放大器310_0檢測出分頁緩衝器PB_0的感測節點SNS_0以及與其鄰接的分頁緩衝器PB_1的感測節點SNS_1的電位差，將表示這個檢出結果的資料Dout_0輸出。其他的差動感測放大器310也同樣地，檢測出鄰接的分頁緩衝器的感測節點的電位差，將表示該檢出結果的資料Dout_1、…、Dout_n-1/2輸出。當偶數位元線被位元線選擇電路200選擇的情況下，差動感測放大器310檢測出連接到鄰接的偶數位元線的感測節點的電位差，又，當奇數位元線被位元線選擇電路200選擇的情況下，差動感測放大器310檢測出連接到鄰接的奇數位元線的感測節點的電位差。差動感測放大器310在固有資料產生時，被控制器140所活性化。 The differential sense amplifier 310_0 detects the potential difference between the sensing node SNS_0 of the paging buffer PB_0 and the sensing node SNS_1 of the paging buffer PB_1 adjacent thereto, and outputs data Dout_0 indicating the detection result. Similarly, other differential sense amplifiers 310 detect the potential difference between the sensing nodes of the adjacent page buffers, and output data Dout_1,..., Dout_n-1 / 2 indicating the detection results. When the even bit line is selected by the bit line selection circuit 200, the differential sense amplifier 310 detects the potential difference between the sensing nodes connected to the adjacent even bit line, and when the odd bit line is selected by the bit line, When the selection circuit 200 selects, the differential sense amplifier 310 detects a potential difference between the sensing nodes connected to the adjacent odd-numbered bit lines. When the unique data is generated, the differential sense amplifier 310 is activated by the controller 140.

第6圖係顯示在快閃記憶體的各動作時施加的偏壓電壓的一例的表。讀出動作中，施加某個正電壓到位元線，施加某個讀出電壓(例如0V)到選擇字元線，施加讀出通過電壓Vpass(例如4.5V)到不被選擇的字元線，施加正的電壓(例如4.5V)到選擇閘極線SGD、SGS，將NAND串列的位元線側選擇電晶體、源極線側選擇電晶體導通，施加0V至共通源極線。程式化(寫入)動作中，會施加高電壓的程式化電壓Vpgm(15~20V)到被選擇的字元線，施加中間電位(例如10V)到不被選擇的字元線，將位元線側選擇電晶體導通，將源極線側選擇電晶體關閉，將對應到「0」或者是「1」的資料的電位供給 到位元線。抹除動作中，施加0V至塊內被選擇的字元線，施加高電壓(例如20V)至P井，將浮動閘極的電子抽出到基板上，藉此以塊為單位抹除資料。關於產生固有資料時的偏壓將在後述。 FIG. 6 is a table showing an example of a bias voltage applied during each operation of the flash memory. In the read operation, a certain positive voltage is applied to the bit line, a certain read voltage (for example, 0V) is applied to the selected word line, and a read pass voltage Vpass (for example, 4.5V) is applied to the unselected word line. A positive voltage (for example, 4.5V) is applied to the selection gate lines SGD and SGS, the bit line side selection transistor and the source line side selection transistor of the NAND string are turned on, and 0V is applied to the common source line. In the programming (writing) operation, a high-voltage programming voltage Vpgm (15-20V) is applied to the selected word line, and an intermediate potential (for example, 10V) is applied to the unselected word line. The line-side selection transistor is turned on, the source line-side selection transistor is turned off, and the potential of the data corresponding to "0" or "1" is supplied Line of bits. In the erasing operation, 0V is applied to the selected word line in the block, high voltage (for example, 20V) is applied to the P well, and the electrons of the floating gate are extracted to the substrate, thereby erasing data in units of blocks. The bias at the time of generating unique data will be described later.

接著，說明本實施型態的NAND型快閃記憶體的固有資料的產生動作。第7圖係用來說明固有資料的產生動作的流程圖。控制器140例如是由能夠執行軟體程式的微電腦或是狀態機所構成。控制器140根據來自外部控制信號或來自外部的指令，除了一般的讀出動作、程式化動作、以及抹除動作的控制外，還會控制固有資料的產生。 Next, an operation of generating unique data of the NAND-type flash memory according to this embodiment will be described. Fig. 7 is a flowchart for explaining the operation of generating unique data. The controller 140 is configured by, for example, a microcomputer or a state machine capable of executing software programs. The controller 140 controls the generation of unique data in addition to the control of a general read operation, a programmed operation, and an erase operation according to an external control signal or an external command.

在某個實施態樣中，控制器140具有判定是否要執行固有資料的產生的功能(S100)。例如，控制器140接收到來自外部的指示固有資料的產生的指令時，執行固有資料的產生。或者是，控制器140在執行電源載入時的開機程序時，或者是執行預先決定的動作時，執行固有資料的產生。 In one embodiment, the controller 140 has a function of determining whether or not to generate the unique data (S100). For example, when the controller 140 receives an instruction from the outside to instruct generation of specific data, the controller 140 executes generation of the specific data. Alternatively, the controller 140 executes the generation of the unique data when the power-on procedure is performed when the power is loaded, or when a predetermined action is performed.

控制器140在判定要執行固有資料的產生的情況下，會透過字元線選擇電路150開始記憶胞陣列110的虛擬陣列的讀出(S110)。虛擬陣列是記憶胞陣列上適合產生固有資料的特定區域，用來預先選擇虛擬陣列的位址資訊會除存在控制器140的記憶體等。在某個實施型態中，虛擬陣列如第8圖所示，被設定在距離分頁緩衝器/感測電路160最遠端的塊BLK(m-1)或者是其附近的塊。換言之，虛擬陣列DA是將塊與分頁緩衝器/感測電路160連接的通用位元線的配線長度最長的區域。又，虛擬陣列DA可以是使用者所不能存取的區域，也可以是利用使用者能夠存取的記憶體的區域。 When the controller 140 determines that the generation of the unique data is to be performed, the controller 140 starts the reading of the virtual array of the memory cell array 110 through the word line selection circuit 150 (S110). The virtual array is a specific area on the memory cell array suitable for generating inherent data. The address information used to select the virtual array in advance is stored in the memory of the controller 140 and the like. In an implementation form, as shown in FIG. 8, the virtual array is set at a block BLK (m-1) at the farthest end from the paging buffer / sensing circuit 160 or a block near it. In other words, the virtual array DA is an area where the wiring length of the general-purpose bit line connecting the block to the paging buffer / sensing circuit 160 is the longest. The virtual array DA may be an area that cannot be accessed by a user, or an area that uses a memory that the user can access.

最遠端的塊BLK(m-1)比起其他的塊來說，通用位元線的配線長度長，因此配線的不均(例如線寬、膜厚、間距等)會大大地影響到配線的RC值(時間常數)。因此，鄰接的位元線之間，充放電的特性容易產生很大的差異。 The farthest block BLK (m-1) has a longer wiring length than the other general-purpose bit lines. Therefore, uneven wiring (such as line width, film thickness, and pitch) will greatly affect the wiring. RC value (time constant). Therefore, the characteristics of charge and discharge between adjacent bit lines are likely to vary greatly.

虛擬陣列DA的讀出與一般的讀出同樣地，被位元線選擇電路200所選擇的偶數位元線或者是奇數位元線被預充，不被選擇的奇數位元線或者是偶數位元線被供給GND。預充後，字元線選擇電路150對最為虛擬陣列DA而被選擇的塊的全部字元線，施加無關於記憶胞的記憶狀態並且記憶胞開啟的通過電壓Vpuf。也就是說，通過電壓Vpuf如第9圖所示，是比抹除記憶胞(資料「1」)以及程式化記憶胞(資料「0」)導通時的閾值更高許多的電壓。另外，通過電壓Vpuf也可以是與讀出動作時施加給不被選擇的字元線的通過電壓相同的位準(參照第6圖)。 The reading of the virtual array DA is the same as the general reading. The even bit lines or odd bit lines selected by the bit line selection circuit 200 are precharged, and the unselected odd bit lines or even bits are precharged. The element line is supplied to GND. After pre-charging, the word line selection circuit 150 applies a pass voltage Vpuf to all the word lines of the block selected as the virtual array DA regardless of the memory state of the memory cell and the memory cell is turned on. That is, as shown in FIG. 9, the pass voltage Vpuf is a voltage much higher than the threshold when the erased cell (data “1”) and the programmed memory cell (data “0”) are turned on. The pass voltage Vpuf may be at the same level as the pass voltage applied to the unselected word line during a read operation (see FIG. 6).

虛擬陣列DA會被施加通過電壓Vpuf，因此虛擬陣列DA的全部的記憶胞開啟，而通用位元線的預充電壓，也就是感測節點sns的電壓會透過NAND串列放電到GND位準的源極線SL。與此感測的同時，藉由連接到感測節點SNS的差動感測放大器300，鄰接的位元線對的電位差會被檢出(S120)。例如，當SNSk>SNSk+1的話，差動感測放大器300會輸出「0」做為Dout_k；當SNSk≦SNSk+1的話，差動感測放大器300會輸出「1」做為Dout_k。 The virtual array DA is applied with the passing voltage Vpuf, so all the memory cells of the virtual array DA are turned on, and the precharge voltage of the general-purpose bit line, that is, the voltage of the sensing node sns is discharged to the GND level through the NAND string. Source line SL. At the same time as the sensing, with the differential sense amplifier 300 connected to the sensing node SNS, the potential difference of the adjacent bit line pairs is detected (S120). For example, when SNSk> SNSk + 1, the differential sense amplifier 300 outputs “0” as Dout_k; when SNSk ≦ SNSk + 1, the differential sense amplifier 300 outputs “1” as Dout_k.

控制器140藉由虛擬陣列DA的讀出而檢出位元線對的電位差後，會根據其檢出結果輸出固有資料到外部(S130)。產生固 有資料時，虛擬陣列DA的讀出可以是偶數位元線或者是奇數位元線的任一者，也可以是偶數位元線與奇數位元線雙方。固有資料的輸出方法是任意的，例如可以將檢出的全部的資料輸出，也可以將行選擇電路170所預先決定的位元線或者是位元數的資料輸出。又，也可以因應NAND型快閃記憶體的輸出入端子，來調整要輸出的固有資料的位元數。又，NAND型快閃記憶體搭載SPI(Serial Peripheral Interface)功能的情況下。可以與外部序列時脈同步來輸出固有資料。 After the controller 140 detects the potential difference of the bit line pair by reading out the virtual array DA, it outputs the unique data to the outside according to the detection result (S130). Produce solid When there is data, the readout of the virtual array DA can be any of the even bit lines or the odd bit lines, or it can be both the even bit lines and the odd bit lines. The method of outputting the unique data is arbitrary, and for example, all the detected data may be output, or a bit line or a number of bits of data determined in advance by the row selection circuit 170 may be output. In addition, the number of bits of the unique data to be output may be adjusted in accordance with the input / output terminals of the NAND flash memory. When the NAND flash memory is equipped with a Serial Peripheral Interface (SPI) function. The inherent data can be output in synchronization with the external sequence clock.

根據本實施例，在虛擬陣列的讀出時檢出位元線對的電位差，產生半導體裝置的固有資料，因此能夠藉由比較簡單的構造來獲得重現性高的非預測性的固有資料。 According to this embodiment, the potential difference between the bit line pairs is detected during the reading of the virtual array, and unique data of the semiconductor device is generated. Therefore, it is possible to obtain non-predictive unique data with high reproducibility by a relatively simple structure.

接著，說明本發明的其他的實施例。第10圖顯示其他實施例的固有資料產生電路300A的構造。本實施例中，固有資料產生電路300A具備會接收複數的差動感測放大器310_0、310_1、...、300_n-1/2的輸出資料Dout_0、Dout_1、...、Dout_n-1/2，並將這些資料做計算處理的計算電路320。計算電路320可以例如將差動感測放大器310的輸出資料的一部分遮蔽(mask)，或者是將輸出資料編碼化(壓縮)，或者是邏輯運算偶數位元的輸出資料及奇數位元的輸出資料，將結果做為固有資料Dout_x輸出。 Next, other embodiments of the present invention will be described. FIG. 10 shows a structure of a unique data generating circuit 300A of another embodiment. In this embodiment, the unique data generating circuit 300A is provided with output data Dout_0, Dout_1, ..., Dout_n-1 / 2 that receive complex differential sense amplifiers 310_0, 310_1, ..., 300_n-1 / 2, and A calculation circuit 320 that performs these calculations on these data. The computing circuit 320 may, for example, mask a part of the output data of the differential sense amplifier 310, or encode (compress) the output data, or logically output the output data of even bits and the output data of odd bits. The result is output as the inherent data Dout_x.

上述實施例中，產生固有資料時，會師加通過電壓到虛擬陣列DA的全部字元線來進行讀出，但也可以只讀出虛擬陣列DA的特定的頁。特定的頁能夠設定WL0~WL63的任意頁，特定的頁的選擇字元線會施加與一般的讀出時相同的讀出電壓(例如0V)，除此之 外的不被選擇的字元線會被施加通過電壓Vpuf(例如4.5V)。在這個情況下，特定的頁的記憶胞需要被設定為儲存資料「1」的抹除記憶胞。藉此，能夠在與一般的讀出動作相同的偏壓條件下，進行用以產生固有資料的讀出。 In the above-mentioned embodiment, when the unique data is generated, the reading is applied by applying voltage to all the word lines of the virtual array DA, but a specific page of the virtual array DA may also be read out. Any page can be set to any page from WL0 to WL63. The selected word line of the specific page will be applied with the same read voltage (for example, 0V) as in normal read. The unselected word lines are applied with a pass voltage Vpuf (for example, 4.5V). In this case, the memory cell of a specific page needs to be set as the erase memory cell storing the data "1". Thereby, it is possible to perform reading for generating unique data under the same bias condition as in a normal reading operation.

上述實施例中，差動感測放大器310在讀出時檢測出鄰接的位元線間的電位差，但這只是一例，也可以是其他的態樣。例如，差動感測感放大器310也可以檢測出第偶數個的分頁緩衝器/感測電路的各感測節點，與第奇數個的分頁緩衝器/感測電路的各感測節點的電位差，除此之外，也可以按照預先決定的規則，檢測出被選擇的分頁緩衝器/感測電路的各感測節點的電位差。 In the above embodiment, the differential sense amplifier 310 detects the potential difference between adjacent bit lines during reading, but this is only an example, and other aspects are also possible. For example, the differential sense amplifier 310 can also detect the potential difference between each sensing node of the even-numbered paging buffer / sensing circuit and the sensing node of the odd-numbered paging buffer / sensing circuit. In addition, the potential difference of each sensing node of the selected paging buffer / sensing circuit may be detected according to a predetermined rule.

又，上述實施例中，雖然顯示了分頁緩衝器/感測電路160對應1頁的量，差動感測放大器310對應1/2頁的量的例子，但差動感測放大器310的數目是任意，只要能夠獲得做為固有資料的非預測性(隨機性)的話，也可以是比1/2頁更少的數字。 Moreover, in the above embodiment, although the example in which the page buffer / sensing circuit 160 corresponds to an amount of one page and the differential sense amplifier 310 corresponds to an amount of 1/2 page is shown, the number of differential sense amplifiers 310 is arbitrary. As long as the non-predictability (randomness) can be obtained as the inherent data, the number may be smaller than 1/2 page.

又上述實施例中，顯示了位元線選擇電路所選擇的偶數位元線或者是奇數位元線的遮蔽讀出的例子，但本發明中遮蔽讀出並非必須。在這個情況下，選擇頁的讀出會以全部位元線來進行，差動感測放大器可以檢出物理上鄰接的偶數位元線與奇數位元線的電位差。 Also in the above embodiment, the example of the masked readout of the even bit line or the odd bit line selected by the bit line selection circuit is shown, but the masked readout is not necessary in the present invention. In this case, the reading of the selection page is performed with all bit lines, and the differential sense amplifier can detect the potential difference between the physically adjacent even-numbered bit lines and the odd-numbered bit lines.

又，上述實施例中，做為連接到虛擬陣列DA的字元線之單元是以記憶胞為例，但本發明中也可以使用一般的MOS電晶體來取代記憶胞。也就是說，構成虛擬陣列DA的NAND串列的一部分或者 全部的記憶胞可以被置換成一般的MOS電晶體。在此，一般的MOS電晶體是指因為程式化或抹除而導通時的閾值不會變動的MOS電晶體。代表性的MOS電晶體有描繪型，增強型或內在型，使用任一種MOS電晶體來替代記憶胞也能夠進行用來產生固有資料的讀出。 Moreover, in the above embodiment, the memory cell is used as a unit of the word line connected to the virtual array DA. However, in the present invention, a general MOS transistor may be used instead of the memory cell. That is, a part of the NAND string constituting the virtual array DA or All memory cells can be replaced with ordinary MOS transistors. Here, a general MOS transistor refers to a MOS transistor whose threshold value does not change when it is turned on due to programming or erasing. The representative MOS transistor has a drawing type, an enhanced type, or an intrinsic type. Using any kind of MOS transistor instead of a memory cell can also be used to read out the inherent data.

雖然詳述了本發明較佳的實施型態，但本發明並不限定於特定的實施型態，在申請專利範圍所記載的發明要旨的範圍內，能夠做各式各樣的變形與變更。 Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to a specific embodiment, and various modifications and changes can be made within the scope of the gist of the invention described in the scope of the patent application.

Claims (11)

一種半導體裝置，包括：記憶體陣列，包括NAND型串列；選擇構件，選擇該記憶體陣列的特定區域；讀出構件，讀出該選擇構件所選擇的特定的區域；檢出構件，檢測出該讀出構件所讀出的特定的區域的位元線對的電位差；產生構件，根據該檢出構件的檢出結果產生半導體裝置的固有資料；以及控制構件，控制固有資料的產生，其中該控制構件在開機程序時或者是回應外部的要求，控制該選擇構件、該讀出構件、該檢出構件以及該產生構件，產生該固有資料。A semiconductor device includes: a memory array including a NAND-type string; a selection member that selects a specific area of the memory array; a readout member that reads out a specific area selected by the selection member; a detection member that detects A potential difference of a bit line pair in a specific area read by the readout means; a generating means that generates specific data of the semiconductor device according to a detection result of the detection means; and a control means that controls the generation of the specific data, wherein the The control component controls the selection component, the readout component, the detection component, and the generation component to generate the inherent data during a startup procedure or in response to an external request. 如申請專利範圍第1項所述之半導體裝置，其中該特定的區域是物理上距離該讀出構件最遠端的塊。The semiconductor device according to item 1 of the patent application scope, wherein the specific area is a block physically farthest from the readout member. 如申請專利範圍第1項所述之半導體裝置，其中該特定的區域是物理上距離該讀出構件最遠端的塊所包含的頁。The semiconductor device according to item 1 of the scope of patent application, wherein the specific area is a page contained in a block physically farthest from the readout member. 如申請專利範圍第1項所述之半導體裝置，其中該特定的區域是使用者無法存取的區域。The semiconductor device according to item 1 of the scope of patent application, wherein the specific area is an area inaccessible to a user. 如申請專利範圍第1項所述之半導體裝置，其中該特定的區域是連接到NAND型串列的MOS電晶體。The semiconductor device according to item 1 of the scope of patent application, wherein the specific region is a MOS transistor connected to a NAND type string. 如申請專利範圍第2或3項所述之半導體裝置，其中該選擇構件會施加無關於記憶胞的記憶狀態並且導通記憶胞的電壓至選擇的塊內的全部字元線上。The semiconductor device according to item 2 or 3 of the scope of the patent application, wherein the selection member applies a memory state irrespective of the memory cell and turns on the voltage of the memory cell to all character lines in the selected block. 如申請專利範圍第1至5項任一項所述之半導體裝置，其中該檢出構件電性連接到該讀出構件的感測節點，該檢出構件包括用來檢測出該感測節點的電位差的差動感測放大器。The semiconductor device according to any one of claims 1 to 5, wherein the detecting member is electrically connected to a sensing node of the reading member, and the detecting member includes a detecting node for detecting the sensing node. Potential difference differential sense amplifier. 如申請專利範圍第1至5項任一項所述之半導體裝置，其中該位元線對是在讀出動作時鄰接的位元線。The semiconductor device according to any one of claims 1 to 5, wherein the bit line pair is a bit line adjacent to each other during a read operation. 如申請專利範圍第1至5項任一項所述之半導體裝置，其中該讀出構件進行偶數位元線或奇數位元線的讀出時，該位元線對是鄰接的偶數位元線或者是奇數位元線。The semiconductor device according to any one of claims 1 to 5, wherein when the readout means reads out an even bit line or an odd bit line, the bit line pair is an adjacent even bit line Or an odd bit line. 如申請專利範圍第1至5項任一項所述之半導體裝置，其中該位元線對是依照預先決定的規則而選擇的位元線。The semiconductor device according to any one of claims 1 to 5, wherein the bit line pair is a bit line selected according to a predetermined rule. 如申請專利範圍第1至5項任一項所述之半導體裝置，其中該產生構件包括計算電路，用來計算表示該檢出構件的檢出結果的資料，該產生構件將該計算電路的計算結果做為固有資料輸出。The semiconductor device according to any one of claims 1 to 5, wherein the generating component includes a calculation circuit for calculating data representing a detection result of the detection component, and the generation component calculates the calculation of the calculation circuit. The results are output as inherent data.