TWI659404B - Display device - Google Patents
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- TWI659404B TWI659404B TW107102731A TW107102731A TWI659404B TW I659404 B TWI659404 B TW I659404B TW 107102731 A TW107102731 A TW 107102731A TW 107102731 A TW107102731 A TW 107102731A TW I659404 B TWI659404 B TW I659404B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
一種顯示裝置包括：一源極驅動器、一多工器、以及一控制器。源極驅動器用以根據一觸發訊號，依序輸出一第一資料電壓及一第二資料電壓。多工器用以接收該第一資料電壓及該第二資料電壓，並根據一第一多工訊號及一第二多工訊號，依序輸出該第一資料電壓及該第二資料電壓至不同資料線。控制器用以產生一控制訊號，以控制該第一多工訊號的一中止時間點與該第二多工訊號的一開始時間點彼此大致相同，並用以控制該源極驅動器相應於該控制訊號停止輸出該第一資料電壓。 A display device includes: a source driver, a multiplexer, and a controller. The source driver is configured to sequentially output a first data voltage and a second data voltage according to a trigger signal. A multiplexer is used to receive the first data voltage and the second data voltage, and sequentially output the first data voltage and the second data voltage to different data according to a first multiplex signal and a second multiplex signal. line. The controller is used to generate a control signal to control a suspension time point of the first multiplex signal and a start time point of the second multiplex signal to be substantially the same as each other, and to control the source driver to stop corresponding to the control signal The first data voltage is output.
Description
本案涉及一種電子裝置。具體而言，本案涉及一種顯示裝置。 This case relates to an electronic device. Specifically, the present application relates to a display device.
隨著科技的發展，顯示裝置已廣泛地應用在人們的生活當中。 With the development of technology, display devices have been widely used in people's lives.
典型的顯示裝置，可包括閘極驅動器、源極驅動器、與像素電路。閘極驅動器用以提供閘極訊號至像素電路，以令像素電路之開關開啟。源極驅動器用以提供資料電壓至開關開啟的像素電路，以令像素電路相應於資料電壓進行顯示。 A typical display device may include a gate driver, a source driver, and a pixel circuit. The gate driver is used to provide a gate signal to the pixel circuit, so that the switch of the pixel circuit is turned on. The source driver is used to provide the data voltage to the pixel circuit with the switch turned on, so that the pixel circuit performs display corresponding to the data voltage.
本案一實施態樣涉及一種顯示裝置。根據本案一實施例，顯示裝置的源極驅動器包括：一源極驅動器、一多工器、以及一控制器。源極驅動器用以根據一觸發訊號，依序輸出一第一資料電壓及一第二資料電壓。多工器 用以接收該第一資料電壓及該第二資料電壓，並根據一第一多工訊號及一第二多工訊號，依序輸出該第一資料電壓及該第二資料電壓至不同資料線。控制器用以產生一控制訊號，以控制該第一多工訊號的一中止時間點與該第二多工訊號的一開始時間點彼此大致相同，並用以控制該源極驅動器相應於該控制訊號停止輸出該第一資料電壓。 An embodiment of the present invention relates to a display device. According to an embodiment of the present invention, the source driver of the display device includes a source driver, a multiplexer, and a controller. The source driver is configured to sequentially output a first data voltage and a second data voltage according to a trigger signal. Multiplexer It is used to receive the first data voltage and the second data voltage, and sequentially output the first data voltage and the second data voltage to different data lines according to a first multiplex signal and a second multiplex signal. The controller is used to generate a control signal to control a suspension time point of the first multiplex signal and a start time point of the second multiplex signal to be substantially the same as each other, and to control the source driver to stop corresponding to the control signal The first data voltage is output.
本案另一實施態樣涉及一種顯示裝置。根據本案一實施例，源極驅動器包括一源極驅動器、一多工器、一控制器、以及一切換電路。源極驅動器用以根據一觸發訊號，依序輸出一第一資料電壓及一第二資料電壓。多工器用以接收該第一資料電壓及該第二資料電壓，並根據一第一多工訊號及一第二多工訊號，依序輸出該第一資料電壓及該第二資料電壓至一第一資料線及一第二資料線。控制器用以產生一控制訊號，以控制該第一多工訊號的一下降緣的時間點與該第二多工訊號的一上升緣的時間點彼此大致相同，或控制該第一多工訊號的一上升緣的時間點與該第二多工訊號的一下降緣的時間點彼此大致相同。切換電路用以根據該控制訊號進行切換，以阻止該第一資料電壓提供至該第二資料線。 Another aspect of the present invention relates to a display device. According to an embodiment of the present invention, the source driver includes a source driver, a multiplexer, a controller, and a switching circuit. The source driver is configured to sequentially output a first data voltage and a second data voltage according to a trigger signal. A multiplexer is used for receiving the first data voltage and the second data voltage, and sequentially outputting the first data voltage and the second data voltage to a first data voltage according to a first multiplex signal and a second multiplex signal. A data line and a second data line. The controller is configured to generate a control signal to control a time point of a falling edge of the first multiplexing signal and a time point of a rising edge of the second multiplexing signal to be substantially the same as each other, or to control the first multiplexing signal. The time point of a rising edge and the time point of a falling edge of the second multiplex signal are substantially the same as each other. The switching circuit is used for switching according to the control signal to prevent the first data voltage from being provided to the second data line.
透過應用上述一實施例，可減低第一多工訊號、第二多工訊號造成的雜訊，並避免提供第一資料電壓至錯誤的資料線。 By applying the above-mentioned embodiment, noise caused by the first multiplex signal and the second multiplex signal can be reduced, and the provision of the first data voltage to the wrong data line can be avoided.
10‧‧‧顯示裝置 10‧‧‧ display device
40‧‧‧閘極驅動器 40‧‧‧Gate driver
100‧‧‧控制器 100‧‧‧ Controller
106‧‧‧像素電路 106‧‧‧pixel circuit
SD‧‧‧源極驅動器 SD‧‧‧Source Driver
MUX‧‧‧多工器 MUX‧‧‧Multiplexer
P1、P2‧‧‧輸出接腳 P1, P2‧‧‧ output pins
DL1-DL6‧‧‧資料線 DL1-DL6‧‧‧Data line
GL1、GL2‧‧‧閘極線 GL1, GL2‧‧‧Gate line
G1、G2‧‧‧閘極訊號 G1, G2‧‧‧Gate signal
VD1、VD2‧‧‧資料電壓 VD1, VD2‧‧‧ data voltage
VD1_R、VD1_G、VD1_B‧‧‧資料電壓 VD1_R, VD1_G, VD1_B‧‧‧Data voltage
VD2_R、VD2_G、VD2_B‧‧‧資料電壓 VD2_R, VD2_G, VD2_B‧‧‧Data voltage
CTL‧‧‧控制訊號 CTL‧‧‧Control signal
XSTB‧‧‧觸發訊號 XSTB‧‧‧Trigger signal
SL1-SL3‧‧‧多工訊號 SL1-SL3 ‧‧‧ Multiplex Signal
t0-t8‧‧‧時間點 t0-t8‧‧‧Time
DR‧‧‧資料暫存器 DR‧‧‧Data Register
LT‧‧‧閂鎖器 LT‧‧‧Latch
OT‧‧‧輸出電路 OT‧‧‧ output circuit
OTC‧‧‧輸出時間控制器 OTC‧‧‧Output time controller
SW‧‧‧切換電路 SW‧‧‧Switching circuit
STB‧‧‧觸發訊號 STB‧‧‧Trigger signal
HiZ‧‧‧高阻抗狀態 HiZ‧‧‧High impedance state
第1圖為根據本案一實施例所繪示的顯示裝置的示意圖；第2圖為根據本案一實施例所繪示的多工器的示意圖；第3圖為根據本案一操作例所繪示的顯示裝置的訊號示意圖；第4圖為根據本案一實施例所繪示的源極驅動器的示意圖；第5圖為根據本案一實施例所繪示的切換電路的示意圖；第6圖為根據本案另一實施例所繪示的源極驅動器的示意圖；第7圖為根據本案另一實施例所繪示的切換電路的示意圖；第8圖為根據本案另一實施例所繪示的顯示裝置的示意圖；及第9圖為根據本案另一實施例所繪示的顯示裝置的示意圖。 FIG. 1 is a schematic diagram of a display device according to an embodiment of the present case; FIG. 2 is a schematic diagram of a multiplexer according to an embodiment of the present case; and FIG. 3 is a schematic diagram of a multiplexer according to an embodiment of the present case Signal schematic diagram of a display device; FIG. 4 is a schematic diagram of a source driver according to an embodiment of the present case; FIG. 5 is a schematic diagram of a switching circuit according to an embodiment of the present case; A schematic diagram of a source driver according to an embodiment; FIG. 7 is a schematic diagram of a switching circuit according to another embodiment of the present invention; and FIG. 8 is a schematic diagram of a display device according to another embodiment of the present invention. And FIG. 9 is a schematic diagram of a display device according to another embodiment of the present invention.
以下將以圖式及詳細敘述清楚說明本揭示內容之精神，任何所屬技術領域中具有通常知識者在瞭解本揭示內容之實施例後，當可由本揭示內容所教示之技術，加以改變及修飾，其並不脫離本揭示內容之精神與範圍。 The following will clearly illustrate the spirit of the present disclosure with diagrams and detailed descriptions. Any person with ordinary knowledge in the technical field who understands the embodiments of the present disclosure can be changed and modified by the techniques taught in the present disclosure. It does not depart from the spirit and scope of this disclosure.
關於本文中所使用之『第一』、『第二』、...等，並非特別指稱次序或順位的意思，亦非用以限定本發明，其僅為了區別以相同技術用語描述的元件或操作。 Regarding the "first", "second", ..., etc. used herein, they do not specifically mean the order or order, nor are they used to limit the present invention. They are only used to distinguish elements described in the same technical terms or operating.
關於本文中所使用之『電性耦接』，可指二或多個元件相互直接作實體或電性接觸，或是相互間接作實體或電性接觸，而『電性耦接』還可指二或多個元件相互操作或動作。 As used in this article, "electrical coupling" can mean that two or more components make direct physical or electrical contact with each other, or indirectly make physical or electrical contact with each other, and "electrical coupling" can also mean Two or more elements operate or act on each other.
關於本文中所使用之『包含』、『包括』、『具有』、『含有』等等，均為開放性的用語，即意指包含但不限於。 The terms "including", "including", "having", "containing" and the like used in this article are all open-ended terms, which means including but not limited to.
關於本文中所使用之『及/或』，係包括所述事物的任一或全部組合。 As used herein, "and / or" includes any and all combinations of the things described.
關於本文中所使用之用詞(terms)，除有特別註明外，通常具有每個用詞使用在此領域中、在此揭露之內容中與特殊內容中的平常意義。某些用以描述本揭露之用詞將於下或在此說明書的別處討論，以提供本領域技術人員在有關本揭露之描述上額外的引導。 Regarding the terms used in this article, unless otherwise specified, each term usually has the ordinary meaning of being used in this field, the content disclosed here, and the special content. Certain terms used to describe this disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art on the description of this disclosure.
第1圖為根據本案一實施例所繪示的顯示裝置10的示意圖。在本實施例中，顯示裝置10包括控制器100、像素電路106、源極驅動器SD、閘極驅動器40、資料線DL1-DL6、閘極線GL1、GL2、以及多工器MUX。在本實施例中，像素電路106以矩陣形式排列。在一實施例中，控制器100電性連接源極驅動器SD、閘極驅動器40、以及多工器MUX。在一實施例中，多工器MUX電性連接於資料線 DL1-DL6與源極驅動器SD的輸出接腳P1、P2之間。 FIG. 1 is a schematic diagram of a display device 10 according to an embodiment of the present invention. In this embodiment, the display device 10 includes a controller 100, a pixel circuit 106, a source driver SD, a gate driver 40, data lines DL1-DL6, gate lines GL1, GL2, and a multiplexer MUX. In this embodiment, the pixel circuits 106 are arranged in a matrix form. In one embodiment, the controller 100 is electrically connected to the source driver SD, the gate driver 40 and the multiplexer MUX. In one embodiment, the multiplexer MUX is electrically connected to the data line. Between DL1-DL6 and the output pins P1 and P2 of the source driver SD.
應注意到，在本實施例中，雖以2*6尺寸的顯示裝置10為例進行說明，然而顯示裝置10中的各元件及線路的數量並不以此為限，其它數量的上述元件及線路，亦在本案範圍之中。 It should be noted that in this embodiment, although a 2 * 6 size display device 10 is used as an example for description, the number of each component and circuit in the display device 10 is not limited to this. The line is also within the scope of this case.
在一實施例中，閘極驅動器40用以透過閘極線GL1、GL2逐列提供閘極訊號G1、G2至像素電路106，以逐列開啟像素電路106中的像素電路106的開關。 In one embodiment, the gate driver 40 is used to provide the gate signals G1 and G2 to the pixel circuit 106 row by row through the gate lines GL1 and GL2 to turn on the switches of the pixel circuit 106 in the pixel circuit 106 row by row.
在一實施例中，源極驅動器SD用以根據觸發訊號XSTB，分別透過輸出接腳P1、P2提供資料電壓VD1(包括下述資料電壓VD1_R、VD1_G、VD1_B)、VD2(包括下述資料電壓VD2_R、VD2_G、VD2_B)至多工器MUX。此外，源極驅動器SD亦用以根據控制訊號CTL，停止輸出資料電壓VD1、VD2至多工器MUX。 In one embodiment, the source driver SD is used to provide data voltages VD1 (including the following data voltages VD1_R, VD1_G, VD1_B) and VD2 (including the following data voltages VD2_R) through the output pins P1 and P2 according to the trigger signal XSTB. , VD2_G, VD2_B) to the multiplexer MUX. In addition, the source driver SD is also used to stop outputting the data voltages VD1, VD2 to the multiplexer MUX according to the control signal CTL.
在一實施例中，多工器MUX用以根據多工訊號SL1-SL3，選擇性導通輸出接腳P1至資料線DL1-DL6中一對應者，及導通輸出接腳P2至資料線DL1-DL6中另一對應者，以將資料電壓VD1、VD2提供至像素電路106中的對應者。 In one embodiment, the multiplexer MUX is used to selectively turn on a corresponding one of the output pins P1 to the data lines DL1-DL6 and to turn on the output pins P2 to the data lines DL1-DL6 according to the multiplex signals SL1-SL3. The other corresponding one is to provide the data voltages VD1 and VD2 to the corresponding one in the pixel circuit 106.
舉例而言，同時參照第2圖，在源極驅動器SD透過輸出接腳P1輸出資料電壓VD1_R(例如是對應紅色子像素的資料電壓)、並透過輸出接腳P2輸出資料電壓VD2_R(例如是對應紅色子像素的資料電壓)時，多工器MUX可根據多工訊號SL1，以將資料電壓VD1_R提供至資 料線DL1及其連接的像素電路106(例如是紅色子像素電路)、並將資料電壓VD2_R提供至資料線DL4及其連接的像素電路106(例如是紅色子像素電路)。 For example, referring to FIG. 2 at the same time, the source driver SD outputs the data voltage VD1_R (for example, the data voltage corresponding to the red sub-pixel) through the output pin P1, and outputs the data voltage VD2_R (for example, the corresponding corresponding voltage) through the output pin P2. Data voltage of the red sub-pixel), the multiplexer MUX can provide the data voltage VD1_R to the source according to the multiplex signal SL1. The material line DL1 and the connected pixel circuit 106 (for example, a red sub-pixel circuit), and the data voltage VD2_R are provided to the data line DL4 and the connected pixel circuit 106 (for example, a red sub-pixel circuit).
而後，在源極驅動器SD透過輸出接腳P1輸出資料電壓VD1_G(例如是對應綠色子像素的資料電壓)、並透過輸出接腳P2輸出資料電壓VD2_G(例如是對應綠色子像素的資料電壓)時，多工器MUX可根據多工訊號SL2，以將資料電壓VD1_G提供至資料線DL5及其連接的像素電路106(例如是綠色子像素電路)、並將資料電壓VD2_G提供至資料線DL2及其連接的像素電路106(例如是綠色子像素電路)。 Then, when the source driver SD outputs the data voltage VD1_G (for example, the data voltage corresponding to the green sub-pixel) through the output pin P1, and outputs the data voltage VD2_G (for example, the data voltage corresponding to the green sub-pixel) through the output pin P2 The multiplexer MUX can provide the data voltage VD1_G to the data line DL5 and the connected pixel circuit 106 (such as a green sub-pixel circuit) according to the multiplex signal SL2, and the data voltage VD2_G to the data line DL2 and its The connected pixel circuit 106 (for example, a green sub-pixel circuit).
而後，在源極驅動器SD透過輸出接腳P1輸出資料電壓VD1_B(例如是對應藍色子像素的資料電壓)、並透過輸出接腳P2輸出資料電壓VD2_B(例如是對應藍色子像素的資料電壓)時，多工器MUX可根據多工訊號SL3，以將資料電壓VD1_B提供至資料線DL3及其連接的像素電路106(例如是藍色子像素電路)、並將資料電壓VD2_B提供至資料線DL6及其連接的像素電路106(例如是藍色子像素電路)。 Then, the source driver SD outputs the data voltage VD1_B (for example, the data voltage corresponding to the blue sub-pixel) through the output pin P1, and outputs the data voltage VD2_B (for example, the data voltage corresponding to the blue sub-pixel) through the output pin P1. ), The multiplexer MUX can provide the data voltage VD1_B to the data line DL3 and its connected pixel circuit 106 (such as a blue sub-pixel circuit) and the data voltage VD2_B to the data line according to the multiplex signal SL3. DL6 and the connected pixel circuit 106 (for example, a blue sub-pixel circuit).
藉此，開關受閘極訊號G1、G2開啟的像素電路106便可根據資料電壓VD1、VD2進行顯示操作。 Thereby, the pixel circuit 106 which is turned on by the gate signals G1 and G2 can perform a display operation according to the data voltages VD1 and VD2.
應注意到，上述多工器MUX的連接方式僅為例示，本案並不以此為限，其它形式的連接方式亦在本案範圍之中。 It should be noted that the connection mode of the above-mentioned multiplexer MUX is merely an example, and this case is not limited thereto, and other connection modes are also within the scope of this case.
在一實施例中，控制器100用以產生前述控制訊號CTL、觸發訊號XSTB、及多工訊號SL1-SL3。控制器100利用控制訊號CTL調整多工訊號SL1-SL3的開始時間點(例如是上升緣及下降緣中的一者)及/或中止時間點(例如是上升緣及下降緣中的另一者)，從而減低多工訊號SL1-SL3造成的雜訊。此外，控制器100亦利用控制訊號CTL，以令源極驅動器SD相應地停止輸出資料電壓VD1、VD2，以避免因調整多工訊號SL1-SL3的開始時間點及/或中止時間點造成資料電壓VD1、VD2的錯誤輸出。 In one embodiment, the controller 100 is used to generate the aforementioned control signals CTL, trigger signals XSTB, and multiplex signals SL1-SL3. The controller 100 uses the control signal CTL to adjust the start time point of the multiplex signals SL1-SL3 (for example, one of the rising edge and the falling edge) and / or the stop time point (for example, the other of the rising edge and the falling edge). ) To reduce the noise caused by the multiplex signals SL1-SL3. In addition, the controller 100 also uses the control signal CTL to cause the source driver SD to stop outputting the data voltages VD1 and VD2 accordingly, so as to avoid the data voltage caused by adjusting the start time and / or the suspension time of the multiplex signals SL1-SL3. VD1, VD2 error output.
在一實施例中，控制器100可接收來自主機的影像訊號，並根據影像訊號產生前述控制訊號CTL、觸發訊號XSTB、及多工訊號SL1-SL3。在一實施例中，控制器100是相應於影像訊號，在預設時間點產生控制訊號CTL的脈波，從而調整多工訊號SL1-SL3。在一實施例中，前述預設時間點可根據像素電路106的充電速度決定。 In one embodiment, the controller 100 may receive an image signal from the host, and generate the aforementioned control signal CTL, trigger signal XSTB, and multiplex signals SL1-SL3 according to the image signal. In an embodiment, the controller 100 generates a pulse of the control signal CTL at a preset time corresponding to the image signal, thereby adjusting the multiplex signals SL1-SL3. In one embodiment, the aforementioned predetermined time point may be determined according to the charging speed of the pixel circuit 106.
在一實施例中，控制器100可用時序控制器(timing controller)實現，然本案不以此為限。在一實施例中，控制器100的功能可用其中的可程式邏輯裝置(programmable logic device，PLD)及/或其它硬體電路實現，然本案不以此為限。 In one embodiment, the controller 100 may be implemented by a timing controller, but the present invention is not limited thereto. In an embodiment, the functions of the controller 100 may be implemented by a programmable logic device (PLD) and / or other hardware circuits therein, but the present invention is not limited thereto.
以下將搭配第1-3圖，說明本案一操作例的具體細節，然而本案不以下述操作例為限。 The details of an operation example of this case will be described below with reference to FIGS. 1-3, but this case is not limited to the following operation examples.
參照第3圖，在時間點t0時，閘極訊號G1開始輸出，以開啟第一列像素電路106的開關。 Referring to FIG. 3, at a time point t0, the gate signal G1 starts to output to turn on the switches of the pixel circuit 106 in the first column.
在時間點t1時，觸發訊號XSTB處於下降緣。此時，源極驅動器SD根據觸發訊號XSTB的下降緣，開始透過輸出接腳P1輸出資料電壓VD1_R至多工器MUX。此時，控制器100開始輸出多工訊號SL1，亦即時間點t1大致為多工訊號SL1的開始時間點，且此時多工訊號SL1處於上升緣。 At time point t1, the trigger signal XSTB is at the falling edge. At this time, the source driver SD starts to output the data voltage VD1_R to the multiplexer MUX through the output pin P1 according to the falling edge of the trigger signal XSTB. At this time, the controller 100 starts to output the multiplex signal SL1, that is, the time point t1 is approximately the start time of the multiplex signal SL1, and the multiplex signal SL1 is at the rising edge at this time.
在時間點t1至時間點t2中，多工器MUX根據多工訊號SL1，導通輸出接腳P1與資料線DL1，以令資料線DL1接收來自源極驅動器SD的資料電壓VD1_R，從而使第一列像素電路106中對應資料線DL1的一者(如位於第一行、第一列的像素電路106)接收資料電壓VD1_R。 From time point t1 to time point t2, the multiplexer MUX turns on the output pin P1 and the data line DL1 according to the multiplexing signal SL1, so that the data line DL1 receives the data voltage VD1_R from the source driver SD, so that the first One of the column pixel circuits 106 corresponding to the data line DL1 (such as the pixel circuit 106 located in the first row and the first column) receives the data voltage VD1_R.
在時間點t2時，控制訊號CTL處於上升緣。此時，源極驅動器SD根據控制訊號CTL的上升緣停止輸出資料電壓VD1_R。此外，控制器100相應於控制訊號CTL的上升緣中止輸出多工訊號SL1，亦即時間點t2大致為多工訊號SL1的中止時間點，且此時多工訊號SL1處於下降緣。另外，控制器100相應於控制訊號CTL的上升緣，開始輸出多工訊號SL2，亦即時間點t2大致為多工訊號SL2的開始時間點，且此時多工訊號SL2處於上升緣。 At time t2, the control signal CTL is on the rising edge. At this time, the source driver SD stops outputting the data voltage VD1_R according to the rising edge of the control signal CTL. In addition, the controller 100 stops outputting the multiplexing signal SL1 corresponding to the rising edge of the control signal CTL, that is, the time point t2 is approximately the suspension time point of the multiplexing signal SL1, and the multiplexing signal SL1 is at the falling edge at this time. In addition, the controller 100 starts to output the multiplex signal SL2 corresponding to the rising edge of the control signal CTL, that is, the time point t2 is approximately the start time of the multiplex signal SL2, and the multiplex signal SL2 is at the rising edge at this time.
在時間點t3時，控制訊號CTL處於下降緣，且觸發訊號XSTB處於上升緣。 At time t3, the control signal CTL is on the falling edge, and the trigger signal XSTB is on the rising edge.
在時間點t4時，觸發訊號XSTB處於下降緣。此時，源極驅動器SD根據觸發訊號XSTB的下降緣，透過輸出接腳P1開始輸出資料電壓VD1_G至多工器MUX。 At time t4, the trigger signal XSTB is at the falling edge. At this time, the source driver SD starts to output the data voltage VD1_G to the multiplexer MUX through the output pin P1 according to the falling edge of the trigger signal XSTB.
在時間點t4至時間點t5中，多工器MUX根據多工訊號SL2，導通輸出接腳P1與資料線DL5，以令資料線DL5接收來自源極驅動器SD的資料電壓VD1_G，從而使第一列像素電路106中對應資料線DL1的一者(如位於第五行、第一列的像素電路106)接收資料電壓VD1_G。 From time point t4 to time point t5, the multiplexer MUX turns on the output pin P1 and the data line DL5 according to the multiplexing signal SL2, so that the data line DL5 receives the data voltage VD1_G from the source driver SD, so that the first One of the column pixel circuits 106 corresponding to the data line DL1 (such as the pixel circuit 106 located in the fifth row and the first column) receives the data voltage VD1_G.
在時間點t5時，控制訊號CTL處於上升緣。此時，源極驅動器SD根據控制訊號CTL的上升緣停止輸出資料電壓VD1_G。此外，控制器100相應於控制訊號CTL的上升緣中止輸出多工訊號SL2，亦即時間點t5大致為多工訊號SL2的中止時間點，且此時多工訊號SL2處於下降緣。另外，控制器100相應於控制訊號CTL的上升緣，開始輸出多工訊號SL3，亦即時間點t5大致為多工訊號SL3的開始時間點，且此時多工訊號SL3處於上升緣。 At time t5, the control signal CTL is on the rising edge. At this time, the source driver SD stops outputting the data voltage VD1_G according to the rising edge of the control signal CTL. In addition, the controller 100 stops outputting the multiplex signal SL2 in response to the rising edge of the control signal CTL, that is, the time point t5 is approximately the suspension time point of the multiplex signal SL2, and the multiplex signal SL2 is at the falling edge at this time. In addition, the controller 100 starts to output the multiplex signal SL3 corresponding to the rising edge of the control signal CTL, that is, the time point t5 is approximately the start time of the multiplex signal SL3, and the multiplex signal SL3 is at the rising edge at this time.
在時間點t6時，觸發訊號XSTB處於上升緣。 At time t6, the trigger signal XSTB is on the rising edge.
在時間點t7時，觸發訊號XSTB處於下降緣。此時，源極驅動器SD根據觸發訊號XSTB的下降緣，開始透過輸出接腳P1輸出資料電壓VD1_B至多工器MUX。 At time point t7, the trigger signal XSTB is at the falling edge. At this time, the source driver SD starts to output the data voltage VD1_B to the multiplexer MUX through the output pin P1 according to the falling edge of the trigger signal XSTB.
在時間點t7至時間點t8中，多工器MUX根據多工訊號SL3，導通輸出接腳P1與資料線DL3，以令資料線DL3接收來自源極驅動器SD的資料電壓VD1_B，從而使第一列像素電路106中對應資料線DL3的一者(如位於第三行、第一列的像素電路106)接收資料電壓VD1_B。 From time point t7 to time point t8, the multiplexer MUX turns on the output pin P1 and the data line DL3 according to the multiplexing signal SL3, so that the data line DL3 receives the data voltage VD1_B from the source driver SD, so that the first One of the column pixel circuits 106 corresponding to the data line DL3 (such as the pixel circuit 106 located in the third row and the first column) receives the data voltage VD1_B.
在時間點t8時，閘極訊號G1中止輸出，而關閉第一列像素電路106的開關。此時，控制訊號CTL處於上升 緣。此時，源極驅動器SD根據控制訊號CTL的上升緣停止輸出資料電壓VD1_B。此外，控制器100相應於控制訊號CTL的上升緣中止輸出多工訊號SL3，亦即時間點t8大致為多工訊號SL3的中止時間點，且此時多工訊號SL3處於下降緣。 At time point t8, the gate signal G1 stops outputting, and the switches of the pixel circuit 106 in the first column are turned off. At this time, the control signal CTL is on the rise edge. At this time, the source driver SD stops outputting the data voltage VD1_B according to the rising edge of the control signal CTL. In addition, the controller 100 stops outputting the multiplex signal SL3 corresponding to the rising edge of the control signal CTL, that is, the time point t8 is approximately the suspension time point of the multiplex signal SL3, and the multiplex signal SL3 is at the falling edge at this time.
藉由上述的操作，可使多工訊號SL2的開始時間點大致相同於多工訊號SL1的中止時間點，並使多工訊號SL3的開始時間點大致相同於多工訊號SL2的中止時間點，從而使多工訊號SL1-SL3造成的雜訊彼此抵消。 Through the above operations, the start time point of the multiplex signal SL2 can be made substantially the same as the stop time point of the multiplex signal SL1, and the start time point of the multiplex signal SL3 can be made substantially the same as the stop time point of the multiplex signal SL2. Thus, the noise caused by the multiplex signals SL1-SL3 cancels each other.
此外，由於源極驅動器SD相應於控制訊號CTL停止輸出資料電壓VD1_R、VD1_G、VD1_B，故即便多工訊號SL2的開始時間點大致相同於多工訊號SL1的中止時間點，亦不致於使資料電壓VD1_R錯誤地提供至資料線DL5。同樣地，即便多工訊號SL3的開始時間點大致相同於多工訊號SL2的中止時間點，亦不致於使資料電壓VD1_G錯誤地提供至資料線DL3。 In addition, since the source driver SD stops outputting the data voltages VD1_R, VD1_G, and VD1_B corresponding to the control signal CTL, even if the start time point of the multiplex signal SL2 is substantially the same as the suspend time of the multiplex signal SL1, it will not cause the data voltage VD1_R is incorrectly provided to data line DL5. Similarly, even if the start time point of the multiplex signal SL3 is substantially the same as the stop time point of the multiplex signal SL2, the data voltage VD1_G is not erroneously provided to the data line DL3.
應注意到，以上雖以源極驅動器SD輸出資料電壓VD1的相關操作為例進行說明，然資料電壓VD2的相關操作亦大致相同，故在此不贅述。 It should be noted that, although the above description is based on the related operation of the source driver SD outputting the data voltage VD1 as an example, the related operation of the data voltage VD2 is also substantially the same, so it will not be repeated here.
另外，應注意到，上述訊號G1、XSTB、CTL、SL1-SL3的極性可以實際需要進行變化，故上述訊號的上升緣、下降緣亦會依實際情況進行調換。例如，觸發訊號XSTB、控制訊號CTL可為反向脈波，故在時間點t3時，觸發訊號XSTB處於下降緣，且控制訊號CTL處於上升緣。是 以，本案不以上述操作例為限。 In addition, it should be noted that the polarity of the above signals G1, XSTB, CTL, SL1-SL3 can be changed as needed, so the rising and falling edges of the above signals will also be exchanged according to the actual situation. For example, the trigger signal XSTB and the control signal CTL may be reverse pulses, so at time point t3, the trigger signal XSTB is on the falling edge and the control signal CTL is on the rising edge. Yes Therefore, this case is not limited to the above operation examples.
在本案一實施例中，在上述在時間點t2至時間點t4的部份或全部期間中，及/或時間點t5至時間點t7的部份或全部期間中，源極驅動器SD可使輸出接腳P1、P2處於高阻抗狀態。在一些實施方式中，處於高阻抗狀態可以是使得輸出接腳P1、P2連接到一大阻抗，或是處於浮接(floating)狀態。 In an embodiment of the present invention, during a part or all of the period from time point t2 to time point t4, and / or a part or all of period from time point t5 to time point t7, the source driver SD can make the output Pins P1 and P2 are in a high impedance state. In some embodiments, being in a high-impedance state may be such that the output pins P1 and P2 are connected to a large impedance, or may be in a floating state.
在本案一實施例中，在上述在時間點t2至時間點t4的部份或全部期間中，及/或時間點t5至時間點t7的部份或全部期間中，源極驅動器SD可使輸出接腳P1、P2接地，以重置資料線DL2、DL3、DL5、DL6上的電壓。 In an embodiment of the present invention, during a part or all of the period from time point t2 to time point t4, and / or a part or all of period from time point t5 to time point t7, the source driver SD can make the output The pins P1 and P2 are grounded to reset the voltages on the data lines DL2, DL3, DL5, and DL6.
例如，在時間點t2時，源極驅動器SD可根據控制訊號CTL的上升緣開始使輸出接腳P1、P2接地，以停止輸出資料電壓VD1_R、VD2_R。並且，在時間點t3時，源極驅動器SD可根據觸發訊號XSTB的上升緣開始使輸出接腳P1、P2處於高阻抗狀態。 For example, at time point t2, the source driver SD may start to ground the output pins P1 and P2 according to the rising edge of the control signal CTL to stop outputting the data voltages VD1_R and VD2_R. In addition, at time point t3, the source driver SD can start to make the output pins P1 and P2 in a high-impedance state according to the rising edge of the trigger signal XSTB.
在不同實施例中，在時間點t2時，源極驅動器SD可根據控制訊號CTL的上升緣開始使輸出接腳P1、P2處於高阻抗狀態，以停止輸出資料電壓VD1_R、VD2_R。並且，在時間點t3時，源極驅動器SD可根據觸發訊號XSTB的上升緣開始使輸出接腳P1、P2接地。 In different embodiments, at time t2, the source driver SD may start to put the output pins P1 and P2 in a high-impedance state according to the rising edge of the control signal CTL to stop outputting the data voltages VD1_R and VD2_R. In addition, at time t3, the source driver SD can start to ground the output pins P1 and P2 according to the rising edge of the trigger signal XSTB.
第4圖為根據本案一實施例所繪示的源極驅動器SD的示意圖。在一實施例中，源極驅動器SD包括資料暫存器DR、閂鎖器LT、輸出電路OT、輸出時間控制器OTC、 及切換電路SW。 FIG. 4 is a schematic diagram of a source driver SD according to an embodiment of the present invention. In one embodiment, the source driver SD includes a data register DR, a latch LT, an output circuit OT, an output time controller OTC, And switching circuit SW.
在一實施例中，資料暫存器DR用以提供資料電壓VD1、VD2至閂鎖器LT。輸出時間控制器OTC用以相應於觸發訊號XSTB，控制閂鎖器LT提供資料電壓VD1、VD2至輸出電路OT。輸出電路OT經由切換電路SW提供資料電壓VD1、VD2至輸出接腳P1、P2。 In one embodiment, the data register DR is used to provide the data voltages VD1 and VD2 to the latch LT. The output time controller OTC is used to control the latch signal LT to provide data voltages VD1 and VD2 to the output circuit OT in response to the trigger signal XSTB. The output circuit OT provides the data voltages VD1 and VD2 to the output pins P1 and P2 via the switching circuit SW.
在一實施例中，切換電路SW可根據控制訊號CTL，選擇性電性連接輸出接腳P1、P2至地面。在一實施例中，切換電路SW可根據觸發訊號XSTB進行切換，以令輸出接腳P1、P2處於高阻抗狀態。 In one embodiment, the switching circuit SW can selectively electrically connect the output pins P1 and P2 to the ground according to the control signal CTL. In one embodiment, the switching circuit SW can switch according to the trigger signal XSTB, so that the output pins P1 and P2 are in a high-impedance state.
例如，同時參照第5圖，在前述時間點t2時，切換電路SW可根據控制訊號CTL的上升緣進行切換，以開始使輸出接腳P1、P2接地。並且，在前述時間點t3時，切換電路SW可根據觸發訊號XSTB的上升緣進行切換，以使輸出接腳P1、P2開始處於高阻抗狀態(例如表示為高阻抗狀態HiZ)。而後，在前述時間點t4時，切換電路SW可根據觸發訊號XSTB的下降緣進行切換，以開始使輸出接腳P1、P2輸出資料電壓VD1、VD2。 For example, referring to FIG. 5 at the same time, at the aforementioned time point t2, the switching circuit SW may switch according to the rising edge of the control signal CTL to start grounding the output pins P1 and P2. In addition, at the aforementioned time point t3, the switching circuit SW may switch according to the rising edge of the trigger signal XSTB, so that the output pins P1 and P2 start to be in a high-impedance state (for example, expressed as a high-impedance state HiZ). Then, at the aforementioned time point t4, the switching circuit SW can switch according to the falling edge of the trigger signal XSTB to start the output pins P1 and P2 to output the data voltages VD1 and VD2.
應注意到，在一些實施例中，切換電路SW亦可整合於輸出電路OT之中，本案不以上述實施例為限。 It should be noted that, in some embodiments, the switching circuit SW can also be integrated into the output circuit OT, and this case is not limited to the above embodiments.
參照第6圖，在另外一些實施例中，輸出電路OT的連接切換電路SW的輸出端亦具處於高阻抗狀態HiZ的能力。在此些實施例中，輸出電路OT可接收觸發訊號XSTB，並據以決定輸出或資料電壓VD1、VD2、或使其 輸出端處於高阻抗狀態HiZ。切換電路SW用以根據控制訊號CTL與觸發訊號XSTB進行切換，以使輸出接腳P1、P2接地，或使輸出接腳P1、P2輸出來自輸出電路OT的資料電壓VD1、VD2或呈現來自輸出電路OT的輸出端的高阻抗狀態HiZ。 Referring to FIG. 6, in other embodiments, the output terminal of the connection switching circuit SW of the output circuit OT also has the capability of being in a high-impedance state HiZ. In these embodiments, the output circuit OT can receive the trigger signal XSTB and determine the output or data voltage VD1, VD2, or make it The output is HiZ. The switching circuit SW is used to switch the control signal CTL and the trigger signal XSTB to ground the output pins P1 and P2 or output the data voltages VD1 and VD2 from the output circuit OT to the output pins P1 and P2 or present them from the output circuit. High-Z state HiZ at the output of OT.
例如，同時參照第7圖，在前述時間點t2時，切換電路SW可根據控制訊號CTL的上升緣進行切換，以開始使輸出接腳P1、P2接地。在前述時間點t3時，輸出電路OT的輸出端可根據觸發訊號XSTB的上升緣開始處於高阻抗狀態HiZ。並且，切換電路SW可根據觸發訊號XSTB的上升緣進行切換，以開始使輸出接腳P1、P2呈現來自輸出電路OT的輸出端的高阻抗狀態HiZ。在前述時間點t4時，輸出電路OT可根據觸發訊號XSTB的下降緣，開始輸出資料電壓VD1、VD2，以開始使切換電路SW將資料電壓VD1、VD2輸出至輸出接腳P1、P2。 For example, referring to FIG. 7 at the same time, at the aforementioned time point t2, the switching circuit SW may switch according to the rising edge of the control signal CTL to start grounding the output pins P1 and P2. At the aforementioned time point t3, the output terminal of the output circuit OT may start to be in a high-impedance state HiZ according to the rising edge of the trigger signal XSTB. In addition, the switching circuit SW can switch according to the rising edge of the trigger signal XSTB to start making the output pins P1 and P2 present a high-impedance state HiZ from the output terminal of the output circuit OT. At the aforementioned time point t4, the output circuit OT can start to output the data voltages VD1 and VD2 according to the falling edge of the trigger signal XSTB, so as to start the switching circuit SW to output the data voltages VD1 and VD2 to the output pins P1 and P2.
參照第8圖，在另外一些實施例中，切換電路SW亦可獨立於源極驅動器SD設置。在此些實施例中，源極驅動器SD可接收觸發訊號XSTB，並據以決定使輸出接腳P1、P2呈現高阻抗狀態HiZ或輸出資料電壓VD1、VD2。切換電路SW用以根據控制訊號CTL與觸發訊號XSTB進行切換，以使資料線DL1-DL6中的對應者接地，或使資料線DL1-DL6中的對應者接收來自源極驅動器SD資料電壓VD1、VD2或接收來自輸出接腳P1、P2的高阻抗狀態HiZ。相關細節可參照上述段落，故在此不贅述。此外，在不同 實施例中，切換電路SW亦可在三種狀態間進行切換，以進行接地、呈現高阻抗狀態HiZ、或輸出資料電壓VD1、VD2(例如類似於相應第5圖的實施例)。 Referring to FIG. 8, in other embodiments, the switching circuit SW may be provided independently of the source driver SD. In these embodiments, the source driver SD can receive the trigger signal XSTB, and then decide to cause the output pins P1 and P2 to assume the high-impedance state HiZ or output the data voltages VD1 and VD2. The switching circuit SW is used for switching according to the control signal CTL and the trigger signal XSTB to ground the counterparts in the data lines DL1-DL6, or to cause the counterparts in the data lines DL1-DL6 to receive the SD data voltage VD1 from the source driver VD2 or receives high-impedance state HiZ from output pins P1 and P2. Relevant details can refer to the above paragraphs, so they will not be repeated here. Also, in different In the embodiment, the switching circuit SW can also switch between three states to perform grounding, present a high-impedance state HiZ, or output data voltages VD1 and VD2 (for example, similar to the embodiment in FIG. 5).
參照第9圖，在另外一些實施例中，切換電路SW亦可設置於多工器MUX與資料線DL1-DL6之間。切換電路SW用以根據控制訊號CTL與觸發訊號XSTB進行切換，以使資料線DL1-DL6中的對應者接地，或使資料線DL1-DL6中的對應者接收來自源極驅動器SD與多工器MUX的資料電壓VD1、VD2或接收來自輸出接腳P1、P2的高阻抗狀態HiZ。相關細節可參照上述段落，故在此不贅述。類似地，在不同實施例中，切換電路SW亦可在三種狀態間進行切換，以進行接地、呈現高阻抗狀態HiZ、或輸出資料電壓VD1、VD2(例如類似於相應第5圖的實施例)。 Referring to FIG. 9, in other embodiments, the switching circuit SW may also be disposed between the multiplexer MUX and the data lines DL1 to DL6. The switching circuit SW is used to switch according to the control signal CTL and the trigger signal XSTB, so as to ground the counterparts in the data lines DL1-DL6, or cause the counterparts in the data lines DL1-DL6 to receive from the source driver SD and the multiplexer. The data voltage VD1, VD2 of the MUX or receives the high-impedance state HiZ from the output pins P1, P2. Relevant details can refer to the above paragraphs, so they will not be repeated here. Similarly, in different embodiments, the switching circuit SW can also switch between three states to ground, present a high-impedance state HiZ, or output data voltages VD1, VD2 (such as the embodiment similar to the corresponding FIG. 5) .
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed as above by way of example, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall be determined by the scope of the attached patent application.
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