TWI658587B - Thin film transistor of display device and method thereof - Google Patents
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Abstract
本發明提供顯示裝置及其薄膜電晶體與形成方法。顯示裝置包含微結晶矽氧化物層及位於微結晶矽氧化物層上的矽層，且微結晶矽氧化物層之矽與氧的元素比大於1。顯示裝置之薄膜電晶體包含閘極電極、位於閘極電極上的微結晶矽化合物層、位於微結晶矽化合物層上的主動層以及位於主動層上的源極與汲極電極，其中微結晶矽化合物層之結晶粒徑實質小於或等於20奈米(nm)。 The invention provides a display device, a thin film transistor and a forming method thereof. The display device includes a microcrystalline silicon oxide layer and a silicon layer on the microcrystalline silicon oxide layer, and an element ratio of silicon to oxygen of the microcrystalline silicon oxide layer is greater than 1. The thin film transistor of a display device includes a gate electrode, a microcrystalline silicon compound layer on the gate electrode, an active layer on the microcrystalline silicon compound layer, and a source and drain electrode on the active layer. The microcrystalline silicon The crystalline particle size of the compound layer is substantially less than or equal to 20 nanometers (nm).
Description
本發明一般係關於顯示裝置及其薄膜電晶體與形成方法，具體而言，本發明係關於提升微結晶矽層與其下層間之界面平整性與結晶率的顯示裝置及其薄膜電晶體與形成方法。 The present invention generally relates to a display device, a thin film transistor and a method for forming the same. Specifically, the present invention relates to a display device, a thin film transistor, and a method for improving the flatness and crystallinity of an interface between a microcrystalline silicon layer and a lower layer thereof. .
平板顯示器通常是藉由薄膜電晶體開關陣列來控制各畫素的運作，因此薄膜電晶體的良莠直接影響顯示器的品質。習知顯示器的薄膜電晶體是在玻璃基板上形成閘極，再依序形成閘極絕緣層、作為主動層的非晶矽層及源極與汲極電極。非晶矽層相較於微結晶矽層具有較低的遷移率(mobility)及較差的電性穩定性，因此近年來逐漸提出使用微結晶矽層作為主動層。 Flat panel displays usually use thin film transistor switch arrays to control the operation of each pixel, so the quality of thin film transistors directly affects the quality of the display. A thin film transistor of a conventional display is formed with a gate electrode on a glass substrate, and then a gate insulating layer, an amorphous silicon layer as an active layer, and a source and a drain electrode are sequentially formed. The amorphous silicon layer has lower mobility and poorer electrical stability than the microcrystalline silicon layer. Therefore, in recent years, it has been proposed to use the microcrystalline silicon layer as an active layer.
微結晶矽層一般是利用化學氣相沉積法(CVD)形成。然而，沉積微結晶矽層時，不論是在閘極絕緣層或是玻璃基板上，都容易在與其相接的界面有非晶矽及空洞的形成，使得界面不平整而影響通道的形成及電子的傳輸，進而會影響整體元件的特性。 The microcrystalline silicon layer is generally formed by a chemical vapor deposition (CVD) method. However, when depositing a microcrystalline silicon layer, whether on a gate insulating layer or a glass substrate, it is easy to form amorphous silicon and voids at the interface with it, making the interface uneven and affecting the formation of channels and electrons. Transmission, which in turn affects the characteristics of the overall component.
本發明之一目的在於提供一種顯示裝置及其薄膜電晶體與形成方法，其藉由微結晶矽化合物的緩衝，使得後續成長的矽層有較佳的 匹配性，改善整體元件特性。 An object of the present invention is to provide a display device, a thin film transistor, and a method for forming the same. By using a buffer of a microcrystalline silicon compound, a subsequent growth of a silicon layer is better. Matching to improve overall component characteristics.
本發明之另一目的在於提供一種顯示裝置及其薄膜電晶體與形成方法，其藉由微結晶矽化合物層作為閘極絕緣層，提升主動層的結晶率，並改善界面的平整性。 Another object of the present invention is to provide a display device, a thin film transistor and a forming method thereof, which use a microcrystalline silicon compound layer as a gate insulating layer to improve the crystallization rate of the active layer and improve the flatness of the interface.
於一實施例，本發明提供一種顯示裝置之薄膜電晶體，其包含：閘極電極、位於閘極電極上的微結晶矽化合物層，且微結晶矽化合物層之結晶粒徑實質小於或等於20奈米(nm)、位於微結晶矽化合物層上的主動層、以及位於主動層上的源極與汲極電極。 In one embodiment, the present invention provides a thin film transistor for a display device, which includes a gate electrode, a microcrystalline silicon compound layer on the gate electrode, and a crystal grain size of the microcrystalline silicon compound layer is substantially less than or equal to 20 Nanometer (nm), an active layer on the microcrystalline silicon compound layer, and a source and drain electrode on the active layer.
於一實施例，微結晶矽化合物層包含微結晶矽氧化物、微結晶矽氮化物或微結晶矽氮氧化物。 In one embodiment, the microcrystalline silicon compound layer includes microcrystalline silicon oxide, microcrystalline silicon nitride, or microcrystalline silicon oxynitride.
於一實施例，微結晶矽氧化物之矽與氧的元素比大於1。 In one embodiment, the element ratio of silicon to oxygen of the microcrystalline silicon oxide is greater than one.
於一實施例，微結晶矽氧化物之矽與氧的元素比大於1.5且小於12。 In one embodiment, the element ratio of silicon to oxygen of the microcrystalline silicon oxide is greater than 1.5 and less than 12.
於一實施例，微結晶矽化合物層係作為閘極絕緣層。 In one embodiment, the microcrystalline silicon compound layer is used as a gate insulating layer.
於一實施例，本發明之顯示裝置之薄膜電晶體更包含閘極絕緣層，其中閘極絕緣層位於閘極電極與微結晶矽化合物層之間。 In one embodiment, the thin film transistor of the display device of the present invention further includes a gate insulating layer, wherein the gate insulating layer is located between the gate electrode and the microcrystalline silicon compound layer.
於一實施例，閘極絕緣層包含非晶矽化合物層。 In one embodiment, the gate insulating layer includes an amorphous silicon compound layer.
於一實施例，主動層包含微結晶矽層。 In one embodiment, the active layer includes a microcrystalline silicon layer.
於一實施例，本發明之顯示裝置之薄膜電晶體更包含非晶矽層，其中非晶矽層位於微結晶矽層上。 In one embodiment, the thin film transistor of the display device of the present invention further includes an amorphous silicon layer, wherein the amorphous silicon layer is located on the microcrystalline silicon layer.
於另一實施例，本發明提供一種顯示裝置，其包含微結晶矽氧化物層以及位於微結晶矽氧化物層上的矽層，其中微結晶矽氧化物層之 矽與氧的元素比大於1。 In another embodiment, the present invention provides a display device including a microcrystalline silicon oxide layer and a silicon layer on the microcrystalline silicon oxide layer. The element ratio of silicon to oxygen is greater than one.
於一實施例，微結晶矽氧化物層之結晶粒徑實質小於或等於20奈米(nm)。 In one embodiment, the crystal grain size of the microcrystalline silicon oxide layer is substantially less than or equal to 20 nanometers (nm).
於一實施例，矽層包含微結晶矽層。 In one embodiment, the silicon layer includes a microcrystalline silicon layer.
於另一實施例，本發明提供一種形成顯示裝置之薄膜電晶體的方法，其包含：形成閘極電極；形成微結晶矽化合物層於閘極電極上，該微結晶矽化合物層之結晶粒徑實質小於或等於20奈米(nm)；形成主動層於微結晶矽化合物層上；以及形成源極與汲極電極於主動層上。 In another embodiment, the present invention provides a method for forming a thin film transistor of a display device, comprising: forming a gate electrode; forming a microcrystalline silicon compound layer on the gate electrode, and a crystal grain size of the microcrystalline silicon compound layer Substantially less than or equal to 20 nanometers (nm); forming an active layer on the microcrystalline silicon compound layer; and forming a source electrode and a drain electrode on the active layer.
於一實施例，形成微結晶矽化合物層之步驟包含利用化學氣相沉積提高矽烷及氫氣的流量，以形成微結晶矽氧化物層。 In one embodiment, the step of forming a microcrystalline silicon compound layer includes using chemical vapor deposition to increase the flow of silane and hydrogen to form a microcrystalline silicon oxide layer.
於一實施例，化學氣相沉積的溫度為200~500℃，氫氣的流量與氫氣和矽烷的總流量(H2/(H2+SiH4))之百分比為80%~100%，矽烷的流量與矽烷和一氧化二氮的總流量(SiH4/(SiH4+N2O))之百分比為10%~80%。 In one embodiment, the temperature of the chemical vapor deposition is 200 to 500 ° C., and the percentage of the flow rate of hydrogen to the total flow of hydrogen and silane (H 2 / (H 2 + SiH 4 )) is 80% to 100%. The percentage of the flow rate to the total flow rate of silane and nitrous oxide (SiH 4 / (SiH 4 + N 2 O)) is 10% ~ 80%.
於一實施例，形成主動層之步驟包含直接形成微結晶矽層於微結晶矽化合物層上。 In one embodiment, the step of forming the active layer includes directly forming a microcrystalline silicon layer on the microcrystalline silicon compound layer.
於一實施例，本發明之形成顯示裝置之薄膜電晶體的方法更包含形成閘極絕緣層於閘極電極與微結晶矽化合物層之間。 In one embodiment, the method for forming a thin film transistor of a display device according to the present invention further includes forming a gate insulating layer between the gate electrode and the microcrystalline silicon compound layer.
於一實施例，形成閘極絕緣之步驟包含形成非晶矽化合物層於閘極電極與微結晶矽化合物層之間。 In one embodiment, the step of forming the gate insulation includes forming an amorphous silicon compound layer between the gate electrode and the microcrystalline silicon compound layer.
於另一實施例，本發明提供一種形成顯示裝置的方法，其包含：形成微結晶矽氧物層，微結晶矽氧化物層之矽與氧的元素比大於1；以及形成矽層於微結晶矽氧化物層上。 In another embodiment, the present invention provides a method for forming a display device, comprising: forming a microcrystalline silicon oxide layer; a silicon to oxygen element ratio of the microcrystalline silicon oxide layer is greater than 1; and forming a silicon layer on the microcrystal On the silicon oxide layer.
於一實施例，形成矽層之步驟包含直接形成微結晶矽層於微結晶矽氧化物層上。 In one embodiment, the step of forming a silicon layer includes directly forming a microcrystalline silicon layer on the microcrystalline silicon oxide layer.
相較於習知技術，本發明之顯示裝置及其薄膜電晶體藉由微結晶矽化合物層做為緩衝層或閘極介電層，有助於後續成長微結晶矽層時的長晶，使得界面平整性得以改善，並有效提升結晶率，減少或甚至消除界面的空洞及非結晶狀態。本發明之顯示裝置及其薄膜電晶體的形成方法藉由提高矽烷及氫氣相對於一氧化二氮的流量比，使得微結晶矽化合物層中產生微結晶矽，以減少或甚至消除後續主動層或矽層長晶界面的空洞及非結晶狀態，改善界面平整性並有效提升結晶率。 Compared with the conventional technology, the display device and the thin-film transistor of the present invention use the microcrystalline silicon compound layer as a buffer layer or a gate dielectric layer, which is helpful for the subsequent growth of the microcrystalline silicon layer, so that The interface flatness is improved, and the crystallization rate is effectively increased, and the voids and amorphous state of the interface are reduced or even eliminated. The display device and the method for forming a thin film transistor of the present invention increase the flow ratio of silane and hydrogen relative to nitrous oxide, so that microcrystalline silicon is generated in the microcrystalline silicon compound layer to reduce or even eliminate subsequent active layers or The voids and amorphous state of the silicon crystal's long crystal interface improve the interface flatness and effectively increase the crystallization rate.
1‧‧‧顯示裝置 1‧‧‧ display device
10、10’‧‧‧顯示裝置之薄膜電晶體 10, 10’‧‧‧ thin film transistors for display devices
100‧‧‧基板 100‧‧‧ substrate
110‧‧‧閘極電極 110‧‧‧Gate electrode
115‧‧‧閘極絕緣層 115‧‧‧Gate insulation
120‧‧‧微結晶矽化合物層 120‧‧‧Microcrystalline silicon compound layer
130‧‧‧主動層 130‧‧‧Active Level
140‧‧‧源極與汲極電極 140‧‧‧source and drain electrodes
140a‧‧‧導電層 140a‧‧‧ conductive layer
142‧‧‧源極 142‧‧‧Source
144‧‧‧汲極 144‧‧‧Drain
150‧‧‧非晶矽層 150‧‧‧amorphous silicon layer
152‧‧‧源極摻雜區 152‧‧‧Source doped region
154‧‧‧汲極摻雜區 154‧‧‧drain region
210‧‧‧基板 210‧‧‧ substrate
220‧‧‧微結晶矽氧化物層 220‧‧‧Microcrystalline silicon oxide layer
230‧‧‧矽層 230‧‧‧ silicon layer
圖1為本發明一實施例之顯示裝置之薄膜電晶體之示意圖。 FIG. 1 is a schematic diagram of a thin film transistor of a display device according to an embodiment of the present invention.
圖2為本發明另一實施例之顯示裝置之薄膜電晶體之示意圖。 FIG. 2 is a schematic diagram of a thin film transistor of a display device according to another embodiment of the present invention.
圖3-5為本發明一實施例之形成顯示裝置之薄膜電晶體的方法的示意圖。 3-5 are schematic diagrams of a method for forming a thin film transistor of a display device according to an embodiment of the present invention.
圖6為本發明一實施例之顯示裝置之穿透式電子顯微鏡(TEM)圖式。 FIG. 6 is a transmission electron microscope (TEM) diagram of a display device according to an embodiment of the present invention.
本發明提供一種顯示裝置及其薄膜電晶體與形成方法，其藉由微結晶矽化合物層，使得後續成長的矽層有較佳的匹配性，改善矽層的結晶性以及與下層界面的平整性，進而提升整體元件特性。於後，參考圖式詳細說明本發明實施例之顯示裝置及其薄膜電晶體與形成方法之細節。 The invention provides a display device, a thin film transistor and a method for forming the same, by using a microcrystalline silicon compound layer, the subsequent growth of the silicon layer has better matching properties, improving the crystallinity of the silicon layer and the flatness of the interface with the lower layer. , Thereby improving the overall component characteristics. Hereinafter, details of the display device, the thin film transistor, and the forming method thereof according to the embodiments of the present invention will be described in detail with reference to the drawings.
請參考圖1，圖1為本發明一實施例之顯示裝置之薄膜電晶體 之示意圖。於一實施例，如圖1所示，本發明之顯示裝置之薄膜電晶體10包含閘極電極110、微結晶矽化合物層120、主動層130及源極與汲極電極140。微結晶矽化合物層120位於閘極電極110上，主動層130位於微結晶矽化合物層120上，且源極與汲極電極140位於主動層130上。微結晶矽化合物層120之結晶粒徑實質小於或等於20奈米(nm)。 Please refer to FIG. 1. FIG. 1 is a thin film transistor of a display device according to an embodiment of the present invention. The schematic. In an embodiment, as shown in FIG. 1, the thin film transistor 10 of the display device of the present invention includes a gate electrode 110, a microcrystalline silicon compound layer 120, an active layer 130, and a source and drain electrode 140. The microcrystalline silicon compound layer 120 is located on the gate electrode 110, the active layer 130 is positioned on the microcrystalline silicon compound layer 120, and the source and drain electrodes 140 are positioned on the active layer 130. The crystal grain size of the microcrystalline silicon compound layer 120 is substantially less than or equal to 20 nanometers (nm).
具體而言，顯示裝置之薄膜電晶體10係製作於基板100上，基板可為例如玻璃、聚合物、石英等透明基板。閘極電極110較佳為金屬層，例如鎢(W)、鋁(Al)、鉻(Cr)、銅(Cu)、鉬(Mo)或其合金。於此實施例，微結晶矽化合物層120係作為閘極絕緣層，且直接覆蓋於閘極電極110上。微結晶矽化合物層120可包含微結晶矽氧化物、微結晶矽氮化物或微結晶矽氮氧化物。舉例而言，微結晶矽化合物層120較佳包含微結晶矽氧化物，且微結晶矽氧化物之矽與氧的元素比大於1。於一實施例，微結晶矽氧化物之矽與氧的元素比較佳大於1.5且小於12。主動層130包含微結晶矽層。顯示裝置之薄膜電晶體1更包含非晶矽層150，其中非晶矽層150位於微結晶矽層上，以作為源極與汲極的摻雜區，例如n+摻雜非晶矽。源極與汲極電極140包含金屬材料或非金屬導電材料，且較佳為金屬材料。於一實施例，金屬材料包含例如鎢(W)、鋁(Al)、鉻(Cr)、銅(Cu)、鉬(Mo)或其合金，但不以此為限。於另一實施例，非金屬導電材料包含例如氧化銦錫，但不以此為限。 Specifically, the thin film transistor 10 of the display device is fabricated on a substrate 100, and the substrate may be, for example, a transparent substrate such as glass, polymer, or quartz. The gate electrode 110 is preferably a metal layer, such as tungsten (W), aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), or an alloy thereof. In this embodiment, the microcrystalline silicon compound layer 120 serves as a gate insulating layer, and directly covers the gate electrode 110. The microcrystalline silicon compound layer 120 may include microcrystalline silicon oxide, microcrystalline silicon nitride, or microcrystalline silicon oxynitride. For example, the microcrystalline silicon compound layer 120 preferably includes microcrystalline silicon oxide, and the element ratio of silicon to oxygen of the microcrystalline silicon oxide is greater than 1. In one embodiment, the elements of silicon and oxygen of the microcrystalline silicon oxide are preferably greater than 1.5 and less than 12. The active layer 130 includes a microcrystalline silicon layer. The thin film transistor 1 of a display device further includes an amorphous silicon layer 150, wherein the amorphous silicon layer 150 is located on the microcrystalline silicon layer as a doped region of a source and a drain, such as n + doped amorphous silicon. The source and drain electrodes 140 include a metal material or a non-metal conductive material, and are preferably a metal material. In an embodiment, the metal material includes, for example, tungsten (W), aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), or an alloy thereof, but is not limited thereto. In another embodiment, the non-metal conductive material includes, for example, indium tin oxide, but is not limited thereto.
請參考圖2，圖2為本發明另一實施例之顯示裝置之薄膜電晶體之示意圖。如圖2所示，本發明之顯示裝置之薄膜電晶體10’與圖1實施例之差異在於更包含閘極絕緣層115，其中閘極絕緣層115位於閘極電極110與微結晶矽化合物層120之間，且閘極絕緣層115可包含非晶矽化合物層，例 如氧化矽、氮化矽、氮氧化矽，但不限於此。換言之，於本實施例中，微結晶矽化合物層120係作為閘極絕緣層115與主動層130之間的緩衝層，以提升後續矽層的結晶率及界面平整性。 Please refer to FIG. 2, which is a schematic diagram of a thin film transistor of a display device according to another embodiment of the present invention. As shown in FIG. 2, the thin film transistor 10 ′ of the display device of the present invention is different from the embodiment in FIG. 1 in that it further includes a gate insulating layer 115, wherein the gate insulating layer 115 is located on the gate electrode 110 and the microcrystalline silicon compound layer. 120, and the gate insulating layer 115 may include an amorphous silicon compound layer, for example Such as, but not limited to, silicon oxide, silicon nitride, and silicon oxynitride. In other words, in this embodiment, the microcrystalline silicon compound layer 120 is used as a buffer layer between the gate insulating layer 115 and the active layer 130 to improve the crystallinity and interface flatness of the subsequent silicon layer.
於後參考圖3-5說明本發明一實施例之形成顯示裝置之薄膜電晶體的方法，以形成例如圖1或圖2之顯示裝置之薄膜電晶體10、10’。如圖3所示，本發明形成顯示裝置之薄膜電晶體的方法包含：形成閘極電極110。舉例而言，首先在基板100上沉積金屬層，並使用微影及蝕刻技術對金屬層進行圖案化，以於基板100上形成閘極電極110。 Hereinafter, a method for forming a thin film transistor of a display device according to an embodiment of the present invention will be described with reference to FIGS. 3-5 to form, for example, the thin film transistors 10, 10 'of the display device of FIG. 1 or FIG. As shown in FIG. 3, the method for forming a thin film transistor of a display device according to the present invention includes forming a gate electrode 110. For example, a metal layer is first deposited on the substrate 100, and the metal layer is patterned using lithography and etching techniques to form a gate electrode 110 on the substrate 100.
如圖3所示，本發明形成顯示裝置之薄膜電晶體的進一步包含：形成微結晶矽化合物層120於閘極電極110上，其中微結晶矽化合物層120之結晶粒徑實質小於或等於20奈米(nm)。舉例而言，形成微結晶矽化合物層120之步驟包含利用化學氣相沉積提高矽烷(SiH4)及氫氣(H2)的流量，以形成微結晶矽氧化物層。於一實施例，化學氣相沉積的溫度較佳為200~500℃，氫氣的流量與氫氣和矽烷的總流量之百分比(即(H2/(H2+SiH4)的百分比)較佳為80%~100%，且矽烷的流量與矽烷和一氧化二氮(N2O)的總流量之百分比(即(SiH4/(SiH4+N2O)的百分比)較佳為10%~80%。再者，化學氣相沉積的功率較佳為0.2W/cm2~20.2W/cm2，且壓力較佳為3000mT~9000mT。 As shown in FIG. 3, the thin film transistor for forming a display device according to the present invention further includes: forming a microcrystalline silicon compound layer 120 on the gate electrode 110, wherein the crystal grain size of the microcrystalline silicon compound layer 120 is substantially less than or equal to 20 nanometers. Meters (nm). For example, the step of forming the microcrystalline silicon compound layer 120 includes using chemical vapor deposition to increase the flow of silane (SiH 4 ) and hydrogen (H 2 ) to form a microcrystalline silicon oxide layer. In one embodiment, the temperature of the chemical vapor deposition is preferably 200 to 500 ° C. The percentage of the flow rate of hydrogen to the total flow rate of hydrogen and silane (that is, (H 2 / (H 2 + SiH 4 )) is preferably 80% ~ 100%, and the percentage of the flow of silane to the total flow of silane and nitrous oxide (N 2 O) (that is, the percentage of (SiH 4 / (SiH 4 + N 2 O)) is preferably 10% ~ 80%. Furthermore, the power of chemical vapor deposition is preferably 0.2 W / cm 2 to 20.2 W / cm 2 , and the pressure is preferably 3000 mT to 9000 mT.
具體而言，形成微結晶矽化合物層120之步驟藉由提高氫氣與矽烷的流量比(H2/SiH4)以及矽烷與一氧化二氮(SiH4/N2O)的流量比，使得沉積時的非晶氧化矽膜中產生微結晶的矽，以利於後續矽層的成長。舉例而言，形成微結晶矽氧化物層時，先使矽烷的流量大於一氧化二氮的流量而達到富矽(silicon-rich)狀態，再由氫氣稀釋以增加電漿的轟擊與蝕刻，進 而改善矽氧化物層的結構，而達到微結晶矽氧化物層。因此，相較於習知矽氧化物結構中矽與氧的元素比遠小於1的情況(即Si/O<<1)，本發明所形成之微結晶矽氧化物之矽與氧的元素比大於1(即Si/O>1)，且矽與氧的元素比較佳大於1.5且小於12(即1.5<Si/O<12)。藉此，可減少界面間非晶矽及空洞的形成，提升結晶性，增加製程的操作範圍(process window)。 Specifically, the step of forming the microcrystalline silicon compound layer 120 increases the flow ratio of hydrogen to silane (H 2 / SiH 4 ) and the flow ratio of silane to nitrous oxide (SiH 4 / N 2 O), so that the deposition At this time, microcrystalline silicon is generated in the amorphous silicon oxide film to facilitate the subsequent growth of the silicon layer. For example, when forming a microcrystalline silicon oxide layer, the flow of silane is made greater than the flow of nitrous oxide to reach a silicon-rich state, and then diluted with hydrogen to increase plasma bombardment and etching, and further Improve the structure of the silicon oxide layer to achieve a microcrystalline silicon oxide layer. Therefore, compared to the case where the element ratio of silicon to oxygen in the conventional silicon oxide structure is much smaller than 1 (that is, Si / O << 1), the element ratio of silicon to oxygen of the microcrystalline silicon oxide formed by the present invention is More than 1 (that is, Si / O> 1), and the elements of silicon and oxygen are better than 1.5 and less than 12 (that is, 1.5 <Si / O <12). This can reduce the formation of amorphous silicon and voids between interfaces, improve crystallinity, and increase the process window of the process.
在此需注意，於上述實施例中形成微結晶矽化合物層的步驟雖以形成微結晶矽氧化物層為例說明，但不限於此。當微結晶矽化合物層為微結晶矽氮化物層或微結晶矽氮氧化物層時，亦可藉由調整相關製程氣體的流量以達到富矽狀態，使得所形成的矽氮化物層或矽氮氧化物層的結構具有微結晶矽的形成，進而達到微結晶矽氮化物層或微結晶矽氮氧化物層。 It should be noted that, although the step of forming the microcrystalline silicon compound layer in the above embodiments is described by taking the formation of the microcrystalline silicon oxide layer as an example, it is not limited thereto. When the microcrystalline silicon compound layer is a microcrystalline silicon nitride layer or a microcrystalline silicon nitride oxide layer, the flow rate of the relevant process gas can be adjusted to achieve a silicon-rich state, so that the formed silicon nitride layer or silicon nitrogen The structure of the oxide layer has the formation of microcrystalline silicon, thereby reaching a microcrystalline silicon nitride layer or a microcrystalline silicon oxynitride layer.
再如圖3所示，本發明形成顯示裝置之薄膜電晶體的進一步包含：形成主動層130於微結晶矽化合物層120上。舉例而言，形成主動層130之步驟包含利用化學氣相沉積技術直接形成微結晶矽層於微結晶矽化合物層120上。本發明形成顯示裝置之薄膜電晶體的進一步包含：形成非晶矽層150於微結晶矽層上。舉例而言，利用化學氣相沉積技術沉積非晶矽層150於微結晶矽層上，且非晶矽層150可為摻雜的非晶矽層，例如n+摻雜非晶矽層，但不以此為限。 As shown in FIG. 3, the thin film transistor for forming a display device according to the present invention further includes: forming an active layer 130 on the microcrystalline silicon compound layer 120. For example, the step of forming the active layer 130 includes directly forming a microcrystalline silicon layer on the microcrystalline silicon compound layer 120 by using a chemical vapor deposition technique. The thin film transistor for forming a display device of the present invention further includes: forming an amorphous silicon layer 150 on the microcrystalline silicon layer. For example, the chemical vapor deposition technology is used to deposit the amorphous silicon layer 150 on the microcrystalline silicon layer, and the amorphous silicon layer 150 may be a doped amorphous silicon layer, such as an n + doped amorphous silicon layer, but not This is the limit.
接著，如圖4所示，利用微影及蝕刻技術，將全面沉積形成的微結晶矽化合物層120、主動層130及非晶矽層150進行圖案化，以定義出類似圖1之薄膜電晶體1所示的微結晶矽化合物層120、主動層130及非晶矽層150的堆疊結構。在此需注意，當微結晶矽化合物層120作為緩衝層時， 在沉積微結晶矽化合物層120前，本發明形成顯示裝置之薄膜電晶體的方法更包含形成閘極絕緣層115於閘極電極110上。舉例而言，利用化學氣相沉積形成非晶矽化合物層(例如氧化矽、氮化矽、氮氧化矽等)於閘極電極110上，以作為閘極絕緣層115，但不以此為限。然後，再如上所述，依序形成作為緩衝層的微結晶矽化合物層120、主動層130及非晶矽層150，並進行類似圖4的圖案化。因此，進行圖案化後，可定義出類似圖2之薄膜電晶體10’所示的微結晶矽化合物層120、閘極絕緣層115、主動層130及非晶矽層150的堆疊結構(未繪示)。 Next, as shown in FIG. 4, the microcrystalline silicon compound layer 120, the active layer 130, and the amorphous silicon layer 150 are patterned by using lithography and etching techniques to define a thin film transistor similar to FIG. 1. The stacked structure of the microcrystalline silicon compound layer 120, the active layer 130, and the amorphous silicon layer 150 shown in FIG. It should be noted here that when the microcrystalline silicon compound layer 120 is used as a buffer layer, Before the microcrystalline silicon compound layer 120 is deposited, the method for forming a thin film transistor of a display device according to the present invention further includes forming a gate insulating layer 115 on the gate electrode 110. For example, an amorphous silicon compound layer (such as silicon oxide, silicon nitride, silicon oxynitride, etc.) is formed on the gate electrode 110 by using chemical vapor deposition as the gate insulating layer 115, but not limited thereto. . Then, as described above, the microcrystalline silicon compound layer 120, the active layer 130, and the amorphous silicon layer 150 as the buffer layer are sequentially formed, and patterned similarly to FIG. 4. Therefore, after patterning, a stack structure (not shown) of the microcrystalline silicon compound layer 120, the gate insulating layer 115, the active layer 130, and the amorphous silicon layer 150 (not shown) similar to the thin film transistor 10 'shown in FIG. 2 can be defined.示).
如圖5所示，本發明形成顯示裝置之薄膜電晶體的方法進一步包含：形成源極與汲極電極140於主動層130上。舉例而言，利用化學氣相沉積形成導電層140a於非晶矽層150上。導電層140a可為例如上述的金屬導電材料或非金屬導電材料。接著，利用微影及蝕刻技術，圖案化非晶矽層150及導電層140a，以使非晶矽層150包含分離的源極摻雜區152與汲極摻雜區154，而源極與汲極電極140包含源極142與汲極144且分別電連接源極摻雜區152與汲極摻雜區154。藉此，完成圖1或圖2之顯示裝置之薄膜電晶體10、10’的製作。 As shown in FIG. 5, the method for forming a thin film transistor of a display device according to the present invention further includes: forming a source electrode and a drain electrode 140 on the active layer 130. For example, a conductive layer 140 a is formed on the amorphous silicon layer 150 by chemical vapor deposition. The conductive layer 140a may be, for example, the above-mentioned metal conductive material or non-metal conductive material. Next, using lithography and etching techniques, the amorphous silicon layer 150 and the conductive layer 140a are patterned so that the amorphous silicon layer 150 includes separate source-doped regions 152 and drain-doped regions 154, and the source and drain The electrode electrode 140 includes a source electrode 142 and a drain electrode 144 and is electrically connected to the source doped region 152 and the drain doped region 154, respectively. This completes the fabrication of the thin film transistors 10, 10 'of the display device of Fig. 1 or Fig. 2.
在此需注意，雖未繪示，在形成源極與汲極電極140的金屬層140a前，本發明方法可包含形成畫素電極的步驟，以使得後續形成的源極與汲極電極140中的例如汲極144電連接畫素電極。於一實施例，畫素電極可包含氧化銦錫層。 It should be noted here that although not shown, before forming the metal layer 140a of the source and drain electrodes 140, the method of the present invention may include a step of forming a pixel electrode, so that the source and drain electrodes 140 formed later For example, the drain electrode 144 is electrically connected to the pixel electrode. In one embodiment, the pixel electrode may include an indium tin oxide layer.
此外，上述實施例中，微結晶矽化合物層雖作為顯示裝置之薄膜電晶體的緩衝層或閘極絕緣層，但不以此為限。於其他實施例，微結 晶矽化合物層(尤其是微結晶矽氧化物層)可設置在任何需要與矽層形成界面的位置，以提升矽層成長的結晶性及界面平整性。請參考圖6，圖6為本發明一實施例之顯示裝置之穿透式電子顯微鏡(TEM)圖式。如圖6所示，於另一實施例，本發明提供一種顯示裝置1，其包含微結晶矽氧化物層220及位於微結晶矽氧化物層上的矽層230，其中微結晶矽氧化物層220之矽與氧的元素比大於1。 In addition, in the above embodiments, the microcrystalline silicon compound layer is used as a buffer layer or a gate insulating layer of a thin film transistor of a display device, but it is not limited thereto. In other embodiments, microjunction The crystalline silicon compound layer (especially the microcrystalline silicon oxide layer) can be arranged at any position where an interface with the silicon layer is required to improve the crystallinity and interface flatness of the silicon layer growth. Please refer to FIG. 6, which is a transmission electron microscope (TEM) diagram of a display device according to an embodiment of the present invention. As shown in FIG. 6, in another embodiment, the present invention provides a display device 1 including a microcrystalline silicon oxide layer 220 and a silicon layer 230 on the microcrystalline silicon oxide layer, wherein the microcrystalline silicon oxide layer The elemental ratio of silicon to oxygen of 220 is greater than 1.
在此需注意，微結晶矽氧化物層220及矽層230之形成方法可參考上述圖3之微結晶矽化合物層120及主動層130的相關說明，亦即利用化學氣相沉積提高矽烷及氫氣的流量，以形成微結晶矽氧化物層220，然後再沉積微結晶矽層於微結晶矽氧化物層220上，於此不再贅述。藉此，形成的微結晶矽氧化物層220之矽與氧的元素比較佳大於1.5且小於12，且微結晶矽氧化物層之結晶粒徑實質小於或等於20奈米(nm)。 It should be noted here that the formation method of the microcrystalline silicon oxide layer 220 and the silicon layer 230 can refer to the related description of the microcrystalline silicon compound layer 120 and the active layer 130 in FIG. 3 described above, that is, chemical vapor deposition is used to improve silane and hydrogen. Flow rate to form a microcrystalline silicon oxide layer 220, and then deposit a microcrystalline silicon layer on the microcrystalline silicon oxide layer 220, which is not repeated here. Accordingly, the elements of silicon and oxygen of the formed microcrystalline silicon oxide layer 220 are preferably greater than 1.5 and less than 12, and the crystal grain size of the microcrystalline silicon oxide layer 220 is substantially less than or equal to 20 nanometers (nm).
由圖6可知，微結晶矽層230與微結晶矽氧化物層220之間具有良好的晶界，且微結晶矽層230與微結晶矽氧化物層220之界面間的非晶矽及空洞減少或甚至消失，有效提升後續成長的矽層230的結晶率，並改善矽層230與微結晶矽氧化物層220之間的界面的平整性，進而有助於改善整體元件特性。具體而言，微結晶矽氧化物層220可藉由上述方法及製程條件形成於基板210上，以藉由微結晶矽氧化物層220，使得後續成長的微結晶矽層有較佳的匹配性。基板210可為顯示裝置1於任何合宜製程階段的基板，例如上述實施例的基板100或上述實施例中包含基板100及閘極電極110的半成品基板，但不以此為限。 It can be seen from FIG. 6 that the microcrystalline silicon layer 230 and the microcrystalline silicon oxide layer 220 have good grain boundaries, and the amorphous silicon and voids at the interface between the microcrystalline silicon layer 230 and the microcrystalline silicon oxide layer 220 are reduced. Or even disappear, effectively improving the crystallization rate of the subsequently grown silicon layer 230, and improving the flatness of the interface between the silicon layer 230 and the microcrystalline silicon oxide layer 220, thereby helping to improve the overall device characteristics. Specifically, the microcrystalline silicon oxide layer 220 can be formed on the substrate 210 by using the above method and process conditions, so that the microcrystalline silicon oxide layer 220 that is subsequently grown has better matching properties. . The substrate 210 may be a substrate of the display device 1 at any suitable manufacturing process stage, such as the substrate 100 in the above embodiment or a semi-finished substrate including the substrate 100 and the gate electrode 110 in the above embodiment, but is not limited thereto.
本發明已由上述實施例加以描述，然而上述實施例僅為例示 目的而非用於限制。熟此技藝者當知在不悖離本發明精神下，於此特別說明的實施例可有例示實施例的其他修改。因此，本發明範疇亦涵蓋此類修改且僅由所附申請專利範圍限制。 The present invention has been described by the above embodiments, but the above embodiments are merely examples Purpose, not limitation. Those skilled in the art will appreciate that the embodiments specifically described herein may have other modifications to the illustrated embodiments without departing from the spirit of the invention. Therefore, the scope of the present invention also covers such modifications and is limited only by the scope of the appended patent applications.
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