TWI657699B

TWI657699B - Display panel

Info

Publication number: TWI657699B
Application number: TW106115682A
Authority: TW
Inventors: 王澄光; 塗俊達
Original assignee: 友達光電股份有限公司
Priority date: 2017-05-12
Filing date: 2017-05-12
Publication date: 2019-04-21
Also published as: TW201902201A; CN107145021A

Abstract

一種顯示面板，包括顯示區以及非顯示區、多條閘極線、多條資料線、畫素陣列以及閘極驅動電路。非顯示區位於顯示區之一側。多條閘極線與多條資料線設置於顯示區。畫素陣列位於顯示區之中，且畫素陣列藉由多個重複排列的畫素單元所構成，其中畫素單元包括三條閘極線、兩條資料線以及六個子畫素，且各子畫素分別與畫素陣列中的其中一條閘極線以及其中一條資料線電性連接。閘極驅動電路位於畫素陣列之中。A display panel includes a display area and a non-display area, a plurality of gate lines, a plurality of data lines, a pixel array, and a gate driving circuit. The non-display area is located on one side of the display area. Multiple gate lines and multiple data lines are set in the display area. The pixel array is located in the display area, and the pixel array is composed of a plurality of pixel units arranged repeatedly, wherein the pixel unit includes three gate lines, two data lines, and six sub pixels, and each sub pixel The pixels are electrically connected to one of the gate lines and one of the data lines in the pixel array, respectively. The gate driving circuit is located in the pixel array.

Description

顯示面板Display panel

本發明是有關於一種顯示面板，且特別是有關於一種將閘極驅動電路設置於畫素陣列之中的顯示面板。The present invention relates to a display panel, and more particularly, to a display panel in which a gate driving circuit is arranged in a pixel array.

閘極驅動電路基板技術(Gate on Array；GOA)指的是在面板設計時，直接將閘極驅動電路製作在主動元件陣列基板上，以代替外接之驅動晶片的技術。一般而言，閘極驅動電路是設置在面板的顯示區之外，位於面板的邊框位置。然而，閘極驅動電路通常是佔了邊框面積的很大一部分。若是能夠將閘極驅動電路移到顯示區之中，則勢必能夠大幅減小邊框面積設計，並且增加顯示區面積。就現有技術來說，將閘極驅動電路設置在顯示區之中的嘗試尚未成功。因此，有必要對現有的閘極驅動電路基板技術進行改進。Gate drive circuit substrate technology (Gate on Array; GOA) refers to the technology of directly fabricating the gate drive circuit on the active element array substrate during panel design, instead of the external drive chip. Generally speaking, the gate driving circuit is disposed outside the display area of the panel, and is located at the frame position of the panel. However, the gate driving circuit usually occupies a large portion of the frame area. If the gate driving circuit can be moved into the display area, it is bound to greatly reduce the design of the frame area and increase the area of the display area. As far as the prior art is concerned, attempts to place a gate driving circuit in a display area have not been successful. Therefore, it is necessary to improve the existing gate drive circuit substrate technology.

本發明提供一種顯示面板，能夠解決傳統閘極驅動電路設計不佳的問題。The invention provides a display panel, which can solve the problem of poor design of the traditional gate driving circuit.

本發明的顯示面板包括顯示區以及非顯示區、多條閘極線、多條資料線、畫素陣列以及閘極驅動電路。非顯示區位於顯示區之一側。多條閘極線與多條資料線設置於顯示區。畫素陣列位於顯示區之中，且畫素陣列藉由多個重複排列的畫素單元所構成，其中畫素單元包括三條閘極線、兩條資料線以及六個子畫素，且各子畫素分別與畫素陣列中的其中一條閘極線以及其中一條資料線電性連接。閘極驅動電路位於畫素陣列之中。The display panel of the present invention includes a display area and a non-display area, a plurality of gate lines, a plurality of data lines, a pixel array, and a gate driving circuit. The non-display area is located on one side of the display area. Multiple gate lines and multiple data lines are set in the display area. The pixel array is located in the display area, and the pixel array is composed of a plurality of pixel units arranged repeatedly, wherein the pixel unit includes three gate lines, two data lines, and six sub pixels, and each sub pixel The pixels are electrically connected to one of the gate lines and one of the data lines in the pixel array, respectively. The gate driving circuit is located in the pixel array.

基於上述，由於本發明實施例的顯示面板的每一畫素單元是包括三條閘極線、兩條資料線以及六個子畫素，因此，能夠有多餘的空間將閘極驅動電路設置在顯示區的畫素陣列之中。據此，將閘極驅動電路移到顯示區時，能夠達到降低成本、大幅縮減邊框及增加顯示區面積的技術效果。Based on the foregoing, since each pixel unit of the display panel of the embodiment of the present invention includes three gate lines, two data lines, and six sub-pixels, there can be extra space for setting the gate driving circuit in the display area. Pixel array. According to this, when the gate driving circuit is moved to the display area, the technical effects of reducing costs, greatly reducing the frame, and increasing the area of the display area can be achieved.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

圖1為依據本發明一實施例的顯示面板的上視示意圖。請參考圖1，本發明實施例的顯示面板100包括有顯示區DR以及非顯示區NR，其中，非顯示區NR位於顯示區DR的一側，或是非顯示區NR會環繞顯示區DR。換言之，非顯示區NR可為於顯示區DR的其中一側邊，但可依不同需求而調整。舉例而言，非顯示區NR係環繞於顯示區DR，應用於矩形顯示區時，非顯示區NR可位於顯示區DR的其中一側邊、兩側邊、三側邊或四側邊；應用於非矩形顯示區或圓形顯示區時，非顯示區NR可鄰近於顯示區DR，形成顯示區DR的部分周邊或全部周邊為非顯示區NR。一般來說，閘極驅動電路(Gate on Array；GOA)通常是製作在面板的非顯示區上，位於邊框的位置。然而，在本發明實施例中，閘極驅動電路是設置在顯示區DR中。以下，將對如何設置閘極驅動電路於顯示區DR中進行說明。FIG. 1 is a schematic top view of a display panel according to an embodiment of the present invention. Referring to FIG. 1, a display panel 100 according to an embodiment of the present invention includes a display area DR and a non-display area NR. The non-display area NR is located on one side of the display area DR, or the non-display area NR surrounds the display area DR. In other words, the non-display area NR may be on one side of the display area DR, but may be adjusted according to different needs. For example, the non-display area NR is surrounded by the display area DR. When applied to a rectangular display area, the non-display area NR may be located on one side, two sides, three sides, or four sides of the display area DR. Application In a non-rectangular display area or a circular display area, the non-display area NR may be adjacent to the display area DR, and part or all of the periphery forming the display area DR is the non-display area NR. Generally speaking, the gate driving circuit (Gate on Array; GOA) is usually fabricated on the non-display area of the panel and is located at the position of the frame. However, in the embodiment of the present invention, the gate driving circuit is provided in the display area DR. Hereinafter, how to provide the gate driving circuit in the display area DR will be described.

詳細來說，本實施例的顯示面板100可以包括有畫素陣列設置在顯示區DR之中。畫素陣列的排列可以例如有圖2A至圖2C三種不同的實施態樣。In detail, the display panel 100 of this embodiment may include a pixel array disposed in the display area DR. The pixel array may be arranged in three different implementations, for example, as shown in FIG. 2A to FIG. 2C.

圖2A為依據本發明一實施例的畫素陣列的排列示意圖。如圖2A所示，畫素陣列101位於圖1的顯示區DR之中，且畫素陣列101藉由多個重複排列的畫素單元(PX1、PX2、PX3、PX4)所構成。在圖2A中是以畫素單元PX1、畫素單元PX2、畫素單元PX3與畫素單元PX4的四組重複排列的畫素單元來進行說明。但需注意的是，顯示面板100實際上應包括更多個重複排列的畫素單元。畫素單元PX2、畫素單元PX3與畫素單元PX4的設置方式與畫素單元PX1的設置方式相同，因此，僅以畫素單元PX1做為代表來說明。FIG. 2A is an arrangement diagram of a pixel array according to an embodiment of the present invention. As shown in FIG. 2A, the pixel array 101 is located in the display area DR of FIG. 1, and the pixel array 101 is composed of a plurality of pixel units (PX1, PX2, PX3, and PX4) arranged repeatedly. In FIG. 2A, four pixel units PX1, pixel unit PX2, pixel unit PX3, and pixel unit PX4 that are repeatedly arranged are used for description. It should be noted that the display panel 100 should actually include more pixel units that are repeatedly arranged. The setting method of the pixel unit PX2, the pixel unit PX3, and the pixel unit PX4 is the same as the setting method of the pixel unit PX1. Therefore, only the pixel unit PX1 will be described as a representative.

參考圖2A的實施例，畫素陣列101包括有多條閘極線(GL1、GL2、GL3…)設置於顯示區DR之中，以及多條資料線(DL1、DL2、…)設置於顯示區DR之中。每一個畫素單元(PX1、PX2、PX3、PX4)各自包括三條閘極線(GL1、GL2、GL3)、兩條資料線(DL1、DL2)以及六個子畫素(102A、102B、102C、102D、102E、102F)，且各子畫素分別與畫素陣列101中的其中一條閘極線以及其中一條資料線電性連接。在本實施例中，閘極線(GL1、GL2、GL3…)與資料線(DL1、DL2、…)彼此交錯設置，且閘極線(GL1、GL2、GL3…)與資料線(DL1、DL2、…)之間夾有絕緣層。換言之，閘極線(GL1、GL2、GL3…)的延伸方向與資料線(DL1、DL2、…)的延伸方向不平行，較佳的是，閘極線(GL1、GL2、GL3…)的延伸方向與資料線(DL1、DL2、…)的延伸方向正相交，但不以此為限。基於導電性的考量，閘極線(GL1、GL2、GL3…)與資料線(DL1、DL2、…)一般是使用金屬材料。然，本發明不限於此，根據其他實施例，閘極線(GL1、GL2、GL3…)與資料線(DL1、DL2、…)也可以使用其他導電材料。例如：合金、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物、或其它合適的材料)、或是金屬材料與其它導材料的堆疊層。Referring to the embodiment of FIG. 2A, the pixel array 101 includes a plurality of gate lines (GL1, GL2, GL3 ...) disposed in the display area DR, and a plurality of data lines (DL1, DL2, ...) disposed in the display area. DR. Each pixel unit (PX1, PX2, PX3, PX4) includes three gate lines (GL1, GL2, GL3), two data lines (DL1, DL2), and six sub-pixels (102A, 102B, 102C, 102D) , 102E, 102F), and each sub-pixel is electrically connected to one of the gate lines and one of the data lines in the pixel array 101, respectively. In this embodiment, the gate lines (GL1, GL2, GL3 ...) and the data lines (DL1, DL2, ...) are staggered with each other, and the gate lines (GL1, GL2, GL3 ...) and the data lines (DL1, DL2) , ...) with an insulation layer in between. In other words, the extension direction of the gate lines (GL1, GL2, GL3, ...) is not parallel to the extension direction of the data lines (DL1, DL2, ...). Preferably, the extension of the gate lines (GL1, GL2, GL3, ...) is not parallel. The direction intersects the extension direction of the data lines (DL1, DL2, ...), but is not limited to this. Based on considerations of electrical conductivity, the gate lines (GL1, GL2, GL3 ...) and the data lines (DL1, DL2, ...) are generally made of metal materials. However, the present invention is not limited to this. According to other embodiments, the gate lines (GL1, GL2, GL3, ...) and the data lines (DL1, DL2, ...) may also use other conductive materials. For example: alloys, nitrides of metallic materials, oxides of metallic materials, oxynitrides of metallic materials, or other suitable materials), or stacked layers of metallic materials and other conductive materials.

詳細來說，如圖2A所示，畫素單元PX1的三條閘極線包括第一閘極線GL1、第二閘極線GL2以及第三閘極線GL3。畫素單元PX1的兩條資料線包括第一資料線DL1以及第二資料線DL2。畫素單元PX1的六個子畫素包含第一子畫素102A、第二子畫素102B、第三子畫素102C、第四子畫素102D、第五子畫素102E與第六子畫素102F。在畫素單元PX1中，第一子畫素102A透過開關元件A1分別與第一閘極線GL1以及第一資料線DL1電性連接，第二子畫素102B透過開關元件A2分別與第一閘極線GL1以及第二資料線GL2電性連接，第三子畫素102C透過開關元件A3分別與第二閘極線GL2以及鄰接於畫素單元PX1的另一畫素單元PX2之第一資料線DL1電性連接。在本實施例中，「鄰接」於畫素單元PX1的畫素單元意指與畫素單元PX1最為相近的另一畫素單元，且例如是沿著閘極線延伸方向接續排列的下一個畫素單元。In detail, as shown in FIG. 2A, the three gate lines of the pixel unit PX1 include a first gate line GL1, a second gate line GL2, and a third gate line GL3. The two data lines of the pixel unit PX1 include a first data line DL1 and a second data line DL2. The six sub pixels of the pixel unit PX1 include the first sub pixel 102A, the second sub pixel 102B, the third sub pixel 102C, the fourth sub pixel 102D, the fifth sub pixel 102E, and the sixth sub pixel. 102F. In the pixel unit PX1, the first sub-pixel 102A is electrically connected to the first gate line GL1 and the first data line DL1 through the switching element A1, and the second sub-pixel 102B is connected to the first gate through the switching element A2, respectively. The polar line GL1 and the second data line GL2 are electrically connected. The third sub-pixel 102C is respectively connected to the second gate line GL2 and the first data line of the other pixel unit PX2 adjacent to the pixel unit PX1 through the switching element A3. DL1 is electrically connected. In this embodiment, a pixel unit “adjacent” to the pixel unit PX1 means another pixel unit that is closest to the pixel unit PX1, and is, for example, the next picture that is successively arranged along the gate line extension direction.素 Unit.

此外，在圖2A中，第四子畫素102D透過開關元件A4分別與第二閘極線GL2以及第二資料線DL2電性連接，第五子畫素102E透過開關元件A5分別與第三閘極線GL3以及第二資料線DL2電性連接，第六子畫素102F透過開關元件A6分別與第三閘極線GL3以及另一畫素單元PX2之第一資料線DL1電性連接。在本實施例中，第一子畫素102A、第二子畫素102B以及第三子畫素102C位於第一閘極線GL1與第二閘極線GL2之間，而第四子畫素102D、第五子畫素102E以及第六子畫素102F位於第二閘極線GL2與第三閘極線GL3之間。In addition, in FIG. 2A, the fourth sub-pixel 102D is electrically connected to the second gate line GL2 and the second data line DL2 through the switching element A4, and the fifth sub-pixel 102E is respectively connected to the third gate through the switching element A5. The polar line GL3 and the second data line DL2 are electrically connected, and the sixth sub-pixel 102F is electrically connected to the third gate line GL3 and the first data line DL1 of the other pixel unit PX2 through the switching element A6, respectively. In this embodiment, the first sub-pixel 102A, the second sub-pixel 102B, and the third sub-pixel 102C are located between the first gate line GL1 and the second gate line GL2, and the fourth sub-pixel 102D The fifth sub-pixel 102E and the sixth sub-pixel 102F are located between the second gate line GL2 and the third gate line GL3.

請繼續參考圖2A，閘極驅動電路是設置在顯示區DR的畫素陣列101之中，且閘極驅動電路包括多個驅動單元200，而各驅動單元200包括多個主動元件TFT與多條訊號線SL。在圖2A的實施例中，由於每一畫素單元(PX1、PX2、PX3、PX4)僅有設置兩條資料線(DL1、DL2)，省略了第三條資料線，因此，驅動單元200能夠對應設置於相鄰的子畫素或畫素單元所形成的區域之間。更具體地，驅動單元200例如是設置在第二子畫素102B與第三子畫素102C之間的空間，以及設置在第五子畫素102E與第六子畫素102F之間的空間。另外，驅動單元200中的其中一條訊號線SL是位於畫素單元PX1的第二子畫素102B與第三子畫素102C之間，且其中一條訊號線SL是與資料線(DL1、DL2)實質上平行設置。在圖2A的實施例中，各子畫素是矩形排列且資料線(DL1、DL2)與閘極線(GL1、GL2、GL3)正相交，因此，訊號線SL可與資料線(DL1、DL2)實質上平行，但本發明不以此為限。在其它實施例中，子畫素排列可為非矩形，因此，訊號線SL有可能不是與資料線(DL1、DL2)完全平行。藉由圖2A所示的配置方式，能夠有效地將閘極驅動電路設置在顯示區DR的畫素陣列101之中，達到降低成本、大幅縮減邊框及增加顯示區面積的技術效果。Please continue to refer to FIG. 2A, the gate driving circuit is disposed in the pixel array 101 of the display area DR, and the gate driving circuit includes a plurality of driving units 200, and each driving unit 200 includes a plurality of active element TFTs and a plurality of TFTs. Signal line SL. In the embodiment of FIG. 2A, since each pixel unit (PX1, PX2, PX3, PX4) has only two data lines (DL1, DL2), and the third data line is omitted, the driving unit 200 can Correspondingly set between the areas formed by adjacent sub-pixels or pixel units. More specifically, the driving unit 200 is, for example, a space provided between the second sub-pixel 102B and the third sub-pixel 102C, and a space provided between the fifth sub-pixel 102E and the sixth sub-pixel 102F. In addition, one of the signal lines SL in the driving unit 200 is located between the second sub-pixel 102B and the third sub-pixel 102C of the pixel unit PX1, and one of the signal lines SL is the data line (DL1, DL2). Arranged substantially in parallel. In the embodiment of FIG. 2A, each sub-pixel is arranged in a rectangle and the data lines (DL1, DL2) and the gate lines (GL1, GL2, GL3) intersect positively. Therefore, the signal line SL can be connected to the data lines (DL1, DL2 ) Is substantially parallel, but the invention is not limited thereto. In other embodiments, the sub-pixel arrangement may be non-rectangular. Therefore, the signal line SL may not be completely parallel to the data lines (DL1, DL2). With the arrangement shown in FIG. 2A, the gate driving circuit can be effectively arranged in the pixel array 101 of the display area DR, and the technical effects of reducing costs, greatly reducing the frame, and increasing the area of the display area can be achieved.

圖2B為依據本發明另一實施例的畫素陣列的排列示意圖。圖2B與圖2A的畫素陣列101類似，因此，相同元件以相同標號表示，且不予贅述。圖2B與圖2A的實施例差異在於各子畫素的連接方式不同。如圖2B所示，在畫素單元PX1中，第一子畫素102A透過開關元件A1分別與第一閘極線GL1以及第二資料線DL2電性連接，第二子畫素102B透過開關元件A2分別與第一閘極線GL1以及鄰接於畫素單元PX1的另一畫素單元PX2之第一資料線DL1電性連接。在本實施例中，「鄰接」於畫素單元PX1的畫素單元意指與畫素單元PX1最為相近的另一畫素單元，且例如是沿著閘極線延伸方向接續排列的下一個畫素單元。FIG. 2B is an arrangement diagram of a pixel array according to another embodiment of the present invention. FIG. 2B is similar to the pixel array 101 of FIG. 2A. Therefore, the same elements are denoted by the same reference numerals, and will not be described again. The difference between the embodiment of FIG. 2B and FIG. 2A is that the connection methods of the sub-pixels are different. As shown in FIG. 2B, in the pixel unit PX1, the first sub-pixel 102A is electrically connected to the first gate line GL1 and the second data line DL2 through the switching element A1, respectively, and the second sub-pixel 102B passes through the switching element. A2 is electrically connected to the first gate line GL1 and the first data line DL1 of another pixel unit PX2 adjacent to the pixel unit PX1. In this embodiment, a pixel unit “adjacent” to the pixel unit PX1 means another pixel unit that is closest to the pixel unit PX1, and is, for example, the next picture that is successively arranged along the gate line extension direction.素 Unit.

此外，在圖2B中，第三子畫素102C透過開關元件A3分別與第二閘極線GL2以及第二資料線DL2電性連接，第四子畫素102D透過開關元件A4分別與第二閘極線GL2以及第一資料線DL1電性連接，第五子畫素102E透過開關元件A5分別與第三閘極線GL3以及第二資料線DL2電性連接，第六子畫素102F透過開關元件A6分別與第三閘極線GL3以及另一畫素單元PX2之第一資料線DL1電性連接。在本實施例中，第一子畫素102A、第二子畫素102B以及第三子畫素102C位於第一閘極線GL1與第二閘極線GL2之間，而第四子畫素102D、第五子畫素102E以及第六子畫素102F位於第二閘極線GL2與第三閘極線GL3之間。畫素單元PX2、畫素單元PX3與畫素單元PX4的設置方式與畫素單元PX1相同，因此，不予贅述且省略標示。In addition, in FIG. 2B, the third sub-pixel 102C is electrically connected to the second gate line GL2 and the second data line DL2 through the switching element A3, and the fourth sub-pixel 102D is respectively connected to the second gate through the switching element A4. The polar line GL2 and the first data line DL1 are electrically connected. The fifth sub-pixel 102E is electrically connected to the third gate line GL3 and the second data line DL2 through the switching element A5. The sixth sub-pixel 102F is connected through the switching element. A6 is electrically connected to the third gate line GL3 and the first data line DL1 of another pixel unit PX2, respectively. In this embodiment, the first sub-pixel 102A, the second sub-pixel 102B, and the third sub-pixel 102C are located between the first gate line GL1 and the second gate line GL2, and the fourth sub-pixel 102D The fifth sub-pixel 102E and the sixth sub-pixel 102F are located between the second gate line GL2 and the third gate line GL3. The pixel unit PX2, the pixel unit PX3, and the pixel unit PX4 are set in the same manner as the pixel unit PX1, and therefore are not described in detail and are omitted from the description.

相同地，在圖2B的實施例中，閘極驅動電路是設置在顯示區DR的畫素陣列101之中。由於每一畫素單元(PX1、PX2、PX3、PX4)僅有設置兩條資料線(DL1、DL2)，省略了第三條資料線，因此，驅動單元200能夠對應設置於相鄰的子畫素或畫素單元(102B與102C；102E與102F)所形成的區域之間。藉由圖2B所示的配置方式，能夠有效地將閘極驅動電路設置在顯示區DR的畫素陣列101之中，達到降低成本、大幅縮減邊框及增加顯示區面積的技術效果。Similarly, in the embodiment of FIG. 2B, the gate driving circuit is disposed in the pixel array 101 of the display area DR. As each pixel unit (PX1, PX2, PX3, PX4) is provided with only two data lines (DL1, DL2), and the third data line is omitted, the driving unit 200 can be correspondingly disposed on an adjacent sub-picture. Between pixels or pixel units (102B and 102C; 102E and 102F). With the arrangement shown in FIG. 2B, the gate driving circuit can be effectively arranged in the pixel array 101 of the display area DR, and the technical effects of reducing costs, greatly reducing the frame, and increasing the area of the display area can be achieved.

圖2C為依據本發明另一實施例的畫素陣列的排列示意圖。圖2C與圖2A的畫素陣列101類似，因此，相同元件以相同標號表示，且不予贅述。圖2C與圖2A的實施例差異在於各子畫素的連接方式不同。如圖2C所示，在畫素單元PX1中，第一子畫素102A透過開關元件A1分別與第一閘極線GL1以及第二資料線DL2電性連接，第二子畫素102B透過開關元件A2分別與第二閘極線GL2以及第二資料線DL2電性連接，第三子畫素102C透過開關元件A3與第一閘極線GL1以及鄰接畫素單元PX1的另一畫素單元PX2之第一資料線DL1電性連接。在本實施例中，「鄰接」於畫素單元PX1的畫素單元意指與畫素單元PX1最為相近的另一畫素單元，且例如是沿著閘極線延伸方向接續排列的下一個畫素單元。FIG. 2C is an arrangement diagram of a pixel array according to another embodiment of the present invention. FIG. 2C is similar to the pixel array 101 of FIG. 2A, and therefore, the same elements are denoted by the same reference numerals, and will not be described again. The difference between the embodiment of FIG. 2C and FIG. 2A is that the connection methods of the sub-pixels are different. As shown in FIG. 2C, in the pixel unit PX1, the first sub-pixel 102A is electrically connected to the first gate line GL1 and the second data line DL2 through the switching element A1, respectively, and the second sub-pixel 102B passes through the switching element. A2 is electrically connected to the second gate line GL2 and the second data line DL2, respectively. The third sub-pixel 102C is connected to the first gate line GL1 and another pixel unit PX2 adjacent to the pixel unit PX1 through the switching element A3. The first data line DL1 is electrically connected. In this embodiment, a pixel unit “adjacent” to the pixel unit PX1 means another pixel unit that is closest to the pixel unit PX1, and is, for example, the next picture that is successively arranged along the gate line extension direction.素 Unit.

此外，在圖2C中，第四子畫素102D透過開關元件A4分別與第二閘極線GL2以及第一資料線DL1電性連接，第五子畫素102E透過開關元件A5分別與第三閘極線GL3以及第二資料線DL2電性連接，第六子畫素102F透過開關元件A6分別與第三閘極線GL3以及另一畫素單元PX2之第一資料線DL1電性連接。在本實施例中，第一子畫素102A、第二子畫素102B以及第三子畫素102C位於第一閘極線GL1與第二閘極線GL2之間，而第四子畫素102D、第五子畫素102E以及第六子畫素102F位於第二閘極線GL2與第三閘極線GL3之間。畫素單元PX2、畫素單元PX3與畫素單元PX4的設置方式與畫素單元PX1相同，因此，不予贅述且省略標示。In addition, in FIG. 2C, the fourth sub-pixel 102D is electrically connected to the second gate line GL2 and the first data line DL1 through the switching element A4, and the fifth sub-pixel 102E is respectively connected to the third gate through the switching element A5. The polar line GL3 and the second data line DL2 are electrically connected, and the sixth sub-pixel 102F is electrically connected to the third gate line GL3 and the first data line DL1 of the other pixel unit PX2 through the switching element A6, respectively. In this embodiment, the first sub-pixel 102A, the second sub-pixel 102B, and the third sub-pixel 102C are located between the first gate line GL1 and the second gate line GL2, and the fourth sub-pixel 102D The fifth sub-pixel 102E and the sixth sub-pixel 102F are located between the second gate line GL2 and the third gate line GL3. The pixel unit PX2, the pixel unit PX3, and the pixel unit PX4 are set in the same manner as the pixel unit PX1, and therefore are not described in detail and are omitted from the description.

相同地，在圖2C的實施例中，閘極驅動電路是設置在顯示區DR的畫素陣列101之中。由於每一畫素單元(PX1、PX2、PX3、PX4)僅有設置兩條資料線(DL1、DL2)，省略了第三條資料線，因此，驅動單元200能夠對應設置於相鄰的畫素單元(102B與102C；102E與102F)所形成的區域之間。藉由圖2C所示的配置方式，能夠有效地將閘極驅動電路設置在顯示區DR的畫素陣列101之中，達到降低成本、大幅縮減邊框及增加顯示區面積的技術效果。Similarly, in the embodiment of FIG. 2C, the gate driving circuit is disposed in the pixel array 101 of the display area DR. Since each pixel unit (PX1, PX2, PX3, PX4) has only two data lines (DL1, DL2), and the third data line is omitted, the driving unit 200 can be correspondingly set to an adjacent pixel Between the cells (102B and 102C; 102E and 102F). With the arrangement shown in FIG. 2C, the gate driving circuit can be effectively arranged in the pixel array 101 of the display area DR, and the technical effects of reducing costs, greatly reducing the frame, and increasing the area of the display area can be achieved.

在圖2A至圖2C的實例中，僅有說明閘極驅動電路包括多個驅動單元200，而各驅動單元200包括多個主動元件TFT與多條訊號線SL，但對於主動元件TFT與訊號線SL的連接/設置方式並未多做描述。以下，將對驅動單元200的不同實施態樣進行說明。In the examples of FIG. 2A to FIG. 2C, only the gate driving circuit includes a plurality of driving units 200, and each driving unit 200 includes a plurality of active element TFTs and a plurality of signal lines SL. The connection / setting method of the SL is not described in detail. Hereinafter, different embodiments of the driving unit 200 will be described.

圖3為依據本發明一實施例的驅動單元之電路圖。在本實施例中，位於圖2A至圖2C之畫素陣列101中的閘極驅動電路可由多個如圖3所示的驅動單元200所構成。詳言之，閘極驅動電路係為多個驅動單元200所串接而形成多級驅動單元，且每一級驅動單元可輸出至對應之閘極線。舉例來說，第一級之驅動單元可輸出至第一條閘極線，第二級之驅動單元可輸出至第二條閘極線，依序形成相對關係，為便於說明，下述內容則以第N級來說明，亦即第N級驅動單元可輸出至第N條閘極線，其中N為一正整數。在本實施例中，圖2A至圖2C的訊號線SL可例如包含電源訊號線VSS、時脈訊號線CK、前級輸入線IN1、後級輸入線IN2與輸出線OP。參考圖3，驅動單元200包括四個主動元件(T1~T4)。更具體地，第一主動元件T1，具有控制端Gx、第一端點X1與第二端點X2，其中控制端Gx與第一端點X1連接於前級輸入線IN1。第二主動元件T2具有控制端Gx、第一端點X1與第二端點X2，而控制端Gx連接於第一主動元件T1之第二端點X2，且第一端點X1電性連接於時脈訊號線CK，第二端點X2連接於輸出線OP。第三主動元件T3具有控制端Gx、第一端點X1與第二端點X2，而第一端點X1連接於電源訊號線VSS，第二端點X2電性連接第一主動元件T1之該第二端點X2，且控制端Gx連接於後級輸入線IN2。另外，第四主動元件T4具有控制端Gx、第一端點X1與第二端點X2，而控制端Gx電性連接於後級輸入線IN2，第一端點X1則電性連接於輸出線OP，第二端點X2則連接於電源訊號線VSS。FIG. 3 is a circuit diagram of a driving unit according to an embodiment of the present invention. In this embodiment, the gate driving circuit located in the pixel array 101 of FIGS. 2A to 2C may be composed of a plurality of driving units 200 as shown in FIG. 3. In detail, the gate driving circuit is a multi-stage driving unit formed by a plurality of driving units 200 connected in series, and each stage driving unit can output to a corresponding gate line. For example, the driving unit of the first stage can be output to the first gate line, and the driving unit of the second stage can be output to the second gate line, which form a relative relationship in order. For the convenience of explanation, the following content is Take the Nth level for description, that is, the Nth level driving unit can output to the Nth gate line, where N is a positive integer. In this embodiment, the signal lines SL of FIGS. 2A to 2C may include, for example, a power signal line VSS, a clock signal line CK, a front stage input line IN1, a rear stage input line IN2, and an output line OP. Referring to FIG. 3, the driving unit 200 includes four active elements (T1 to T4). More specifically, the first active element T1 has a control terminal Gx, a first terminal X1, and a second terminal X2, wherein the control terminal Gx and the first terminal X1 are connected to the previous-stage input line IN1. The second active device T2 has a control terminal Gx, a first terminal X1, and a second terminal X2. The control terminal Gx is connected to the second terminal X2 of the first active device T1, and the first terminal X1 is electrically connected to The clock signal line CK and the second terminal X2 are connected to the output line OP. The third active device T3 has a control terminal Gx, a first terminal X1, and a second terminal X2. The first terminal X1 is connected to the power signal line VSS, and the second terminal X2 is electrically connected to the first active device T1. The second end point X2, and the control end Gx is connected to the subsequent input line IN2. In addition, the fourth active element T4 has a control terminal Gx, a first terminal X1, and a second terminal X2. The control terminal Gx is electrically connected to the input line IN2 of the rear stage, and the first terminal X1 is electrically connected to the output line. OP, the second terminal X2 is connected to the power signal line VSS.

如圖3所示，當前級輸入線IN1是電性連接至第(N-1)條閘極線G(n-1)時，則輸出線OP是電性連接至第N條閘極線G(n)，且後級輸入線IN2是電性連接至第(N+1)條閘極線G(n+1)，其中N為大於1的整數。舉例來說，若前級輸入線IN1是電性連接至第一條閘極線時，則輸出線OP是電性連接至第二條閘極線，且後級輸入線IN2是電性連接至第三條閘極線。依據圖3的電性連接方式做為基礎，驅動單元200於畫素陣列101中的設置方式有圖4A以及圖4B兩種實施方式。As shown in FIG. 3, when the current input line IN1 is electrically connected to the (N-1) th gate line G (n-1), the output line OP is electrically connected to the Nth gate line G (n), and the subsequent input line IN2 is electrically connected to the (N + 1) th gate line G (n + 1), where N is an integer greater than 1. For example, if the previous-stage input line IN1 is electrically connected to the first gate line, the output line OP is electrically connected to the second gate line, and the subsequent-stage input line IN2 is electrically connected to The third gate line. Based on the electrical connection method shown in FIG. 3, the driving unit 200 can be arranged in the pixel array 101 in two ways, as shown in FIG. 4A and FIG. 4B.

圖4A為依據圖3實施例的驅動單元的一種設置方式示意圖。在圖4A的實施例中，驅動單元200包括第一驅動單元200A、第二驅動單元200B以及第三驅動單元200C的重複排列所構成。也就是說，閘極驅動電路會依序有多個第一驅動單元200A、第二驅動單元200B以及第三驅動單元200C的重複排列所構成。如圖4A所示，每一個驅動單元(200A、200B、200C)的前級輸入線IN1、後級輸入線IN2與輸出線OP分別連接至位於顯示區DR內的其中三條閘極線，且至少一個子畫素102是位於時脈訊號線CK與其中一條該資料線DL之間。另外，每一個驅動單元(200A、200B、200C)的連接方式可參考圖3的實施例進行設置。FIG. 4A is a schematic diagram of a setting manner of the driving unit according to the embodiment in FIG. 3. In the embodiment of FIG. 4A, the driving unit 200 includes a repeating arrangement of a first driving unit 200A, a second driving unit 200B, and a third driving unit 200C. In other words, the gate driving circuit is composed of a plurality of repeated arrangements of the first driving unit 200A, the second driving unit 200B, and the third driving unit 200C in order. As shown in FIG. 4A, the front-stage input line IN1, the rear-stage input line IN2, and the output line OP of each driving unit (200A, 200B, 200C) are respectively connected to three gate lines in the display area DR, and at least A sub-pixel 102 is located between the clock signal line CK and one of the data lines DL. In addition, the connection mode of each drive unit (200A, 200B, 200C) can be set with reference to the embodiment of FIG. 3.

詳細來說，在圖4A的實施例中，閘極線包含第N-1條閘極線、第N條閘極線、第N+1條閘極線、第N+2條閘極線與第N+3條閘極線，其中N為大於1的整數。如圖4A所示，於第一驅動單元200A中，前級輸入線IN1是連接至該第(N-1)條閘極線G(n-1)，後級輸入線IN2是連接至該第(N+1)閘極線G(n+1)，而輸出線OP是連接於第N條閘極線G(n)。於第二驅動單元200B中，前級輸入線IN1是連接至第N條閘極線G(n)，後級輸入線IN2是連接於該第(N+2)條閘極線G(n+2)，而輸出線OP連接於第N+1條閘極線G(n+1)。此外，於第三驅動單元200C中，前級輸入線IN1是連接至該第(N+1)條閘極線G(n+1)，後級輸入線IN2是連接於第(N+3)條閘極線G(n+3)，且輸出線OP連接至第(N+2)條閘極線G(n+2)。In detail, in the embodiment of FIG. 4A, the gate lines include the N-1th gate line, the Nth gate line, the N + 1th gate line, the N + 2th gate line and The N + 3 gate line, where N is an integer greater than 1. As shown in FIG. 4A, in the first driving unit 200A, the front stage input line IN1 is connected to the (N-1) th gate line G (n-1), and the rear stage input line IN2 is connected to the first The (N + 1) gate line G (n + 1), and the output line OP is connected to the Nth gate line G (n). In the second driving unit 200B, the front-stage input line IN1 is connected to the Nth gate line G (n), and the rear-stage input line IN2 is connected to the (N + 2) th gate line G (n + 2), and the output line OP is connected to the N + 1th gate line G (n + 1). In addition, in the third driving unit 200C, the front stage input line IN1 is connected to the (N + 1) th gate line G (n + 1), and the rear stage input line IN2 is connected to the (N + 3) th Gate lines G (n + 3), and the output line OP is connected to the (N + 2) th gate line G (n + 2).

另外，請參考圖4A，第一驅動單元200A、第二驅動單元200B與第三驅動單元200C中的第一主動元件T1、第二主動元件T2、第三主動元件T3以及第四主動元件T4分別是沿著閘極線(G(n-1)、G(n)、G(n+1)…)的延伸方向設置在同一水平線LN1上。舉例來說，「同一水平線」的設置意指所有驅動單元的第一主動元件T1、第二主動元件T2、第三主動元件T3以及第四主動元件T4是設置在位於其中一條閘極線延伸方向兩側的相鄰兩排子畫素102之間的空間。以圖4A之第(N+1)條閘極線G(n+1)來說，水平線LN1係位於第(N+1)條閘極線G(n+1)兩側之兩排子畫素102之間的空間，且其空間可與第(N+1)條閘極線G(n+1)的延伸方向而延伸。因此，於本實施例中，驅動單元的第一主動元件T1、第二主動元件T2、第三主動元件T3以及第四主動元件T4是設置同一空間中。更特別是，在圖4A中，第一驅動單元200A、第二驅動單元200B與第三驅動單元200C中的四個主動元件(T1~T4)在水平線LN1上分別具有規律的排列順序，且依序為第三主動元件T3、第一主動元件T1、第二主動元件T2以及第四主動元件T4。在本發明實施例中，「規律的排列順序」意指在每一個驅動單元(200A、200B、200C)中，所有的主動元件由左至右都是以第三主動元件T3、第一主動元件T1、第二主動元件T2以及第四主動元件T4順序進行排列。據此，藉由圖4A所示的配置方式，能夠有效將包括四個主動元件的驅動單元200設置在顯示區DR的畫素陣列101之中。In addition, please refer to FIG. 4A, the first driving unit 200A, the second driving unit 200B, and the third driving unit 200C include the first active element T1, the second active element T2, the third active element T3, and the fourth active element T4, respectively. It is arranged on the same horizontal line LN1 along the extending direction of the gate lines (G (n-1), G (n), G (n + 1), ...). For example, the setting of "the same horizontal line" means that the first active element T1, the second active element T2, the third active element T3, and the fourth active element T4 of all the driving units are disposed in a direction where one of the gate lines extends. The space between two adjacent rows of sub-pixels 102 on both sides. Taking the (N + 1) th gate line G (n + 1) in FIG. 4A, the horizontal line LN1 is two rows of sub-pictures located on both sides of the (N + 1) th gate line G (n + 1) The space between the primes 102 can extend with the extending direction of the (N + 1) th gate line G (n + 1). Therefore, in this embodiment, the first active element T1, the second active element T2, the third active element T3, and the fourth active element T4 of the driving unit are disposed in the same space. More specifically, in FIG. 4A, the four active elements (T1 to T4) in the first driving unit 200A, the second driving unit 200B, and the third driving unit 200C respectively have a regular arrangement order on the horizontal line LN1, and according to The sequence is a third active element T3, a first active element T1, a second active element T2, and a fourth active element T4. In the embodiment of the present invention, “regular arrangement order” means that in each driving unit (200A, 200B, 200C), all the active elements from the left to the right are the third active element T3 and the first active element. T1, second active element T2, and fourth active element T4 are sequentially arranged. Accordingly, with the arrangement shown in FIG. 4A, the driving unit 200 including four active elements can be effectively disposed in the pixel array 101 of the display area DR.

圖4B為依據圖3實施例的驅動單元的另一種設置方式示意圖。圖4B與圖4A的實施例中，驅動單元200同樣是由包括第一驅動單元200A、第二驅動單元200B以及第三驅動單元200C的重複排列所構成。圖4B與圖4A的差異在於訊號線的走線方式及主動元件的設置方式不同。然而，在圖4B中，其驅動單元(200A、200B、200C)的連接方式仍是對應於圖3的實施例進行設置。FIG. 4B is a schematic diagram of another arrangement manner of the driving unit according to the embodiment in FIG. 3. In the embodiment of FIG. 4B and FIG. 4A, the driving unit 200 is also composed of a repeated arrangement including a first driving unit 200A, a second driving unit 200B, and a third driving unit 200C. The difference between FIG. 4B and FIG. 4A lies in the routing of the signal lines and the arrangement of the active components. However, in FIG. 4B, the connection mode of the driving units (200A, 200B, 200C) is still set corresponding to the embodiment of FIG. 3.

如圖4B所示，第一驅動單元200A的第二主動元件T2以及第四主動元件T4是經由第二驅動單元200B的第一主動元件T1連接至第N條閘極線G(n)。也就是說，第一驅動單元200A的輸出線OP與第二驅動單元200B的前級輸入線IN1為相同的走線。另外，第二驅動單元200B的第三主動元件T3以及第四主動元件T4與第三驅動單元200C的第二主動元件T2是透過相同走線共同連接到第(N+2)條閘極線G(n+2)。也就是說，第二驅動單元200B的後級輸入線IN2與第三驅動單元200C的輸出線OP為相同走線。藉由圖4B的走線方式，可將第二驅動單元200B的第三主動元件T3與第四主動元件T4合併，且將第三驅動單元200C的第一主動元件T1與第三主動元件T3合併。據此，能夠進一步節省走線設置空間，達到更佳的面板設計。As shown in FIG. 4B, the second active element T2 and the fourth active element T4 of the first driving unit 200A are connected to the Nth gate line G (n) via the first active element T1 of the second driving unit 200B. That is, the output line OP of the first driving unit 200A and the previous-stage input line IN1 of the second driving unit 200B are the same wiring. In addition, the third active element T3 and the fourth active element T4 of the second driving unit 200B and the second active element T2 of the third driving unit 200C are commonly connected to the (N + 2) gate line G through the same wiring. (n + 2). That is, the input line IN2 of the second stage of the second driving unit 200B and the output line OP of the third driving unit 200C are the same. 4B, the third active element T3 and the fourth active element T4 of the second driving unit 200B can be combined, and the first active element T1 and the third active element T3 of the third driving unit 200C can be combined. . Accordingly, the space for wiring arrangement can be further saved, and a better panel design can be achieved.

另外，請繼續參考圖4B，在本實施例中，第一驅動單元200A與第二驅動單元200B的第一主動元件T1、第二主動元件T2、第三主動元件T3以及第四主動元件T4分別是沿著閘極線(G(n-1)、G(n+1)、G(n+3)…)的延伸方向設置在同一水平線LN1上，且第三驅動單元200C的第四主動元件T4是設置在與第三驅動單元200C的第一主動元件T1、第二主動元件T2以及第三主動元件T3不同的水平線上。詳細來說，在第三驅動單元200C中，第一主動元件T1、第二主動元件T2以及第三主動元件T3仍是位於水平線LN1上，而第三驅動單元200C的第四主動元件T4則是位於水平線LN2上。In addition, please continue to refer to FIG. 4B. In this embodiment, the first driving unit 200A and the second driving unit 200B have a first active element T1, a second active element T2, a third active element T3, and a fourth active element T4, respectively. The fourth active element of the third driving unit 200C is arranged on the same horizontal line LN1 along the extension direction of the gate lines (G (n-1), G (n + 1), G (n + 3) ...). T4 is disposed on a different horizontal line from the first active element T1, the second active element T2, and the third active element T3 of the third driving unit 200C. In detail, in the third driving unit 200C, the first active element T1, the second active element T2, and the third active element T3 are still located on the horizontal line LN1, and the fourth active element T4 of the third driving unit 200C is Located on the horizontal line LN2.

更詳細來說，在圖4B的實施例中，第一驅動單元200A與第二驅動單元200B的第一主動元件T1、第二主動元件T2、第三主動元件T3以及第四主動元件T4是設置於第N+1條閘極線G(n+1)與第N+2條閘極線G(n+2)之間，以使該些主動元件位於相同水平線LN1。此外，在第三驅動單元200C中的第一主動元件T1、第二主動元件T2以及第三主動元件T3同樣是設置於第N+1條閘極線G(n+1)與第N+2條閘極線G(n+2)之間以位於相同水平線LN1。在第三驅動單元200C的第四主動元件T4則是設置於第N+2條閘極線G(n+2)與第N+3條閘極線G(n+3)之間，以位於水平線LN2上。於圖4B之實施例中，水平線LN1係位於第(N+1)條閘極線G(n+1)兩側之兩排子畫素102之間的空間，且其空間可依第(N+1)條閘極線G(n+1)的延伸方向而延伸；而水平線LN2則係位於第(N+2)條閘極線G(n+2)兩側之兩排子畫素102之間的空間，且其空間可依第(N+2)條閘極線G(n+2)的延伸方向而延伸。In more detail, in the embodiment of FIG. 4B, the first driving element T1, the second driving element T2, the third driving element T3, and the fourth driving element T4 of the first driving unit 200A and the second driving unit 200B are provided. Between the N + 1th gate line G (n + 1) and the N + 2th gate line G (n + 2), so that the active components are located on the same horizontal line LN1. In addition, the first active element T1, the second active element T2, and the third active element T3 in the third driving unit 200C are also disposed on the N + 1th gate line G (n + 1) and the N + 2th The gate lines G (n + 2) are located between the same horizontal lines LN1. The fourth active element T4 in the third driving unit 200C is disposed between the N + 2th gate line G (n + 2) and the N + 3th gate line G (n + 3) so as to be located between On the horizontal line LN2. In the embodiment of FIG. 4B, the horizontal line LN1 is a space between two rows of the sub-pixels 102 on both sides of the (N + 1) gate line G (n + 1), and the space can be determined according to the (N +1) extend along the extension direction of the gate line G (n + 1); and the horizontal line LN2 is two rows of sub-pixels 102 on both sides of the (N + 2) th gate line G (n + 2) The space between them can extend according to the extending direction of the (N + 2) th gate line G (n + 2).

再者，在本實施例中，第一驅動單元200A、第二驅動單元200B與第三驅動單元200C中沿著閘極線(G(n-1)、G(n)、G(n+1)…)的延伸方向設置的四個主動元件(T1、T2、T3、T4)分別具有不規律的排列順序。也就是說，在每一個驅動單元(200A、200B、200C)中，所有的主動元件由左至右的排列順序皆不同。更具體地，第一驅動單元200A中主動元件由左至右的順序為第三主動元件T3、第一主動元件T1、第二主動元件T2與第四主動元件T4。在第二驅動單元200B中主動元件由左至右的順序為第一主動元件T1、第二主動元件T2、第三主動元件T3與第四主動元件T4。而在第三驅動單元200C中主動元件由左至右的順序為第二主動元件T2、第一主動元件T1、第三主動元件T3與第四主動元件T4。據此，能夠有效將包括四個主動元件的驅動單元200設置在顯示區DR的畫素陣列101之中。Moreover, in this embodiment, the first driving unit 200A, the second driving unit 200B, and the third driving unit 200C are along the gate lines (G (n-1), G (n), G (n + 1) ) ...), the four active elements (T1, T2, T3, T4) are arranged in an irregular order. That is, in each driving unit (200A, 200B, 200C), the arrangement order of all the active components from left to right is different. More specifically, the order of the active elements in the first driving unit 200A from left to right is the third active element T3, the first active element T1, the second active element T2, and the fourth active element T4. The order of the active elements in the second driving unit 200B from left to right is the first active element T1, the second active element T2, the third active element T3, and the fourth active element T4. In the third driving unit 200C, the order of the active elements from left to right is the second active element T2, the first active element T1, the third active element T3, and the fourth active element T4. Accordingly, the driving unit 200 including the four active elements can be effectively disposed in the pixel array 101 of the display area DR.

在上述圖3、圖4A及圖4B的實施例中，各個驅動單元(200A、200B、200C)都是包括四個主動元件，然而，本發明不以此為限。在其它實施例中，驅動單元中的主動元件數量可以依據需求來進行調整。舉例來說，在以下圖5及圖6的實施例中，是以各個驅動單元包括七個主動元件來做說明。In the above-mentioned embodiments of FIGS. 3, 4A, and 4B, each driving unit (200A, 200B, 200C) includes four active elements, however, the present invention is not limited thereto. In other embodiments, the number of active components in the driving unit can be adjusted according to requirements. For example, in the following embodiments of FIG. 5 and FIG. 6, each driving unit includes seven active elements for description.

圖5為依據本發明另一實施例的驅動單元之電路圖。在本實施例中，位於圖2A至圖2C之畫素陣列101中的閘極驅動電路可由多個如圖5所示的驅動單元200’所構成。在本實施例中，圖2A至圖2C訊號線SL可例如包含電源訊號線VSS、第一時脈訊號線CK1、第二時脈訊號線CK2、前級輸入線IN1、後級輸入線IN2與輸出線OP。參考圖5，驅動單元200’包括七個主動元件(M1~M7)。FIG. 5 is a circuit diagram of a driving unit according to another embodiment of the present invention. In this embodiment, the gate driving circuit in the pixel array 101 shown in FIGS. 2A to 2C may be composed of a plurality of driving units 200 'as shown in FIG. In this embodiment, the signal lines SL in FIGS. 2A to 2C may include, for example, a power signal line VSS, a first clock signal line CK1, a second clock signal line CK2, a front-stage input line IN1, and a rear-stage input line IN2 and Output line OP. Referring to FIG. 5, the driving unit 200 'includes seven active elements (M1 to M7).

更具體地，第一主動元件M1具有控制端Gx、第一端點X1與第二端點X2，其中第一主動元件M1的控制端Gx連接至後級輸入線IN2，第一端點X1連接至電源訊號線VSS。第二主動元件M2具有控制端Gx、第一端點X1與第二端點X2，其中第二主動元件M2的第一端點X1連接至電源訊號線VSS，控制端Gx連接至第一主動元件M1之第二端點X2。第三主動元件M3具有控制端Gx、第一端點X1與第二端點X2，其中第三主動元件M3的控制端Gx連接至第二主動元件M2之第二端點X2，第一端點X1連接至電源訊號線VSS，第二端點X2連接第一主動元件M1之第二端點X2。第四主動元件M4具有控制端Gx、第一端點X1與第二端點X2，其中第四主動元件M4的控制端Gx與第一端點X1連接於前級輸入線IN2，第二端點X2連接至第一主動元件M1的第二端點X2。第五主動元件M5具有控制端Gx、第一端點X1與第二端點X2，其中第五主動元件M5的控制端Gx連接至第二時脈訊號線CK2，第一端點X1連接至輸出線OP，且第二端點X2連接至電源訊號線VSS。第六主動元件M6具有控制端Gx、第一端點X1與第二端點X2，其中第六主動元件M6的控制端Gx連接至第二主動元件M2之第二端點X2，第一端點X1連接至電源訊號線VSS，且第二端點X2連接至輸出線OP。第七主動元件M7具有控制端Gx、第一端點X1與第二端點X2，其中第七主動元件M7的控制端Gx連接至第四主動元件M4的第二端點X2，第七主動元件M7的第一端點M1連接至輸出線OP，且第二端點X2連接至第一時脈訊號線CK1。More specifically, the first active element M1 has a control end Gx, a first end point X1, and a second end point X2, wherein the control end Gx of the first active element M1 is connected to the subsequent input line IN2, and the first end point X1 is connected To the power signal line VSS. The second active device M2 has a control terminal Gx, a first terminal X1, and a second terminal X2. The first terminal X1 of the second active device M2 is connected to the power signal line VSS, and the control terminal Gx is connected to the first active device. The second endpoint X2 of M1. The third active element M3 has a control end Gx, a first end point X1, and a second end point X2. The control end Gx of the third active element M3 is connected to the second end point X2 of the second active element M2. The first end point X1 is connected to the power signal line VSS, and the second terminal X2 is connected to the second terminal X2 of the first active device M1. The fourth active element M4 has a control terminal Gx, a first terminal X1 and a second terminal X2, wherein the control terminal Gx and the first terminal X1 of the fourth active element M4 are connected to the previous input line IN2, and the second terminal X2 is connected to the second terminal X2 of the first active element M1. The fifth active device M5 has a control terminal Gx, a first terminal X1, and a second terminal X2. The control terminal Gx of the fifth active device M5 is connected to the second clock signal line CK2, and the first terminal X1 is connected to the output. Line OP, and the second terminal X2 is connected to the power signal line VSS. The sixth active element M6 has a control end Gx, a first end point X1, and a second end point X2. The control end Gx of the sixth active element M6 is connected to the second end point X2 of the second active element M2. The first end point X1 is connected to the power signal line VSS, and the second terminal X2 is connected to the output line OP. The seventh active element M7 has a control end Gx, a first end point X1, and a second end point X2, wherein the control end Gx of the seventh active element M7 is connected to the second end point X2 of the fourth active element M4, and the seventh active element The first terminal M1 of M7 is connected to the output line OP, and the second terminal X2 is connected to the first clock signal line CK1.

如圖5所示，當輸出線OP是電性連接至第N條閘極線G(n)時，則前級輸入線IN1是電性連接至第N-4條閘極線G(n-4)，且後級輸入線IN2是電性連接至第N+7條閘極線G(n+7) ，其中N為整數。此外，在圖5的實施例中，驅動單元200’更包括第一電容C1與第二電容C2。第一電容C1包括第一端點X1與第二端點X2，其中第一端點X1連接至輸出線OP，且第二端點X2連接至第一主動元件M1的第二端點X2。第二電容C2包括第一端點X1與第二端點X2，其中第一端點X1連接至第二主動元件M2的第二端點X2，且第二端點X2連接至第一時脈訊號線CK1。依據圖5的電性連接方式做為基礎，驅動單元200’於畫素陣列101中的設置方式是如圖6所示。As shown in FIG. 5, when the output line OP is electrically connected to the Nth gate line G (n), the previous-stage input line IN1 is electrically connected to the N-4th gate line G (n- 4), and the subsequent input line IN2 is electrically connected to the N + 7th gate line G (n + 7), where N is an integer. In addition, in the embodiment of FIG. 5, the driving unit 200 'further includes a first capacitor C1 and a second capacitor C2. The first capacitor C1 includes a first terminal X1 and a second terminal X2. The first terminal X1 is connected to the output line OP, and the second terminal X2 is connected to the second terminal X2 of the first active device M1. The second capacitor C2 includes a first terminal X1 and a second terminal X2. The first terminal X1 is connected to the second terminal X2 of the second active device M2, and the second terminal X2 is connected to the first clock signal. Line CK1. Based on the electrical connection method of FIG. 5, the arrangement of the driving unit 200 ′ in the pixel array 101 is as shown in FIG. 6.

圖6為依據圖5實施例的驅動單元的一種設置方式示意圖。如圖6所示，在具有七個主動元件的實施例中，第一主動元件M1、第四主動元件M4、第五主動元件M5以及第七主動元件M7是沿著閘極線(G(n)、G(n+1)…)的延伸方向設置在同一水平線LN1上，且第二主動元件M2、第三主動元件M3以及第六主動元件M6是沿著閘極線(G(n+3)、G(n+4)…)的延伸方向設置在另一相同的水平線LN2上。更具體地，第一主動元件M1、第四主動元件M4、第五主動元件M5以及第七主動元件M7是設置於閘極線G(n)以及閘極線G(n+1)之間，以位於水平線LN1上。此外，第二主動元件M2、第三主動元件M3以及第六主動元件M6是設置於閘極線G(n+3)以及閘極線G(n+4)之間，以位於水平線LN2上。換言之，於圖6之實施例中，水平線LN1係位於第N條閘極線G(n)兩側之兩排子畫素102之間的空間，且其空間可依第N條閘極線G(n)的延伸方向而延伸；而水平線LN2則係位於第(N+3)條閘極線G(n+3)兩側之兩排子畫素102之間的空間，且其空間可依第(N+3)條閘極線G(n+3)的延伸方向而延伸。據此，能夠有效將包括七個主動元件的驅動單元200’設置在顯示區DR的畫素陣列101之中。FIG. 6 is a schematic diagram of a setting manner of the driving unit according to the embodiment of FIG. 5. As shown in FIG. 6, in an embodiment having seven active elements, the first active element M1, the fourth active element M4, the fifth active element M5, and the seventh active element M7 are along the gate line (G (n ), G (n + 1) ...) are set on the same horizontal line LN1, and the second active element M2, the third active element M3, and the sixth active element M6 are along the gate line (G (n + 3 ), G (n + 4) ...) are set on the same horizontal line LN2. More specifically, the first active element M1, the fourth active element M4, the fifth active element M5, and the seventh active element M7 are disposed between the gate line G (n) and the gate line G (n + 1), To be located on the horizontal line LN1. In addition, the second active element M2, the third active element M3, and the sixth active element M6 are disposed between the gate line G (n + 3) and the gate line G (n + 4) so as to be located on the horizontal line LN2. In other words, in the embodiment of FIG. 6, the horizontal line LN1 is a space between two rows of sub-pixels 102 located on both sides of the Nth gate line G (n), and the space can be determined according to the Nth gate line G (n) extends; and the horizontal line LN2 is the space between the two rows of sub-pixels 102 on both sides of the (N + 3) gate line G (n + 3), and the space can be determined according to The (N + 3) th gate line G (n + 3) extends. Accordingly, the driving unit 200 'including the seven active elements can be effectively disposed in the pixel array 101 of the display area DR.

綜上所述，本發明顯示面板的每一畫素單元是包括三條閘極線、兩條資料線以及六個子畫素，因此，能夠有多餘的空間將閘極驅動電路設置在顯示區的畫素陣列之中。具體來說，可將閘極驅動電路的各驅動單元設置在位於沒有資料線的子畫素之間的空間。據此，將閘極驅動電路移到顯示區時，能夠達到降低成本、大幅縮減邊框及增加顯示區面積的技術效果。In summary, each pixel unit of the display panel of the present invention includes three gate lines, two data lines, and six sub-pixels. Therefore, there can be extra space for setting the gate drive circuit in the display area. Prime array. Specifically, each driving unit of the gate driving circuit may be disposed in a space between sub-pixels without data lines. According to this, when the gate driving circuit is moved to the display area, the technical effects of reducing costs, greatly reducing the frame, and increasing the area of the display area can be achieved.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100‧‧‧顯示面板100‧‧‧ display panel

101‧‧‧畫素陣列101‧‧‧ pixel array

102、102A、102B、102C、102D、102E、102F‧‧‧子畫素102, 102A, 102B, 102C, 102D, 102E, 102F ‧‧‧ sub pixels

200、200’、200A、200B、200C‧‧‧驅動單元200, 200 ’, 200A, 200B, 200C‧‧‧ drive units

A1、A2、A3、A4、A5、A6‧‧‧開關元件A1, A2, A3, A4, A5, A6‧‧‧ switching elements

C1‧‧‧第一電容C1‧‧‧first capacitor

C2‧‧‧第二電容C2‧‧‧Second capacitor

CK、CK1、CK2‧‧‧時脈訊號線CK, CK1, CK2 ‧‧‧ clock signal line

DL、DL1、DL2‧‧‧資料線DL, DL1, DL2‧‧‧ data line

DR‧‧‧顯示區DR‧‧‧Display Area

GL1、GL2、GL3、G(n-4)、G(n-1)、G(n)、G(n+1)、G(n+2)、G(n+3)、G(n+4)、G(n+5)、G(n+6)、G(n+7)‧‧‧閘極線GL1, GL2, GL3, G (n-4), G (n-1), G (n), G (n + 1), G (n + 2), G (n + 3), G (n + 4), G (n + 5), G (n + 6), G (n + 7) ‧‧‧Gate line

Gx‧‧‧控制端Gx‧‧‧Control

IN1‧‧‧前級輸入線IN1‧‧‧Previous input line

IN2‧‧‧後級輸入線IN2‧‧‧ post input line

LN1、LN2‧‧‧水平線LN1, LN2‧‧‧Horizontal

NR‧‧‧非顯示區NR‧‧‧non-display area

OP‧‧‧輸出線OP‧‧‧ output line

PX1、PX2、PX3、PX4‧‧‧畫素單元PX1, PX2, PX3, PX4 ‧‧‧ pixel units

SL‧‧‧訊號線SL‧‧‧Signal line

M1、M2、M3、M4、M5、M6、M7、T1、T2、T3、T4、TFT‧‧‧主動元件M1, M2, M3, M4, M5, M6, M7, T1, T2, T3, T4, TFT‧‧‧ active components

VSS‧‧‧電源訊號線VSS‧‧‧Power signal line

X1‧‧‧第一端點X1‧‧‧ first endpoint

X2‧‧‧第二端點X2‧‧‧Second endpoint

圖1為依據本發明一實施例的顯示面板的上視示意圖。圖2A為依據本發明一實施例的畫素陣列的排列示意圖。圖2B為依據本發明另一實施例的畫素陣列的排列示意圖。圖2C為依據本發明另一實施例的畫素陣列的排列示意圖。圖3為依據本發明一實施例的驅動單元之電路圖。圖4A為依據圖3實施例的驅動單元的一種設置方式示意圖。圖4B為依據圖3實施例的驅動單元的另一種設置方式示意圖。圖5為依據本發明另一實施例的驅動單元之電路圖。圖6為依據圖5實施例的驅動單元的一種設置方式示意圖。FIG. 1 is a schematic top view of a display panel according to an embodiment of the present invention. FIG. 2A is an arrangement diagram of a pixel array according to an embodiment of the present invention. FIG. 2B is an arrangement diagram of a pixel array according to another embodiment of the present invention. FIG. 2C is an arrangement diagram of a pixel array according to another embodiment of the present invention. FIG. 3 is a circuit diagram of a driving unit according to an embodiment of the present invention. FIG. 4A is a schematic diagram of a setting manner of the driving unit according to the embodiment in FIG. 3. FIG. 4B is a schematic diagram of another arrangement manner of the driving unit according to the embodiment in FIG. 3. FIG. 5 is a circuit diagram of a driving unit according to another embodiment of the present invention. FIG. 6 is a schematic diagram of a setting manner of the driving unit according to the embodiment of FIG. 5.

Claims

一種顯示面板，包括：一顯示區以及一非顯示區，該非顯示區位於該顯示區之一側；多條閘極線，設置於該顯示區；多條資料線，設置於該顯示區；畫素陣列，位於該顯示區之中，且該畫素陣列藉由多個重複排列的畫素單元所構成，其中各該畫素單元包括三條閘極線、兩條資料線以及六個子畫素，且各該子畫素分別與該畫素陣列中的其中一條閘極線以及其中一條資料線電性連接；以及一閘極驅動電路，位於該畫素陣列之中。A display panel includes: a display area and a non-display area, the non-display area is located on one side of the display area; a plurality of gate lines are provided in the display area; a plurality of data lines are provided in the display area; A pixel array is located in the display area, and the pixel array is composed of a plurality of pixel units arranged repeatedly, wherein each pixel unit includes three gate lines, two data lines, and six sub pixels, Each of the sub-pixels is electrically connected to one of the gate lines and one of the data lines in the pixel array; and a gate driving circuit is located in the pixel array.

如申請專利範圍第1項所述的顯示面板，其中該閘極驅動電路包括多個驅動單元，各該驅動單元包括多個主動元件與多條訊號線，其中該些訊號線的其中之一與該些資料線實質上平行設置。The display panel according to item 1 of the scope of patent application, wherein the gate driving circuit includes a plurality of driving units, each of the driving units includes a plurality of active components and a plurality of signal lines, and one of the signal lines and The data lines are arranged substantially in parallel.

如申請專利範圍第2項所述的顯示面板，其中該些訊號線可包含一電源訊號線、一時脈訊號線、一前級輸入線、一後級輸入線與一輸出線，其中該前級輸入線、該後級輸入線與該輸出線分別連接至位於該顯示區內之三條閘極線，且至少一個該子畫素是位於該時脈訊號線與其中一條該資料線之間。The display panel according to item 2 of the scope of patent application, wherein the signal lines may include a power signal line, a clock signal line, a front input line, a rear input line and an output line, wherein the front stage The input line, the subsequent input line and the output line are respectively connected to three gate lines located in the display area, and at least one of the sub-pixels is located between the clock signal line and one of the data lines.

如申請專利範圍第3項所述的顯示面板，其中該些驅動單元包括一第一驅動單元、一第二驅動單元以及一第三驅動單元的重複排列所構成，且該第一驅動單元、該第二驅動單元以及該第三驅動單元各自包括四個主動元件。The display panel according to item 3 of the scope of patent application, wherein the driving units include a repeating arrangement of a first driving unit, a second driving unit, and a third driving unit, and the first driving unit, the Each of the second driving unit and the third driving unit includes four active elements.

如申請專利範圍第4項所述的顯示面板，其中該第一驅動單元、該第二驅動單元與該第三驅動單元分別包含：一第一主動元件，具有一控制端、一第一端點與一第二端點，其中該控制端與該第一端點連接於該前級輸入線；一第二主動元件，具有一控制端、一第一端點與一第二端點，而該控制端連接於該第一主動元件之該第二端點，且該第一端點電性連接於該時脈訊號線，該第二端點連接於該輸出線；一第三主動元件，具有一控制端、一第一端點與一第二端點，而該第一端點連接於該電源訊號線，該第二端點電性連接該第一主動元件之該第二端點，且該控制端連接於該後級輸入線；以及一第四主動元件，具有一控制端、一第一端點與一第二端點，而該控制端電性連接於該後級輸入線，該第一端點則電性連接於該輸出線。The display panel according to item 4 of the scope of patent application, wherein the first driving unit, the second driving unit, and the third driving unit each include: a first active element having a control end and a first end point And a second end point, wherein the control end and the first end point are connected to the front-end input line; a second active element having a control end, a first end point and a second end point, and the The control end is connected to the second end of the first active element, and the first end is electrically connected to the clock signal line, and the second end is connected to the output line; a third active element, having A control terminal, a first terminal, and a second terminal, and the first terminal is connected to the power signal line, the second terminal is electrically connected to the second terminal of the first active component, and The control terminal is connected to the rear-stage input line; and a fourth active element having a control terminal, a first terminal and a second terminal, and the control terminal is electrically connected to the rear-stage input line, the The first terminal is electrically connected to the output line.

如申請專利範圍第5項所述的顯示面板，其中該些閘極線包含一第(N-1)條閘極線、一第N條閘極線、一第(N+1)條閘極線、一第(N+2)條閘極線與一第(N+3)條閘極線，其中N為大於1之整數，且於該第一驅動單元中，該前級輸入線連接至該第(N-1)閘極線，該後級輸入線連接至該第(N+1)閘極線，該輸出線連接於該第N條閘極線；於該第二驅動單元中，該前級輸入線連接至該第N條閘極線，該後級輸入線連接於該第(N+2)條閘極線，而該輸出線連接於該第(N+1)條閘極線；於該第三驅動單元中，該前級輸入線連接至該第(N+1)條閘極線，該後級輸入線連接於該第(N+3)條閘極線，且該輸出線連接至該第(N+2)條閘極線。The display panel according to item 5 of the scope of patent application, wherein the gate lines include an (N-1) gate line, an N gate line, and an (N + 1) gate line Line, a (N + 2) th gate line and a (N + 3) th gate line, where N is an integer greater than 1, and in the first driving unit, the previous input line is connected to The (N-1) th gate line, the subsequent input line is connected to the (N + 1) th gate line, and the output line is connected to the Nth gate line; in the second driving unit, The front stage input line is connected to the Nth gate line, the rear stage input line is connected to the (N + 2) th gate line, and the output line is connected to the (N + 1) th gate Line; in the third driving unit, the front-stage input line is connected to the (N + 1) th gate line, the rear-stage input line is connected to the (N + 3) th gate line, and the The output line is connected to the (N + 2) th gate line.

如申請專利範圍第6項所述的顯示面板，其中該第一驅動單元、該第二驅動單元與該第三驅動單元中的該第一主動元件、該第二主動元件、該第三主動元件以及該第四主動元件分別是沿著該些閘極線的延伸方向設置在同一水平線上。The display panel according to item 6 of the scope of patent application, wherein the first driving unit, the second driving unit, and the third driving unit of the first active element, the second active element, and the third active element And the fourth active element is respectively disposed on the same horizontal line along the extending directions of the gate lines.

如申請專利範圍第7項所述的顯示面板，其中在該第一驅動單元、該第二驅動單元與該第三驅動單元中的四個主動元件在該水平線上分別具有規律的排列順序，且依序為該第三主動元件、該第一主動元件、該第二主動元件以及該第四主動元件。The display panel according to item 7 of the scope of patent application, wherein the four active elements in the first driving unit, the second driving unit, and the third driving unit respectively have a regular arrangement order on the horizontal line, and The third active element, the first active element, the second active element, and the fourth active element are in this order.

如申請專利範圍第6項所述的顯示面板，其中該第一驅動單元與該第二驅動單元的該第一主動元件、該第二主動元件、該第三主動元件以及該第四主動元件分別是沿著該些閘極線的延伸方向設置在同一水平線上，且該第三驅動單元的該第四主動元件是設置在與該第三驅動單元的該第一主動元件、該第二主動元件以及該第三主動元件不同的水平線上。The display panel according to item 6 of the scope of patent application, wherein the first driving element, the second driving element, the third driving element, and the fourth driving element of the first driving unit and the second driving unit are respectively Are arranged on the same horizontal line along the extension direction of the gate lines, and the fourth active element of the third driving unit is provided on the same level as the first active element and the second active element of the third driving unit And different horizontal lines of the third active element.

如申請專利範圍第9項所述的顯示面板，其中在該第一驅動單元、該第二驅動單元與該第三驅動單元中沿著該些閘極線的延伸方向設置的四個主動元件分別具有不規律的排列順序。The display panel according to item 9 of the scope of patent application, wherein the four active elements provided in the first driving unit, the second driving unit, and the third driving unit along the extending direction of the gate lines are respectively Has an irregular arrangement order.

如申請專利範圍第9項所述的顯示面板，其中在該第三驅動單元中的該第一主動元件、該第二主動元件以及該第三主動元件設置於該第(N+1)條閘極線與該第(N+2)條閘極線之間，且該第四主動元件設置於該第(N+2)條閘極線與該第(N+3)條閘極線之間。The display panel according to item 9 of the scope of patent application, wherein the first active element, the second active element, and the third active element in the third driving unit are disposed in the (N + 1) th gate Between the polar line and the (N + 2) th gate line, and the fourth active element is disposed between the (N + 2) th gate line and the (N + 3) th gate line .

如申請專利範圍第2項所述的顯示面板，其中該些驅動單元各自包括七個主動元件，其中該些訊號線可包含一電源訊號線、一第一時脈訊號線、一第二時脈訊號線、一前級輸入線、一後級輸入線與一輸出線。The display panel according to item 2 of the scope of patent application, wherein the driving units each include seven active components, wherein the signal lines may include a power signal line, a first clock signal line, and a second clock Signal line, a front input line, a rear input line and an output line.

如申請專利範圍第12項所述的顯示面板，其中該些驅動單元分別包含：一第一主動元件，具有一控制端、一第一端點與一第二端點，其中該第一主動元件的該控制端連接至該後級輸入線，該第一端點連接至該電源訊號線；一第二主動元件，具有一控制端、一第一端點與一第二端點，其中該第二主動元件的一第一端點連接至該電源訊號線，該控制端連接至該第一主動元件之該第二端點；一第三主動元件，具有一控制端、一第一端點與一第二端點，其中該第三主動元件的該控制端連接至該第二主動元件之該第二端點，該第一端點連接至該電源訊號線；一第四主動元件，具有一控制端、一第一端點與一第二端點，其中該第四主動元件的該控制端與該第一端點連接於該前級輸入線，該第二端點連接至該第一主動元件的該第二端點；一第五主動元件，具有一控制端、一第一端點與一第二端點，其中該第五主動元件的該控制端連接至該第二時脈訊號線，該第一端點連接至該輸出線，且該第二端點連接至該電源訊號線；一第六主動元件，具有一控制端、一第一端點與一第二端點，其中該第六主動元件的該控制端連接至該第二主動元件之該第二端點，該第一端點連接至該電源訊號線，且該第二端點連接至該輸出線；一第七主動元件，具有一控制端、一第一端點與一第二端點，其中該第七主動元件的該控制端連接至該第四主動元件的該第二端點，該第七主動元件的該第一端點連接至該輸出線，且該第二端點連接至該第一時脈訊號線。The display panel according to item 12 of the scope of patent application, wherein the driving units each include: a first active element having a control end, a first end point, and a second end point, wherein the first active element The control terminal is connected to the rear-stage input line, and the first terminal is connected to the power signal line; a second active element having a control terminal, a first terminal, and a second terminal, wherein the first A first terminal of two active components is connected to the power signal line, and the control terminal is connected to the second terminal of the first active component; a third active component has a control terminal, a first terminal and A second endpoint, wherein the control end of the third active element is connected to the second endpoint of the second active element, the first endpoint is connected to the power signal line; a fourth active element having a A control end, a first end point, and a second end point, wherein the control end and the first end point of the fourth active element are connected to the previous input line, and the second end point is connected to the first active end; The second endpoint of the element; a fifth active element having A control end, a first end point and a second end point, wherein the control end of the fifth active element is connected to the second clock signal line, the first end point is connected to the output line, and the first Two end points are connected to the power signal line; a sixth active element having a control end, a first end point and a second end point, wherein the control end of the sixth active element is connected to the second active element The second end point, the first end point is connected to the power signal line, and the second end point is connected to the output line; a seventh active element having a control end, a first end point, and a first Two endpoints, wherein the control end of the seventh active element is connected to the second endpoint of the fourth active element, the first endpoint of the seventh active element is connected to the output line, and the second end The dot is connected to the first clock signal line.

如申請專利範圍第13項所述的顯示面板，其中該些驅動單元中的該第一主動元件、該第四主動元件、該第五主動元件以及該第七主動元件沿著該些閘極線的延伸方向設置在同一水平線上，且該第二主動元件、該第三主動元件以及該第六主動元件沿著該些閘極線的延伸方向設置在另一相同的水平線上。The display panel according to item 13 of the scope of patent application, wherein the first active element, the fourth active element, the fifth active element, and the seventh active element in the driving units are along the gate lines. The extending direction of the second active element, the third active element, and the sixth active element are set on the same horizontal line along the extending directions of the gate lines.

如申請專利範圍第1項所述的顯示面板，其中各該畫素單元的三條閘極線包括一第一閘極線、一第二閘極線以及一第三閘極線，各該畫素單元的兩條資料線包括一第一資料線以及一第二資料線，各該畫素單元的六個子畫素包含一第一子畫素、一第二子畫素、一第三子畫素、一第四子畫素、一第五子畫素與一第六子畫素，其中於各該畫素單元中，該第一子畫素分別與該第一閘極線以及該第一資料線電性連接，該第二子畫素分別與該第一閘極線以及該第二資料線電性連接，該第三子畫素分別與該第二閘極線以及鄰接於該畫素單元的一另一畫素單元之該第一資料線電性連接，該第四子畫素分別與該第二閘極線以及該第二資料線電性連接，該第五子畫素分別與該第三閘極線以及該第二資料線電性連接，該第六子畫素分別與該第三閘極線以及該另一畫素單元之該第一資料線電性連接，且該第一子畫素、該第二子畫素以及該第三子畫素位於該第一閘極線與該第二閘極線之間，而該第四子畫素、該第五子畫素以及該第六子畫素位於該第二閘極線與該第三閘極線之間。The display panel according to item 1 of the scope of patent application, wherein each of the three gate lines of the pixel unit includes a first gate line, a second gate line, and a third gate line. The two data lines of the unit include a first data line and a second data line. Each of the six sub-pixels of the pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. , A fourth sub-pixel, a fifth sub-pixel, and a sixth sub-pixel, wherein in each of the pixel units, the first sub-pixel is respectively connected to the first gate line and the first data Line is electrically connected, the second sub-pixel is electrically connected to the first gate line and the second data line respectively, and the third sub-pixel is respectively connected to the second gate line and adjacent to the pixel unit The first data line of another pixel unit is electrically connected, the fourth sub-pixel is electrically connected to the second gate line and the second data line, respectively, and the fifth sub-pixel is respectively connected to the The third gate line and the second data line are electrically connected, and the sixth sub-pixel is respectively connected to the third gate line and the other pixel unit. The first data line is electrically connected, and the first sub-pixel, the second sub-pixel, and the third sub-pixel are located between the first gate line and the second gate line, and the first Four sub-pixels, the fifth sub-pixel, and the sixth sub-pixel are located between the second gate line and the third gate line.

如申請專利範圍第1項所述的顯示面板，其中各該畫素單元的三條閘極線包括一第一閘極線、一第二閘極線以及一第三閘極線，各該畫素單元的兩條資料線包括一第一資料線以及一第二資料線，各該畫素單元的六個子畫素包含一第一子畫素、一第二子畫素、一第三子畫素、一第四子畫素、一第五子畫素與一第六子畫素，其中於各該畫素單元中，該第一子畫素分別與該第一閘極線以及該第二資料線電性連接，該第二子畫素分別與該第一閘極線以及鄰接於該畫素單元的一另一畫素單元之該第一資料線電性連接，該第三子畫素分別與該第二閘極線以及該第二資料線電性連接，該第四子畫素分別與該第二閘極線以及該第一資料線電性連接，該第五子畫素分別與該第三閘極線以及該第二資料線電性連接，該第六子畫素分別與該第三閘極線以及該另一畫素單元之該第一資料線電性連接，該第一子畫素、該第二子畫素以及該第三子畫素位於該第一閘極線與該第二閘極線之間，而該第四子畫素、該第五子畫素以及該第六子畫素位於該第二閘極線與該第三閘極線之間。The display panel according to item 1 of the scope of patent application, wherein each of the three gate lines of the pixel unit includes a first gate line, a second gate line, and a third gate line. The two data lines of the unit include a first data line and a second data line. Each of the six sub-pixels of the pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. , A fourth sub-pixel, a fifth sub-pixel, and a sixth sub-pixel, wherein in each pixel unit, the first sub-pixel is respectively connected to the first gate line and the second data Line is electrically connected, the second sub-pixel is electrically connected to the first gate line and the first data line of another pixel unit adjacent to the pixel unit, respectively, and the third sub-pixel is respectively Is electrically connected to the second gate line and the second data line, the fourth sub-pixel is electrically connected to the second gate line and the first data line, and the fifth sub-pixel is respectively connected to the The third gate line and the second data line are electrically connected, and the sixth sub-pixel is respectively connected to the third gate line and the other pixel unit. The first data line is electrically connected, the first sub-pixel, the second sub-pixel, and the third sub-pixel are located between the first gate line and the second gate line, and the fourth The sub-pixel, the fifth sub-pixel, and the sixth sub-pixel are located between the second gate line and the third gate line.

如申請專利範圍第1項所述的顯示面板，其中各該畫素單元的三條閘極線包括一第一閘極線、一第二閘極線以及一第三閘極線，各該畫素單元的兩條資料線包括一第一資料線以及一第二資料線，各該畫素單元的六個子畫素包含一第一子畫素、一第二子畫素、一第三子畫素、一第四子畫素、一第五子畫素與一第六子畫素，其中於各該畫素單元中，該第一子畫素分別與該第一閘極線以及該第二資料線電性連接，該第二子畫素分別與該第二閘極線以及該第二資料線電性連接，該第三子畫素與該第一閘極線以及鄰接該畫素單元的一另一畫素單元之該第一資料線電性連接，該第四子畫素分別與該第二閘極線以及該第一資料線電性連接，該第五子畫素分別與該第三閘極線以及該第二資料線電性連接，該第六子畫素分別與該第三閘極線以及該另一畫素單元之該第一資料線電性連接，且該第一子畫素、該第二子畫素以及該第三子畫素位於該第一閘極線與該第二閘極線之間，而該第四子畫素、該第五子畫素以及該第六子畫素位於該第二閘極線與該第三閘極線之間。The display panel according to item 1 of the scope of patent application, wherein each of the three gate lines of the pixel unit includes a first gate line, a second gate line, and a third gate line. The two data lines of the unit include a first data line and a second data line. Each of the six sub-pixels of the pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. , A fourth sub-pixel, a fifth sub-pixel, and a sixth sub-pixel, wherein in each pixel unit, the first sub-pixel is respectively connected to the first gate line and the second data Line is electrically connected, the second sub-pixel is electrically connected to the second gate line and the second data line respectively, the third sub-pixel is connected to the first gate line and a pixel adjacent to the pixel unit The first data line of another pixel unit is electrically connected, the fourth sub-pixel is electrically connected to the second gate line and the first data line, respectively, and the fifth sub-pixel is connected to the third The gate line and the second data line are electrically connected, and the sixth sub-pixel is respectively connected to the third gate line and the first pixel unit of the other pixel unit. The data lines are electrically connected, and the first sub-pixel, the second sub-pixel, and the third sub-pixel are located between the first gate line and the second gate line, and the fourth sub-picture The pixel, the fifth sub-pixel, and the sixth sub-pixel are located between the second gate line and the third gate line.

如申請專利範圍第15至17項中任一項所述的顯示面板，其中該閘極驅動電路包括多個驅動單元，各該驅動單元包括多個主動元件與多條訊號線，而各該驅動單元則對應設置於相鄰之該些畫素單元所形成的區域。The display panel according to any one of claims 15 to 17, wherein the gate driving circuit includes a plurality of driving units, each of the driving units includes a plurality of active elements and a plurality of signal lines, and each of the driving units The unit is correspondingly arranged in the area formed by the adjacent pixel units.

如申請專利範圍第18項所述的顯示面板，其中各該驅動單元包含多個主動元件與多條訊號線，而該些訊號線的其中一條該訊號線位於其中一個該畫素單元中的該第二子畫素與該第三子畫素之間。The display panel according to item 18 of the scope of patent application, wherein each of the driving units includes a plurality of active components and a plurality of signal lines, and one of the signal lines of the signal lines is located in one of the pixel units. Between the second sub-pixel and the third sub-pixel.