TWI657251B - Semiconductor testing apparatus, semiconductor testing system and semiconductor testing method - Google Patents
Semiconductor testing apparatus, semiconductor testing system and semiconductor testing method Download PDFInfo
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Abstract
本揭露提供一種半導體測試裝置，包括：一基板；一金手指觸片結構，設置於該基板之一側。The present disclosure provides a semiconductor testing device comprising: a substrate; a gold finger contact structure disposed on one side of the substrate.
Description
本揭露係有關於半導體之領域，尤指一種半導體測試裝置、半導體測試系統以及半導體測試方法。 The disclosure relates to the field of semiconductors, and more particularly to a semiconductor test device, a semiconductor test system, and a semiconductor test method.
目前全球市場迫使大量產品的製造商以低價提供高品質的產品。因此，重要的是要提高良率及製程效率，以便將生產成本降至最低。此種情況尤其發生在半導體製造的領域，這是因為該領域將尖端技術(cutting edge technology)與大量生產技術結合。因此，半導體製造商之目標在於改善開發階段的效率同時提高量產階段製程的良率。 The global market currently forces manufacturers of a large number of products to provide high quality products at low prices. Therefore, it is important to increase yield and process efficiency to minimize production costs. This is especially the case in the field of semiconductor manufacturing because it combines cutting edge technology with mass production technology. Therefore, the goal of semiconductor manufacturers is to improve the efficiency of the development phase while improving the yield of the mass production process.
有鑑於此，本發明的目的在於提供一種半導體測試裝置以及相關系統和方法，以提升開發階段時的板階可靠度測試(Board Level Reliability Tests,BLRT)的效率。 In view of this, it is an object of the present invention to provide a semiconductor test apparatus and related systems and methods to improve the efficiency of Board Level Reliability Tests (BLRT) during development.
本揭露的一些實施例係提供一種半導體測試裝置，包括：一基板；一金手指觸片結構，設置於該基板之一側。 Some embodiments of the present disclosure provide a semiconductor testing device including: a substrate; a gold finger contact structure disposed on one side of the substrate.
本揭露的一些實施例係提供一種半導體測試系統，包括：一測試載板，具有複數個通道；一插槽設置於該測試載板上；複數個導線設置於該 插槽；以及如申請專利範圍第1項所述的半導體測試裝置***該插槽；其中該半導體測試裝置之該金手指觸片結構的複數個導線分別接觸該插槽之該複數個導線。 Some embodiments of the present disclosure provide a semiconductor test system including: a test carrier having a plurality of channels; a slot disposed on the test carrier; a plurality of wires disposed on the And a semiconductor test device as described in claim 1 is inserted into the slot; wherein the plurality of wires of the gold finger contact structure of the semiconductor test device respectively contact the plurality of wires of the slot.
本揭露的一些實施例係提供一種半導體測試方法，用來測試一待測封裝元件在一基板上的板階可靠度，其中該基板係利用一金手指觸片結構連接至一測試載板，該方法包括：利用一短迴授路徑來測試該金手指觸片結構；將該待測封裝元件以表面黏著技術銲黏於該基板；以及利用一長迴授路徑測試來測試該待測封裝元件在該基板上的板階可靠度。 Some embodiments of the present disclosure provide a semiconductor testing method for testing the board reliability of a package component to be tested on a substrate, wherein the substrate is connected to a test carrier by a gold finger contact structure. The method includes: testing the gold finger contact structure by using a short feedback path; soldering the package component to be tested to the substrate by surface adhesion technology; and testing the package component to be tested by using a long feedback path test Board reliability on the substrate.
本揭露所提出的半導體測試裝置、半導體測試系統以及半導體測試方法可提升板階可靠度測試(Board Level Reliability Tests,BLRT)的效率。 The semiconductor test device, the semiconductor test system, and the semiconductor test method proposed by the present disclosure can improve the efficiency of Board Level Reliability Tests (BLRT).
100、500‧‧‧半導體測試裝置 100, 500‧‧‧ semiconductor test equipment
102、502‧‧‧基板 102, 502‧‧‧ substrate
104_1~104_4‧‧‧集成扇出型封裝元件 104_1~104_4‧‧‧Integrated fan-out package components
504_1~504_4‧‧‧集成扇出型封裝元件 504_1~504_4‧‧‧Integrated fan-out package components
106、506‧‧‧金手指觸片結構 106, 506‧‧‧ Gold finger contact structure
108、508‧‧‧複數個導線 108, 508‧‧‧ a plurality of wires
108_1、108_2‧‧‧複數個導線 108_1, 108_2‧‧‧Multiple wires
110、510‧‧‧測試載板 110, 510‧‧‧ test carrier
112_1~112_n‧‧‧插槽 112_1~112_n‧‧‧Slots
512_1‧‧‧插槽 512_1‧‧‧ slots
114、514‧‧‧複數個導線 114, 514‧‧‧ a plurality of wires
114_1~114_2‧‧‧複數個導線 114_1~114_2‧‧‧Multiple wires
100_1~100_n‧‧‧半導體測試裝置 100_1~100_n‧‧‧Semiconductor test device
A、A'‧‧‧導入結構 A, A'‧‧‧ import structure
Chain1_H‧‧‧第一測試鍊的輸入端 Chain1_H‧‧‧Input of the first test chain
Chain1_T‧‧‧第一測試鍊的輸出端 Chain1_T‧‧‧output of the first test chain
Ch1‧‧‧第一通道 Ch1‧‧‧ first channel
Ch2‧‧‧第二通道 Ch2‧‧‧Second channel
Ch3‧‧‧第三通道 Ch3‧‧‧ third channel
Ch4‧‧‧第四通道 Ch4‧‧‧fourth channel
1200‧‧‧方法 1200‧‧‧ method
1202~1216‧‧‧步驟 1202~1216‧‧‧Steps
為協助讀者達到最佳理解效果，建議在閱讀本揭露時同時參考附件圖示及其詳細文字敘述說明。請注意為遵循業界標準作法，本專利說明書中的圖式不一定按照正確的比例繪製。在某些圖式中，尺寸可能刻意放大或縮小，以協助讀者清楚了解其中的討論內容。 In order to assist the reader to achieve the best understanding, it is recommended to refer to the attached figure and its detailed text description when reading this disclosure. Please note that in order to comply with industry standards, the drawings in this patent specification are not necessarily drawn to the correct scale. In some drawings, the dimensions may be deliberately enlarged or reduced to assist the reader in understanding the discussion.
圖1為本揭露的半導體測試裝置的一實施例的示意圖；圖2為本揭露圖1的半導體測試裝置的側視圖；圖3為圖1的半導體測試裝置插設於半導體測試機台的測試載板的半導體測試系統的一實施例的示意圖；圖4為圖1的半導體測試裝置插設於半導體測試機台的測試載板的側視圖；圖5為本揭露的半導體測試裝置插設於半導體測試機台的測試載板的 半導體測試系統的另一實施例的示意圖；圖6和圖7為本揭露的半導體測試系統的測試線路配置的一實施例示意圖；圖8為本揭露的半導體測試系統的測試線路配置的另一實施例示意圖；圖9為圖6~7的半導體測試系統的測試線路延伸的一實施例示意圖；圖10為圖8的半導體測試系統的測試線路延伸的一實施例示意圖；圖11為本揭露的半導體測試系統在高低溫測試時的一實施例示意圖；以及圖12為本揭露的半導體測試方法的一實施例的示意圖。 1 is a schematic view of an embodiment of a semiconductor testing device according to the present disclosure; FIG. 2 is a side view of the semiconductor testing device of FIG. 1; FIG. 3 is a test load of the semiconductor testing device of FIG. FIG. 4 is a side view of the test carrier board of the semiconductor test device of FIG. 1 inserted in the semiconductor test machine; FIG. 5 is a semiconductor test device of the present disclosure inserted in the semiconductor test Machine test board FIG. 6 and FIG. 7 are schematic diagrams showing an embodiment of a test circuit configuration of a semiconductor test system according to the present disclosure; FIG. 8 is another embodiment of a test circuit configuration of the semiconductor test system of the present disclosure. FIG. 9 is a schematic diagram of an embodiment of a test circuit extension of the semiconductor test system of FIGS. 6-7; FIG. 10 is a schematic diagram of an embodiment of a test circuit extension of the semiconductor test system of FIG. 8; FIG. A schematic diagram of an embodiment of a test system during high and low temperature testing; and FIG. 12 is a schematic diagram of an embodiment of the semiconductor testing method of the present disclosure.
本揭露提供了數個不同的實施方法或實施例，可用於實現本發明的不同特徵。為簡化說明起見，本揭露也同時描述了特定零組件與佈置的範例。請注意提供這些特定範例的目的僅在於示範，而非予以任何限制。舉例而言，在以下說明第一特徵如何在第二特徵上或上方的敘述中，可能會包括某些實施例，其中第一特徵與第二特徵為直接接觸，而敘述中也可能包括其他不同實施例，其中第一特徵與第二特徵中間另有其他特徵，以致於第一特徵與第二特徵並不直接接觸。此外，本揭露中的各種範例可能使用重複的參考數字和/或文字註記，以使文件更加簡單化和明確，這些重複的參考數字與註記不代表不同的實施例與配置之間的關聯性。 The disclosure provides several different implementations or embodiments that can be used to implement different features of the invention. For simplicity of explanation, the present disclosure also describes examples of specific components and arrangements. Please note that these specific examples are provided for demonstration purposes only and are not intended to be limiting. For example, in the following description of how the first feature is on or above the second feature, certain embodiments may be included, where the first feature is in direct contact with the second feature, and the description may include other differences Embodiments wherein there are other features in between the first feature and the second feature such that the first feature is not in direct contact with the second feature. In addition, various examples in the disclosure may use repeated reference numerals and/or text annotations to make the document more simplistic and clear, and such repeated reference numerals and annotations do not represent an association between different embodiments and configurations.
另外，本揭露在使用與空間相關的敘述詞彙，如“在...之下”，“低”，“下”，“上方”，“之上”，“下”，“頂”，“底”和類似詞彙時，為便於敘述，其用法均在於描述圖示中一個元件或特徵與另一個 (或多個)元件或特徵的相對關係。除了圖示中所顯示的角度方向外，這些空間相對詞彙也用來描述該裝置在使用中以及操作時的可能角度和方向。該裝置的角度方向可能不同(旋轉90度或其它方位)，而在本揭露所使用的這些空間相關敘述可以同樣方式加以解釋。 In addition, the disclosure uses spatially related narrative vocabulary such as "under", "low", "lower", "above", "above", "down", "top", "bottom" And similar terms, for ease of description, are used to describe one element or feature in the illustration and another The relative relationship of (or more) elements or features. In addition to the angular orientations shown in the figures, these spatial relative terms are also used to describe the possible angles and directions of the device in use and during operation. The angular orientation of the device may vary (rotating 90 degrees or other orientations), and the spatially related descriptions used in this disclosure may be interpreted in the same manner.
儘管本揭露提出廣範圍的數值範圍與餐數係約略值，然而特定範例中所提出的數值係盡可能精準。然而，任何數值本質包含在個別測試量測中得到之標準偏差所造成的一些必要誤差。同樣地，如本文所使用，「約」一詞通常係指給定值或範圍的10%、5%、1%、或0.5%之內。或者，當該技藝中具有通常技術者考量時，「約」一詞係指平均值之可接受的標準誤差。除了在操作/工作範例中，或是除非特別說明，否則例如材料的量、時間期間、溫度、操作條件、量的比例、以及本文所揭露之類似者之所有的數值範圍、數量、值、以及百分比應被理解為在所有例子中受到該詞「約」的修飾。據此，除非有相反的指示，否則本揭露與所附之申請專利範圍所提供的數值參數係約略值，並且可視需要而改變。至少，應至少根據報導的有效位數以及應用習知的進位技術而解讀每一個數值參數。本文中，範圍可表示為從一端點至另一端點或是在兩端點之間。除非特別聲明，否則本文所揭露的所有範圍包含端點。 Although the present disclosure proposes a wide range of numerical values and approximate number of meals, the numerical values set forth in the specific examples are as accurate as possible. However, any numerical nature contains some of the necessary errors caused by the standard deviations obtained in individual test measurements. Similarly, as used herein, the term "about" generally refers to within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term "about" refers to an acceptable standard error of the average when considered by one of ordinary skill in the art. Except in the operating/working examples, or unless otherwise stated, such as the amount of material, time period, temperature, operating conditions, proportions of quantities, and all numerical ranges, quantities, values, and The percentage should be understood as being modified by the word "about" in all cases. Accordingly, the numerical parameters set forth in the disclosure and the appended claims are intended to be a At a minimum, each numerical parameter should be interpreted at least in terms of the number of significant digits reported and the well-known carry technique. In this context, a range can be expressed as from one end to another or between two ends. Unless otherwise stated, all ranges disclosed herein are inclusive of the endpoints.
在先進製程中，伴隨積體電路(Integrated Circuit,IC)信號輸出引腳數目增加，對焊球間距(Ball Pitch)的要求趨於嚴格，加上印刷電路板(Printed Circuit Board,PCB)構裝對於積體電路封裝後尺寸以及信號輸出引腳位置的調整需求，使用集成扇出型(Integrated Fan-Out,InFO)封裝技術的封裝方式應運而生。集成扇出型封裝技術採取拉線出來的方式，利用晶圓級封裝(Wafer Level Packaging,WLP)工藝將讓多 種不同裸晶埋入，實質地等同於減少了一道封裝手續。換句話說，在放置超過一顆裸晶的情況下，集成扇出型封裝技術可以節省超過一層的封裝結構，從而降低了封裝的外觀尺寸，以及整體的製造成本。 In the advanced process, the number of output pins of the integrated circuit (IC) increases, the requirements for the ball pitch (Ball Pitch) tend to be strict, and the printed circuit board (PCB) is mounted. For the adjustment of the size of the integrated circuit package and the position of the signal output pin, a package method using integrated fan-out (InFO) packaging technology has emerged. Integrated fan-out package technology takes the form of a pull-out, using Wafer Level Packaging (WLP) technology to make more Different kinds of bare crystal embedding are essentially equivalent to reducing one packaging procedure. In other words, the integrated fan-out package technology can save more than one layer of package structure when more than one die is placed, thereby reducing the package size and overall manufacturing cost.
集成扇出型封裝技術可搭配表面黏著技術(Surface Mount Technology,SMT)來設置於印刷電路板上，表面黏著技術為一方便快速的新興技術，藉由表面黏著技術可將電子零件快速的銲於基板上並維持零件與基板間電路的通暢。然而，使用表面黏著技術的集成扇出型封裝元件可能會因為某些原因，例如「熱」、「水氣」等，造成元件短路或是斷路的問題。板階可靠度測試(Board Level Reliability Tests,BLRT)是用來在開發階段確保元件的銲接沒有發生短路及/或斷路問題的程序。以下的實施例提出的半導體測試裝置、半導體測試系統以及半導體測試方法，可以提高板階可靠度測試的效能，達到自動化測試的目的。 The integrated fan-out package technology can be mounted on a printed circuit board with Surface Mount Technology (SMT). The surface mount technology is a convenient and fast emerging technology. The surface adhesion technology can quickly solder electronic parts to the surface. The circuit between the part and the substrate is maintained on the substrate. However, integrated fan-out package components using surface mount technology may cause short-circuit or open-circuit problems for some reasons, such as "hot" or "water vapor". Board Level Reliability Tests (BLRT) are procedures used to ensure that components are soldered without shorts and/or open circuits during the development phase. The semiconductor test device, the semiconductor test system and the semiconductor test method proposed in the following embodiments can improve the performance of the board reliability test and achieve the purpose of automated test.
圖1為本揭露的半導體測試裝置的一實施例的示意圖。一半導體測試裝置100包含有一基板102與一金手指觸片結構106，金手指觸片結構106係設置於基板102之一側，金手指觸片結構106包含由導電材質所組成的複數個導線108，例如可以鍍金或鍍錫之加工所製成，其中金手指結構106之格式係可為一雙列直插式記憶體模組(Dual Inlined Memory Module,DIMM)介面、一周邊元件連接介面(Peripheral Component Interface,PCI)、一快速周邊元件連接介面(Peripheral Component Interface-Express,PCI-E)、一通用序列匯流排(Universal Serial Bus,USB)介面、或一圖形加速連接埠(Accelerated Graphics Port,AGP)介面等，也就是說半導體測試裝置100可為各種不同信號傳輸格式之介面卡。說明書中稍後會詳細說明半導體測試裝置100如何插設於半導體測試 機台的測試載板之一插槽內，藉以利用半導體測試系統進行半導體測試裝置100之自動化測試方法。 FIG. 1 is a schematic diagram of an embodiment of a semiconductor testing device according to the present disclosure. A semiconductor testing device 100 includes a substrate 102 and a gold finger contact structure 106. The gold finger contact structure 106 is disposed on one side of the substrate 102. The gold finger contact structure 106 includes a plurality of wires 108 composed of a conductive material. For example, it can be made by gold plating or tin plating. The format of the gold finger structure 106 can be a dual inline memory module (DIMM) interface and a peripheral component connection interface (Peripheral). Component Interface (PCI), a Peripheral Component Interface-Express (PCI-E), a Universal Serial Bus (USB) interface, or an Accelerated Graphics Port (AGP) The interface, etc., that is, the semiconductor test device 100 can be an interface card of various signal transmission formats. The semiconductor test device 100 is inserted into the semiconductor test in detail later in the specification. An automated test method for the semiconductor test apparatus 100 is performed using a semiconductor test system in one of the slots of the test board of the machine.
複數個集成扇出型封裝元件104_1~104_4係以表面黏著技術設置於基板102上。在此實施例中，集成扇出型封裝元件104_1~104_4的配置僅為示範性，實際上集成扇出型封裝元件的數量和配置方式並不以此為限。此外，應注意的是，雖然本揭露實施例中係針對集成扇出型封裝技術搭配表面黏著技術設置於印刷電路板上的板階可靠度測試進行改善，但本揭露並不以此為限。本揭露實施例亦可應用在任何其他可行的封裝技術以及任何其他可行的黏銲技術。 A plurality of integrated fan-out package components 104_1 104104_4 are disposed on the substrate 102 by surface adhesion techniques. In this embodiment, the configurations of the integrated fan-out package components 104_1 104104_4 are merely exemplary. In fact, the number and configuration of the integrated fan-out package components are not limited thereto. In addition, it should be noted that although the embodiment of the present disclosure improves the board reliability test of the integrated fan-out package technology with the surface mount technology on the printed circuit board, the disclosure is not limited thereto. The disclosed embodiments can also be applied to any other feasible packaging technique as well as any other feasible bonding technique.
圖2為本揭露圖1的半導體測試裝置的側視圖。由圖2可以看出，在此實施例中，金手指觸片結構106的複數個導線108又分為配置於金手指觸片結構106正面的複數個導線108_1，以及配置於金手指觸片結構106背面的複數個導線108_2，藉以增加可被測試的信號的數量，最終達到增加測試覆蓋率(test coverage)的目的，然而本揭露並不以此為限。 2 is a side view of the semiconductor testing device of FIG. 1 . As can be seen from FIG. 2, in this embodiment, the plurality of wires 108 of the gold finger contact structure 106 are further divided into a plurality of wires 108_1 disposed on the front surface of the gold finger contact structure 106, and configured in the gold finger contact structure. The plurality of wires 108_2 on the back of the 106 are used to increase the number of signals that can be tested, and finally achieve the purpose of increasing the test coverage. However, the disclosure is not limited thereto.
圖3為圖1的半導體測試裝置插設於半導體測試機台的測試載板的半導體測試系統的一實施例的示意圖。一測試載板110上設置有至少一插槽112_1，插槽112_1係用來容納半導體測試裝置100的金手指觸片結構106，插槽112_1並設置有複數個導線114以對應金手指觸片結構106的複數個導線108，藉以使半導體測試裝置100電連接於該半導體測試機台的測試載板110。為便於說明，在圖3的正面視角僅繪示插槽112_1，然而本實施例中實際上可包含複數個插槽112_1~112_n，n為大於1的任意整數。圖4為圖1的半導體測試裝置插設於半導體測試機台的測試載板的側視圖，參閱圖4可瞭解本實施例的插槽112_1~112_n的設置方式，其中n個 半導體測試裝置100_1~100_n分別對應插槽112_1~112_n。圖4亦繪示了複數個導線114又分為對應金手指觸片結構106正面的複數個導線108_1的複數個導線114_1，以及對應金手指觸片結構106背面的複數個導線108_2的複數個導線114_2。當半導體測試裝置100_1~100_n分別***插槽112_1~112_n時，金手指觸片結構106會嵌入插槽的凹部，使金手指觸片結構106正面的複數個導線108_1接觸位於插槽凹部的複數個導線114_1，以及使金手指觸片結構106背面的複數個導線108_2接觸位於插槽凹部的複數個導線114_2。 3 is a schematic diagram of an embodiment of a semiconductor test system of the semiconductor test device of FIG. 1 inserted into a test carrier of a semiconductor test machine. A test carrier 110 is provided with at least one slot 112_1 for receiving the gold finger contact structure 106 of the semiconductor testing device 100, and the slot 112_1 is provided with a plurality of wires 114 for corresponding to the gold finger contact structure. A plurality of wires 108 of 106 are used to electrically connect the semiconductor test device 100 to the test carrier 110 of the semiconductor test machine. For the sake of convenience, only the slot 112_1 is shown in the front view of FIG. 3. However, in this embodiment, a plurality of slots 112_1~112_n may be actually included, and n is an arbitrary integer greater than 1. 4 is a side view of the test carrier board of the semiconductor test device of FIG. 1 inserted into the semiconductor test machine. Referring to FIG. 4, the arrangement of the slots 112_1~112_n of the embodiment can be understood, wherein n The semiconductor test apparatuses 100_1 to 100_n correspond to the slots 112_1 to 112_n, respectively. 4 also illustrates that the plurality of wires 114 are further divided into a plurality of wires 114_1 corresponding to the plurality of wires 108_1 on the front surface of the gold finger contact structure 106, and a plurality of wires corresponding to the plurality of wires 108_2 on the back surface of the gold finger contact structure 106. 114_2. When the semiconductor test devices 100_1~100_n are respectively inserted into the slots 112_1~112_n, the gold finger contact structure 106 is embedded in the recess of the slot, so that the plurality of wires 108_1 on the front surface of the gold finger contact structure 106 contact a plurality of recesses located in the recess of the slot. The wire 114_1, and the plurality of wires 108_2 on the back side of the gold finger contact structure 106, contact a plurality of wires 114_2 located in the recess of the slot.
圖5為本揭露的半導體測試裝置插設於半導體測試機台的測試載板的半導體測試系統的另一實施例的示意圖。一半導體測試裝置500具有和半導體測試裝置100相似的結構，包含有一基板502與一金手指觸片結構506，複數個集成扇出型封裝元件504_1~504_4係以表面黏著技術設置於基板502上。一測試載板510具有和測試載板110相似的結構，設置有至少一插槽512_1，插槽512_1係用來容納半導體測試裝置500的金手指觸片結構506，插槽512_1並設置有複數個導線514以對應金手指觸片結構506的複數個導線508，藉以使半導體測試裝置500電連接於該半導體測試機台的測試載板510。 5 is a schematic diagram of another embodiment of a semiconductor test system in which a semiconductor test device of the present disclosure is inserted into a test carrier of a semiconductor test machine. A semiconductor test device 500 has a structure similar to that of the semiconductor test device 100, and includes a substrate 502 and a gold finger contact structure 506. The plurality of integrated fan-out package components 504_1~504_4 are disposed on the substrate 502 by surface adhesion technology. A test carrier 510 has a structure similar to that of the test carrier 110, and is provided with at least one slot 512_1 for accommodating the gold finger contact structure 506 of the semiconductor testing device 500, and the socket 512_1 is provided with a plurality of Wire 514 is coupled to a plurality of wires 508 of gold finger contact structure 506 to electrically connect semiconductor test device 500 to test carrier 510 of the semiconductor test machine.
半導體測試裝置500和半導體測試裝置100的不同之處在於金手指觸片結構506具有一導入結構A，而插槽512_1和圖3的插槽112_1的不同之處在於插槽512_1具有一導入結構A'，其外型特徵對應於導入結構A並可彼此結合。在本實施例中，導入結構A係一內凹結構；導入結構A'係一外凸結構，在半導體測試裝置500的金手指觸片結構506進入插槽512_1的過程中，金手指觸片結構506的內凹的導入結構A可幫助金手指觸片結構506 被導入到正確的位置，最終和插槽512_1的外凸的導入結構A'緊密結合，確保複數個導線508正確地接觸到相對應的複數個導線514。然本揭露不以此為限，金手指觸片結構506的導入結構A可具有其他外型特徵，插槽512_1的導入結構A'可具有對應導入結構A的外型特徵。例如導入結構A可以係一外凸結構，而導入結構A'可以係一內凹結構。 The semiconductor test device 500 differs from the semiconductor test device 100 in that the gold finger contact structure 506 has an lead-in structure A, and the slot 512_1 is different from the slot 112_1 of FIG. 3 in that the slot 512_1 has an lead-in structure A. ', its appearance features correspond to the introduction structure A and can be combined with each other. In the present embodiment, the introduction structure A is a concave structure; the introduction structure A' is a convex structure, and the gold finger contact structure is in the process of the gold finger contact structure 506 of the semiconductor testing device 500 entering the slot 512_1. The concave introduction structure A of the 506 can help the gold finger contact structure 506 It is introduced into the correct position and is ultimately tightly coupled to the convex lead-in structure A' of the slot 512_1 to ensure that the plurality of wires 508 are properly in contact with the corresponding plurality of wires 514. However, the present disclosure is not limited thereto. The introduction structure A of the gold finger contact structure 506 may have other external features, and the introduction structure A' of the slot 512_1 may have an appearance characteristic corresponding to the introduction structure A. For example, the introduction structure A may be a convex structure, and the introduction structure A' may be a concave structure.
圖6和圖7為本揭露的半導體測試系統的測試線路配置的一實施例示意圖。圖6和圖7的測試線路配置包含有複數個短迴授(short loopback)路徑和複數個長迴授(long loopback)路徑。在圖6中，短迴授路徑以箭頭標示，主要係用來測試金手指觸片結構106的複數個導線108是否皆正常地和插槽112_1的複數個導線114接觸。在本實施例中，插槽112_1的複數個導線114分別電連接到測試載板110上的複數個通道(channel)，而金手指觸片結構106的複數個導線108在進入基板102後被配置為兩兩相連接，因此，當金手指觸片結構106***插槽112_1時，測試信號可從測試載板110的一第一通道Ch1經過插槽112_1和金手指觸片結構106到達基板102，並在不經過複數個集成扇出型封裝元件104_1~104_4的情況下，直接透過金手指觸片結構106和插槽112_1來迴授到測試載板110的一第二通道Ch2。利用該複數個短迴授路徑，可在正式開始測試基板102和集成扇出型封裝元件104_1~104_4之前，先確保金手指觸片結構106的複數個導線108皆能夠正常地和插槽112_1的複數個導線114電連接。舉例來說，若金手指觸片結構106的導線數量為204條，則會有102條短迴授路徑產生，需要使用測試載板110上的102個通道。 6 and FIG. 7 are schematic diagrams showing an embodiment of a test circuit configuration of a semiconductor test system according to the present disclosure. The test line configuration of Figures 6 and 7 includes a plurality of short loopback paths and a plurality of long loopback paths. In FIG. 6, the short feedback path is indicated by an arrow, and is primarily used to test whether the plurality of wires 108 of the gold finger contact structure 106 are normally in contact with the plurality of wires 114 of the slot 112_1. In the present embodiment, the plurality of wires 114 of the slot 112_1 are electrically connected to a plurality of channels on the test carrier 110, respectively, and the plurality of wires 108 of the gold finger contact structure 106 are configured after entering the substrate 102. For the two-phase connection, when the gold finger contact structure 106 is inserted into the slot 112_1, the test signal can reach the substrate 102 from the first channel Ch1 of the test carrier 110 through the slot 112_1 and the gold finger contact structure 106. And a second channel Ch2 of the test carrier 110 is directly sent back through the gold finger contact structure 106 and the slot 112_1 without passing through the plurality of integrated fan-out package components 104_1 104104_4. By using the plurality of short feedback paths, it is possible to ensure that the plurality of wires 108 of the gold finger contact structure 106 can normally and the slots 112_1 before the test substrate 102 and the integrated fan-out package components 104_1 104104_4 are formally started. A plurality of wires 114 are electrically connected. For example, if the number of wires of the gold finger contact structure 106 is 204, then 102 short feedback paths will be generated, and 102 channels on the test carrier 110 need to be used.
在圖7中，長迴授路徑以箭頭標示，主要係用來測試複數個集成扇出型封裝元件104_1~104_4是否如預期地電連接至基板102。在本實施例 中，金手指觸片結構106的複數個導線108規劃有冗餘(redundancy)配置，可降低金手指觸片結構106和插槽112_1之間因接觸不良而導致測試失敗的機率。具體來說，複數個導線108中，會有超過一條的導線被接入到每一測試鍊的輸入端，例如複數個導線108中的兩條導線被連接到一第一測試鍊的一輸入端Chain1_H，以及會有超過一條的導線被接入到每一測試鍊的輸出端，例如複數個導線108中的另兩條導線被連接到該第一測試鍊的一輸出端Chain1_T。該第一測試鍊會經過複數個集成扇出型封裝元件104_1~104_4的至少其中之一。當金手指觸片結構106***插槽112_1時，測試信號可從測試載板110的第一通道Ch1及第二通道Ch2經過插槽112_1和金手指觸片結構106到達基板102，並進入該第一測試鍊的輸入端Chain1_H。該第一測試鍊會經過複數個集成扇出型封裝元件104_1~104_4的至少其中之一，並從輸出端Chain1_T透過金手指觸片結構106和插槽112_1迴授到測試載板110的第三通道Ch3及第四通道Ch4。 In FIG. 7, the long feedback path is indicated by an arrow and is primarily used to test whether a plurality of integrated fan-out package components 104_1 104104_4 are electrically connected to substrate 102 as intended. In this embodiment The plurality of wires 108 of the gold finger contact structure 106 are planned to have a redundancy configuration, which reduces the probability of test failure between the gold finger contact structure 106 and the slot 112_1 due to poor contact. Specifically, more than one of the plurality of wires 108 is connected to the input of each test chain. For example, two of the plurality of wires 108 are connected to an input of a first test chain. Chain1_H, and there will be more than one wire being connected to the output of each test chain, for example the other two wires of the plurality of wires 108 are connected to an output terminal Chain1_T of the first test chain. The first test chain passes through at least one of a plurality of integrated fan-out package components 104_1 104104_4. When the gold finger contact structure 106 is inserted into the slot 112_1, the test signal can reach the substrate 102 from the first channel Ch1 and the second channel Ch2 of the test carrier 110 through the slot 112_1 and the gold finger contact structure 106, and enter the first The input of the test chain, Chain1_H. The first test chain passes through at least one of the plurality of integrated fan-out package components 104_1 104104_4, and is fed back from the output terminal Chain1_T through the gold finger contact structure 106 and the slot 112_1 to the third of the test carrier 110. Channel Ch3 and fourth channel Ch4.
由於在長迴授路徑的測試時第一通道Ch1及第二通道Ch2為相同信號，第三通道Ch3及第四通道Ch4為相同信號，其後通道亦兩兩同，故圖8中將圖7中原本的第一通道Ch1及第二通道Ch2合併，第三通道Ch3及第四通道Ch4合併，其後通道亦兩兩合併，亦可達到相同的效果。 Since the first channel Ch1 and the second channel Ch2 are the same signal when testing the long feedback path, the third channel Ch3 and the fourth channel Ch4 are the same signal, and the subsequent channels are also the same, so FIG. 7 will be FIG. The first channel Ch1 and the second channel Ch2 are merged in the middle, and the third channel Ch3 and the fourth channel Ch4 are merged, and the subsequent channels are also merged in pairs, and the same effect can be achieved.
圖9為圖6~7的半導體測試系統的測試線路延伸的一實施例示意圖。圖9中的n個半導體測試裝置100_1~100_n分別***測試載板110的插槽112_1~112_n。在每一半導體測試裝置100_1~100_n都分別具有相同的短迴授路徑和長迴授路徑配置的情況下，可將每一半導體測試裝置100_1~100_n的相對應短迴授路徑/長迴授路徑串連起來一起進行測試，以節省測試的時間。舉例來說，原本要對半導體測試裝置100_1~100_n分別進 行該第一測試鍊的測試，也就是說半導體測試裝置100_1~100_n之該第一測試鍊的信號輸出端原本應該是分別接到第三通道Ch3及第四通道Ch4，但在圖9中，半導體測試裝置100_1之該第一測試鍊的信號輸出端被串接到半導體測試裝置100_2之該第一測試鍊的信號輸入端，半導體測試裝置100_2之該第一測試鍊的信號輸出端被串接到半導體測試裝置100_3之該第一測試鍊的信號輸入端，並依此方式一路串接到半導體測試裝置100_n，最後才將半導體測試裝置100_n之該第一測試鍊的信號輸出端接到第三通道Ch3及第四通道Ch4。 9 is a schematic diagram of an embodiment of a test line extension of the semiconductor test system of FIGS. 6-7. The n semiconductor test devices 100_1 100 100_n in FIG. 9 are respectively inserted into the slots 112_1 - 112_n of the test carrier 110. In the case where each of the semiconductor test apparatuses 100_1 100 100_n has the same short feedback path and long feedback path configuration, the corresponding short feedback path/long feedback path of each of the semiconductor test apparatuses 100_1 100 100_n can be adopted. Test together in series to save test time. For example, the semiconductor test equipment 100_1~100_n should be separately entered. The test of the first test chain is performed, that is, the signal output ends of the first test chain of the semiconductor test devices 100_1~100_n should be respectively connected to the third channel Ch3 and the fourth channel Ch4, but in FIG. 9, The signal output end of the first test chain of the semiconductor test device 100_1 is serially connected to the signal input end of the first test chain of the semiconductor test device 100_2, and the signal output end of the first test chain of the semiconductor test device 100_2 is serially connected. Going to the signal input end of the first test chain of the semiconductor testing device 100_3, and in this way, serially connecting to the semiconductor testing device 100_n, and finally connecting the signal output end of the first testing chain of the semiconductor testing device 100_n to the third Channel Ch3 and fourth channel Ch4.
圖10為圖8的半導體測試系統的測試線路延伸的一實施例示意圖。圖10中的n個半導體測試裝置100_1~100_n分別***測試載板110的插槽112_1~112_n。在每一半導體測試裝置100_1~100-n都分別具有相同的長迴授路徑配置的情況下，可將每一半導體測試裝置100_1~100_n的相對應長迴授路徑串連起來一起進行測試，以節省測試的時間。舉例來說，原本要對半導體測試裝置100_1~100_n分別進行該第一測試鍊的測試，也就是說半導體測試裝置100_1~100_n之該第一測試鍊的信號輸出端原本應該是接到第二通道Ch2，但在圖10中，半導體測試裝置100_1之該第一測試鍊的信號輸出端被串接到半導體測試裝置100_2之該第一測試鍊的信號輸入端，半導體測試裝置100_2之該第一測試鍊的信號輸出端被串接到半導體測試裝置100_3之該第一測試鍊的信號輸入端，並依此方式一路串接到半導體測試裝置100_n，最後才將半導體測試裝置100_n之該第一測試鍊的信號輸出端接到第二通道Ch2。 10 is a schematic diagram of an embodiment of a test line extension of the semiconductor test system of FIG. The n semiconductor test devices 100_1~100_n in FIG. 10 are respectively inserted into the slots 112_1~112_n of the test carrier 110. In the case that each of the semiconductor test devices 100_1 100-100 has the same long feedback path configuration, the corresponding long feedback paths of each of the semiconductor test devices 100_1 100 100_n can be connected together for testing. Save time on testing. For example, the test of the first test chain is performed on the semiconductor test devices 100_1~100_n, that is, the signal output end of the first test chain of the semiconductor test devices 100_1~100_n should be connected to the second channel. Ch2, but in FIG. 10, the signal output end of the first test chain of the semiconductor testing device 100_1 is serially connected to the signal input end of the first test chain of the semiconductor testing device 100_2, and the first test of the semiconductor testing device 100_2 The signal output end of the chain is serially connected to the signal input end of the first test chain of the semiconductor testing device 100_3, and is connected in series to the semiconductor testing device 100_n in this manner, and finally the first test chain of the semiconductor testing device 100_n The signal output is connected to the second channel Ch2.
圖11為本揭露的半導體測試系統在高低溫測試時的一實施例示意圖。在進行高低溫測試時，可利用一隔溫裝置(未繪示於圖中)覆蓋於測 試載板110的虛線處，使該隔溫裝置內產生所需的溫度進行測試。在本實施例中，依據該隔溫裝置的規格，部分半導體測試裝置需要配合測試的位置從插槽移除。例如若欲將該隔溫裝置覆蓋於半導體測試裝置100_2時，需將半導體測試裝置100_1和100_3從插槽112_1和112_3移除。然而本揭露並不以此為限。 FIG. 11 is a schematic diagram of an embodiment of a semiconductor test system according to the present disclosure during high and low temperature testing. When performing high and low temperature tests, it can be covered by a temperature isolation device (not shown in the figure). At the dotted line of the test carrier 110, the temperature required in the temperature dividing device is tested for testing. In this embodiment, depending on the specifications of the temperature isolation device, a portion of the semiconductor test device needs to be removed from the slot in conjunction with the test. For example, if the temperature barrier device is to be overlaid on the semiconductor test device 100_2, the semiconductor test devices 100_1 and 100_3 are removed from the slots 112_1 and 112_3. However, this disclosure is not limited to this.
圖12為本揭露的半導體測試方法的一實施例的示意圖。半導體測試方法1200包含有步驟1202~1216，其中各個步驟的順序並不意味著這些步驟必須按照該順序來執行。相反地，可以以任何合適的順序來執行這些步驟。其中步驟1202~1204係利用本揭露前述實施例中的短迴授路徑來達成，步驟1208~1216係利用本揭露前述實施例中的長迴授路徑來達成。在步驟1202中，針對本揭露實施例的金手指觸片結構106進行一連續性測試(continuity test)來驗證金手指觸片結構106的複數個導線108是否皆正常地和插槽112_1的複數個導線114接觸。在步驟1204中，針對本揭露實施例的金手指觸片結構106進行一短路測試來驗證金手指觸片結構106的複數個導線108和插槽112_1的複數個導線114是否發生有彼此短路的現象，在本實施例中，該短路測試可包含漏電測試(N-leak test)。在步驟1206中，將集成扇出型封裝元件104_1~104_4以表面黏著技術銲黏於基板102上，以準備進行後續針對集成扇出型封裝元件104_1~104_4和基板102的板階可靠度測試。 FIG. 12 is a schematic diagram of an embodiment of a semiconductor testing method according to the present disclosure. The semiconductor test method 1200 includes steps 1202 through 1216, wherein the order of the various steps does not imply that the steps must be performed in the order. Rather, these steps can be performed in any suitable order. The steps 1202 to 1204 are achieved by using the short feedback path in the foregoing embodiment, and the steps 1208 to 1216 are achieved by using the long feedback path in the foregoing embodiment. In step 1202, a continuation test is performed on the gold finger contact structure 106 of the disclosed embodiment to verify whether the plurality of wires 108 of the gold finger contact structure 106 are normal and a plurality of slots 112_1. The wire 114 is in contact. In step 1204, a short-circuit test is performed on the gold finger contact structure 106 of the disclosed embodiment to verify whether the plurality of wires 108 of the gold finger contact structure 106 and the plurality of wires 114 of the slot 112_1 are short-circuited with each other. In this embodiment, the short circuit test may include a N-leak test. In step 1206, the integrated fan-out package components 104_1 104104_4 are soldered to the substrate 102 by surface bonding techniques to prepare for subsequent board reliability testing of the integrated fan-out package components 104_1 104104_4 and the substrate 102.
在步驟1208中，進行一測試鍊開路測試，例如在本實施例中，該測試鍊開路測試包含測試鍊阻抗測試(chain resistance test)。在步驟1210中，進行一測試鍊短路測試，例如在本實施例中，該測試鍊短路測試包含測試鍊漏電測試(chain N-leak test)。當進行完第一輪的測試鍊開路測 試和測試鍊短路測試，在步驟1212中，利用一測試鍊高電壓短路測試(chain N-leak stress)來對測試鍊經過的路徑進行在高電壓情況下的短路測試。最後，在步驟1214~1216中，重複步驟1208~1210的測試，以檢查測試鍊經過的路徑在經過高電壓之後是否依然正常。 In step 1208, a test chain open circuit test is performed. For example, in the present embodiment, the test chain open circuit test includes a chain resistance test. In step 1210, a test chain short circuit test is performed. For example, in the present embodiment, the test chain short circuit test includes a chain N-leak test. When the first round of test chain open circuit test is completed In the test and test chain short-circuit test, in step 1212, a test chain high-short stress test (chain N-leak stress) is used to perform a short-circuit test at a high voltage condition on the path through which the test chain passes. Finally, in steps 1214~1216, the tests of steps 1208~1210 are repeated to check if the path passed by the test chain is still normal after passing the high voltage.
本揭露的一些實施例係提供一種半導體測試裝置，可用以將一待測封裝元件設置於上，該半導體測試裝置包括：一基板；以及一金手指觸片結構，設置於該基板之一側。 Some embodiments of the present disclosure provide a semiconductor testing device for arranging a package component to be tested, the semiconductor testing device comprising: a substrate; and a gold finger contact structure disposed on one side of the substrate.
本揭露的一些實施例係提供一種半導體測試系統，包括：一測試載板，具有複數個通道；一插槽設置於該測試載板上；複數個導線設置於該插槽；以及如申請專利範圍第1項所述的半導體測試裝置***該插槽；其中該半導體測試裝置之該金手指觸片結構的複數個導線分別接觸該插槽之該複數個導線。 Some embodiments of the present disclosure provide a semiconductor test system including: a test carrier having a plurality of channels; a slot disposed on the test carrier; a plurality of wires disposed in the slot; and, as claimed in the patent application The semiconductor test device of item 1 is inserted into the socket; wherein the plurality of wires of the gold finger contact structure of the semiconductor test device respectively contact the plurality of wires of the socket.
本揭露的一些實施例係提供一種半導體測試方法，用來測試一集成扇出型封裝元件在一基板上的板階可靠度，其中該基板係利用一金手指觸片結構連接至一測試載板，該方法包括：利用一短迴授路徑來測試該金手指觸片結構；將該集成扇出型封裝元件以表面黏著技術銲黏於該基板；以及利用一長迴授路徑測試來測試該集成扇出型封裝元件在該基板上的板階可靠度。 Some embodiments of the present disclosure provide a semiconductor test method for testing the board reliability of an integrated fan-out package component on a substrate, wherein the substrate is connected to a test carrier by a gold finger contact structure. The method includes: testing the gold finger contact structure with a short feedback path; soldering the integrated fan-out package component to the substrate by surface adhesion technology; and testing the integration using a long feedback path test The board reliability of the fan-out package component on the substrate.
前述內容概述一些實施方式的特徵，因而熟知此技藝之人士可更加理解本揭露之各方面。熟知此技藝之人士應理解可輕易使用本揭露作為基礎，用於設計或修飾其他製程與結構而實現與本申請案所述之實施例具有相同目的與/或達到相同優點。熟知此技藝之人士亦應理解此均等架構並不脫離本揭露揭示內容的精神與範圍，並且熟知此技藝之人士可進行各種 變化、取代與替換，而不脫離本揭露之精神與範圍。 The foregoing is a summary of the features of the embodiments, and those skilled in the art can understand the various aspects of the disclosure. Those skilled in the art will appreciate that the present disclosure can be readily utilized as a basis for designing or modifying other processes and structures to achieve the same objectives and/or the same advantages as the embodiments described herein. It should be understood by those skilled in the art that this equivalent structure does not depart from the spirit and scope of the disclosure, and those skilled in the art can Changes, substitutions and substitutions are made without departing from the spirit and scope of the disclosure.
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| TWI299164B (en) * | 2005-01-28 | 2008-07-21 | Power Quotient Int Co Ltd | Memory ic testing tool and probe structure |
| TW200933867A (en) * | 2008-01-18 | 2009-08-01 | Hon Hai Prec Ind Co Ltd | Semiconductor package structure |
| TW200944090A (en) * | 2008-04-07 | 2009-10-16 | Mediatek Inc | Printed circuit board |
| TW201101969A (en) * | 2009-06-26 | 2011-01-01 | Nichepac Technology Inc | Test fixture having printed circuit board |
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| TWI299164B (en) * | 2005-01-28 | 2008-07-21 | Power Quotient Int Co Ltd | Memory ic testing tool and probe structure |
| TW200933867A (en) * | 2008-01-18 | 2009-08-01 | Hon Hai Prec Ind Co Ltd | Semiconductor package structure |
| TW200944090A (en) * | 2008-04-07 | 2009-10-16 | Mediatek Inc | Printed circuit board |
| TW201101969A (en) * | 2009-06-26 | 2011-01-01 | Nichepac Technology Inc | Test fixture having printed circuit board |
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