TWI655540B

TWI655540B - Storage device

Info

Publication number: TWI655540B
Application number: TW106128569A
Authority: TW
Inventors: 林峻葦
Original assignee: 慧榮科技股份有限公司
Priority date: 2016-03-23
Filing date: 2016-03-23
Publication date: 2019-04-01
Also published as: TW201741884A

Abstract

一種記憶裝置，包括一處理器、一控制器以及一開關。處理器用以控制一邏輯電路的操作，並在一主重置信號被致能時，根據邏輯電路的操作狀態產生一次重置信號。控制器根據主重置信號以及次重置信號產生一遮罩信號。當遮罩信號被致能時，開關不傳送主重置信號予邏輯電路。當遮罩信號未被致能時，開關傳送主重置信號予邏輯電路，用以重置邏輯電路。 A memory device includes a processor, a controller, and a switch. The processor is configured to control the operation of a logic circuit and generate a reset signal according to an operational state of the logic circuit when a primary reset signal is enabled. The controller generates a mask signal based on the primary reset signal and the secondary reset signal. When the mask signal is enabled, the switch does not transmit the main reset signal to the logic circuit. When the mask signal is not enabled, the switch transmits a master reset signal to the logic circuit to reset the logic circuit.

Description

記憶裝置 Memory device

本發明係有關於一種記憶裝置，特別是有關於一種可在內部的邏輯電路停止運作時重置邏輯電路的記憶裝置。 The present invention relates to a memory device, and more particularly to a memory device that can reset a logic circuit when an internal logic circuit ceases to function.

一般的電子裝置具有一重置開關，用以重置電子裝置的操作系統。當電子裝置發生當機時，使用者可按下重置開關使電子裝置重新開機，以恢復正常運作。然而，由於電子裝置裡的記憶裝置可能正在進行寫入操作或讀取操作，因此，當使用者按下重置開關時，很有可能造成資料的流失。 A typical electronic device has a reset switch for resetting the operating system of the electronic device. When the electronic device is down, the user can press the reset switch to turn the electronic device back on to resume normal operation. However, since the memory device in the electronic device may be performing a write operation or a read operation, when the user presses the reset switch, there is a high possibility that data is lost.

本發明提供一種記憶裝置，包括一處理器、一控制器以及一開關。處理器用以控制一邏輯電路的操作，並在一主重置信號被致能時，根據邏輯電路的操作狀態產生一次重置信號。控制器根據主重置信號以及次重置信號產生一遮罩信號。當遮罩信號被致能時，開關不傳送主重置信號予邏輯電路。當遮罩信號未被致能時，開關傳送主重置信號予邏輯電路，用以重置邏輯電路。 The invention provides a memory device comprising a processor, a controller and a switch. The processor is configured to control the operation of a logic circuit and generate a reset signal according to an operational state of the logic circuit when a primary reset signal is enabled. The controller generates a mask signal based on the primary reset signal and the secondary reset signal. When the mask signal is enabled, the switch does not transmit the main reset signal to the logic circuit. When the mask signal is not enabled, the switch transmits a master reset signal to the logic circuit to reset the logic circuit.

本發明另提供一種重置方法，用以重置一記憶裝置裡的一邏輯電路。本發明之重置方法包括，根據一主重置信號調整一計數值，並令邏輯電路在完成一工作後便停止運作，其中該工作係為邏輯電路正在進行的工作；判斷該邏輯電路是否停止運作；當該邏輯電路未停止運作時，重置該計數值，並重新調整該計數值；判斷該計數值是否等於一預設值；以及當該計數值等於該預設值時，重置該邏輯電路。 The present invention further provides a reset method for resetting a logic circuit in a memory device. The reset method of the present invention includes adjusting a count value according to a main reset signal, and causing the logic circuit to stop operating after completing a work, Where the work is the ongoing work of the logic circuit; determining whether the logic circuit stops operating; when the logic circuit does not stop operating, resetting the count value, and re-adjusting the count value; determining whether the count value is equal to a pre- Setting a value; and resetting the logic circuit when the count value is equal to the preset value.

為讓本發明之特徵和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下： In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments are described below, and are described in detail with reference to the accompanying drawings.

100A、100B‧‧‧記憶裝置 100A, 100B‧‧‧ memory device

110A、110B‧‧‧開關 110A, 110B‧‧ ‧ switch

120A、120B‧‧‧處理器 120A, 120B‧‧‧ processor

130A、130B‧‧‧邏輯電路 130A, 130B‧‧‧ logic circuits

140A、140B‧‧‧控制器 140A, 140B‧‧‧ controller

141A、141B‧‧‧計數器 141A, 141B‧‧‧ counter

150‧‧‧偵測器 150‧‧‧Detector

151‧‧‧低通濾波器 151‧‧‧Low-pass filter

210、220、230、240‧‧‧期間 210, 220, 230, 240‧‧

S_M‧‧‧遮罩信號 S _M ‧‧‧mask signal

HW_RSTn‧‧‧主重置信號 HW_RSTn‧‧‧Main reset signal

S_C‧‧‧控制信號 S _C ‧‧‧ control signal

S_SR‧‧‧次重置信號 S _SR ‧ ‧ reset signal

S_N‧‧‧通知信號 S _N ‧‧‧Notice signal

OUT₁₅₀、OUT_110B‧‧‧輸出信號 OUT ₁₅₀ , OUT _110B ‧‧‧ Output signal

VAL‧‧‧計數值 VAL‧‧‧ count value

T1、T2‧‧‧時間點 T1, T2‧‧‧ time points

S311~S315‧‧‧步驟 S311~S315‧‧‧Steps

第1A及1B圖為本發明的記憶裝置的示意圖。 1A and 1B are schematic views of a memory device of the present invention.

第2圖為第1B圖的記憶裝置的控制時序圖。 Fig. 2 is a control timing chart of the memory device of Fig. 1B.

第3圖為本發明之重置方法的流程示意圖。 Figure 3 is a schematic flow chart of the reset method of the present invention.

第1A圖為本發明的記憶裝置的示意圖。如圖所示，記憶裝置100A包括一開關110A、一處理器120A、一邏輯電路130A以及一控制器140A。開關110A根據一遮罩信號S_M決定是否傳送一主重置信號HW_RSTn予處理器120A與邏輯電路130A。在一可能實施例中，當遮罩信號S_M被致能時，開關110A不傳送主重置信號HW_RSTn予處理器120A與邏輯電路130A。當遮罩信號S_M未被致能時，開關110A傳送主重置信號HW_RSTn予處理器120A及邏輯電路130A。 Fig. 1A is a schematic view of a memory device of the present invention. As shown, the memory device 100A includes a switch 110A, a processor 120A, a logic circuit 130A, and a controller 140A. The switch 110A determines whether to transmit a main reset signal HW_RSTn to the processor 120A and the logic circuit 130A based on a mask signal S _M . In a possible embodiment, when the mask signal S _M is enabled, the switch 110A does not transmit the main reset signal HW_RSTn to the processor 120A and the logic circuit 130A. When the mask signal S _M is not enabled, the switch 110A transmits the main reset signal HW_RSTn to the processor 120A and the logic circuit 130A.

在一可能實施例中，開關110A係根據遮罩信號S_M的位準傳送主重置信號HW_RSTn。舉例而言，當遮罩信號S_M為高位準時，表示遮罩信號S_M被致能。因此，開關110A不傳送主重置信號HW_RSTn。當遮罩信號S_M為低位準時，表示遮罩信號S_M不被致能。因此，開關110A傳送主重置信號HW_RSTn。在其它實施例中，當遮罩信號S_M為低位準時，表示遮罩信號S_M被致能。因此，開關110A不傳送主重置信號HW_RSTn。當遮罩信號S_M為高位準時，表示遮罩信號S_M不被致能。因此，開關110A傳送主重置信號HW_RSTn。 In a possible embodiment, the switch 110A transmits the main reset signal HW_RSTn according to the level of the mask signal S _M . For example, when the mask signal S _M is at a high level, it indicates that the mask signal S _M is enabled. Therefore, the switch 110A does not transmit the main reset signal HW_RSTn. When the mask signal S _M is at a low level, it indicates that the mask signal S _{M is} not enabled. Therefore, the switch 110A transmits the main reset signal HW_RSTn. In other embodiments, when the mask signal S _M is at a low level, it indicates that the mask signal S _M is enabled. Therefore, the switch 110A does not transmit the main reset signal HW_RSTn. When the mask signal S _M is at a high level, it indicates that the mask signal S _{M is} not enabled. Therefore, the switch 110A transmits the main reset signal HW_RSTn.

處理器120A用以控制邏輯電路130A的操作。在一可能實施例中，處理器120A透過邏輯電路130A將一外部資料寫入一記憶體(未顯示)中。在一可能實施例中，記憶體至少包括一唯讀記憶體(ROM)以及一隨機存取記憶體(RAM)。在另一可能實施例中，處理器120A透過邏輯電路130A讀取記憶體所儲存的資料，並將讀取資料提供予一外部裝置(未顯示)。在一可能實施例中，該外部裝置係獨立在記憶裝置100A之外。 The processor 120A is used to control the operation of the logic circuit 130A. In one possible embodiment, processor 120A writes an external data into a memory (not shown) via logic circuit 130A. In a possible embodiment, the memory includes at least a read only memory (ROM) and a random access memory (RAM). In another possible embodiment, the processor 120A reads the data stored in the memory through the logic circuit 130A and provides the read data to an external device (not shown). In a possible embodiment, the external device is independent of the memory device 100A.

在本實施例中，當開關110A輸出主重置信號HW_RSTn，並且主重置信號HW_RSTn被致能時，處理器120A根據邏輯電路130A的操作狀態產生一次重置信號S_SR。舉例而言，當主重置信號HW_RSTn被致能時，處理器120A發出一控制信號S_C，用以命令邏輯電路130A完成目前正在執行的工作，如一寫入操作或是一讀取操作。邏輯電路130A在接收到控制信號S_C後，先完成正在進行的工作，然後停止運作。 In the present embodiment, when the switch 110A outputs the main reset signal HW_RSTn, and the main reset signal HW_RSTn is enabled, the processor 120A generates a reset signal S _SR according to the operational state of the logic circuit 130A. For example, when the main reset signal HW_RSTn is enabled, the processor 120A issues a control signal S _{C for} instructing the logic circuit 130A to perform the work currently being performed, such as a write operation or a read operation. After receiving the control signal S _C , the logic circuit 130A completes the ongoing work and then stops operating.

在一可能實施例中，處理器120A在發出控制信號S_C後，每隔一固定時間便偵測邏輯電路130A是否已停止運作。若邏輯電路130A尚未停止運作，則處理器120A致能次重置信號S_SR。若邏輯電路130A已停止運作，處理器120A不致能次重置信號S_SR。在一可能實施例中，當次重置信號S_SR為高位準時，表示次重置信號S_SR被致能。相反地，當次重置信號S_SR為低位準時，表示重置信號S_SR不被致能。在另一可能實施例中，當次重置信號S_SR為低位準時，表示次重置信號S_SR被致能，當次重置信號S_SR為高位準時，表示次重置信號S_SR不被致能。 In a possible embodiment, after the control signal S _{C is} issued, the processor 120A detects whether the logic circuit 130A has stopped operating every fixed time. If the logic circuit 130A has not stopped operating, the processor 120A enables the secondary reset signal _SSR . If logic circuit 130A has ceased to function, processor 120A does not enable secondary reset signal _SSR . In a possible embodiment, when the secondary reset signal S _SR is at a high level, it indicates that the secondary reset signal S _SR is enabled. Conversely, when the secondary reset signal S _SR is at a low level, it indicates that the reset signal S _{SR is} not enabled. In another possible embodiment, when the secondary reset signal S _SR is at a low level, indicating that the secondary reset signal S _SR is enabled, when the secondary reset signal S _SR is at a high level, indicating that the secondary reset signal S _{SR is} not Enable.

在其它實施例中，次重置信號S_SR維持在一固定位準，如高位準或低位準。當處理器120A致能次重置信號S_SR時，次重置信號S_SR的位準會有短暫的變化，因而使得次重置信號S_SR具有至少一正脈衝(positive pulse)或是至少一負脈衝(negative pulse)。在此例中，脈衝的數量等於處理器120A致能次重置信號S_SR的次數。 In other embodiments, the secondary reset signal _{SSR is} maintained at a fixed level, such as a high level or a low level. When the processor 120A enable reset signal S _SR views, views of the reset signal S _SR transient level will change, thereby making the reset signal S _SR views having at least one positive pulse (positive pulse) or at least a Negative pulse. In this example, the number of pulses is equal to the number of times the processor 120A enables the secondary reset signal _SSR .

本發明並不限定處理器120A如何得知主重置信號HW_RSTn已被致能。在本實施例中，處理器120A係根據控制器140A所產生的通知信號S_N，得知主重置信號HW_RSTn是否已被致能。在另一可能實施例中，處理器120A係直接接收主重置信號HW_RSTn，用以判斷主重置信號HW_RSTn是否被致能。 The present invention does not limit how the processor 120A knows that the primary reset signal HW_RSTn has been enabled. In this embodiment, the processor 120A determines whether the main reset signal HW_RSTn has been enabled according to the notification signal S _N generated by the controller 140A. In another possible embodiment, the processor 120A directly receives the main reset signal HW_RSTn to determine whether the main reset signal HW_RSTn is enabled.

本發明並不限定主重置信號HW_RSTn被致能時的位準。在一可能實施例中，當主重置信號HW_RSTn被致能時，主重置信號HW_RSTn為高位準。當主重置信號HW_RSTn不被致能時，主重置信號HW_RSTn為低位準時。在另一可能實施例中，當主重置信號HW_RSTn被致能，主重置信號HW_RSTn為低位準。當主重置信號HW_RSTn不被致能時，主重置信號HW_RSTn為高位準。在一些實施例中，主重置信號HW_RSTn被致能時的位準可能等於或不等於次重置信號S_SR被致能時的位準。在其它實施例中，主重置信號HW_RSTn被致能時的位準可能等於或不等於遮罩信號S_M被致能時的位準。 The present invention does not limit the level at which the main reset signal HW_RSTn is enabled. In a possible embodiment, when the main reset signal HW_RSTn is enabled, the main reset signal HW_RSTn is at a high level. When the main reset signal HW_RSTn is not enabled, the main reset signal HW_RSTn is low level. In another possible embodiment, when the main reset signal HW_RSTn is enabled, the main reset signal HW_RSTn is at a low level. When the main reset signal HW_RSTn is not enabled, the main reset signal HW_RSTn is at a high level. In some embodiments, the level at which the primary reset signal HW_RSTn is enabled may be equal to or not equal to the level at which the secondary reset signal S _SR is enabled. In other embodiments, the level at which the main reset signal HW_RSTn is enabled may be equal to or not equal to the level at which the mask signal S _M is enabled.

控制器140A根據主重置信號HW_RSTn以及次重置信號S_SR產生一遮罩信號S_M。舉例而言，當次重置信號S_SR被致能時，表示邏輯電路130A正在運作。由於邏輯電路130A的部分操作是不能夠被中斷，如果直接重置邏輯電路130A，很有可能造成部分元件發生故障。因此，當主重置信號HW_RSTn被致能時，控制器140A判斷次重置信號S_SR是否被致能。若次重置信號S_SR被致能，控制器140A致能遮罩信號S_M，用以不導通開關110A，使得開關110A不傳送主重置信號HW_RSTn予處理器120A與邏輯電路130A。 The controller 140A generates a mask signal S _M based on the main reset signal HW_RSTn and the secondary reset signal S _SR . For example, when the secondary reset signal S _SR is enabled, it indicates that the logic circuit 130A is operating. Since part of the operation of the logic circuit 130A cannot be interrupted, if the logic circuit 130A is directly reset, it is likely that some of the elements are malfunctioning. Therefore, when the main reset signal HW_RSTn is enabled, the controller 140A determines whether the sub reset signal S _SR is enabled. If the secondary reset signal S _SR is enabled, the controller 140A enables the mask signal S _M to not turn on the switch 110A such that the switch 110A does not transmit the primary reset signal HW_RSTn to the processor 120A and the logic circuit 130A.

然而，當次重置信號S_SR不被致能時，表示邏輯電路130A已停止運作。因此，控制器140A不致能遮罩信號S_M，用以導通開關110A。此時，開關110A傳送主重置信號HW_RSTn予處理器120A與邏輯電路130A。處理器120A與邏輯電路130A根據主重置信號HW_RSTn進行一重置動作。在一可能實施例中，處理器120A具有一邏輯重置電路(logic reset root)。邏輯重置電路根據主重置信號HW_RSTn重置處理器120A以及邏輯電路130A。 However, when the secondary reset signal S _{SR is} not enabled, it indicates that the logic circuit 130A has stopped operating. Therefore, the controller 140A does not enable the masking signal S _M to turn on the switch 110A. At this time, the switch 110A transmits the main reset signal HW_RSTn to the processor 120A and the logic circuit 130A. The processor 120A and the logic circuit 130A perform a reset operation according to the main reset signal HW_RSTn. In one possible embodiment, processor 120A has a logic reset root. The logic reset circuit resets the processor 120A and the logic circuit 130A according to the main reset signal HW_RSTn.

本發明並不限定控制器140A的內部架構。在一可能實施例中，控制器140A係為一計數器(counter)141A。計數器141A可能是一上數計數器(up counter)或是一下數計數器(down counter)。當主重置信號HW_RSTn被致能時，如果次重置信號S_SR未被致能，計數器141A逐漸調整一計數值。如果次重置信號S_SR被致能時，表示邏輯電路130A尚未停止動作，因此，計數器141A的計數值會被重置成一初始值，故藉由計數器141A的計數值可得知邏輯電路130A是否已停止動作。 The present invention does not limit the internal architecture of the controller 140A. In one possible embodiment, controller 140A is a counter 141A. Counter 141A may be an up counter or a down counter. When the main reset signal HW_RSTn is enabled, if the secondary reset signal S _SR is not enabled, the counter 141A gradually adjusts a count value. If the secondary reset signal S _SR is enabled, it indicates that the logic circuit 130A has not stopped the operation, and therefore, the count value of the counter 141A is reset to an initial value, so whether the logic circuit 130A can be known by the count value of the counter 141A The action has been stopped.

當計數器141A的計數值不等於一預設值時，表示邏輯電路130A尚未停止動作，因此計數器141A致能遮罩信號S_M，用以不導通開關110A。此時，開關110A不傳送主重置信號HW_RSTn予處理器120A與邏輯電路130A。然而，當計數器141A的計數值等於預設值時，表示邏輯電路130A已完全停止動作，因此，計數器141A不致能遮罩信號S_M，用以導通開關110A。此時，開關110A傳送主重置信號HW_RSTn予處理器120A與邏輯電路130A。當處理器120A與邏輯電路130A接收到主重置信號HW_RSTn時，處理器120A與邏輯電路130A分別進行一重置操作，用以初始化處理器120A與邏輯電路130A內部的暫存器。 When the count value of the counter 141A is not equal to a predetermined value, it indicates that the logic circuit 130A has not stopped the operation, so the counter 141A enables the mask signal S _M to not turn on the switch 110A. At this time, the switch 110A does not transmit the main reset signal HW_RSTn to the processor 120A and the logic circuit 130A. However, when the count value of the counter 141A is equal to the preset value, it indicates that the logic circuit 130A has completely stopped the operation, and therefore, the counter 141A does not enable the mask signal S _M to turn on the switch 110A. At this time, the switch 110A transmits the main reset signal HW_RSTn to the processor 120A and the logic circuit 130A. When the processor 120A and the logic circuit 130A receive the main reset signal HW_RSTn, the processor 120A and the logic circuit 130A respectively perform a reset operation for initializing the processor 120A and the register inside the logic circuit 130A.

本發明並不限定計數器141A如何調整計數值。舉例而言，當計數器141A係為一上數計數器時，計數器141A係逐漸增加計數值。當計數器141A係為一下數計數器時，計數器141A係逐漸減少計數值。 The present invention does not limit how the counter 141A adjusts the count value. For example, when the counter 141A is an up counter, the counter 141A gradually increments the count value. When the counter 141A is a lower counter, the counter 141A gradually decreases the count value.

第1B圖為本發明之記憶裝置的另一示意圖。第1B圖相似第1A圖，不同之處在於，第1B圖的記憶裝置100B多了一偵測器150。偵測器150接收主重置信號HW_RSTn，用以判斷主重置信號HW_RSTn被致能的時間是否小於一預設時間。舉例而言，當主重置信號HW_RSTn被致能的時間小於預設時間時，表示主重置信號HW_RSTn可能受到雜訊的干擾。因此，偵測器150不輸出主重置信號HW_RSTn予開關110B及控制器140B。此時，開關110B及控制器140B暫不運作。 Fig. 1B is another schematic view of the memory device of the present invention. Fig. 1B is similar to Fig. 1A except that the memory device 100B of Fig. 1B has a detector 150. The detector 150 receives the main reset signal HW_RSTn for determining whether the time when the main reset signal HW_RSTn is enabled is less than a preset time. For example, when the main reset signal HW_RSTn is enabled for less than the preset time, it indicates that the main reset signal HW_RSTn may be interfered by noise. therefore, The detector 150 does not output the main reset signal HW_RSTn to the switch 110B and the controller 140B. At this time, the switch 110B and the controller 140B are temporarily not in operation.

然而，當主重置信號HW_RSTn被致能的時間不小於預設時間時，偵測器150輸出主重置信號HW_RSTn予開關110B及控制器140B。此時，控制器140B根據處理器120B所產生的次重置信號S_SR決定是否導通開關110B。由於開關110B、控制器140B、處理器120B與邏輯電路130B的動作原理與第1A圖的開關110A、控制器140A、處理器120A與邏輯電路130A的動作原理相同，故不再贅述。本發明並不限定偵測器150的電路架構。只要能夠偵測主重置信號HW_RSTn被致能的時間的電路，均可作為偵測器150。在一可能實施例中，偵測器150係為一低通濾波器151。 However, when the main reset signal HW_RSTn is enabled for not less than the preset time, the detector 150 outputs the main reset signal HW_RSTn to the switch 110B and the controller 140B. At this time, the controller 140B determines whether to turn on the switch 110B based on the secondary reset signal S _SR generated by the processor 120B. Since the operation principle of the switch 110B, the controller 140B, the processor 120B, and the logic circuit 130B is the same as that of the switch 110A, the controller 140A, the processor 120A, and the logic circuit 130A of FIG. 1A, the description thereof will not be repeated. The present invention does not limit the circuit architecture of the detector 150. As long as the circuit capable of detecting the time when the main reset signal HW_RSTn is enabled can be used as the detector 150. In a possible embodiment, the detector 150 is a low pass filter 151.

第2圖為第1B圖的記憶裝置的控制時序圖。符號OUT₁₅₀表示偵測器150的輸出信號。符號OUT_110B表示開關110B的輸出信號。符號VAL表示計數器141B的計數值。為方便說明，假設計數器141B係為一上數計數器。 Fig. 2 is a control timing chart of the memory device of Fig. 1B. Symbol OUT ₁₅₀ represents the output signal of detector 150. Symbol OUT _110B represents the output signal of switch 110B. The symbol VAL indicates the count value of the counter 141B. For convenience of explanation, it is assumed that the counter 141B is an up counter.

在期間210，主重置信號HW_RSTn為低位準，表示主重置信號HW_RSTn被致能。然而，由於主重置信號HW_RSTn被致能的時間未達一預設時間，因此，偵測器150不輸出主重置信號HW_RSTn。在本實施例中，偵測器150的輸出信號維持在高位準，但並非用以限制本發明。在其它實施例中，當主重置信號HW_RSTn被致能時的位準為高位準時，則在主重置信號HW_RSTn被致能的時間小於預設時間或是在主重置信號HW_RSTn未被致能時，偵測器150的輸出信號維持在低位準。 During the period 210, the main reset signal HW_RSTn is at a low level, indicating that the main reset signal HW_RSTn is enabled. However, since the main reset signal HW_RSTn is enabled for less than a predetermined time, the detector 150 does not output the main reset signal HW_RSTn. In the present embodiment, the output signal of the detector 150 is maintained at a high level, but is not intended to limit the present invention. In other embodiments, when the level of the main reset signal HW_RSTn is enabled, the time when the main reset signal HW_RSTn is enabled is less than a preset time or the main reset signal HW_RSTn is not When possible, the output signal of the detector 150 is maintained at a low level.

在期間220，主重置信號HW_RSTn為低位準，表示主重置信號HW_RSTn被致能。由於主重置信號HW_RSTn被致能的時間達預設時間，因此，在時間點T1，偵測器150輸出主重置信號HW_RSTn。如圖所示，在時間點T1，偵測器150的輸出信號由高位準變化至低位準。此時，由於偵測器150輸出主重置信號HW_RSTn，並且主重置信號HW_RSTn被致能，因此，計數器141B開始計數。在本實施例中，計數器141B的計數值係從0開始逐漸增加。由於計數器141B的計數值未達一預設值(如8)，因此，在時間點T1，計數器141B致能遮罩信號S_M，使得遮罩信號S_M為高位準。由於遮罩信號S_M被致能，故開關110^B不傳送主重置信號HW_RSTn。 During the period 220, the main reset signal HW_RSTn is at a low level, indicating that the main reset signal HW_RSTn is enabled. Since the main reset signal HW_RSTn is enabled for a preset time, the detector 150 outputs the main reset signal HW_RSTn at the time point T1. As shown, at time point T1, the output signal of detector 150 changes from a high level to a low level. At this time, since the detector 150 outputs the main reset signal HW_RSTn, and the main reset signal HW_RSTn is enabled, the counter 141B starts counting. In the present embodiment, the count value of the counter 141B gradually increases from 0. Since the count value of the counter 141B does not reach a predetermined value (e.g., 8), and therefore, at the time point Tl, 141B counter enable mask signal S _M, S _M such that the mask signal is at the high level. Since the mask signal S _M is enabled, the switch 110 ^B does not transmit the main reset signal HW_RSTn.

在期間230與240，處理器120B判斷邏輯電路130B是否停止運作。由於邏輯電路130B尚未停止運作，因此，處理器120B致能次重置信號S_SR。在本實施例中，次重置信號S_SR維持在低位準。當處理器120B致能次重置信號S_SR時，次重置信號S_SR具有一正脈衝。由於處理器120B致能次重置信號S_SR兩次，故次重置信號S_SR具有兩正脈衝。當次重置信號S_SR具有正脈衝時，計數器141B的計數值被重置為0，並重新增加計數值。 During periods 230 and 240, processor 120B determines if logic circuit 130B is down. Since the logic circuit 130B has not stopped operating, the processor 120B enables the secondary reset signal _SSR . In this embodiment, the secondary reset signal S _{SR is} maintained at a low level. When the processor 120B enables the secondary reset signal S _SR , the secondary reset signal S _SR has a positive pulse. Since the processor 120B enables the secondary reset signal S _SR twice, the secondary reset signal S _SR has two positive pulses. When the secondary reset signal S _SR has a positive pulse, the count value of the counter 141B is reset to 0, and the count value is re-incremented.

在時間點T2，由於計數器141B的計數值等於預設值，因此，計數器141B不致能遮罩信號S_M，故遮罩信號S_M由高位準變化至低位準。由於遮罩信號S_M不被致能，因此，開關110B傳送主重置信號HW_RSTn予處理器120B與邏輯電路130B。處理器120B與邏輯電路130B根據主重置信號HW_RSTn進行重置動作。 At the time point T2, since the count value of the counter 141B is equal to the preset value, the counter 141B does not enable the mask signal S _M to be masked, so the mask signal S _M changes from the high level to the low level. Since the mask signal S _{M is} not enabled, the switch 110B transmits the main reset signal HW_RSTn to the processor 120B and the logic circuit 130B. The processor 120B and the logic circuit 130B perform a reset operation according to the main reset signal HW_RSTn.

第3圖為本發明之重置方法的流程示意圖。本發明的重置方法適用於一記憶裝置，用以重置記憶裝置裡的邏輯電路。首先，根據一主重置信號調整一計數值，並令該邏輯電路在完成目前的工作後便停止運作(步驟S311)。在一可能實施例中，利用一計數器調整計數值。在此例中，當主重置信號被致能時，計數器開始增加或減少一計數值。然而，當主重置信號未被致能時，計數器不調整計數值。 Figure 3 is a schematic flow chart of the reset method of the present invention. The reset method of the present invention is applicable to a memory device for resetting logic circuits in a memory device. First, a count value is adjusted according to a main reset signal, and the logic circuit is stopped after the current work is completed (step S311). In a possible embodiment, a counter is used to adjust the count value. In this example, when the primary reset signal is enabled, the counter begins to increase or decrease a count value. However, when the primary reset signal is not enabled, the counter does not adjust the count value.

在另一可能實施例中，當主重置信號被致能，並且主重置信號被致能的時間小於一預設時間時，表示主重置信號可能受到雜訊的干擾。因此，計數器不調整計數值。然而，當主重置信號被致能的時間不小於預設時間時，計數器增加計數值。 In another possible embodiment, when the primary reset signal is enabled and the primary reset signal is enabled for less than a predetermined time, it indicates that the primary reset signal may be interfered by noise. Therefore, the counter does not adjust the count value. However, when the main reset signal is enabled for not less than the preset time, the counter increments the count value.

接著，判斷邏輯電路是否停止運作(步驟S312)。當邏輯電路未停止運作時，重置計數值(步驟S313)，並回到步驟S311，重新調整計數值。當邏輯電路停止運作時，判斷計數值是否等於一預設值(步驟S314)。當計數值等於預設值時，表示邏輯電路已確實停止運作，因此，重置邏輯電路(步驟S315)。在一可能實施例中，步驟S315係初始化邏輯電路內部的暫存器所儲存的資料。 Next, it is judged whether or not the logic circuit is stopped (step S312). When the logic circuit has not stopped operating, the count value is reset (step S313), and the process returns to step S311 to re-adjust the count value. When the logic circuit stops operating, it is judged whether or not the count value is equal to a predetermined value (step S314). When the count value is equal to the preset value, it indicates that the logic circuit has actually stopped operating, and therefore, the logic circuit is reset (step S315). In a possible embodiment, step S315 is to initialize the data stored by the temporary register inside the logic circuit.

當主重置信號被致能時，便開始調整計數值。但只要邏輯電路還在運作，便重置計數值，令計數值等於一起始值，直到邏輯電路停止運作，才停止重置計數值。當不再重置計數值時，計數值會逐漸趨近於一預設值。當計數值等於一預設值時，發出主重置信號予邏輯電路，用以重置邏輯電路。此時，由於邏輯電路已停止運作，故可避免邏輯電路的操作物，如NAND快閃記憶體，發生故障。 When the main reset signal is enabled, the count value is adjusted. However, as long as the logic circuit is still operating, the count value is reset so that the count value is equal to a start value until the logic circuit stops operating, and the reset count value is stopped. When the count value is no longer reset, the count value gradually approaches a preset value. When the count value is equal to a predetermined value, a main reset signal is issued to the logic circuit for resetting the logic circuit. this At the time, since the logic circuit has stopped operating, the operation of the logic circuit, such as the NAND flash memory, can be avoided.

除非另作定義，在此所有詞彙(包含技術與科學詞彙)均屬本發明所屬技術領域中具有通常知識者之一般理解。此外，除非明白表示，詞彙於一般字典中之定義應解釋為與其相關技術領域之文章中意義一致，而不應解釋為理想狀態或過分正式之語態。 Unless otherwise defined, all terms (including technical and scientific terms) are used in the ordinary meaning Moreover, unless expressly stated, the definition of a vocabulary in a general dictionary should be interpreted as consistent with the meaning of an article in its related art, and should not be interpreted as an ideal state or an overly formal voice.

雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims

一種記憶裝置，包括：一處理器，用以控制一邏輯電路的操作，並判斷一主重置信號是否被致能，其中當該主重置信號被致能時，該處理器根據該邏輯電路的操作產生一次重置信號；一控制器，根據該次重置信號產生一遮罩信號；一開關，當該遮罩信號被致能時，不傳送該主重置信號予該邏輯電路，當該遮罩信號未被致能時，傳送該主重置信號予該邏輯電路，用以重置該邏輯電路；以及一偵測器，偵測該主重置信號被致能的時間，當該主重置信號被致能的時間小於一預設時間時，該偵測器不輸出該主重置信號予該開關。 A memory device includes: a processor for controlling operation of a logic circuit and determining whether a master reset signal is enabled, wherein when the master reset signal is enabled, the processor is configured according to the logic circuit The operation generates a reset signal; a controller generates a mask signal according to the reset signal; and a switch, when the mask signal is enabled, does not transmit the main reset signal to the logic circuit, when When the mask signal is not enabled, the main reset signal is transmitted to the logic circuit for resetting the logic circuit; and a detector is configured to detect when the main reset signal is enabled. When the main reset signal is enabled for less than a predetermined time, the detector does not output the main reset signal to the switch.

如申請專利範圍第1項所述之記憶裝置，其中該處理器係根據該主重置信號的位準，得知該主重置信號是否被致能，當該主重置信號的位準等於一特定位準時，該處理器根據該邏輯電路的操作產生該次重置信號，當該邏輯電路正在運作時，該處理器致能該次重置信號。 The memory device of claim 1, wherein the processor determines whether the main reset signal is enabled according to a level of the main reset signal, when the level of the main reset signal is equal to At a specific level, the processor generates the reset signal according to the operation of the logic circuit, and when the logic circuit is in operation, the processor enables the reset signal.

如申請專利範圍第1項所述之記憶裝置，其中當該次重置信號被致能時，該次重置信號具有一正脈衝。 The memory device of claim 1, wherein the reset signal has a positive pulse when the reset signal is enabled.

如申請專利範圍第1項所述之記憶裝置，其中當該次重置信號被致能時，該次重置信號具有一負脈衝。 The memory device of claim 1, wherein the reset signal has a negative pulse when the reset signal is enabled.

如申請專利範圍第1項所述之記憶裝置，其中該次重置信號被致能時的位準等於該特定位準。 The memory device of claim 1, wherein the level at which the reset signal is enabled is equal to the specific level.

如申請專利範圍第1項所述之記憶裝置，其中該次重置信號被致能時的位準不等於該特定位準。 The memory device of claim 1, wherein the reset signal The level at which it is enabled is not equal to the specific level.

如申請專利範圍第1項所述之記憶裝置，其中該遮置信號被致能時的位準等於該特定位準。 The memory device of claim 1, wherein the level at which the occlusion signal is enabled is equal to the specific level.

如申請專利範圍第1項所述之記憶裝置，其中該遮置信號被致能時的位準不等於該特定位準。 The memory device of claim 1, wherein the level at which the occlusion signal is enabled is not equal to the specific level.

如申請專利範圍第1項所述之記憶裝置，其中當該開關傳送該主重置信號予該邏輯電路時，該處理器與該邏輯電路進行一重置動作。 The memory device of claim 1, wherein the processor performs a reset operation with the logic circuit when the switch transmits the main reset signal to the logic circuit.

如申請專利範圍第9項所述之記憶裝置，其中該處理器包括：一邏輯重置電路，用以重置該處理器及該邏輯電路。 The memory device of claim 9, wherein the processor comprises: a logic reset circuit for resetting the processor and the logic circuit.